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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=66.111.4.28; envelope-from=its@irrelevant.dk; helo=out4-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , Padmakar Kalghatgi , qemu-block@nongnu.org, Klaus Jensen , Max Reitz , Klaus Jensen , Stefan Hajnoczi , Keith Busch Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Padmakar Kalghatgi Implement v1.4 logic for configuring the Controller Memory Buffer. The x-legacy-cmb nvme device parameter can be set to revert to v1.3 behavior. Signed-off-by: Padmakar Kalghatgi Signed-off-by: Klaus Jensen --- hw/block/nvme.h | 1 + include/block/nvme.h | 106 +++++++++++++++++++++++++++++++++++++++---- hw/block/nvme.c | 86 ++++++++++++++++++++++++++++------- 3 files changed, 167 insertions(+), 26 deletions(-) diff --git a/hw/block/nvme.h b/hw/block/nvme.h index 574333caa3f9..daeaa24eb2e4 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -16,6 +16,7 @@ typedef struct NvmeParams { uint32_t aer_max_queued; uint8_t mdts; bool use_intel_id; + bool legacy_cmb; } NvmeParams; =20 typedef struct NvmeAsyncEvent { diff --git a/include/block/nvme.h b/include/block/nvme.h index 11ac1c2b7dfb..4700566a5017 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -15,7 +15,9 @@ typedef struct QEMU_PACKED NvmeBar { uint64_t acq; uint32_t cmbloc; uint32_t cmbsz; - uint8_t padding[3520]; /* not used by QEMU */ + uint64_t cmbmsc; + uint32_t cmbsts; + uint8_t padding[3508]; /* not used by QEMU */ uint32_t pmrcap; uint32_t pmrctl; uint32_t pmrsts; @@ -36,6 +38,7 @@ enum NvmeCapShift { CAP_MPSMIN_SHIFT =3D 48, CAP_MPSMAX_SHIFT =3D 52, CAP_PMR_SHIFT =3D 56, + CAP_CMBS_SHIFT =3D 57, }; =20 enum NvmeCapMask { @@ -49,6 +52,7 @@ enum NvmeCapMask { CAP_MPSMIN_MASK =3D 0xf, CAP_MPSMAX_MASK =3D 0xf, CAP_PMR_MASK =3D 0x1, + CAP_CMBS_MASK =3D 0x1, }; =20 #define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK) @@ -60,6 +64,7 @@ enum NvmeCapMask { #define NVME_CAP_CSS(cap) (((cap) >> CAP_CSS_SHIFT) & CAP_CSS_MASK) #define NVME_CAP_MPSMIN(cap)(((cap) >> CAP_MPSMIN_SHIFT) & CAP_MPSMIN_MASK) #define NVME_CAP_MPSMAX(cap)(((cap) >> CAP_MPSMAX_SHIFT) & CAP_MPSMAX_MASK) +#define NVME_CAP_CMBS(cap) (((cap) >> CAP_CMBS_SHIFT) & CAP_CMBS_MASK) =20 #define NVME_CAP_SET_MQES(cap, val) (cap |=3D (uint64_t)(val & CAP_MQES_= MASK) \ << CAP_MQES_SHI= FT) @@ -81,6 +86,8 @@ enum NvmeCapMask { << CAP_MPSMAX_= SHIFT) #define NVME_CAP_SET_PMRS(cap, val) (cap |=3D (uint64_t)(val & CAP_PMR_MAS= K)\ << CAP_PMR_SHI= FT) +#define NVME_CAP_SET_CMBS(cap, val) (cap |=3D (uint64_t)(val & CAP_CMBS_= MASK)\ + << CAP_CMBS_SH= IFT) =20 enum NvmeCapCss { NVME_CAP_CSS_NVM =3D 1 << 0, @@ -162,25 +169,64 @@ enum NvmeAqaMask { #define NVME_AQA_ACQS(aqa) ((aqa >> AQA_ACQS_SHIFT) & AQA_ACQS_MASK) =20 enum NvmeCmblocShift { - CMBLOC_BIR_SHIFT =3D 0, - CMBLOC_OFST_SHIFT =3D 12, + CMBLOC_BIR_SHIFT =3D 0, + CMBLOC_CQMMS_SHIFT =3D 3, + CMBLOC_CQPDS_SHIFT =3D 4, + CMBLOC_CDPMLS_SHIFT =3D 5, + CMBLOC_CDPCILS_SHIFT =3D 6, + CMBLOC_CDMMMS_SHIFT =3D 7, + CMBLOC_CQDA_SHIFT =3D 8, + CMBLOC_OFST_SHIFT =3D 12, }; =20 enum NvmeCmblocMask { - CMBLOC_BIR_MASK =3D 0x7, - CMBLOC_OFST_MASK =3D 0xfffff, + CMBLOC_BIR_MASK =3D 0x7, + CMBLOC_CQMMS_MASK =3D 0x1, + CMBLOC_CQPDS_MASK =3D 0x1, + CMBLOC_CDPMLS_MASK =3D 0x1, + CMBLOC_CDPCILS_MASK =3D 0x1, + CMBLOC_CDMMMS_MASK =3D 0x1, + CMBLOC_CQDA_MASK =3D 0x1, + CMBLOC_OFST_MASK =3D 0xfffff, }; =20 -#define NVME_CMBLOC_BIR(cmbloc) ((cmbloc >> CMBLOC_BIR_SHIFT) & \ - CMBLOC_BIR_MASK) -#define NVME_CMBLOC_OFST(cmbloc)((cmbloc >> CMBLOC_OFST_SHIFT) & \ - CMBLOC_OFST_MASK) +#define NVME_CMBLOC_BIR(cmbloc) \ + ((cmbloc >> CMBLOC_BIR_SHIFT) & CMBLOC_BIR_MASK) +#define NVME_CMBLOC_CQMMS(cmbloc) \ + ((cmbloc >> CMBLOC_CQMMS_SHIFT) & CMBLOC_CQMMS_MASK) +#define NVME_CMBLOC_CQPDS(cmbloc) \ + ((cmbloc >> CMBLOC_CQPDS_SHIFT) & CMBLOC_CQPDS_MASK) +#define NVME_CMBLOC_CDPMLS(cmbloc) \ + ((cmbloc >> CMBLOC_CDPMLS_SHIFT) & CMBLOC_CDPMLS_MASK) +#define NVME_CMBLOC_CDPCILS(cmbloc) \ + ((cmbloc >> CMBLOC_CDPCILS_SHIFT) & CMBLOC_CDPCILS_MASK) +#define NVME_CMBLOC_CDMMMS(cmbloc) \ + ((cmbloc >> CMBLOC_CDMMMS_SHIFT) & CMBLOC_CDMMMS_MASK) +#define NVME_CMBLOC_CQDA(cmbloc) \ + ((cmbloc >> CMBLOC_CQDA_SHIFT) & CMBLOC_CQDA_MASK) +#define NVME_CMBLOC_OFST(cmbloc) \ + ((cmbloc >> CMBLOC_OFST_SHIFT) & CMBLOC_OFST_MASK) =20 -#define NVME_CMBLOC_SET_BIR(cmbloc, val) \ +#define NVME_CMBLOC_SET_BIR(cmbloc, val) \ (cmbloc |=3D (uint64_t)(val & CMBLOC_BIR_MASK) << CMBLOC_BIR_SHIFT) +#define NVME_CMBLOC_SET_CQMMS(cmbloc, val) \ + (cmbloc |=3D (uint64_t)(val & CMBLOC_CQMMS_MASK) << CMBLOC_CQMMS_SHIFT) +#define NVME_CMBLOC_SET_CQPDS(cmbloc, val) \ + (cmbloc |=3D (uint64_t)(val & CMBLOC_CQPDS_MASK) << CMBLOC_CQPDS_SHIFT) +#define NVME_CMBLOC_SET_CDPMLS(cmbloc, val) \ + (cmbloc |=3D (uint64_t)(val & CMBLOC_CDPMLS_MASK) << CMBLOC_CDPMLS_SHI= FT) +#define NVME_CMBLOC_SET_CDPCILS(cmbloc, val) \ + (cmbloc |=3D (uint64_t)(val & CMBLOC_CDPCILS_MASK) << CMBLOC_CDPCILS_S= HIFT) +#define NVME_CMBLOC_SET_CDMMMS(cmbloc, val) \ + (cmbloc |=3D (uint64_t)(val & CMBLOC_CDMMMS_MASK) << CMBLOC_CDMMMS_SHI= FT) +#define NVME_CMBLOC_SET_CQDA(cmbloc, val) \ + (cmbloc |=3D (uint64_t)(val & CMBLOC_CQDA_MASK) << CMBLOC_CQDA_SHIFT) #define NVME_CMBLOC_SET_OFST(cmbloc, val) \ (cmbloc |=3D (uint64_t)(val & CMBLOC_OFST_MASK) << CMBLOC_OFST_SHIFT) =20 +#define NVME_CMBMSMC_SET_CRE (cmbmsc, val) \ + (cmbmsc |=3D (uint64_t)(val & CMBLOC_OFST_MASK) << CMBMSC_CRE_SHIFT) + enum NvmeCmbszShift { CMBSZ_SQS_SHIFT =3D 0, CMBSZ_CQS_SHIFT =3D 1, @@ -227,6 +273,46 @@ enum NvmeCmbszMask { #define NVME_CMBSZ_GETSIZE(cmbsz) \ (NVME_CMBSZ_SZ(cmbsz) * (1 << (12 + 4 * NVME_CMBSZ_SZU(cmbsz)))) =20 +enum NvmeCmbmscShift { + CMBMSC_CRE_SHIFT =3D 0, + CMBMSC_CMSE_SHIFT =3D 1, + CMBMSC_CBA_SHIFT =3D 12, +}; + +enum NvmeCmbmscMask { + CMBMSC_CRE_MASK =3D 0x1, + CMBMSC_CMSE_MASK =3D 0x1, + CMBMSC_CBA_MASK =3D ((1L << 52) - 1), +}; + +#define NVME_CMBMSC_CRE(cmbmsc) \ + ((cmbmsc >> CMBMSC_CRE_SHIFT) & CMBMSC_CRE_MASK) +#define NVME_CMBMSC_CMSE(cmbmsc) \ + ((cmbmsc >> CMBMSC_CMSE_SHIFT) & CMBMSC_CMSE_MASK) +#define NVME_CMBMSC_CBA(cmbmsc) \ + ((cmbmsc >> CMBMSC_CBA_SHIFT) & CMBMSC_CBA_MASK) + + +#define NVME_CMBMSC_SET_CRE(cmbmsc, val) \ + (cmbmsc |=3D (uint64_t)(val & CMBMSC_CRE_MASK) << CMBMSC_CRE_SHIFT) +#define NVME_CMBMSC_SET_CMSE(cmbmsc, val) \ + (cmbmsc |=3D (uint64_t)(val & CMBMSC_CMSE_MASK) << CMBMSC_CMSE_SHIFT) +#define NVME_CMBMSC_SET_CBA(cmbmsc, val) \ + (cmbmsc |=3D (uint64_t)(val & CMBMSC_CBA_MASK) << CMBMSC_CBA_SHIFT) + +enum NvmeCmbstsShift { + CMBSTS_CBAI_SHIFT =3D 0, +}; +enum NvmeCmbstsMask { + CMBSTS_CBAI_MASK =3D 0x1, +}; + +#define NVME_CMBSTS_CBAI(cmbsts) \ + ((cmbsts >> CMBSTS_CBAI_SHIFT) & CMBSTS_CBAI_MASK) + +#define NVME_CMBSTS_SET_CBAI(cmbsts, val) \ + (cmbsts |=3D (uint64_t)(val & CMBSTS_CBAI_MASK) << CMBSTS_CBAI_SHIFT) + enum NvmePmrcapShift { PMRCAP_RDS_SHIFT =3D 3, PMRCAP_WDS_SHIFT =3D 4, diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 28416b18a5c0..f3c111ee0a5c 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -130,17 +130,32 @@ static uint16_t nvme_sqid(NvmeRequest *req) =20 static bool nvme_addr_is_cmb(NvmeCtrl *n, hwaddr addr) { - hwaddr low =3D n->ctrl_mem.addr; - hwaddr hi =3D n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size); + hwaddr hi, low; + + if (n->params.legacy_cmb) { + low =3D n->ctrl_mem.addr; + } else { + low =3D NVME_CMBMSC_CBA(n->bar.cmbmsc) << CMBMSC_CBA_SHIFT; + } + + hi =3D low + int128_get64(n->ctrl_mem.size); =20 return addr >=3D low && addr < hi; } =20 static inline void *nvme_addr_to_cmb(NvmeCtrl *n, hwaddr addr) { + hwaddr cba; + assert(nvme_addr_is_cmb(n, addr)); =20 - return &n->cmbuf[addr - n->ctrl_mem.addr]; + if (n->params.legacy_cmb) { + cba =3D n->ctrl_mem.addr; + } else { + cba =3D NVME_CMBMSC_CBA(n->bar.cmbmsc) << CMBMSC_CBA_SHIFT; + } + + return &n->cmbuf[addr - cba]; } =20 static int nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size) @@ -2411,6 +2426,19 @@ static int nvme_start_ctrl(NvmeCtrl *n) return 0; } =20 +static void nvme_cmb_enable_regs(NvmeCtrl *n) +{ + NVME_CMBLOC_SET_BIR(n->bar.cmbloc, NVME_CMB_BIR); + + NVME_CMBSZ_SET_SQS(n->bar.cmbsz, 1); + NVME_CMBSZ_SET_CQS(n->bar.cmbsz, 0); + NVME_CMBSZ_SET_LISTS(n->bar.cmbsz, 1); + NVME_CMBSZ_SET_RDS(n->bar.cmbsz, 1); + NVME_CMBSZ_SET_WDS(n->bar.cmbsz, 1); + NVME_CMBSZ_SET_SZU(n->bar.cmbsz, 2); /* MBs */ + NVME_CMBSZ_SET_SZ(n->bar.cmbsz, n->params.cmb_size_mb); +} + static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data, unsigned size) { @@ -2536,6 +2564,34 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offse= t, uint64_t data, NVME_GUEST_ERR(pci_nvme_ub_mmiowr_cmbsz_readonly, "invalid write to read only CMBSZ, ignored"); return; + case 0x50: /* CMBMSC */ + exit(1); + if (!NVME_CAP_CMBS(n->bar.cap)) { + return; + } + + n->bar.cmbmsc =3D data; + + if (NVME_CMBMSC_CRE(data)) { + nvme_cmb_enable_regs(n); + + if (NVME_CMBMSC_CMSE(data)) { + hwaddr cba =3D NVME_CMBMSC_CBA(data) << CMBMSC_CBA_SHIFT; + if (cba + int128_get64(n->ctrl_mem.size) < cba) { + NVME_CMBSTS_SET_CBAI(n->bar.cmbsts, 1); + return; + } + } + } else if (!NVME_CMBMSC_CRE(data)) { + n->bar.cmbsz =3D 0; + n->bar.cmbloc =3D 0; + } + + return; + case 0x54: /* CMBMSC hi */ + n->bar.cmbmsc |=3D data << 32; + return; + case 0xE00: /* PMRCAP */ NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrcap_readonly, "invalid write to PMRCAP register, ignored"); @@ -2880,24 +2936,21 @@ int nvme_register_namespace(NvmeCtrl *n, NvmeNamesp= ace *ns, Error **errp) =20 static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev) { - NVME_CMBLOC_SET_BIR(n->bar.cmbloc, NVME_CMB_BIR); - NVME_CMBLOC_SET_OFST(n->bar.cmbloc, 0); + uint64_t cmb_size =3D n->params.cmb_size_mb * MiB; =20 - NVME_CMBSZ_SET_SQS(n->bar.cmbsz, 1); - NVME_CMBSZ_SET_CQS(n->bar.cmbsz, 0); - NVME_CMBSZ_SET_LISTS(n->bar.cmbsz, 1); - NVME_CMBSZ_SET_RDS(n->bar.cmbsz, 1); - NVME_CMBSZ_SET_WDS(n->bar.cmbsz, 1); - NVME_CMBSZ_SET_SZU(n->bar.cmbsz, 2); /* MBs */ - NVME_CMBSZ_SET_SZ(n->bar.cmbsz, n->params.cmb_size_mb); - - n->cmbuf =3D g_malloc0(NVME_CMBSZ_GETSIZE(n->bar.cmbsz)); + n->cmbuf =3D g_malloc0(cmb_size); memory_region_init_io(&n->ctrl_mem, OBJECT(n), &nvme_cmb_ops, n, - "nvme-cmb", NVME_CMBSZ_GETSIZE(n->bar.cmbsz)); - pci_register_bar(pci_dev, NVME_CMBLOC_BIR(n->bar.cmbloc), + "nvme-cmb", cmb_size); + pci_register_bar(pci_dev, NVME_CMB_BIR, PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64 | PCI_BASE_ADDRESS_MEM_PREFETCH, &n->ctrl_mem); + + if (n->params.legacy_cmb) { + nvme_cmb_enable_regs(n); + } else { + NVME_CAP_SET_CMBS(n->bar.cap, 1); + } } =20 static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev) @@ -3118,6 +3171,7 @@ static Property nvme_props[] =3D { DEFINE_PROP_UINT32("aer_max_queued", NvmeCtrl, params.aer_max_queued, = 64), DEFINE_PROP_UINT8("mdts", NvmeCtrl, params.mdts, 7), DEFINE_PROP_BOOL("use-intel-id", NvmeCtrl, params.use_intel_id, false), + DEFINE_PROP_BOOL("x-legacy-cmb", NvmeCtrl, params.legacy_cmb, false), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.29.2 From nobody Sat May 18 18:57:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1608283739; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=66.111.4.28; envelope-from=its@irrelevant.dk; helo=out4-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , qemu-block@nongnu.org, Klaus Jensen , Max Reitz , Klaus Jensen , Stefan Hajnoczi , Keith Busch Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen With the new CMB logic in place, bump the implemented specification version to v1.4. Signed-off-by: Klaus Jensen --- hw/block/nvme.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index f3c111ee0a5c..16bf05638bf6 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -74,7 +74,7 @@ =20 #define NVME_MAX_IOQPAIRS 0xffff #define NVME_DB_SIZE 4 -#define NVME_SPEC_VER 0x00010300 +#define NVME_SPEC_VER 0x00010400 #define NVME_CMB_BIR 2 #define NVME_PMR_BIR 2 #define NVME_TEMPERATURE 0x143 --=20 2.29.2 From nobody Sat May 18 18:57:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1608284078; cv=none; d=zohomail.com; s=zohoarc; b=ank3pvEK2NEKie4LaejBVH1px2GD7CqUT9ag49tECAbhWo4MpOOhXQqSzKk4CNL7n8rEHYJaeeZh2snOxHUKa4C5rDo3xIvsdSOwEqlQPGKMJyWHtBXpAnklMVEiXt4i3VBYxMLgBXQFL5yqFbt6uTg8vy7oHJiGRnzNnj2O+9c= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=66.111.4.28; envelope-from=its@irrelevant.dk; helo=out4-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , qemu-block@nongnu.org, Klaus Jensen , Max Reitz , Klaus Jensen , Stefan Hajnoczi , Keith Busch Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen The controller now implements v1.4 and we can lift the restrictions on CMB Data Pointer and Command Independent Locations Support (CDPCILS) and CMB Data Pointer Mixed Locations Support (CDPMLS) since the device really does not care about mixed host/cmb pointers in those cases. Signed-off-by: Klaus Jensen --- hw/block/nvme.c | 33 ++------------------------------- 1 file changed, 2 insertions(+), 31 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 16bf05638bf6..bd1de8453cfa 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -336,7 +336,6 @@ static uint16_t nvme_map_prp(NvmeCtrl *n, uint64_t prp1= , uint64_t prp2, trans_len =3D MIN(len, trans_len); int num_prps =3D (len >> n->page_bits) + 1; uint16_t status; - bool prp_list_in_cmb =3D false; int ret; =20 QEMUSGList *qsg =3D &req->qsg; @@ -362,10 +361,6 @@ static uint16_t nvme_map_prp(NvmeCtrl *n, uint64_t prp= 1, uint64_t prp2, uint32_t nents, prp_trans; int i =3D 0; =20 - if (nvme_addr_is_cmb(n, prp2)) { - prp_list_in_cmb =3D true; - } - nents =3D (len + n->page_size - 1) >> n->page_bits; prp_trans =3D MIN(n->max_prp_ents, nents) * sizeof(uint64_t); ret =3D nvme_addr_read(n, prp2, (void *)prp_list, prp_trans); @@ -382,10 +377,6 @@ static uint16_t nvme_map_prp(NvmeCtrl *n, uint64_t prp= 1, uint64_t prp2, return NVME_INVALID_PRP_OFFSET | NVME_DNR; } =20 - if (prp_list_in_cmb !=3D nvme_addr_is_cmb(n, prp_ent))= { - return NVME_INVALID_USE_OF_CMB | NVME_DNR; - } - i =3D 0; nents =3D (len + n->page_size - 1) >> n->page_bits; prp_trans =3D MIN(n->max_prp_ents, nents) * sizeof(uin= t64_t); @@ -519,7 +510,6 @@ static uint16_t nvme_map_sgl(NvmeCtrl *n, QEMUSGList *q= sg, QEMUIOVector *iov, uint64_t nsgld; uint32_t seg_len; uint16_t status; - bool sgl_in_cmb =3D false; hwaddr addr; int ret; =20 @@ -541,18 +531,6 @@ static uint16_t nvme_map_sgl(NvmeCtrl *n, QEMUSGList *= qsg, QEMUIOVector *iov, goto out; } =20 - /* - * If the segment is located in the CMB, the submission queue of the - * request must also reside there. - */ - if (nvme_addr_is_cmb(n, addr)) { - if (!nvme_addr_is_cmb(n, req->sq->dma_addr)) { - return NVME_INVALID_USE_OF_CMB | NVME_DNR; - } - - sgl_in_cmb =3D true; - } - for (;;) { switch (NVME_SGL_TYPE(sgld->type)) { case NVME_SGL_DESCR_TYPE_SEGMENT: @@ -641,15 +619,6 @@ static uint16_t nvme_map_sgl(NvmeCtrl *n, QEMUSGList *= qsg, QEMUIOVector *iov, if (status) { goto unmap; } - - /* - * If the next segment is in the CMB, make sure that the sgl was - * already located there. - */ - if (sgl_in_cmb !=3D nvme_addr_is_cmb(n, addr)) { - status =3D NVME_INVALID_USE_OF_CMB | NVME_DNR; - goto unmap; - } } =20 out: @@ -2428,6 +2397,8 @@ static int nvme_start_ctrl(NvmeCtrl *n) =20 static void nvme_cmb_enable_regs(NvmeCtrl *n) { + NVME_CMBLOC_SET_CDPCILS(n->bar.cmbloc, 1); + NVME_CMBLOC_SET_CDPMLS(n->bar.cmbloc, 1); NVME_CMBLOC_SET_BIR(n->bar.cmbloc, NVME_CMB_BIR); =20 NVME_CMBSZ_SET_SQS(n->bar.cmbsz, 1); --=20 2.29.2