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Wed, 16 Dec 2020 16:45:28 -0800 (PST) Date: Wed, 16 Dec 2020 16:43:45 -0800 In-Reply-To: <20201217004349.3740927-1-wuhaotsh@google.com> Message-Id: <20201217004349.3740927-3-wuhaotsh@google.com> Mime-Version: 1.0 References: <20201217004349.3740927-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.29.2.684.gfbc64c5ab5-goog Subject: [PATCH v4 2/6] hw/timer: Refactor NPCM7XX Timer to use CLK clock To: peter.maydell@linaro.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1049; envelope-from=3KKraXwgKCusjhUNbgfUTbbTYR.PbZdRZh-QRiRYabaTah.beT@flex--wuhaotsh.bounces.google.com; helo=mail-pj1-x1049.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: minyard@acm.org, venture@google.com, qemu-devel@nongnu.org, hskinnemoen@google.com, wuhaotsh@google.com, kfting@nuvoton.com, qemu-arm@nongnu.org, Avi.Fishman@nuvoton.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Hao Wu From: Hao Wu via X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch makes NPCM7XX Timer to use a the timer clock generated by the CLK module instead of the magic number TIMER_REF_HZ. Reviewed-by: Havard Skinnemoen Reviewed-by: Tyrone Ting Signed-off-by: Hao Wu --- hw/arm/npcm7xx.c | 5 +++++ hw/timer/npcm7xx_timer.c | 25 ++++++++++++++----------- include/hw/misc/npcm7xx_clk.h | 6 ------ include/hw/timer/npcm7xx_timer.h | 1 + 4 files changed, 20 insertions(+), 17 deletions(-) diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index 47e2b6fc40..fabfb1697b 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -22,6 +22,7 @@ #include "hw/char/serial.h" #include "hw/loader.h" #include "hw/misc/unimp.h" +#include "hw/qdev-clock.h" #include "hw/qdev-properties.h" #include "qapi/error.h" #include "qemu/units.h" @@ -420,6 +421,10 @@ static void npcm7xx_realize(DeviceState *dev, Error **= errp) int first_irq; int j; =20 + /* Connect the timer clock. */ + qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_= out( + DEVICE(&s->clk), "timer-clock")); + sysbus_realize(sbd, &error_abort); sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]); =20 diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c index d24445bd6e..6e990d611a 100644 --- a/hw/timer/npcm7xx_timer.c +++ b/hw/timer/npcm7xx_timer.c @@ -17,8 +17,8 @@ #include "qemu/osdep.h" =20 #include "hw/irq.h" +#include "hw/qdev-clock.h" #include "hw/qdev-properties.h" -#include "hw/misc/npcm7xx_clk.h" #include "hw/timer/npcm7xx_timer.h" #include "migration/vmstate.h" #include "qemu/bitops.h" @@ -130,7 +130,7 @@ static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *= t, uint32_t count) { int64_t ns =3D count; =20 - ns *=3D NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ; + ns *=3D clock_get_ns(t->ctrl->clock); ns *=3D npcm7xx_tcsr_prescaler(t->tcsr); =20 return ns; @@ -141,7 +141,7 @@ static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer = *t, int64_t ns) { int64_t count; =20 - count =3D ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ); + count =3D ns / clock_get_ns(t->ctrl->clock); count /=3D npcm7xx_tcsr_prescaler(t->tcsr); =20 return count; @@ -167,7 +167,7 @@ static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xx= WatchdogTimer *t, int64_t cycles) { uint32_t prescaler =3D npcm7xx_watchdog_timer_prescaler(t); - int64_t ns =3D (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ) * cycle= s; + int64_t ns =3D clock_get_ns(t->ctrl->clock) * cycles; =20 /* * The reset function always clears the current timer. The caller of t= he @@ -606,10 +606,11 @@ static void npcm7xx_timer_hold_reset(Object *obj) qemu_irq_lower(s->watchdog_timer.irq); } =20 -static void npcm7xx_timer_realize(DeviceState *dev, Error **errp) +static void npcm7xx_timer_init(Object *obj) { - NPCM7xxTimerCtrlState *s =3D NPCM7XX_TIMER(dev); - SysBusDevice *sbd =3D &s->parent; + NPCM7xxTimerCtrlState *s =3D NPCM7XX_TIMER(obj); + DeviceState *dev =3D DEVICE(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); int i; NPCM7xxWatchdogTimer *w; =20 @@ -627,11 +628,12 @@ static void npcm7xx_timer_realize(DeviceState *dev, E= rror **errp) npcm7xx_watchdog_timer_expired, w); sysbus_init_irq(sbd, &w->irq); =20 - memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s, + memory_region_init_io(&s->iomem, obj, &npcm7xx_timer_ops, s, TYPE_NPCM7XX_TIMER, 4 * KiB); sysbus_init_mmio(sbd, &s->iomem); qdev_init_gpio_out_named(dev, &w->reset_signal, NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1); + s->clock =3D qdev_init_clock_in(dev, "clock", NULL, NULL); } =20 static const VMStateDescription vmstate_npcm7xx_base_timer =3D { @@ -675,10 +677,11 @@ static const VMStateDescription vmstate_npcm7xx_watch= dog_timer =3D { =20 static const VMStateDescription vmstate_npcm7xx_timer_ctrl =3D { .name =3D "npcm7xx-timer-ctrl", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .fields =3D (VMStateField[]) { VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState), + VMSTATE_CLOCK(clock, NPCM7xxTimerCtrlState), VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState, NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_t= imer, NPCM7xxTimer), @@ -697,7 +700,6 @@ static void npcm7xx_timer_class_init(ObjectClass *klass= , void *data) QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS); =20 dc->desc =3D "NPCM7xx Timer Controller"; - dc->realize =3D npcm7xx_timer_realize; dc->vmsd =3D &vmstate_npcm7xx_timer_ctrl; rc->phases.enter =3D npcm7xx_timer_enter_reset; rc->phases.hold =3D npcm7xx_timer_hold_reset; @@ -708,6 +710,7 @@ static const TypeInfo npcm7xx_timer_info =3D { .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(NPCM7xxTimerCtrlState), .class_init =3D npcm7xx_timer_class_init, + .instance_init =3D npcm7xx_timer_init, }; =20 static void npcm7xx_timer_register_type(void) diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h index f641f95f3e..d5c8d16ca4 100644 --- a/include/hw/misc/npcm7xx_clk.h +++ b/include/hw/misc/npcm7xx_clk.h @@ -20,12 +20,6 @@ #include "hw/clock.h" #include "hw/sysbus.h" =20 -/* - * The reference clock frequency for the timer modules, and the SECCNT and - * CNTR25M registers in this module, is always 25 MHz. - */ -#define NPCM7XX_TIMER_REF_HZ (25000000) - /* * Number of registers in our device state structure. Don't change this wi= thout * incrementing the version_id in the vmstate. diff --git a/include/hw/timer/npcm7xx_timer.h b/include/hw/timer/npcm7xx_ti= mer.h index 6993fd723a..d45c051b56 100644 --- a/include/hw/timer/npcm7xx_timer.h +++ b/include/hw/timer/npcm7xx_timer.h @@ -101,6 +101,7 @@ struct NPCM7xxTimerCtrlState { =20 uint32_t tisr; =20 + Clock *clock; NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL]; NPCM7xxWatchdogTimer watchdog_timer; }; --=20 2.29.2.684.gfbc64c5ab5-goog