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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id 189sm3625351wma.22.2020.12.16.08.28.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 08:28:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=56BrI+3ByfNWDrlnZrGuWZgk38BOwa5mF2TsZj5KPRY=; b=A9W7gsxa6xahDxGpG9/CAC1cEYH9alNoLLDSRYjLes8LW2VircTK2d5fHL/Dtucis3 vqkOD8AlPJBvfZmwXoMmWg3Tua7TjT0eV7vOnCC2Per260Njf3L4cAU8sR8VnK4anZ5P w/d2OxhQ+yBcmm54C0aK33S11Kr5pkZPICQV3Bk/HcSTJ/bDuAPkff90j5RnRhtVLSg1 ptOCnAWzkQI/TMlhG1xzhBja4mJiEukhGfr+5fahs8nflUNlilqw7Sg6R4dB3hdW+A37 o+FAYGTTHtCmsGeHHTO4CRqmooXbXaVltabygedDMtMmGz43DfqkpIAZPA8sqG5p5VgR Tb+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=56BrI+3ByfNWDrlnZrGuWZgk38BOwa5mF2TsZj5KPRY=; b=ZLMvuifBc81Ps32bNoBk4Fm3cvsPATeh0IkW9sGq3RHgCwE3UwFKkfXxe+Q5RVVap/ o7TjAr70D92Uo/gSk94Set0u/d8BllTvwOqyMCZdE7x8Zlw3sbcKrfi0z7AQ4V8j/9Oq jgHb4UXw8m7rnGRlW4QDKoAlblCkBzrTdObc0Gcwz/kK9UCAFGGNR4NiSSX1QX4Hhoq5 tvE1z44S530BS/KoZERayPDRoKFEWUhYKwjpHa90iCbBmVkDRFGwiaSYpFpvMBXpoLqg p43yCFsox1IIXJqOytvJ+0Pg4TdJuXoJN99vB3m5HQrd9kqqLXqSWlOXbmSMxlcs+T/p vqyA== X-Gm-Message-State: AOAM533ovl6D4GLf2/tJ3+eqLbUF5ZGnpo0jtEp1yJZyH6jowHqBx2ou VJTJzxUnXWr5t+lgNBbERhw= X-Google-Smtp-Source: ABdhPJzlq9MoEhzlFo90C6XaJNQcKKBcyV4eKOelJwjBURGZPHIYAymv9NmLnK9gAvX6pmAUSmzaDA== X-Received: by 2002:a1c:2783:: with SMTP id n125mr4152605wmn.74.1608136087227; Wed, 16 Dec 2020 08:28:07 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Aleksandar Rikalo , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Burton , Jiaxun Yang , Aurelien Jarno Subject: [PATCH v2 04/12] target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2 Date: Wed, 16 Dec 2020 17:27:36 +0100 Message-Id: <20201216162744.895920-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216162744.895920-1-f4bug@amsat.org> References: <20201216162744.895920-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Use the single ISA_MIPS32R2 definition to check if the Release 2 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R2 in few commits. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/mips-defs.h | 3 +-- linux-user/mips/cpu_loop.c | 1 - target/mips/translate.c | 4 ++-- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 2756e72a9d6..9cfa4c346bf 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -24,7 +24,6 @@ #define ISA_MIPS5 0x0000000000000010ULL #define ISA_MIPS32 0x0000000000000020ULL #define ISA_MIPS32R2 0x0000000000000040ULL -#define ISA_MIPS64R2 0x0000000000000100ULL #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS64R3 0x0000000000000400ULL #define ISA_MIPS32R5 0x0000000000000800ULL @@ -81,7 +80,7 @@ =20 /* MIPS Technologies "Release 2" */ #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) -#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) +#define CPU_MIPS64R2 (CPU_MIPS64 | ISA_MIPS32R2) =20 /* MIPS Technologies "Release 3" */ #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index b58dbeb83d1..a2aa8167210 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -386,7 +386,6 @@ void target_cpu_copy_regs(CPUArchState *env, struct tar= get_pt_regs *regs) prog_req.fre &=3D interp_req.fre; =20 bool cpu_has_mips_r2_r6 =3D env->insn_flags & ISA_MIPS32R2 || - env->insn_flags & ISA_MIPS64R2 || env->insn_flags & ISA_MIPS32R6 || env->insn_flags & ISA_MIPS64R6; =20 diff --git a/target/mips/translate.c b/target/mips/translate.c index 12b01d4c35d..de3a6b5ed65 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28212,7 +28212,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) case OPC_DINSM: case OPC_DINSU: case OPC_DINS: - check_insn(ctx, ISA_MIPS64R2); + check_insn(ctx, ISA_MIPS32R2); check_mips_64(ctx); gen_bitops(ctx, op1, rt, rs, sa, rd); break; @@ -28232,7 +28232,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) decode_opc_special3_r6(env, ctx); break; default: - check_insn(ctx, ISA_MIPS64R2); + check_insn(ctx, ISA_MIPS32R2); check_mips_64(ctx); op2 =3D MASK_DBSHFL(ctx->opcode); gen_bshfl(ctx, op2, rt, rd); --=20 2.26.2