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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id c81sm3756241wmd.6.2020.12.16.08.28.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 08:28:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L+8pzijn52zFNvnTsp0BOKURgiDqajyPik6Q5epzma8=; b=IUowv9fquZB8meq7j2d0fnFjKCx3YZ6dki/fzvSGYdeBvMCjYIObPkc2mkRFItLrZK D2yWdWQY2mqWzjqcJpk0qF8rBFPnimRysYFdFeqh5QKcmF/tO/Kdeo22dh/qQ7hmlPma p0woDnO3S3SKV8vysfetQN5P+R671X4yT4v767fDrwslp3u6de3jnYE3erk5TKSkKJ/K xapcLYWbmT7VXePsXMNJ8uKjFsvRHEMAYBPFETXkzMHMA/qbbTH+u7MSnLE/QUxmsHy8 HBvejJi5XKHbfSnuwO9DXOGnOeHCWY5XVEvDA5M63tqUEnNmd1GaC6B4pxzevoXHQTWr KS+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=L+8pzijn52zFNvnTsp0BOKURgiDqajyPik6Q5epzma8=; b=ExhpIn7NNNMzbU7EU+eFVsbdc4ZXCWVgYiT6FJ1gF1pvtI4HewJ8wZWzHdphwzl+eZ 4RJ/fKzUKHCkXvUnpjemrdiSeYmgAwNxCXA8gWGKvW53ci03u1bkXTyENnVW4WexBoWC 65YnYgzwrA0jAE8LTRKzqMNqDo6+uR5Ihklzm3w1ZiPxanfPgpUFWJCASSaWjNicdRNe yTFnlgifRwlWN3cwgr6XtazKM8UgX8L10n9H74RvnZaRKPwyaxYwt0qdLW/fVJ1sWH/Q 7DPvgejq9DGAC45okzCrMMsYahK/M/o14CRX+/2uUcU76ZMH39GOh3RBTm238lasB2Ie /0Lg== X-Gm-Message-State: AOAM532aRUIwsP85uiQHR0hDiT54qhGjFCVn8VG5a4ztSizf9vs9Yrl4 PBn0FnMjGO0ZsXR0lEwgmsF+P0EUbAg= X-Google-Smtp-Source: ABdhPJyV1NcWKH2yZzIX19z9Lx05aHxbOTWqSHDL17DZJLBQEBX0PS8z3Tp3CXtLrgCr28S69rcYGQ== X-Received: by 2002:a1c:3b02:: with SMTP id i2mr3750460wma.141.1608136082253; Wed, 16 Dec 2020 08:28:02 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Aleksandar Rikalo , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Burton , Jiaxun Yang , Aurelien Jarno Subject: [PATCH v2 03/12] target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1 Date: Wed, 16 Dec 2020 17:27:35 +0100 Message-Id: <20201216162744.895920-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216162744.895920-1-f4bug@amsat.org> References: <20201216162744.895920-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Use the single ISA_MIPS32 definition to check if the Release 1 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R1 in few commits. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/mips-defs.h | 3 +-- target/mips/translate.c | 10 +++++----- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index ab621a750d5..2756e72a9d6 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -24,7 +24,6 @@ #define ISA_MIPS5 0x0000000000000010ULL #define ISA_MIPS32 0x0000000000000020ULL #define ISA_MIPS32R2 0x0000000000000040ULL -#define ISA_MIPS64 0x0000000000000080ULL #define ISA_MIPS64R2 0x0000000000000100ULL #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS64R3 0x0000000000000400ULL @@ -78,7 +77,7 @@ =20 /* MIPS Technologies "Release 1" */ #define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) -#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) +#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32) =20 /* MIPS Technologies "Release 2" */ #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) diff --git a/target/mips/translate.c b/target/mips/translate.c index 15265485f76..12b01d4c35d 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -8538,7 +8538,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) const char *register_name =3D "invalid"; =20 if (sel !=3D 0) { - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS32); } =20 switch (reg) { @@ -9264,7 +9264,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) const char *register_name =3D "invalid"; =20 if (sel !=3D 0) { - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS32); } =20 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { @@ -14502,12 +14502,12 @@ static int decode_mips16_opc(CPUMIPSState *env, D= isasContext *ctx) break; #if defined(TARGET_MIPS64) case RR_RY_CNVT_ZEW: - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS32); check_mips_64(ctx); tcg_gen_ext32u_tl(cpu_gpr[rx], cpu_gpr[rx]); break; case RR_RY_CNVT_SEW: - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS32); check_mips_64(ctx); tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]); break; @@ -27203,7 +27203,7 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) #if defined(TARGET_MIPS64) case OPC_DCLO: case OPC_DCLZ: - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS32); check_mips_64(ctx); gen_cl(ctx, op1, rd, rs); break; --=20 2.26.2