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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id r20sm3892217wrg.66.2020.12.16.08.28.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 08:28:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/D7zdCflSZ6xA7e0uhMvc28vP/CHUGVea2/tI230T3c=; b=po+A8HHzMBToeB1ahSUSPCF1wCQsyz2HGMurriWshBekLN5VU3823tB4PDYDn2X8q0 6LPqQZV+miLhPwOOw17nIJNEgSBlejYvWx6TKTN8oo1h1tHJL2D5uUDBewWMGXT00rt1 eSRuz05f8wx/mH3KCp8CBvegd+1LG+VwK0GFz4LQq3Dd5z0FswoTGPg5pxsdaGr5EIWB Ao6tPXc6veMRzdqEcRkhVH6iwKZkyNxbyoec9YrKekdLHutup2yLvnm81Z3djwO5g4UX weSSiyIA6lokAZm4hK9SLY8XEoZp74YxR+I/Yi9I5QZYtgnTbr4sqbHGDT9gkbqXLVNP 5DiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=/D7zdCflSZ6xA7e0uhMvc28vP/CHUGVea2/tI230T3c=; b=khG/BZGxuPoXx2quU8ZHGL96utEJ2+vre+kFNin34mzopnFtWyca9FMsm3Nro1h+jF DcxLS4uyWvTV/7JVyzI1Kl03JMTP1AFFLezRGN43rZHU6vK0SBw8Ih+y64iS0nnxBOvJ GJVLCrf5efCglGvwRbvI/TzG9kJG8eLynosZiE7WDnfv3BCnXZVkcafBqgK1BK9Br3e/ I1pOfwactNvZh61FxQUOtqPbfmrOB+eY00ol9yh5cu25f/Wjf+TBDKksxhFbpwNU4IKm 1V3ahmwjQHBLGzPygxoBG7vVWnBws8wK0m9Lx5WFijsqnMEICNTFJDq0/Exo0Ymt9Zot Gabw== X-Gm-Message-State: AOAM530eNrldBD6oDNCaqdon70OjRgPn/DLHgaKMmP0GlepEclzu8T5i 6vAOPqfxjddK7MFP1alI+GY= X-Google-Smtp-Source: ABdhPJxoPN5e7I0CW51aNBncTh0ZzURIfknV9IiFMnEJdJaIGNhNs82F1T4VkI1GYIjSn7NYNehRHw== X-Received: by 2002:a1c:2182:: with SMTP id h124mr4135400wmh.25.1608136121841; Wed, 16 Dec 2020 08:28:41 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Aleksandar Rikalo , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Burton , Jiaxun Yang , Aurelien Jarno Subject: [PATCH v2 11/12] target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5 Date: Wed, 16 Dec 2020 17:27:43 +0100 Message-Id: <20201216162744.895920-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216162744.895920-1-f4bug@amsat.org> References: <20201216162744.895920-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The MIPS ISA release 5 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/mips-defs.h | 4 ++-- target/mips/translate.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 171d94c16dc..068fe9c8a19 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -25,7 +25,7 @@ #define ISA_MIPS_R1 0x0000000000000020ULL #define ISA_MIPS_R2 0x0000000000000040ULL #define ISA_MIPS_R3 0x0000000000000080ULL -#define ISA_MIPS32R5 0x0000000000000800ULL +#define ISA_MIPS_R5 0x0000000000000100ULL #define ISA_MIPS32R6 0x0000000000002000ULL #define ISA_NANOMIPS32 0x0000000000008000ULL /* @@ -84,7 +84,7 @@ #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3) =20 /* MIPS Technologies "Release 5" */ -#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5) +#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS_R5) #define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5) =20 /* MIPS Technologies "Release 6" */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 34bc083c813..43462c195fe 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -10588,7 +10588,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext= *ctx, uint32_t opc, if (ctx->opcode & (1 << bit_shift)) { /* OPC_ERETNC */ opn =3D "eretnc"; - check_insn(ctx, ISA_MIPS32R5); + check_insn(ctx, ISA_MIPS_R5); gen_helper_eretnc(cpu_env); } else { /* OPC_ERET */ --=20 2.26.2