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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=paolo.bonzini@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: philmd@redhat.com, richard.henderson@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" icache flush is also used by non-TCG accelerators. Do not require users such as physmem.c to include tcg/tcg.h. Signed-off-by: Paolo Bonzini --- include/exec/flush-icache.h | 64 ++++++++++++++++++++++++++++++++++++++++ softmmu/physmem.c | 1 + tcg/aarch64/tcg-target.h | 5 ---- tcg/arm/tcg-target.h | 5 ---- tcg/i386/tcg-target.h | 4 --- tcg/mips/tcg-target.h | 11 ------- tcg/ppc/tcg-target.c.inc | 22 -------------- tcg/ppc/tcg-target.h | 1 - tcg/riscv/tcg-target.h | 5 ---- tcg/s390/tcg-target.h | 4 --- tcg/sparc/tcg-target.h | 8 ----- tcg/tcg.c | 1 + tcg/tci/tcg-target.h | 4 --- util/cacheinfo.c | 25 ++++++++++++++++ 14 files changed, 91 insertions(+), 69 deletions(-) create mode 100644 include/exec/flush-icache.h diff --git a/include/exec/flush-icache.h b/include/exec/flush-icache.h new file mode 100644 index 0000000000..77a7b80ab7 --- /dev/null +++ b/include/exec/flush-icache.h @@ -0,0 +1,64 @@ +/* + * icache flush for QEMU (both TCG or virtualized) + * + * Copyright (c) 2003-2020 QEMU contributors + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef FLUSH_ICACHE_H +#define FLUSH_ICACHE_H + +#if defined HOST_I386 || defined HOST_X86_64 || defined HOST_S390 || defin= ed HOST_S390X +static inline void flush_icache_range(uintptr_t start, uintptr_t stop) +{ +} + +#elif defined HOST_MIPS +#ifdef __OpenBSD__ +#include +#else +#include +#endif + +static inline void flush_icache_range(uintptr_t start, uintptr_t stop) +{ + cacheflush ((void *)start, stop-start, ICACHE); +} + +#elif defined HOST_PPC || defined HOST_PPC64 +extern void flush_icache_range(uintptr_t start, uintptr_t stop); + +#elif defined HOST_SPARC +static inline void flush_icache_range(uintptr_t start, uintptr_t stop) +{ + uintptr_t p; + for (p =3D start & -8; p < ((stop + 7) & -8); p +=3D 8) { + __asm__ __volatile__("flush\t%0" : : "r" (p)); + } +} + +#elif defined HOST_AARCH64 || defined HOST_ARM || defined HOST_RISCV +static inline void flush_icache_range(uintptr_t start, uintptr_t stop) +{ + __builtin___clear_cache((char *)start, (char *)stop); +} +#elif defined CONFIG_TCG_INTERPRETER +static inline void flush_icache_range(uintptr_t start, uintptr_t stop) +{ + assert(tcg_enabled()); +} +#endif + +#endif diff --git a/softmmu/physmem.c b/softmmu/physmem.c index 67b53d39e4..c6a3cb679e 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -53,6 +53,7 @@ #include "qemu/rcu_queue.h" #include "qemu/main-loop.h" #include "exec/translate-all.h" +#include "exec/flush-icache.h" #include "sysemu/replay.h" =20 #include "exec/memory-internal.h" diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 663dd0b95e..8a6b97598e 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -148,11 +148,6 @@ typedef enum { #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 -static inline void flush_icache_range(uintptr_t start, uintptr_t stop) -{ - __builtin___clear_cache((char *)start, (char *)stop); -} - void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); =20 #ifdef CONFIG_SOFTMMU diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 17e771374d..f1955ce4ac 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -134,11 +134,6 @@ enum { #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 -static inline void flush_icache_range(uintptr_t start, uintptr_t stop) -{ - __builtin___clear_cache((char *) start, (char *) stop); -} - /* not defined -- call should be eliminated at compile time */ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); =20 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index abd4ac7fc0..cd067e0b30 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -206,10 +206,6 @@ extern bool have_avx2; #define TCG_TARGET_extract_i64_valid(ofs, len) \ (((ofs) =3D=3D 8 && (len) =3D=3D 8) || ((ofs) + (len)) =3D=3D 32) =20 -static inline void flush_icache_range(uintptr_t start, uintptr_t stop) -{ -} - static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, uintptr_t = addr) { diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index c6b091d849..92c1d63da3 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -198,20 +198,9 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_ext16u_i64 0 /* andi rt, rs, 0xffff */ #endif =20 -#ifdef __OpenBSD__ -#include -#else -#include -#endif - #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 -static inline void flush_icache_range(uintptr_t start, uintptr_t stop) -{ - cacheflush ((void *)start, stop-start, ICACHE); -} - void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); =20 #ifdef CONFIG_SOFTMMU diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 18ee989f95..0d068ec8ab 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -3863,25 +3863,3 @@ void tcg_register_jit(void *buf, size_t buf_size) tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); } #endif /* __ELF__ */ - -void flush_icache_range(uintptr_t start, uintptr_t stop) -{ - uintptr_t p, start1, stop1; - size_t dsize =3D qemu_dcache_linesize; - size_t isize =3D qemu_icache_linesize; - - start1 =3D start & ~(dsize - 1); - stop1 =3D (stop + dsize - 1) & ~(dsize - 1); - for (p =3D start1; p < stop1; p +=3D dsize) { - asm volatile ("dcbst 0,%0" : : "r"(p) : "memory"); - } - asm volatile ("sync" : : : "memory"); - - start &=3D start & ~(isize - 1); - stop1 =3D (stop + isize - 1) & ~(isize - 1); - for (p =3D start1; p < stop1; p +=3D isize) { - asm volatile ("icbi 0,%0" : : "r"(p) : "memory"); - } - asm volatile ("sync" : : : "memory"); - asm volatile ("isync" : : : "memory"); -} diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index be10363956..a509a19628 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -175,7 +175,6 @@ extern bool have_vsx; #define TCG_TARGET_HAS_bitsel_vec have_vsx #define TCG_TARGET_HAS_cmpsel_vec 0 =20 -void flush_icache_range(uintptr_t start, uintptr_t stop); void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); =20 #define TCG_TARGET_DEFAULT_MO (0) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 032439d806..c1bd52bb9a 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -159,11 +159,6 @@ typedef enum { #define TCG_TARGET_HAS_mulsh_i64 1 #endif =20 -static inline void flush_icache_range(uintptr_t start, uintptr_t stop) -{ - __builtin___clear_cache((char *)start, (char *)stop); -} - /* not defined -- call should be eliminated at compile time */ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); =20 diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 63c8797bd3..b4feb2f55a 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -145,10 +145,6 @@ enum { TCG_AREG0 =3D TCG_REG_R10, }; =20 -static inline void flush_icache_range(uintptr_t start, uintptr_t stop) -{ -} - static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, uintptr_t = addr) { diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 633841ebf2..d8b0e32e2e 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -168,14 +168,6 @@ extern bool use_vis3_instructions; #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 =20 -static inline void flush_icache_range(uintptr_t start, uintptr_t stop) -{ - uintptr_t p; - for (p =3D start & -8; p < ((stop + 7) & -8); p +=3D 8) { - __asm__ __volatile__("flush\t%0" : : "r" (p)); - } -} - void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); =20 #define TCG_TARGET_NEED_POOL_LABELS diff --git a/tcg/tcg.c b/tcg/tcg.c index 43c6cf8f52..9974bb3c56 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -43,6 +43,7 @@ #include "cpu.h" =20 #include "exec/exec-all.h" +#include "exec/flush-icache.h" =20 #if !defined(CONFIG_USER_ONLY) #include "hw/boards.h" diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 8c1c1d265d..b84480f989 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -191,10 +191,6 @@ void tci_disas(uint8_t opc); =20 #define HAVE_TCG_QEMU_TB_EXEC =20 -static inline void flush_icache_range(uintptr_t start, uintptr_t stop) -{ -} - /* We could notice __i386__ or __s390x__ and reduce the barriers depending on the host. But if you want performance, you use the normal backend. We prefer consistency across hosts on this. */ diff --git a/util/cacheinfo.c b/util/cacheinfo.c index 7804c186b6..b49093106d 100644 --- a/util/cacheinfo.c +++ b/util/cacheinfo.c @@ -9,6 +9,7 @@ #include "qemu/osdep.h" #include "qemu/host-utils.h" #include "qemu/atomic.h" +#include "exec/flush-icache.h" =20 int qemu_icache_linesize =3D 0; int qemu_icache_linesize_log; @@ -177,6 +178,30 @@ static void fallback_cache_info(int *isize, int *dsize) } } =20 +#if defined HOST_PPC || defined HOST_PPC64 +void flush_icache_range(uintptr_t start, uintptr_t stop) +{ + uintptr_t p, start1, stop1; + size_t dsize =3D qemu_dcache_linesize; + size_t isize =3D qemu_icache_linesize; + + start1 =3D start & ~(dsize - 1); + stop1 =3D (stop + dsize - 1) & ~(dsize - 1); + for (p =3D start1; p < stop1; p +=3D dsize) { + asm volatile ("dcbst 0,%0" : : "r"(p) : "memory"); + } + asm volatile ("sync" : : : "memory"); + + start &=3D start & ~(isize - 1); + stop1 =3D (stop + isize - 1) & ~(isize - 1); + for (p =3D start1; p < stop1; p +=3D isize) { + asm volatile ("icbi 0,%0" : : "r"(p) : "memory"); + } + asm volatile ("sync" : : : "memory"); + asm volatile ("isync" : : : "memory"); +} +#endif + static void __attribute__((constructor)) init_cache_info(void) { int isize =3D 0, dsize =3D 0; --=20 2.28.0