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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id h20sm3486906wrb.21.2020.12.16.05.44.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 05:44:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pAXR0ap5QyHsOud3cHZbUyk7Vfk3//npBQDgukBmgis=; b=ZJuXm0nURzPSzaK1MkWtpPrMhIS5wI1vYCr00TdE7++oWeo/LJ6npLR+YXcCvK7030 lxmEVtmxJYvog7fKQF1cAjOImahHD+oQYJPE52o582C3tKO180P4AhDJ4x5VVmT9kIdZ nEh86CQ+63aKSJU6+f/lyKpP1hawOHgkRBTgUVLO88pqpyw49Hmi/THOx+Dv9SQGtHVM WR1EEU7eRYGfVCRhbNozU4UWpztGogEVXORxYedQV7Sts3CjKSipP1q1zrtOCbECYNEj rAyNdrnPm/mB0rmEi1GXufkZw+WZZnNQiZjuZajHGb9R6eO86htdW2UKAppwzhen5HYj TIBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=pAXR0ap5QyHsOud3cHZbUyk7Vfk3//npBQDgukBmgis=; b=jsYqg9+EHQCDL8Orrhjhu+nD8ChB5OZiUkCBA5bUx7pso4sHV7rawqnZ3CH+ceoblH vgkeH4fOgssnolI6/BgujIiOOZE2A1nIYpiaK8WxzfCXZ3mv/CUFAgfN7OQED92M3/Ry ChI7/F6sRXZx3TPUK0iA9/KwlXAmcvvcKWxVNaB8G5r7+yYNdzO8ECkNdK13afzEARVF cCY/nIPNPny4x+YX7iJkUgZ9e23pVY/WFZqJZA58+Bn+R54LUfRima52igKJzmLoJb/Y YLrATJz+vhL3aOzDdltkR6WgZGwuuzADD2RRaXOrpuvCGixltmXQmfQgUb+FpteUY63n 6ieA== X-Gm-Message-State: AOAM531zDOrW+SzKnHDZFa75wLSRYwt/iOAbqq9K9CP46LwAgtSJeHJQ b8g4Fnz+6aG+H5kd/hjamgc= X-Google-Smtp-Source: ABdhPJyceNeSFEujfUB2VFtTJkbuWXEjtXJE0kbo/lA6XxsD93Y3tFgtC6szOjJe8fg7FoaWKoC4dQ== X-Received: by 2002:adf:cd8f:: with SMTP id q15mr37261367wrj.79.1608126245672; Wed, 16 Dec 2020 05:44:05 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Paul Burton , Richard Henderson , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 07/11] target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1 Date: Wed, 16 Dec 2020 14:43:24 +0100 Message-Id: <20201216134328.851840-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216134328.851840-1-f4bug@amsat.org> References: <20201216134328.851840-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The MIPS ISA release '1' is common to 32/64-bit CPUs. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 2 +- target/mips/mips-defs.h | 4 ++-- target/mips/translate.c | 44 ++++++++++++++++++++--------------------- 3 files changed, 25 insertions(+), 25 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 97899dbd3c8..f71c617a1fe 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -365,7 +365,7 @@ static inline void compute_hflags(CPUMIPSState *env) if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { env->hflags |=3D MIPS_HFLAG_COP1X; } - } else if (env->insn_flags & ISA_MIPS32) { + } else if (env->insn_flags & ISA_MIPS_R1) { if (env->hflags & MIPS_HFLAG_64) { env->hflags |=3D MIPS_HFLAG_COP1X; } diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index df2ffae5718..31c02cc20ef 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -22,7 +22,7 @@ #define ISA_MIPS3 0x0000000000000004ULL /* 64-bit */ #define ISA_MIPS4 0x0000000000000008ULL #define ISA_MIPS5 0x0000000000000010ULL -#define ISA_MIPS32 0x0000000000000020ULL +#define ISA_MIPS_R1 0x0000000000000020ULL #define ISA_MIPS32R2 0x0000000000000040ULL #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS32R5 0x0000000000000800ULL @@ -72,7 +72,7 @@ #define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI) =20 /* MIPS Technologies "Release 1" */ -#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) +#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS_R1) #define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32) =20 /* MIPS Technologies "Release 2" */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 38fbc55ff1e..d4e672ebca6 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7006,7 +7006,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) const char *register_name =3D "invalid"; =20 if (sel !=3D 0) { - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); } =20 switch (reg) { @@ -7774,7 +7774,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) const char *register_name =3D "invalid"; =20 if (sel !=3D 0) { - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); } =20 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { @@ -10601,7 +10601,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext= *ctx, uint32_t opc, break; case OPC_DERET: opn =3D "deret"; - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { goto die; @@ -10616,7 +10616,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext= *ctx, uint32_t opc, break; case OPC_WAIT: opn =3D "wait"; - check_insn(ctx, ISA_MIPS3 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1); if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { goto die; @@ -10651,7 +10651,7 @@ static void gen_compute_branch1(DisasContext *ctx, = uint32_t op, } =20 if (cc !=3D 0) { - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1); } =20 btarget =3D ctx->base.pc_next + 4 + offset; @@ -14020,7 +14020,7 @@ static int decode_extended_mips16_opc(CPUMIPSState = *env, DisasContext *ctx) gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm); break; case I8_SVRS: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); { int xsregs =3D (ctx->opcode >> 24) & 0x7; int aregs =3D (ctx->opcode >> 16) & 0xf; @@ -14270,7 +14270,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) ((int8_t)ctx->opcode) << 3); break; case I8_SVRS: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); { int do_ra =3D ctx->opcode & (1 << 6); int do_s0 =3D ctx->opcode & (1 << 5); @@ -14414,7 +14414,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) int ra =3D (ctx->opcode >> 5) & 0x1; =20 if (nd) { - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); } =20 if (link) { @@ -14435,7 +14435,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) * XXX: not clear which exception should be raised * when in debug mode... */ - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); generate_exception_end(ctx, EXCP_DBp); } break; @@ -14486,7 +14486,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) gen_HILO(ctx, OPC_MFHI, 0, rx); break; case RR_CNVT: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); switch (cnvt_op) { case RR_RY_CNVT_ZEB: tcg_gen_ext8u_tl(cpu_gpr[rx], cpu_gpr[rx]); @@ -15426,7 +15426,7 @@ static void gen_pool16c_insn(DisasContext *ctx) * XXX: not clear which exception should be raised * when in debug mode... */ - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); generate_exception_end(ctx, EXCP_DBp); } break; @@ -15770,7 +15770,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) case CLZ: mips32_op =3D OPC_CLZ; do_cl: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); gen_cl(ctx, mips32_op, rt, rs); break; case RDHWR: @@ -15797,7 +15797,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) mips32_op =3D OPC_DIVU; goto do_div; do_div: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); gen_muldiv(ctx, mips32_op, 0, rs, rt); break; case MADD: @@ -15816,7 +15816,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) check_insn_opc_removed(ctx, ISA_MIPS32R6); mips32_op =3D OPC_MSUBU; do_mul: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); gen_muldiv(ctx, mips32_op, 0, rs, rt); break; default: @@ -15964,7 +15964,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) if (is_uhi(extract32(ctx->opcode, 16, 10))) { gen_helper_do_semihosting(cpu_env); } else { - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); if (ctx->hflags & MIPS_HFLAG_SBRI) { gen_reserved_instruction(ctx); } else { @@ -24482,7 +24482,7 @@ static void decode_opc_special_legacy(CPUMIPSState = *env, DisasContext *ctx) switch (op1) { case OPC_MOVN: /* Conditional move */ case OPC_MOVZ: - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 | + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 | INSN_LOONGSON2E | INSN_LOONGSON2F); gen_cond_move(ctx, op1, rd, rs, rt); break; @@ -24495,7 +24495,7 @@ static void decode_opc_special_legacy(CPUMIPSState = *env, DisasContext *ctx) gen_HILO(ctx, op1, rd & 3, rs); break; case OPC_MOVCI: - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1); if (env->CP0_Config1 & (1 << CP0C1_FP)) { check_cp1_enabled(ctx); gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7, @@ -27168,7 +27168,7 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) case OPC_MADDU: case OPC_MSUB: case OPC_MSUBU: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); gen_muldiv(ctx, op1, rd & 3, rs, rt); break; case OPC_MUL: @@ -27185,7 +27185,7 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) break; case OPC_CLO: case OPC_CLZ: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); gen_cl(ctx, op1, rd, rs); break; case OPC_SDBBP: @@ -27196,7 +27196,7 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) * XXX: not clear which exception should be raised * when in debug mode... */ - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); generate_exception_end(ctx, EXCP_DBp); } break; @@ -28643,7 +28643,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) case OPC_CACHE: check_insn_opc_removed(ctx, ISA_MIPS32R6); check_cp0_enabled(ctx); - check_insn(ctx, ISA_MIPS3 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1); if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { gen_cache_operation(ctx, rt, rs, imm); } @@ -28654,7 +28654,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) if (ctx->insn_flags & INSN_R5900) { /* Treat as NOP. */ } else { - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1); /* Treat as NOP. */ } break; --=20 2.26.2