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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id j9sm3259274wrm.14.2020.12.16.05.43.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 05:44:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FQTagxeMSRlTpSXXXsWsvusOqbZsJsc4nubvf9MNEgI=; b=WuwhmH4a+OHsQ+NED0ibcxT3V5VATle50JDdk3eyDzpeSABX25TQ4o4Zq44GJOHqhi zV5UlHHLOWrQbVDjOc5jG3Y7kbf6InA8zG+W81KCjvD74U1xU9vnc7ftJiI+aouSovZa dpjWK1iKcVDpNGpxl36ZL/uEM1KqImgPQFjVUwG/vqU+Q3ECZBaSews0SvxC+0GcmJdB 8VzuZnxkSp9pt1FMgkfG09uQwypbR4DD8kiGG6u4ciBADBXfIY8xAunP0c69FqOMEMtU U/lxs1+UDaIUbw3UrEcok+8s2xdJypEddxA478cBKkLy/8wlehvTpTNpIfS1e9n4NVgQ fRUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=FQTagxeMSRlTpSXXXsWsvusOqbZsJsc4nubvf9MNEgI=; b=r6XVzT52mBum8+9zmBN0MpJzgNI/a0weGzxJfIo3bFt5XN69wwQnyXrOAnVsGwGPej 5WnjE5onIvLSNuVBWKBNY2ci8D24wUyTL8zUegiXa+MIWvPJH7V6x8vF7SQ+R+uZtL/G LQQbW+cXu0sz4jVPtHWFNne0/xKQ4clAedaC2pTnb31MVNNmwTcPkNvhn2O47RS0v9FP VWO60XX8EmN9QdmrGHYmdzjj4EVx275NZGyr5M+I1hwAYgvDJ4ojpE4hHVaGnINKVgcx 8HkNWSw/S0NSj2S1cC811g/kc6ZAb7IHs3+dA4H4Ep7zfz8dHpnaY2Ju/hFYj3ZOpFgo 83AA== X-Gm-Message-State: AOAM531lhS6/AneasALT0CFNEerleszluzp1BD7mrMSroL12SCxuXx0E 8UB0LCVCUvEEwCpXamuUqhg= X-Google-Smtp-Source: ABdhPJwkhB1AY8o4bOcc8lCpWjwKd8grKudEri8lhwbb+yC/vTPFO+ZOiA1i6Zzr9+tbnExPPGe/3A== X-Received: by 2002:a1c:9a57:: with SMTP id c84mr3307790wme.183.1608126240746; Wed, 16 Dec 2020 05:44:00 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Paul Burton , Richard Henderson , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 06/11] target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6 Date: Wed, 16 Dec 2020 14:43:23 +0100 Message-Id: <20201216134328.851840-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216134328.851840-1-f4bug@amsat.org> References: <20201216134328.851840-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Use the single ISA_MIPS32R6 definition to check if the Release 6 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R6 in few commits. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 2 +- target/mips/mips-defs.h | 3 +-- linux-user/elfload.c | 2 +- linux-user/mips/cpu_loop.c | 3 +-- target/mips/tlb_helper.c | 6 +++--- target/mips/translate.c | 2 +- 6 files changed, 8 insertions(+), 10 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 76269cfc7bb..97899dbd3c8 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -308,7 +308,7 @@ static inline void compute_hflags(CPUMIPSState *env) } else if (((env->hflags & MIPS_HFLAG_KSU) =3D=3D MIPS_HFLAG_UM) && !(env->CP0_Status & (1 << CP0St_UX))) { env->hflags |=3D MIPS_HFLAG_AWRAP; - } else if (env->insn_flags & ISA_MIPS64R6) { + } else if (env->insn_flags & ISA_MIPS32R6) { /* Address wrapping for Supervisor and Kernel is specified in R6 */ if ((((env->hflags & MIPS_HFLAG_KSU) =3D=3D MIPS_HFLAG_SM) && !(env->CP0_Status & (1 << CP0St_SX))) || diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index ea9dcc7c98e..df2ffae5718 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -27,7 +27,6 @@ #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS32R5 0x0000000000000800ULL #define ISA_MIPS32R6 0x0000000000002000ULL -#define ISA_MIPS64R6 0x0000000000004000ULL #define ISA_NANOMIPS32 0x0000000000008000ULL /* * bits 24-39: MIPS ASEs @@ -90,7 +89,7 @@ =20 /* MIPS Technologies "Release 6" */ #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) -#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6) +#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6) =20 /* Wave Computing: "nanoMIPS" */ #define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 0b02a926025..e875a5387cc 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -997,7 +997,7 @@ static uint32_t get_elf_hwcap(void) #define GET_FEATURE(flag, hwcap) \ do { if (cpu->env.insn_flags & (flag)) { hwcaps |=3D hwcap; } } while = (0) =20 - GET_FEATURE(ISA_MIPS32R6 | ISA_MIPS64R6, HWCAP_MIPS_R6); + GET_FEATURE(ISA_MIPS32R6, HWCAP_MIPS_R6); GET_FEATURE(ASE_MSA, HWCAP_MIPS_MSA); =20 #undef GET_FEATURE diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index a2aa8167210..1e4acf3d6e3 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -386,8 +386,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct tar= get_pt_regs *regs) prog_req.fre &=3D interp_req.fre; =20 bool cpu_has_mips_r2_r6 =3D env->insn_flags & ISA_MIPS32R2 || - env->insn_flags & ISA_MIPS32R6 || - env->insn_flags & ISA_MIPS64R6; + env->insn_flags & ISA_MIPS32R6; =20 if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) { env->CP0_Config5 |=3D (1 << CP0C5_FRE); diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c index 94a482e3dbe..68d766f90a3 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tlb_helper.c @@ -1025,7 +1025,7 @@ void mips_cpu_do_interrupt(CPUState *cs) enter_debug_mode: if (env->insn_flags & ISA_MIPS3) { env->hflags |=3D MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS64R6) || + if (!(env->insn_flags & ISA_MIPS32R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &=3D ~MIPS_HFLAG_AWRAP; } @@ -1054,7 +1054,7 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Status |=3D (1 << CP0St_ERL) | (1 << CP0St_BEV); if (env->insn_flags & ISA_MIPS3) { env->hflags |=3D MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS64R6) || + if (!(env->insn_flags & ISA_MIPS32R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &=3D ~MIPS_HFLAG_AWRAP; } @@ -1240,7 +1240,7 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Status |=3D (1 << CP0St_EXL); if (env->insn_flags & ISA_MIPS3) { env->hflags |=3D MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS64R6) || + if (!(env->insn_flags & ISA_MIPS32R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &=3D ~MIPS_HFLAG_AWRAP; } diff --git a/target/mips/translate.c b/target/mips/translate.c index 0923dfdf451..38fbc55ff1e 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -29078,7 +29078,7 @@ static void mips_tr_init_disas_context(DisasContext= Base *dcbase, CPUState *cs) #else ctx->mem_idx =3D hflags_mmu_index(ctx->hflags); #endif - ctx->default_tcg_memop_mask =3D (ctx->insn_flags & (ISA_MIPS32R6 | ISA= _MIPS64R6 | + ctx->default_tcg_memop_mask =3D (ctx->insn_flags & (ISA_MIPS32R6 | INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN; =20 LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx, --=20 2.26.2