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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id o13sm2685057wmc.44.2020.12.16.05.43.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 05:43:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OBt9eJBX3pTIBLp30XCH/Bjd/stHNhDGzJ5XaGYAJJU=; b=t9MfVhMxMbWgQASEuCwaYR1S1dHxFdFpRmdQvdPlIvsdornJbuG7dMa4xSBeu7iqDB bpG3UFiJgLSERb0A5BnwXWnctQKWppNP6XHEZ+t0IoDGuWfaT7hvazakFWXmT0CTErrj rFQYdw2RG9uCipgQKZ9kb1zb/rpEBf+1nweqIFLSeb/71XB1ZtOvRa2apqeJUCQo3c52 6v3fqo2nV+w8Xx8Zyb5pI3WNm24joIuN79/Y9nE6Mz8U6MhN4KWtliyuKmyJWU9bqM/Y +M9lG26QoSorVqg/1jCo83vChZKxvGgCOsMyt6znYuuQb0tpy834X/o/hCO/2FIFmqZS 8AGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=OBt9eJBX3pTIBLp30XCH/Bjd/stHNhDGzJ5XaGYAJJU=; b=TSCkb2k2Af+zLY1G0EdA0bEZdNFUSXkCs1yhG9R8GihNstWEpO0dHq/yb73XfR3wUp xusoNcMkOd9qQm9UQ8RbR5Ug5FLm/QLCPL3L1ZwuiHGJIWnWpSUsHQ9Ox4gJG+aFP4gp sDxn6JaUOA+cVncLyZV2WqkLBE2LajFsr4AN+sqjweP643gZw851xH7hHbvWS8n0BIys +Vv9XXTvX9IsimsYQv7ngvM3KKrmB/FmFOIFEUCybPdXAtkI/0Ku2QDAhB0xnVClkPrs oPnbZWg4QR0UQgfgiRjszY3Txp4TKAnb6IO3CFleCOESkXNEDi1iqfJDvBI/rcf3A0OP aueg== X-Gm-Message-State: AOAM533k5VgW+BKD0qFXW3sHRMdxBvZzM466JZfDRrS8daJ0VVRgFlFx ollwS+8N29PdF29HZdCLO7U= X-Google-Smtp-Source: ABdhPJyFlaeC39Lw8FBllcb4uKna9cveR3MqU4YbpW33QC8ubtsim0bKbvynd1uC6G1w13jNmlpEOA== X-Received: by 2002:adf:9d49:: with SMTP id o9mr39344000wre.413.1608126220968; Wed, 16 Dec 2020 05:43:40 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Paul Burton , Richard Henderson , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 02/11] target/mips/mips-defs: Use ISA_MIPS3 for ISA_MIPS64 Date: Wed, 16 Dec 2020 14:43:19 +0100 Message-Id: <20201216134328.851840-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216134328.851840-1-f4bug@amsat.org> References: <20201216134328.851840-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) MIPS 64-bit ISA is introduced with MIPS3. No need for another bit/definition to check for 64-bit. Simplify CPU_MIPS64 definition as CPU_MIPS5 contains CPU_MIPS4 which contains CPU_MIPS3 which contains ISA_MIPS3. Suggested-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jiaxun Yang --- target/mips/mips-defs.h | 5 ++--- hw/mips/boston.c | 2 +- target/mips/translate.c | 10 +++++----- 3 files changed, 8 insertions(+), 9 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index f4d76e562d1..2756e72a9d6 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -19,12 +19,11 @@ */ #define ISA_MIPS1 0x0000000000000001ULL #define ISA_MIPS2 0x0000000000000002ULL -#define ISA_MIPS3 0x0000000000000004ULL +#define ISA_MIPS3 0x0000000000000004ULL /* 64-bit */ #define ISA_MIPS4 0x0000000000000008ULL #define ISA_MIPS5 0x0000000000000010ULL #define ISA_MIPS32 0x0000000000000020ULL #define ISA_MIPS32R2 0x0000000000000040ULL -#define ISA_MIPS64 0x0000000000000080ULL #define ISA_MIPS64R2 0x0000000000000100ULL #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS64R3 0x0000000000000400ULL @@ -78,7 +77,7 @@ =20 /* MIPS Technologies "Release 1" */ #define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) -#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) +#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32) =20 /* MIPS Technologies "Release 2" */ #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index c3b94c68e1b..f44f681fab5 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -463,7 +463,7 @@ static void boston_mach_init(MachineState *machine) exit(1); } =20 - is_64b =3D cpu_type_supports_isa(machine->cpu_type, ISA_MIPS64); + is_64b =3D cpu_type_supports_isa(machine->cpu_type, ISA_MIPS3); =20 object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS= ); object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type, diff --git a/target/mips/translate.c b/target/mips/translate.c index 15265485f76..8c0ecfa17e1 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -8538,7 +8538,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) const char *register_name =3D "invalid"; =20 if (sel !=3D 0) { - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS3); } =20 switch (reg) { @@ -9264,7 +9264,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) const char *register_name =3D "invalid"; =20 if (sel !=3D 0) { - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS3); } =20 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { @@ -14502,12 +14502,12 @@ static int decode_mips16_opc(CPUMIPSState *env, D= isasContext *ctx) break; #if defined(TARGET_MIPS64) case RR_RY_CNVT_ZEW: - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); tcg_gen_ext32u_tl(cpu_gpr[rx], cpu_gpr[rx]); break; case RR_RY_CNVT_SEW: - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]); break; @@ -27203,7 +27203,7 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) #if defined(TARGET_MIPS64) case OPC_DCLO: case OPC_DCLZ: - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); gen_cl(ctx, op1, rd, rs); break; --=20 2.26.2