From nobody Tue Nov 18 05:50:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) client-ip=209.85.221.42; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f42.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1608126218; cv=none; d=zohomail.com; s=zohoarc; b=adzAU5BO86LY/3yJ4RKMhudtURvWGNT7CSWz6qYzRj6ZkSCcEzHWPkwPEl6azDodjl5KNr8VU8e5me75GIeSJk6ar0ffeg/kK005J5oDtzNfEJeui2kjqsSs2P9+rfrZNniWG/oiwRStxn5styXdy1/No5wkIU+Abr9/OK+G5Us= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608126218; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=oTFmDDA44RDOidqjiT8+P76cR09Vmr7mXPAwAUfdyQ4=; b=JsQoRmr6+KwaHCkmbndyZBREXWiAfJkBiVntIwxrXkwDmR5KWzJj9NsoyOlPwBI6m/zHG1CgFeFwwyM2pCFul8NuvPU1y0N4TEKX0HWbwXl8KrBnFOo9TykzTQaWXDepNRKEksnkYevLLNCe2cefSGSbMw4k9TZBAg5d9mQNMec= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) by mx.zohomail.com with SMTPS id 1608126218636923.8598817949833; Wed, 16 Dec 2020 05:43:38 -0800 (PST) Received: by mail-wr1-f42.google.com with SMTP id t16so23227860wra.3 for ; Wed, 16 Dec 2020 05:43:37 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id i9sm3439945wrs.70.2020.12.16.05.43.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 05:43:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oTFmDDA44RDOidqjiT8+P76cR09Vmr7mXPAwAUfdyQ4=; b=HHYdF7ZSiuZBH+hnyv/y0XGCnZdGwfcGRe5Mk5foWBgg5j33VU+zVMrWNdREAno0eQ +9XNcHB0DW4QYW65QV9q3eUaqOrfzEL+XURBC7Tg/x+DcJ6131uec8HmPXFdlQZp9AvH j48XZfquwQVGoCtmxIbjqlqBkQxXr0H2yLKt2w5s0mrgqbXBk/jjPlVlyTTNpk4SQfNz wsgshU+qI1L4tqdJ+acF5BWwUpGkdQXxeRMdiCjsfaorAZWBBb9F4SwLEx/sQPNo8+yN mw7+cXHKyKOAG+WBMmtpsLgeU2/TZisYMxRFhTiTm+G3WXSaB9ocomcxt1LF7U2klkMV 8yrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=oTFmDDA44RDOidqjiT8+P76cR09Vmr7mXPAwAUfdyQ4=; b=WbPWBhyuQ6mN12eP601LQhHBEW+ncN+H1I4DDHufw2c4OYn66UNfh6ZhV3gTMpGpl8 UEt47nwJweD9wIAiSKrC+TV9JwWhuL0Wz8C0d9MnOx+Dr1hlCztPEdtIi4ZqP9S9z5qf PxGg5zhj9AjgNE/iMtkFzm723sCkv/aU2Lph2x/Z/6TqVBDFkTWd6RezYy9DM03La/qx KvGkQSHREuENhX7JKMifnAlCpcN1xdssqWuWvYaE7yoy5P3Irkpe6B79n/8kb9xnjMXc huJJP4rcnuqMu1BnWdmJpMPcjlM3g7/vFM0pJS+ufM9yhVtKSvt0PNIsMuO7Ycb8qhFk vJrA== X-Gm-Message-State: AOAM533iNvxBoYOEolZrJgfaXCoS2YqzWDo3SyLLo68DRn9aWRZStEFH tLmsJ+jFsnZjgfBVwsRLF5M= X-Google-Smtp-Source: ABdhPJzGcoql/OB58uD9Roli2Wm8Gt4YBB8U++4Tv1kzU4mk7bRCclMbDtczxSWItE17QBIRSd1u7A== X-Received: by 2002:a5d:4f90:: with SMTP id d16mr31800637wru.120.1608126216214; Wed, 16 Dec 2020 05:43:36 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Paul Burton , Richard Henderson , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 01/11] target/mips/mips-defs: Reorder CPU_MIPS5 definition Date: Wed, 16 Dec 2020 14:43:18 +0100 Message-Id: <20201216134328.851840-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216134328.851840-1-f4bug@amsat.org> References: <20201216134328.851840-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move CPU_MIPS5 after CPU_MIPS4 :) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jiaxun Yang --- target/mips/mips-defs.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 805034b8956..f4d76e562d1 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -70,13 +70,12 @@ #define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2) #define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3) #define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4) +#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) #define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX) #define CPU_R5900 (CPU_MIPS3 | INSN_R5900) #define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E) #define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI) =20 -#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) - /* MIPS Technologies "Release 1" */ #define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) #define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) --=20 2.26.2 From nobody Tue Nov 18 05:50:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) client-ip=209.85.221.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1608126223; cv=none; d=zohomail.com; s=zohoarc; b=MjXOpCzk1BZQfmChZyfB080VkMAvgSb87P8IS7VLfy8YjXOmddESKcD8US515VONQNzwjM9XL1yMkjWjsocDrDwQ4lmJl/NOl8DUsWjQTfFXZjfcD3sM2hnvjEpj8TaSe4wyPyje3Zt7NZ3FpM0ACudD+xVp1swhsn9wbjLyZng= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608126223; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OBt9eJBX3pTIBLp30XCH/Bjd/stHNhDGzJ5XaGYAJJU=; b=I7FbvAu5lRkArb/Cm/eUSId6ALXxpkn7JrjbdHnuv2aLkQ1s9la6dXBPvj/Vf3Ng99TyEClHUHlpwWcCji24pOVHsw/KETn6UVRN5CQyVVQU6j0s1swMOLOJbiyVsIPI8nGoYimQwazZylZ3hDBcHCwSd8ZAS/zE2sjn5wOz2Tk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) by mx.zohomail.com with SMTPS id 1608126223260645.1406586594799; Wed, 16 Dec 2020 05:43:43 -0800 (PST) Received: by mail-wr1-f54.google.com with SMTP id d13so4974923wrc.13 for ; Wed, 16 Dec 2020 05:43:42 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id o13sm2685057wmc.44.2020.12.16.05.43.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 05:43:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OBt9eJBX3pTIBLp30XCH/Bjd/stHNhDGzJ5XaGYAJJU=; b=t9MfVhMxMbWgQASEuCwaYR1S1dHxFdFpRmdQvdPlIvsdornJbuG7dMa4xSBeu7iqDB bpG3UFiJgLSERb0A5BnwXWnctQKWppNP6XHEZ+t0IoDGuWfaT7hvazakFWXmT0CTErrj rFQYdw2RG9uCipgQKZ9kb1zb/rpEBf+1nweqIFLSeb/71XB1ZtOvRa2apqeJUCQo3c52 6v3fqo2nV+w8Xx8Zyb5pI3WNm24joIuN79/Y9nE6Mz8U6MhN4KWtliyuKmyJWU9bqM/Y +M9lG26QoSorVqg/1jCo83vChZKxvGgCOsMyt6znYuuQb0tpy834X/o/hCO/2FIFmqZS 8AGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=OBt9eJBX3pTIBLp30XCH/Bjd/stHNhDGzJ5XaGYAJJU=; b=TSCkb2k2Af+zLY1G0EdA0bEZdNFUSXkCs1yhG9R8GihNstWEpO0dHq/yb73XfR3wUp xusoNcMkOd9qQm9UQ8RbR5Ug5FLm/QLCPL3L1ZwuiHGJIWnWpSUsHQ9Ox4gJG+aFP4gp sDxn6JaUOA+cVncLyZV2WqkLBE2LajFsr4AN+sqjweP643gZw851xH7hHbvWS8n0BIys +Vv9XXTvX9IsimsYQv7ngvM3KKrmB/FmFOIFEUCybPdXAtkI/0Ku2QDAhB0xnVClkPrs oPnbZWg4QR0UQgfgiRjszY3Txp4TKAnb6IO3CFleCOESkXNEDi1iqfJDvBI/rcf3A0OP aueg== X-Gm-Message-State: AOAM533k5VgW+BKD0qFXW3sHRMdxBvZzM466JZfDRrS8daJ0VVRgFlFx ollwS+8N29PdF29HZdCLO7U= X-Google-Smtp-Source: ABdhPJyFlaeC39Lw8FBllcb4uKna9cveR3MqU4YbpW33QC8ubtsim0bKbvynd1uC6G1w13jNmlpEOA== X-Received: by 2002:adf:9d49:: with SMTP id o9mr39344000wre.413.1608126220968; Wed, 16 Dec 2020 05:43:40 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Paul Burton , Richard Henderson , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 02/11] target/mips/mips-defs: Use ISA_MIPS3 for ISA_MIPS64 Date: Wed, 16 Dec 2020 14:43:19 +0100 Message-Id: <20201216134328.851840-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216134328.851840-1-f4bug@amsat.org> References: <20201216134328.851840-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) MIPS 64-bit ISA is introduced with MIPS3. No need for another bit/definition to check for 64-bit. Simplify CPU_MIPS64 definition as CPU_MIPS5 contains CPU_MIPS4 which contains CPU_MIPS3 which contains ISA_MIPS3. Suggested-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jiaxun Yang --- target/mips/mips-defs.h | 5 ++--- hw/mips/boston.c | 2 +- target/mips/translate.c | 10 +++++----- 3 files changed, 8 insertions(+), 9 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index f4d76e562d1..2756e72a9d6 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -19,12 +19,11 @@ */ #define ISA_MIPS1 0x0000000000000001ULL #define ISA_MIPS2 0x0000000000000002ULL -#define ISA_MIPS3 0x0000000000000004ULL +#define ISA_MIPS3 0x0000000000000004ULL /* 64-bit */ #define ISA_MIPS4 0x0000000000000008ULL #define ISA_MIPS5 0x0000000000000010ULL #define ISA_MIPS32 0x0000000000000020ULL #define ISA_MIPS32R2 0x0000000000000040ULL -#define ISA_MIPS64 0x0000000000000080ULL #define ISA_MIPS64R2 0x0000000000000100ULL #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS64R3 0x0000000000000400ULL @@ -78,7 +77,7 @@ =20 /* MIPS Technologies "Release 1" */ #define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) -#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) +#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32) =20 /* MIPS Technologies "Release 2" */ #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index c3b94c68e1b..f44f681fab5 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -463,7 +463,7 @@ static void boston_mach_init(MachineState *machine) exit(1); } =20 - is_64b =3D cpu_type_supports_isa(machine->cpu_type, ISA_MIPS64); + is_64b =3D cpu_type_supports_isa(machine->cpu_type, ISA_MIPS3); =20 object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS= ); object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type, diff --git a/target/mips/translate.c b/target/mips/translate.c index 15265485f76..8c0ecfa17e1 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -8538,7 +8538,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) const char *register_name =3D "invalid"; =20 if (sel !=3D 0) { - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS3); } =20 switch (reg) { @@ -9264,7 +9264,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) const char *register_name =3D "invalid"; =20 if (sel !=3D 0) { - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS3); } =20 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { @@ -14502,12 +14502,12 @@ static int decode_mips16_opc(CPUMIPSState *env, D= isasContext *ctx) break; #if defined(TARGET_MIPS64) case RR_RY_CNVT_ZEW: - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); tcg_gen_ext32u_tl(cpu_gpr[rx], cpu_gpr[rx]); break; case RR_RY_CNVT_SEW: - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]); break; @@ -27203,7 +27203,7 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) #if defined(TARGET_MIPS64) case OPC_DCLO: case OPC_DCLZ: - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); gen_cl(ctx, op1, rd, rs); break; --=20 2.26.2 From nobody Tue Nov 18 05:50:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) client-ip=209.85.221.45; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f45.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1608126227; cv=none; d=zohomail.com; s=zohoarc; b=PuehNdOS14qHbyjcag6h8pUDPcGtFGWASyWXVP7ciKmAc+zh5EXtyfDtBu3XPDHRzZRrhELL/rGsAyefk0AmenF0yOy5DuM1NuugPKhFVaflExA8YlV6EuC4t072F9UcesDnrZoYjqO0fWd77gUdgOkyIFDHZDEUweyfimmi398= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608126227; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+qkEnDMdHWRU31cSJg9p2IUmb01k7KNSi4LqckJbiYc=; b=eWW9vWc48mWs6qyZ3ek0Xl8Y9f+h5qsaAt6DHDZqs5wrPbAtUSbKH4wjJB0AyNsFHqgNpXM+7njbJxw34wDgGzRQbyCFhUdlnWgJbFuWd1ijSgem4i3OZYLSVDSDbsZugNyZhKq/Kpo0V0ZN1USV9gmExCvyv9Qca+RWHcnq8XM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) by mx.zohomail.com with SMTPS id 1608126227784875.4921641010503; Wed, 16 Dec 2020 05:43:47 -0800 (PST) Received: by mail-wr1-f45.google.com with SMTP id 91so23217539wrj.7 for ; Wed, 16 Dec 2020 05:43:46 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id h13sm3163733wrm.28.2020.12.16.05.43.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 05:43:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+qkEnDMdHWRU31cSJg9p2IUmb01k7KNSi4LqckJbiYc=; b=KMsq2FYO+4z+v/DnwOmTSLJu07PtTm7D8g6PEVlcA7WxzDRAw93IeeN+AUqDOJmqcA MXMfSj1VtkYvxPNOqBGJmoaAQe9BZe2gi6WFz93ARLxoV9lIXskAQ0F09r1MVj14zwps SRXGSE1sXGhfyd5RpWgn0DQJU7kp4cgm8PIhWYgIRVECh47cUuUj1vkLYf6RCTnRmv5U TGWzHRuSSwxnUI2HJ7n5fl+S636c//373wSzfDicz38T+HOZ5iqI13MKo3YdR8RZMdxK ArA4lARro+f9qWqbIA/H7I2Dosd+1I+AVBm33IT/YeyKxHqKBx+RZ+Q82rGLgl2e6e0D +xTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=+qkEnDMdHWRU31cSJg9p2IUmb01k7KNSi4LqckJbiYc=; b=Yvg8nKK9m6t3PFGav8yxtIzzjSwwMikPokG3xmxR4ecqyQoeQJ5FXrJzqZcetCYRup Jw8jYR+MpS16l01+shNP6Y1q0HpQqxqCR9/Y2nKJAphga6F0g51WD0yzyVjGZ3xuR+d4 p0aIzO3uZUfWAelKXwHCvitW40rrxdwozZFk9ZQ7OR29rFOnxqEJvnSrEkY/1784GgGD 8DA+5fcVt/72RFO4bgMb3TXwx8XIPYT+qK6P62NTwo+A/PUYqiPykb3QB/7uvIcJu3BF e1yzjRrI5oC3aZ5D5YpKh1tGH3zT2861QTWUL5YPvk5NY8Lx1E+2cspseH9yxKpt9FYk ZMRg== X-Gm-Message-State: AOAM533S3FNN/Rq8fV5dfydlUUV9BeM80YowMupqOABUbWZ+kmOsKN7V dUR1TmPdvjhoLO91ggh+1Ka806uO+3I= X-Google-Smtp-Source: ABdhPJxcBJU9P/OhWpbSiiegkLCRBGV8w1zn5WCmA94jBL0JJyrp/jiJhXILv1ZqIymtjw7n9lc1zA== X-Received: by 2002:adf:fd05:: with SMTP id e5mr38919269wrr.225.1608126225781; Wed, 16 Dec 2020 05:43:45 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Paul Burton , Richard Henderson , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 03/11] target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2 Date: Wed, 16 Dec 2020 14:43:20 +0100 Message-Id: <20201216134328.851840-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216134328.851840-1-f4bug@amsat.org> References: <20201216134328.851840-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Use the single ISA_MIPS32R2 definition to check if the Release 2 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R2 in few commits. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/mips-defs.h | 3 +-- linux-user/mips/cpu_loop.c | 1 - target/mips/translate.c | 4 ++-- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 2756e72a9d6..9cfa4c346bf 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -24,7 +24,6 @@ #define ISA_MIPS5 0x0000000000000010ULL #define ISA_MIPS32 0x0000000000000020ULL #define ISA_MIPS32R2 0x0000000000000040ULL -#define ISA_MIPS64R2 0x0000000000000100ULL #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS64R3 0x0000000000000400ULL #define ISA_MIPS32R5 0x0000000000000800ULL @@ -81,7 +80,7 @@ =20 /* MIPS Technologies "Release 2" */ #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) -#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) +#define CPU_MIPS64R2 (CPU_MIPS64 | ISA_MIPS32R2) =20 /* MIPS Technologies "Release 3" */ #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index b58dbeb83d1..a2aa8167210 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -386,7 +386,6 @@ void target_cpu_copy_regs(CPUArchState *env, struct tar= get_pt_regs *regs) prog_req.fre &=3D interp_req.fre; =20 bool cpu_has_mips_r2_r6 =3D env->insn_flags & ISA_MIPS32R2 || - env->insn_flags & ISA_MIPS64R2 || env->insn_flags & ISA_MIPS32R6 || env->insn_flags & ISA_MIPS64R6; =20 diff --git a/target/mips/translate.c b/target/mips/translate.c index 8c0ecfa17e1..0923dfdf451 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28212,7 +28212,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) case OPC_DINSM: case OPC_DINSU: case OPC_DINS: - check_insn(ctx, ISA_MIPS64R2); + check_insn(ctx, ISA_MIPS32R2); check_mips_64(ctx); gen_bitops(ctx, op1, rt, rs, sa, rd); break; @@ -28232,7 +28232,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) decode_opc_special3_r6(env, ctx); break; default: - check_insn(ctx, ISA_MIPS64R2); + check_insn(ctx, ISA_MIPS32R2); check_mips_64(ctx); op2 =3D MASK_DBSHFL(ctx->opcode); gen_bshfl(ctx, op2, rt, rd); --=20 2.26.2 From nobody Tue Nov 18 05:50:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) client-ip=209.85.221.47; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f47.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1608126232; cv=none; d=zohomail.com; s=zohoarc; b=YaB7w4b8e1YL5OcyCFZMBsqcI52ZhCf8n+fJkJTHk9rU4Vtik99zz7QfWHezJuuEZkzYLy3NE/sHXE7kfO2ERPYlafPWzclzQAAd2uSzRMcGyPGp0HHopwm6BM4GSJaTBFxs7As3sZGvPFuE+U3YehZ/FoewR2SzmUm6E6B8+zA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608126232; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rWhkzIf/6CTljorBq+mR8pkgCAWYYKs0Obfa0b4MU1w=; b=MQsC3sV+cz0hvUdH3V0eHVnipWA9FvjasyBz3xqWrp2z9EFqFi7Xy0hivkQX3w8Oa8sQyGLuq+wnTNgEZajXeakwN767C/6wP4Dkz94+hLUWRNw9WlTMcFq7HEZ54SByHScvV8urR2KfT59bkrd5ajAG8O8y+och312gIINYX6Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) by mx.zohomail.com with SMTPS id 1608126232925683.5320038481115; Wed, 16 Dec 2020 05:43:52 -0800 (PST) Received: by mail-wr1-f47.google.com with SMTP id d13so4975413wrc.13 for ; Wed, 16 Dec 2020 05:43:52 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id u85sm2907049wmu.43.2020.12.16.05.43.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 05:43:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rWhkzIf/6CTljorBq+mR8pkgCAWYYKs0Obfa0b4MU1w=; b=qIiZnyWJvffP3c9qPjnrRxkSg9QdQIPYdVRRt1DmCma7hk7ogrzoTrti0hTuhKUqJy ZzBaKs72EDIM0J045DgO9khOHzaC/tyhLXNtcFNOEHb7r2/nPLAVYgXZPbO2Bdm6z7lE WfAckwL60qUb83QSvAnokBJ9xQIPeS3RnkRVQrTKQ4GsaAG6wuEnKNGU0Fe2Xgz9YGPV 6dQCDiAAL79r8qwH7OAKfrC5BzGjCb9L+XBN9BDvCBaK9vb/E2r9pd/dS4BlnAAp9Up9 JDwYerMoLvCLxGgolRA8GUcIipho+OzzmYuMTmAiAjjdrRD1tmO/JfSZcnIV6MK4KnOi 71QA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=rWhkzIf/6CTljorBq+mR8pkgCAWYYKs0Obfa0b4MU1w=; b=kkP0vT9D/JFcpofpo7YEDmmB5mnROb7eXfaDn45W9+E4IVYMFUYlVR9rV45C/2qGXl MOMm8TJAM+safQA8FhL1ETbeDEKy+8JfMCam9yhIftriXygsnid1Lcilk7z0AMw53WKM kX/XigA0AGPCSsEjlhGoer72e0ZjX1riehLLNOpx03V2BXvtpcK9iy+Ve9m79cVc4zeK X+LA2AVufED3qN9nZpE7HMhsabqHybWpqn6uJ1J2/PBioNHNROeK3AlJ2BsEPCGhIaQJ /V/wETDEtsaj+RLA7XGEBIr4bm/7wJ7h3aDyQNQbZT3he82dIVWveTEHqKdK5xyASwz3 AkdQ== X-Gm-Message-State: AOAM531KCNSHqaPHhlABHflwhpaUTgWUZPWx1kYLxO4fc8Oy4rSvyG05 tlx2IxbqkLMvSbbCdKeTeEo= X-Google-Smtp-Source: ABdhPJw4lh8u8K5nhHA4FpZLZX+I3LxbKr3v1SP3XyMUiGhS+ebkajtoHHJ1gky2nV0zxYZdvm6Xiw== X-Received: by 2002:a5d:62c8:: with SMTP id o8mr39289508wrv.51.1608126230995; Wed, 16 Dec 2020 05:43:50 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Paul Burton , Richard Henderson , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 04/11] target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3 Date: Wed, 16 Dec 2020 14:43:21 +0100 Message-Id: <20201216134328.851840-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216134328.851840-1-f4bug@amsat.org> References: <20201216134328.851840-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Use the single ISA_MIPS32R3 definition to check if the Release 3 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R3 in few commits. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/mips-defs.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 9cfa4c346bf..0d906ca64b3 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -25,7 +25,6 @@ #define ISA_MIPS32 0x0000000000000020ULL #define ISA_MIPS32R2 0x0000000000000040ULL #define ISA_MIPS32R3 0x0000000000000200ULL -#define ISA_MIPS64R3 0x0000000000000400ULL #define ISA_MIPS32R5 0x0000000000000800ULL #define ISA_MIPS64R5 0x0000000000001000ULL #define ISA_MIPS32R6 0x0000000000002000ULL @@ -84,7 +83,7 @@ =20 /* MIPS Technologies "Release 3" */ #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) -#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3) +#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3) =20 /* MIPS Technologies "Release 5" */ #define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5) --=20 2.26.2 From nobody Tue Nov 18 05:50:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) client-ip=209.85.221.47; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f47.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1608126240; cv=none; d=zohomail.com; s=zohoarc; b=aDCMNIJcpyUHBNc+eh35c1pCqC96R1cxMljOEbgoHf6ksWOEdRQqhWYCuX6wz1+xjzPVPA2iivsOvOS7bGVU/Ha0Lf0qygODC/+GcGLMPFchzHrWPyvV98De5HaXURA5s6qyMtb7J4CSp6/XiIRPzlRhrXotHWs8yyGq2V6Zvwg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608126240; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ygBBalz5UyiuOJifXXOKc1oAnXdEKjBaVDLqLiZUgIE=; b=jpjbTKitfFwJv2EGXm9v/VeaV2u13jVjlQHt53duDWpdcpEKiUuAPvgYL8wqocKVOf0xk+cJEbs+ZYmvDbA9WjYxjf/FSZ/3v4K1WKQvV/MdHoIV4Z9NFp9rul9B9bcghhVblSdaEXFoTuKdQp09qK2lJphPwMWhACjqQ3JzARg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) by mx.zohomail.com with SMTPS id 1608126240049632.1779041396055; Wed, 16 Dec 2020 05:44:00 -0800 (PST) Received: by mail-wr1-f47.google.com with SMTP id a12so23195012wrv.8 for ; Wed, 16 Dec 2020 05:43:57 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id a13sm3089593wrt.96.2020.12.16.05.43.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 05:43:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ygBBalz5UyiuOJifXXOKc1oAnXdEKjBaVDLqLiZUgIE=; b=C+QmQvZ1pgM1LQ41KpkchN3AidK5oN+fBo28fExrzvExSbgAx4Kv5iMgZilcFa9Nf8 HGV3+8UApZ7nST4D2/T96SfHaNhjbmGp83kPX8EnDEAM3WEDUCDcVkzAu5wMCJF0UBmq PlzBHPh/HulLAksM9cXqABy5g2x8CTLUI3fGDG+n1V0R5E4/ybbIoVmSOH1VNxS0suHb RXCXBJ3CkjkFCbguUPELQ05JsTzJZ+OyJRrLJcLfHHc3XU/ovRTu6aPbxbcqoF9nBmgc YlW1lRKp4MPzK8A1gwIFWGe2ceHwAS3QOQlMb5AsqI5hZRlViyfxvBsCChOHl1ksxBxu Vjnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ygBBalz5UyiuOJifXXOKc1oAnXdEKjBaVDLqLiZUgIE=; b=qv7S04itRrbn+t27Mns91V8d7dHWtuP0lAWVuxCsv0MOEXwZAPl4RKKNqCiZVZ8zZN buVRX3h3Nl7hmVT+c4WDjUcJHDREgKocKRnEs85ve9tbMbuP75/dwEC+u4d1FnZaCEwW g1g0pjVceyVqdrYCGqXvVkehPsq1yno5eiDk/MUIl1SSFVnhdTtraXrgd7giZhG6jXb3 nfGIjUg5bpfz88frgFu8P4A3IuWhEoGh4aFhFCL1MddRz2wcbunIqN1100tSXg037N5j cRJwMLyXDKgYOao36TiSsnNJqksMXGQw0MKPdBWs+Aw/QvDqBJed8CCfX0UG489GXwcy lM5Q== X-Gm-Message-State: AOAM530zwgzZUr6CTOCZYI0bMCTzFB9uiJc6C3yyNBa0ORiQGtWnx9+3 whtvjAouNTW2RYRocn7Nq/o= X-Google-Smtp-Source: ABdhPJwgr5y9DPyWpYjHfAB5VZap1PbMcMSeCm/PYBwVhrafvovIo08YjvGWC1g27rYMqIoLXjCULQ== X-Received: by 2002:a5d:68c9:: with SMTP id p9mr38251711wrw.139.1608126235845; Wed, 16 Dec 2020 05:43:55 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Paul Burton , Richard Henderson , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 05/11] target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5 Date: Wed, 16 Dec 2020 14:43:22 +0100 Message-Id: <20201216134328.851840-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216134328.851840-1-f4bug@amsat.org> References: <20201216134328.851840-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Use the single ISA_MIPS32R5 definition to check if the Release 5 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R5 in few commits. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/mips-defs.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 0d906ca64b3..ea9dcc7c98e 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -26,7 +26,6 @@ #define ISA_MIPS32R2 0x0000000000000040ULL #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS32R5 0x0000000000000800ULL -#define ISA_MIPS64R5 0x0000000000001000ULL #define ISA_MIPS32R6 0x0000000000002000ULL #define ISA_MIPS64R6 0x0000000000004000ULL #define ISA_NANOMIPS32 0x0000000000008000ULL @@ -87,7 +86,7 @@ =20 /* MIPS Technologies "Release 5" */ #define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5) -#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5) +#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5) =20 /* MIPS Technologies "Release 6" */ #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) --=20 2.26.2 From nobody Tue Nov 18 05:50:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) client-ip=209.85.128.46; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f46.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1608126244; cv=none; d=zohomail.com; s=zohoarc; b=IN8iVIYH1CHmoruIr7vQhGAkjbm8uVNgZpTR6JVgc2425VzEIxk+8MJ8305pShx8PJEfrArArEx/ZwwgNuJrADeaYs3pcIH1F+SSFz77tqHOlLJrBfyvVxUbp8Syyow9IodZjKHcKEjpServf+tsA/jY3RbjCUiFeFkj78xuII0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608126244; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FQTagxeMSRlTpSXXXsWsvusOqbZsJsc4nubvf9MNEgI=; b=lcqP4BtHo5/73VAsQMr8ykDsH1EaOhG2PSXBe+huapaB/lK5HCEX2jbEDUhQ6KAyX6GnI7/jVw+q+5L/gbePRoCNUy5CZZiYF/rrG4saQ0PZNhb/kl3wMhkR161KBnTXQ9oieBrxlPbesppELkbL0zZP19w8rOcKq2kJvwdgIVA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) by mx.zohomail.com with SMTPS id 160812624399733.90156945620299; Wed, 16 Dec 2020 05:44:03 -0800 (PST) Received: by mail-wm1-f46.google.com with SMTP id 190so2405571wmz.0 for ; Wed, 16 Dec 2020 05:44:02 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id j9sm3259274wrm.14.2020.12.16.05.43.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 05:44:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FQTagxeMSRlTpSXXXsWsvusOqbZsJsc4nubvf9MNEgI=; b=WuwhmH4a+OHsQ+NED0ibcxT3V5VATle50JDdk3eyDzpeSABX25TQ4o4Zq44GJOHqhi zV5UlHHLOWrQbVDjOc5jG3Y7kbf6InA8zG+W81KCjvD74U1xU9vnc7ftJiI+aouSovZa dpjWK1iKcVDpNGpxl36ZL/uEM1KqImgPQFjVUwG/vqU+Q3ECZBaSews0SvxC+0GcmJdB 8VzuZnxkSp9pt1FMgkfG09uQwypbR4DD8kiGG6u4ciBADBXfIY8xAunP0c69FqOMEMtU U/lxs1+UDaIUbw3UrEcok+8s2xdJypEddxA478cBKkLy/8wlehvTpTNpIfS1e9n4NVgQ fRUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=FQTagxeMSRlTpSXXXsWsvusOqbZsJsc4nubvf9MNEgI=; b=r6XVzT52mBum8+9zmBN0MpJzgNI/a0weGzxJfIo3bFt5XN69wwQnyXrOAnVsGwGPej 5WnjE5onIvLSNuVBWKBNY2ci8D24wUyTL8zUegiXa+MIWvPJH7V6x8vF7SQ+R+uZtL/G LQQbW+cXu0sz4jVPtHWFNne0/xKQ4clAedaC2pTnb31MVNNmwTcPkNvhn2O47RS0v9FP VWO60XX8EmN9QdmrGHYmdzjj4EVx275NZGyr5M+I1hwAYgvDJ4ojpE4hHVaGnINKVgcx 8HkNWSw/S0NSj2S1cC811g/kc6ZAb7IHs3+dA4H4Ep7zfz8dHpnaY2Ju/hFYj3ZOpFgo 83AA== X-Gm-Message-State: AOAM531lhS6/AneasALT0CFNEerleszluzp1BD7mrMSroL12SCxuXx0E 8UB0LCVCUvEEwCpXamuUqhg= X-Google-Smtp-Source: ABdhPJwkhB1AY8o4bOcc8lCpWjwKd8grKudEri8lhwbb+yC/vTPFO+ZOiA1i6Zzr9+tbnExPPGe/3A== X-Received: by 2002:a1c:9a57:: with SMTP id c84mr3307790wme.183.1608126240746; Wed, 16 Dec 2020 05:44:00 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Paul Burton , Richard Henderson , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 06/11] target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6 Date: Wed, 16 Dec 2020 14:43:23 +0100 Message-Id: <20201216134328.851840-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216134328.851840-1-f4bug@amsat.org> References: <20201216134328.851840-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Use the single ISA_MIPS32R6 definition to check if the Release 6 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R6 in few commits. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 2 +- target/mips/mips-defs.h | 3 +-- linux-user/elfload.c | 2 +- linux-user/mips/cpu_loop.c | 3 +-- target/mips/tlb_helper.c | 6 +++--- target/mips/translate.c | 2 +- 6 files changed, 8 insertions(+), 10 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 76269cfc7bb..97899dbd3c8 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -308,7 +308,7 @@ static inline void compute_hflags(CPUMIPSState *env) } else if (((env->hflags & MIPS_HFLAG_KSU) =3D=3D MIPS_HFLAG_UM) && !(env->CP0_Status & (1 << CP0St_UX))) { env->hflags |=3D MIPS_HFLAG_AWRAP; - } else if (env->insn_flags & ISA_MIPS64R6) { + } else if (env->insn_flags & ISA_MIPS32R6) { /* Address wrapping for Supervisor and Kernel is specified in R6 */ if ((((env->hflags & MIPS_HFLAG_KSU) =3D=3D MIPS_HFLAG_SM) && !(env->CP0_Status & (1 << CP0St_SX))) || diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index ea9dcc7c98e..df2ffae5718 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -27,7 +27,6 @@ #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS32R5 0x0000000000000800ULL #define ISA_MIPS32R6 0x0000000000002000ULL -#define ISA_MIPS64R6 0x0000000000004000ULL #define ISA_NANOMIPS32 0x0000000000008000ULL /* * bits 24-39: MIPS ASEs @@ -90,7 +89,7 @@ =20 /* MIPS Technologies "Release 6" */ #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) -#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6) +#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6) =20 /* Wave Computing: "nanoMIPS" */ #define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 0b02a926025..e875a5387cc 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -997,7 +997,7 @@ static uint32_t get_elf_hwcap(void) #define GET_FEATURE(flag, hwcap) \ do { if (cpu->env.insn_flags & (flag)) { hwcaps |=3D hwcap; } } while = (0) =20 - GET_FEATURE(ISA_MIPS32R6 | ISA_MIPS64R6, HWCAP_MIPS_R6); + GET_FEATURE(ISA_MIPS32R6, HWCAP_MIPS_R6); GET_FEATURE(ASE_MSA, HWCAP_MIPS_MSA); =20 #undef GET_FEATURE diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index a2aa8167210..1e4acf3d6e3 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -386,8 +386,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct tar= get_pt_regs *regs) prog_req.fre &=3D interp_req.fre; =20 bool cpu_has_mips_r2_r6 =3D env->insn_flags & ISA_MIPS32R2 || - env->insn_flags & ISA_MIPS32R6 || - env->insn_flags & ISA_MIPS64R6; + env->insn_flags & ISA_MIPS32R6; =20 if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) { env->CP0_Config5 |=3D (1 << CP0C5_FRE); diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c index 94a482e3dbe..68d766f90a3 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tlb_helper.c @@ -1025,7 +1025,7 @@ void mips_cpu_do_interrupt(CPUState *cs) enter_debug_mode: if (env->insn_flags & ISA_MIPS3) { env->hflags |=3D MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS64R6) || + if (!(env->insn_flags & ISA_MIPS32R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &=3D ~MIPS_HFLAG_AWRAP; } @@ -1054,7 +1054,7 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Status |=3D (1 << CP0St_ERL) | (1 << CP0St_BEV); if (env->insn_flags & ISA_MIPS3) { env->hflags |=3D MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS64R6) || + if (!(env->insn_flags & ISA_MIPS32R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &=3D ~MIPS_HFLAG_AWRAP; } @@ -1240,7 +1240,7 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Status |=3D (1 << CP0St_EXL); if (env->insn_flags & ISA_MIPS3) { env->hflags |=3D MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS64R6) || + if (!(env->insn_flags & ISA_MIPS32R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &=3D ~MIPS_HFLAG_AWRAP; } diff --git a/target/mips/translate.c b/target/mips/translate.c index 0923dfdf451..38fbc55ff1e 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -29078,7 +29078,7 @@ static void mips_tr_init_disas_context(DisasContext= Base *dcbase, CPUState *cs) #else ctx->mem_idx =3D hflags_mmu_index(ctx->hflags); #endif - ctx->default_tcg_memop_mask =3D (ctx->insn_flags & (ISA_MIPS32R6 | ISA= _MIPS64R6 | + ctx->default_tcg_memop_mask =3D (ctx->insn_flags & (ISA_MIPS32R6 | INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN; =20 LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx, --=20 2.26.2 From nobody Tue Nov 18 05:50:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) client-ip=209.85.221.52; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f52.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1608126247; cv=none; d=zohomail.com; s=zohoarc; b=a+TvZ/Wz1eD8P0nAfEb9XfNG0bCBmxzI1wPGhBgKNYhLY86OMG/eTL+eWcO+0idaiHNm+Y2ZHtGMjKJVA+uS33heIh0xaIINHiPI4uNXl0CEDvRflOrY057vrm0h7okm8JHEzz3IlSjuAfeP4DZqIYa9kq02FVOsm3u9X95aSww= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608126247; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pAXR0ap5QyHsOud3cHZbUyk7Vfk3//npBQDgukBmgis=; b=E8nxWacAhYvNQ2ASY40JjT6iXiqCBrFS9WXjrrc8sKIuXPpsUOUTD7mB0vQL+deXTCuislwd78DVoU862Q02dJ6IqbDsc/NsnyGmiGEl4B3ylQV2gIO33+BMHn4GDMzIDw5WcY0NGRUfHSi/yEKJyDqcEwbIhiq5CpIMmgTNFF4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) by mx.zohomail.com with SMTPS id 1608126247700121.1739577772405; Wed, 16 Dec 2020 05:44:07 -0800 (PST) Received: by mail-wr1-f52.google.com with SMTP id d13so4976135wrc.13 for ; Wed, 16 Dec 2020 05:44:06 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id h20sm3486906wrb.21.2020.12.16.05.44.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 05:44:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pAXR0ap5QyHsOud3cHZbUyk7Vfk3//npBQDgukBmgis=; b=ZJuXm0nURzPSzaK1MkWtpPrMhIS5wI1vYCr00TdE7++oWeo/LJ6npLR+YXcCvK7030 lxmEVtmxJYvog7fKQF1cAjOImahHD+oQYJPE52o582C3tKO180P4AhDJ4x5VVmT9kIdZ nEh86CQ+63aKSJU6+f/lyKpP1hawOHgkRBTgUVLO88pqpyw49Hmi/THOx+Dv9SQGtHVM WR1EEU7eRYGfVCRhbNozU4UWpztGogEVXORxYedQV7Sts3CjKSipP1q1zrtOCbECYNEj rAyNdrnPm/mB0rmEi1GXufkZw+WZZnNQiZjuZajHGb9R6eO86htdW2UKAppwzhen5HYj TIBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=pAXR0ap5QyHsOud3cHZbUyk7Vfk3//npBQDgukBmgis=; b=jsYqg9+EHQCDL8Orrhjhu+nD8ChB5OZiUkCBA5bUx7pso4sHV7rawqnZ3CH+ceoblH vgkeH4fOgssnolI6/BgujIiOOZE2A1nIYpiaK8WxzfCXZ3mv/CUFAgfN7OQED92M3/Ry ChI7/F6sRXZx3TPUK0iA9/KwlXAmcvvcKWxVNaB8G5r7+yYNdzO8ECkNdK13afzEARVF cCY/nIPNPny4x+YX7iJkUgZ9e23pVY/WFZqJZA58+Bn+R54LUfRima52igKJzmLoJb/Y YLrATJz+vhL3aOzDdltkR6WgZGwuuzADD2RRaXOrpuvCGixltmXQmfQgUb+FpteUY63n 6ieA== X-Gm-Message-State: AOAM531zDOrW+SzKnHDZFa75wLSRYwt/iOAbqq9K9CP46LwAgtSJeHJQ b8g4Fnz+6aG+H5kd/hjamgc= X-Google-Smtp-Source: ABdhPJyceNeSFEujfUB2VFtTJkbuWXEjtXJE0kbo/lA6XxsD93Y3tFgtC6szOjJe8fg7FoaWKoC4dQ== X-Received: by 2002:adf:cd8f:: with SMTP id q15mr37261367wrj.79.1608126245672; Wed, 16 Dec 2020 05:44:05 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Paul Burton , Richard Henderson , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 07/11] target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1 Date: Wed, 16 Dec 2020 14:43:24 +0100 Message-Id: <20201216134328.851840-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216134328.851840-1-f4bug@amsat.org> References: <20201216134328.851840-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The MIPS ISA release '1' is common to 32/64-bit CPUs. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 2 +- target/mips/mips-defs.h | 4 ++-- target/mips/translate.c | 44 ++++++++++++++++++++--------------------- 3 files changed, 25 insertions(+), 25 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 97899dbd3c8..f71c617a1fe 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -365,7 +365,7 @@ static inline void compute_hflags(CPUMIPSState *env) if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { env->hflags |=3D MIPS_HFLAG_COP1X; } - } else if (env->insn_flags & ISA_MIPS32) { + } else if (env->insn_flags & ISA_MIPS_R1) { if (env->hflags & MIPS_HFLAG_64) { env->hflags |=3D MIPS_HFLAG_COP1X; } diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index df2ffae5718..31c02cc20ef 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -22,7 +22,7 @@ #define ISA_MIPS3 0x0000000000000004ULL /* 64-bit */ #define ISA_MIPS4 0x0000000000000008ULL #define ISA_MIPS5 0x0000000000000010ULL -#define ISA_MIPS32 0x0000000000000020ULL +#define ISA_MIPS_R1 0x0000000000000020ULL #define ISA_MIPS32R2 0x0000000000000040ULL #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS32R5 0x0000000000000800ULL @@ -72,7 +72,7 @@ #define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI) =20 /* MIPS Technologies "Release 1" */ -#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) +#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS_R1) #define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32) =20 /* MIPS Technologies "Release 2" */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 38fbc55ff1e..d4e672ebca6 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7006,7 +7006,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) const char *register_name =3D "invalid"; =20 if (sel !=3D 0) { - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); } =20 switch (reg) { @@ -7774,7 +7774,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) const char *register_name =3D "invalid"; =20 if (sel !=3D 0) { - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); } =20 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { @@ -10601,7 +10601,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext= *ctx, uint32_t opc, break; case OPC_DERET: opn =3D "deret"; - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { goto die; @@ -10616,7 +10616,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext= *ctx, uint32_t opc, break; case OPC_WAIT: opn =3D "wait"; - check_insn(ctx, ISA_MIPS3 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1); if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { goto die; @@ -10651,7 +10651,7 @@ static void gen_compute_branch1(DisasContext *ctx, = uint32_t op, } =20 if (cc !=3D 0) { - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1); } =20 btarget =3D ctx->base.pc_next + 4 + offset; @@ -14020,7 +14020,7 @@ static int decode_extended_mips16_opc(CPUMIPSState = *env, DisasContext *ctx) gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm); break; case I8_SVRS: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); { int xsregs =3D (ctx->opcode >> 24) & 0x7; int aregs =3D (ctx->opcode >> 16) & 0xf; @@ -14270,7 +14270,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) ((int8_t)ctx->opcode) << 3); break; case I8_SVRS: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); { int do_ra =3D ctx->opcode & (1 << 6); int do_s0 =3D ctx->opcode & (1 << 5); @@ -14414,7 +14414,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) int ra =3D (ctx->opcode >> 5) & 0x1; =20 if (nd) { - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); } =20 if (link) { @@ -14435,7 +14435,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) * XXX: not clear which exception should be raised * when in debug mode... */ - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); generate_exception_end(ctx, EXCP_DBp); } break; @@ -14486,7 +14486,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) gen_HILO(ctx, OPC_MFHI, 0, rx); break; case RR_CNVT: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); switch (cnvt_op) { case RR_RY_CNVT_ZEB: tcg_gen_ext8u_tl(cpu_gpr[rx], cpu_gpr[rx]); @@ -15426,7 +15426,7 @@ static void gen_pool16c_insn(DisasContext *ctx) * XXX: not clear which exception should be raised * when in debug mode... */ - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); generate_exception_end(ctx, EXCP_DBp); } break; @@ -15770,7 +15770,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) case CLZ: mips32_op =3D OPC_CLZ; do_cl: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); gen_cl(ctx, mips32_op, rt, rs); break; case RDHWR: @@ -15797,7 +15797,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) mips32_op =3D OPC_DIVU; goto do_div; do_div: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); gen_muldiv(ctx, mips32_op, 0, rs, rt); break; case MADD: @@ -15816,7 +15816,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) check_insn_opc_removed(ctx, ISA_MIPS32R6); mips32_op =3D OPC_MSUBU; do_mul: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); gen_muldiv(ctx, mips32_op, 0, rs, rt); break; default: @@ -15964,7 +15964,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) if (is_uhi(extract32(ctx->opcode, 16, 10))) { gen_helper_do_semihosting(cpu_env); } else { - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); if (ctx->hflags & MIPS_HFLAG_SBRI) { gen_reserved_instruction(ctx); } else { @@ -24482,7 +24482,7 @@ static void decode_opc_special_legacy(CPUMIPSState = *env, DisasContext *ctx) switch (op1) { case OPC_MOVN: /* Conditional move */ case OPC_MOVZ: - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 | + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 | INSN_LOONGSON2E | INSN_LOONGSON2F); gen_cond_move(ctx, op1, rd, rs, rt); break; @@ -24495,7 +24495,7 @@ static void decode_opc_special_legacy(CPUMIPSState = *env, DisasContext *ctx) gen_HILO(ctx, op1, rd & 3, rs); break; case OPC_MOVCI: - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1); if (env->CP0_Config1 & (1 << CP0C1_FP)) { check_cp1_enabled(ctx); gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7, @@ -27168,7 +27168,7 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) case OPC_MADDU: case OPC_MSUB: case OPC_MSUBU: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); gen_muldiv(ctx, op1, rd & 3, rs, rt); break; case OPC_MUL: @@ -27185,7 +27185,7 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) break; case OPC_CLO: case OPC_CLZ: - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); gen_cl(ctx, op1, rd, rs); break; case OPC_SDBBP: @@ -27196,7 +27196,7 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) * XXX: not clear which exception should be raised * when in debug mode... */ - check_insn(ctx, ISA_MIPS32); + check_insn(ctx, ISA_MIPS_R1); generate_exception_end(ctx, EXCP_DBp); } break; @@ -28643,7 +28643,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) case OPC_CACHE: check_insn_opc_removed(ctx, ISA_MIPS32R6); check_cp0_enabled(ctx); - check_insn(ctx, ISA_MIPS3 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1); if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { gen_cache_operation(ctx, rt, rs, imm); } @@ -28654,7 +28654,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) if (ctx->insn_flags & INSN_R5900) { /* Treat as NOP. */ } else { - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1); /* Treat as NOP. */ } break; --=20 2.26.2 From nobody Tue Nov 18 05:50:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) client-ip=209.85.221.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1608126254; cv=none; d=zohomail.com; s=zohoarc; b=Hsc7ntH4X/TaZpqyytBHnvjkCg0gmNLyxLKpVa0NhcGKDI71/tkDAEMuISf8KlcBAqDBGa0tmBAnhc0LjQYqqS1gsCAZAfKsXKlwllspYttwgmPb1IucQnCGbuuC3oLk2GMURvhe7QG0Ds38t+SFoc4YUM1piYr29yl6DzTwEio= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608126254; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=IGnb8JsbBi7GNUwj6XJUK2pRpJXJTjGcg3EqoILGuD0=; b=Wzx9rdjjpf/CZV4RCDlTdYw5eSdyLXRq/l4fJrQKQqrBw6rYI27cfVgR0MkwN7e4yHJ62DsjWMdSFL2w7RdP4c03z8/UPplFHjCs0/3ItQvi9HdXuwmPHdosMdk0nwfdxXf506O/W2L93MNOz3loVxw4dcYryRk3pnGepPHemVw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) by mx.zohomail.com with SMTPS id 1608126253836646.1905021367503; Wed, 16 Dec 2020 05:44:13 -0800 (PST) Received: by mail-wr1-f48.google.com with SMTP id r3so23257589wrt.2 for ; Wed, 16 Dec 2020 05:44:12 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id s8sm2952946wrn.33.2020.12.16.05.44.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 05:44:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IGnb8JsbBi7GNUwj6XJUK2pRpJXJTjGcg3EqoILGuD0=; b=per56/4bQ9sIeikw2wfBeOT2yWFK9Cz8EN8WEhMRSkKTJ01+dOaAkXXRcv3j2lXeLR 7ble7KKD6c2PWlm8zhlPcvH1LnDoK8CP8h62VgAkMwRZuOP/FTT+xxuQIs2JGxEN7MVz zgXcW/CvuECL4QEiEgJBRAX3tYUFjiiGnvgTyUKqihUHjsUawpcndBvKekka45K0OOGo GsNCGARR4qz+dee06ajrHEx2sgrBB353mgILH0eNVi6XQ+aM0VAm0N3D7xeHsP3jZlTM cfntBhiHPYKo8MQr52QP2jiYRvl29chDtUEum5QJXjLroCExLPc/7KQvvU3+HUTpN4BY XV9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=IGnb8JsbBi7GNUwj6XJUK2pRpJXJTjGcg3EqoILGuD0=; b=CL/DiFMSElsQCJugHUVZuybVTEnRtV0JhXcu8iali5x/RDddgPol83RYdQo5cZjEjI /Cc7OCXcUeg3+Wpfz13a39RLKNwjtuunTHc198xFy8sFV071TJXVCr5tlnnePCC90g5A ZbXLH1wMy9vZvC/ls2fBGM35bRU/O3Sq0QzKkP1mydYcd4seoZd5piPc17dAv185lfdu 0alCMSdbnj26er0iT7ZTZ1stmdF88+mPra2Jn5zWdYSSOSC3WYWbdcQWM82ooR1qiKaK ScW+3opd4wiUNxREf/28Apnm12ypmMSl6EfpsQDFwClcbEK0NXrh5rkvxieyqOvT3YS6 LotA== X-Gm-Message-State: AOAM533SPUKAGFMjjlMtysvpoUB/DxoP+itbSb1KjFdXS/gSqM2Ycy8v SVUxMzRXcMqylbZIHCLNej8= X-Google-Smtp-Source: ABdhPJyq6zh2Fdh1NMDBeKs+jVF6vH2mdxsa2csSU1wSZ9g9MAvLEB9OjAFWt5ZnwiYMurvtSgB6UQ== X-Received: by 2002:a5d:650f:: with SMTP id x15mr38570505wru.332.1608126250703; Wed, 16 Dec 2020 05:44:10 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Paul Burton , Richard Henderson , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 08/11] target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2 Date: Wed, 16 Dec 2020 14:43:25 +0100 Message-Id: <20201216134328.851840-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216134328.851840-1-f4bug@amsat.org> References: <20201216134328.851840-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The MIPS ISA release 2 is common to 32/64-bit CPUs. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 2 +- target/mips/mips-defs.h | 6 +- linux-user/mips/cpu_loop.c | 2 +- target/mips/cp0_timer.c | 4 +- target/mips/cpu.c | 2 +- target/mips/translate.c | 138 ++++++++++++++++++------------------- 6 files changed, 77 insertions(+), 77 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index f71c617a1fe..b14671a9a51 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -361,7 +361,7 @@ static inline void compute_hflags(CPUMIPSState *env) } =20 } - if (env->insn_flags & ISA_MIPS32R2) { + if (env->insn_flags & ISA_MIPS_R2) { if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { env->hflags |=3D MIPS_HFLAG_COP1X; } diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 31c02cc20ef..9ef3f517aaa 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -23,7 +23,7 @@ #define ISA_MIPS4 0x0000000000000008ULL #define ISA_MIPS5 0x0000000000000010ULL #define ISA_MIPS_R1 0x0000000000000020ULL -#define ISA_MIPS32R2 0x0000000000000040ULL +#define ISA_MIPS_R2 0x0000000000000040ULL #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS32R5 0x0000000000000800ULL #define ISA_MIPS32R6 0x0000000000002000ULL @@ -76,8 +76,8 @@ #define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32) =20 /* MIPS Technologies "Release 2" */ -#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) -#define CPU_MIPS64R2 (CPU_MIPS64 | ISA_MIPS32R2) +#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS_R2) +#define CPU_MIPS64R2 (CPU_MIPS64 | ISA_MIPS_R2) =20 /* MIPS Technologies "Release 3" */ #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index 1e4acf3d6e3..fc5446ade37 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -385,7 +385,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct tar= get_pt_regs *regs) prog_req.frdefault &=3D interp_req.frdefault; prog_req.fre &=3D interp_req.fre; =20 - bool cpu_has_mips_r2_r6 =3D env->insn_flags & ISA_MIPS32R2 || + bool cpu_has_mips_r2_r6 =3D env->insn_flags & ISA_MIPS_R2 || env->insn_flags & ISA_MIPS32R6; =20 if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) { diff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c index 5ec0d6249e9..70de95d338f 100644 --- a/target/mips/cp0_timer.c +++ b/target/mips/cp0_timer.c @@ -44,7 +44,7 @@ static void cpu_mips_timer_update(CPUMIPSState *env) static void cpu_mips_timer_expire(CPUMIPSState *env) { cpu_mips_timer_update(env); - if (env->insn_flags & ISA_MIPS32R2) { + if (env->insn_flags & ISA_MIPS_R2) { env->CP0_Cause |=3D 1 << CP0Ca_TI; } qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); @@ -93,7 +93,7 @@ void cpu_mips_store_compare(CPUMIPSState *env, uint32_t v= alue) if (!(env->CP0_Cause & (1 << CP0Ca_DC))) { cpu_mips_timer_update(env); } - if (env->insn_flags & ISA_MIPS32R2) { + if (env->insn_flags & ISA_MIPS_R2) { env->CP0_Cause &=3D ~(1 << CP0Ca_TI); } qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 112eb0d9f47..5c571434134 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -111,7 +111,7 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulo= ng val) uint32_t old =3D env->CP0_Cause; int i; =20 - if (env->insn_flags & ISA_MIPS32R2) { + if (env->insn_flags & ISA_MIPS_R2) { mask |=3D 1 << CP0Ca_DC; } if (env->insn_flags & ISA_MIPS32R6) { diff --git a/target/mips/translate.c b/target/mips/translate.c index d4e672ebca6..842db4490ce 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -7207,7 +7207,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) register_name =3D "PageMask"; break; case CP0_REG05__PAGEGRAIN: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain)); register_name =3D "PageGrain"; break; @@ -7255,27 +7255,27 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) register_name =3D "Wired"; break; case CP0_REG06__SRSCONF0: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0)); register_name =3D "SRSConf0"; break; case CP0_REG06__SRSCONF1: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1)); register_name =3D "SRSConf1"; break; case CP0_REG06__SRSCONF2: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2)); register_name =3D "SRSConf2"; break; case CP0_REG06__SRSCONF3: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3)); register_name =3D "SRSConf3"; break; case CP0_REG06__SRSCONF4: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); register_name =3D "SRSConf4"; break; @@ -7291,7 +7291,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_07: switch (sel) { case CP0_REG07__HWRENA: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna)); register_name =3D "HWREna"; break; @@ -7386,17 +7386,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) register_name =3D "Status"; break; case CP0_REG12__INTCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl)); register_name =3D "IntCtl"; break; case CP0_REG12__SRSCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl)); register_name =3D "SRSCtl"; break; case CP0_REG12__SRSMAP: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); register_name =3D "SRSMap"; break; @@ -7432,13 +7432,13 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) register_name =3D "PRid"; break; case CP0_REG15__EBASE: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase)); tcg_gen_ext32s_tl(arg, arg); register_name =3D "EBase"; break; case CP0_REG15__CMGCRBASE: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); CP0_CHECK(ctx->cmgcr); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBa= se)); tcg_gen_ext32s_tl(arg, arg); @@ -7952,7 +7952,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) register_name =3D "PageMask"; break; case CP0_REG05__PAGEGRAIN: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_pagegrain(cpu_env, arg); register_name =3D "PageGrain"; ctx->base.is_jmp =3D DISAS_STOP; @@ -7998,27 +7998,27 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) register_name =3D "Wired"; break; case CP0_REG06__SRSCONF0: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf0(cpu_env, arg); register_name =3D "SRSConf0"; break; case CP0_REG06__SRSCONF1: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf1(cpu_env, arg); register_name =3D "SRSConf1"; break; case CP0_REG06__SRSCONF2: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf2(cpu_env, arg); register_name =3D "SRSConf2"; break; case CP0_REG06__SRSCONF3: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf3(cpu_env, arg); register_name =3D "SRSConf3"; break; case CP0_REG06__SRSCONF4: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf4(cpu_env, arg); register_name =3D "SRSConf4"; break; @@ -8034,7 +8034,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_07: switch (sel) { case CP0_REG07__HWRENA: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_hwrena(cpu_env, arg); ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "HWREna"; @@ -8117,21 +8117,21 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) register_name =3D "Status"; break; case CP0_REG12__INTCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_intctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "IntCtl"; break; case CP0_REG12__SRSCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "SRSCtl"; break; case CP0_REG12__SRSMAP: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; @@ -8176,7 +8176,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) register_name =3D "PRid"; break; case CP0_REG15__EBASE: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_ebase(cpu_env, arg); register_name =3D "EBase"; break; @@ -8715,7 +8715,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) register_name =3D "PageMask"; break; case CP0_REG05__PAGEGRAIN: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain)); register_name =3D "PageGrain"; break; @@ -8760,27 +8760,27 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) register_name =3D "Wired"; break; case CP0_REG06__SRSCONF0: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0)); register_name =3D "SRSConf0"; break; case CP0_REG06__SRSCONF1: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1)); register_name =3D "SRSConf1"; break; case CP0_REG06__SRSCONF2: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2)); register_name =3D "SRSConf2"; break; case CP0_REG06__SRSCONF3: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3)); register_name =3D "SRSConf3"; break; case CP0_REG06__SRSCONF4: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4)); register_name =3D "SRSConf4"; break; @@ -8796,7 +8796,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REGISTER_07: switch (sel) { case CP0_REG07__HWRENA: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna)); register_name =3D "HWREna"; break; @@ -8889,17 +8889,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) register_name =3D "Status"; break; case CP0_REG12__INTCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl)); register_name =3D "IntCtl"; break; case CP0_REG12__SRSCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl)); register_name =3D "SRSCtl"; break; case CP0_REG12__SRSMAP: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); register_name =3D "SRSMap"; break; @@ -8934,12 +8934,12 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) register_name =3D "PRid"; break; case CP0_REG15__EBASE: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase)); register_name =3D "EBase"; break; case CP0_REG15__CMGCRBASE: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); CP0_CHECK(ctx->cmgcr); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBa= se)); register_name =3D "CMGCRBase"; @@ -9442,7 +9442,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) register_name =3D "PageMask"; break; case CP0_REG05__PAGEGRAIN: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_pagegrain(cpu_env, arg); register_name =3D "PageGrain"; break; @@ -9487,27 +9487,27 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) register_name =3D "Wired"; break; case CP0_REG06__SRSCONF0: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf0(cpu_env, arg); register_name =3D "SRSConf0"; break; case CP0_REG06__SRSCONF1: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf1(cpu_env, arg); register_name =3D "SRSConf1"; break; case CP0_REG06__SRSCONF2: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf2(cpu_env, arg); register_name =3D "SRSConf2"; break; case CP0_REG06__SRSCONF3: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf3(cpu_env, arg); register_name =3D "SRSConf3"; break; case CP0_REG06__SRSCONF4: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsconf4(cpu_env, arg); register_name =3D "SRSConf4"; break; @@ -9523,7 +9523,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REGISTER_07: switch (sel) { case CP0_REG07__HWRENA: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_hwrena(cpu_env, arg); ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "HWREna"; @@ -9610,21 +9610,21 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) register_name =3D "Status"; break; case CP0_REG12__INTCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_intctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "IntCtl"; break; case CP0_REG12__SRSCTL: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_srsctl(cpu_env, arg); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "SRSCtl"; break; case CP0_REG12__SRSMAP: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap)); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; @@ -9669,7 +9669,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) register_name =3D "PRid"; break; case CP0_REG15__EBASE: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_helper_mtc0_ebase(cpu_env, arg); register_name =3D "EBase"; break; @@ -13048,7 +13048,7 @@ static void gen_rdhwr(DisasContext *ctx, int rt, in= t rd, int sel) * The Linux kernel will emulate rdhwr if it's not supported natively. * Therefore only check the ISA in system mode. */ - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); #endif t0 =3D tcg_temp_new(); =20 @@ -15864,12 +15864,12 @@ static void gen_pool32axf(CPUMIPSState *env, Disa= sContext *ctx, int rt, int rs) switch (minor) { case RDPGPR: check_cp0_enabled(ctx); - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_load_srsgpr(rs, rt); break; case WRPGPR: check_cp0_enabled(ctx); - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_store_srsgpr(rs, rt); break; default: @@ -24577,7 +24577,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) switch ((ctx->opcode >> 21) & 0x1f) { case 1: /* rotr is decoded as srl on non-R2 CPUs */ - if (ctx->insn_flags & ISA_MIPS32R2) { + if (ctx->insn_flags & ISA_MIPS_R2) { op1 =3D OPC_ROTR; } /* Fallthrough */ @@ -24603,7 +24603,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) switch ((ctx->opcode >> 6) & 0x1f) { case 1: /* rotrv is decoded as srlv on non-R2 CPUs */ - if (ctx->insn_flags & ISA_MIPS32R2) { + if (ctx->insn_flags & ISA_MIPS_R2) { op1 =3D OPC_ROTRV; } /* Fallthrough */ @@ -24675,7 +24675,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) switch ((ctx->opcode >> 21) & 0x1f) { case 1: /* drotr is decoded as dsrl on non-R2 CPUs */ - if (ctx->insn_flags & ISA_MIPS32R2) { + if (ctx->insn_flags & ISA_MIPS_R2) { op1 =3D OPC_DROTR; } /* Fallthrough */ @@ -24693,7 +24693,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) switch ((ctx->opcode >> 21) & 0x1f) { case 1: /* drotr32 is decoded as dsrl32 on non-R2 CPUs */ - if (ctx->insn_flags & ISA_MIPS32R2) { + if (ctx->insn_flags & ISA_MIPS_R2) { op1 =3D OPC_DROTR32; } /* Fallthrough */ @@ -24725,7 +24725,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) switch ((ctx->opcode >> 6) & 0x1f) { case 1: /* drotrv is decoded as dsrlv on non-R2 CPUs */ - if (ctx->insn_flags & ISA_MIPS32R2) { + if (ctx->insn_flags & ISA_MIPS_R2) { op1 =3D OPC_DROTRV; } /* Fallthrough */ @@ -28185,7 +28185,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) switch (op1) { case OPC_EXT: case OPC_INS: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_bitops(ctx, op1, rt, rs, sa, rd); break; case OPC_BSHFL: @@ -28200,7 +28200,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) decode_opc_special3_r6(env, ctx); break; default: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_bshfl(ctx, op2, rt, rd); break; } @@ -28212,7 +28212,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) case OPC_DINSM: case OPC_DINSU: case OPC_DINS: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); check_mips_64(ctx); gen_bitops(ctx, op1, rt, rs, sa, rd); break; @@ -28232,7 +28232,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) decode_opc_special3_r6(env, ctx); break; default: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); check_mips_64(ctx); op2 =3D MASK_DBSHFL(ctx->opcode); gen_bshfl(ctx, op2, rt, rd); @@ -28359,7 +28359,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) gen_reserved_instruction(ctx); break; case OPC_SYNCI: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); /* * Break the TB to be able to sync copied instructions * immediately. @@ -28476,7 +28476,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) } break; case OPC_DI: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); save_cpu_state(ctx, 1); gen_helper_di(t0, cpu_env); gen_store_gpr(t0, rt); @@ -28487,7 +28487,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) ctx->base.is_jmp =3D DISAS_STOP; break; case OPC_EI: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); save_cpu_state(ctx, 1); gen_helper_ei(t0, cpu_env); gen_store_gpr(t0, rt); @@ -28508,11 +28508,11 @@ static bool decode_opc_legacy(CPUMIPSState *env, = DisasContext *ctx) #endif /* !CONFIG_USER_ONLY */ break; case OPC_RDPGPR: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_load_srsgpr(rt, rd); break; case OPC_WRPGPR: - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); gen_store_srsgpr(rt, rd); break; default: @@ -28674,7 +28674,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) case OPC_MFHC1: case OPC_MTHC1: check_cp1_enabled(ctx); - check_insn(ctx, ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS_R2); /* fall through */ case OPC_MFC1: case OPC_CFC1: @@ -28855,21 +28855,21 @@ static bool decode_opc_legacy(CPUMIPSState *env, = DisasContext *ctx) switch (op1) { case OPC_LUXC1: case OPC_SUXC1: - check_insn(ctx, ISA_MIPS5 | ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2); /* Fallthrough */ case OPC_LWXC1: case OPC_LDXC1: case OPC_SWXC1: case OPC_SDXC1: - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2); gen_flt3_ldst(ctx, op1, sa, rd, rs, rt); break; case OPC_PREFX: - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2); /* Treat as NOP. */ break; case OPC_ALNV_PS: - check_insn(ctx, ISA_MIPS5 | ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2); /* Fallthrough */ case OPC_MADD_S: case OPC_MADD_D: @@ -28883,7 +28883,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) case OPC_NMSUB_S: case OPC_NMSUB_D: case OPC_NMSUB_PS: - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32R2); + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2); gen_flt3_arith(ctx, op1, sa, rs, rd, rt); break; default: --=20 2.26.2 From nobody Tue Nov 18 05:50:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.46 as permitted sender) client-ip=209.85.221.46; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f46.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1608126257; cv=none; d=zohomail.com; s=zohoarc; b=bbu5zLWkXlKYAHi5QJS+ybFaSpMeKceH8WJQ3mtPjCcyNspdUsU3gBWYuXNlC49SOfE4+9W51KDNmya7CsBXSrnU0dHL7vxNxScfhuGwPr6VTfDCO8UjBEOmbQkRh2wOUYiMW7yu1h3Dz5H4Spvd5sifA0nN1Q8h5hnXz0G2yM8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608126257; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zRaZ2XrSqwps5n75JXC431veK2scZnrGflijkMP5vE0=; b=fF7JhM8tq7tJp8GsJDwzi2W8YMCSfIJyA4z6+nMcQ8W4OpMv2TzWVqyOZoSptrGYEhw4j6zOgZBV6hy5QPKLqHzC0Nj2JjJ/tAhDaY35bdxyxt2dD0pEE6oD9KLMKpPxltjUvpRztqCq//sNPIu1UXDSQCl9iNuFh4Q/TroSI/s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) by mx.zohomail.com with SMTPS id 1608126257576190.5439179174915; Wed, 16 Dec 2020 05:44:17 -0800 (PST) Received: by mail-wr1-f46.google.com with SMTP id t16so23229704wra.3 for ; Wed, 16 Dec 2020 05:44:16 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id f14sm2844170wme.14.2020.12.16.05.44.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 05:44:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zRaZ2XrSqwps5n75JXC431veK2scZnrGflijkMP5vE0=; b=gPixu00/qQdNIfXMdf4Dj4PGq8/0T9qt+wpxGk7pZYRNOOP9eDvEdC4c8GsT2EmuQe OuzfGpvWrrshYHz0smfbmuXtb/bTsWYYpVDKnX5P8BVKiYpMSRJz9tGRoRoLpjhKtI6Y lnKi8Ckh1T6M9B7BVmlMJBW50Bc61zgGObKWtv1xhc6wiJTgAC0u3mp0H1ug0PgKdOdg 4/uMi4c2P8Q1ZPWOdTg01WsO4/56bedWu79k4yatzvzP3uWlATyVEUtNTaGMhbHv14gv 7qrYjez//4Cs0sLuPhIT5HySnstMGzKD+g7a+0pk6SuRZYaZCOjg3kc70Hi29rrK21hP zkXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=zRaZ2XrSqwps5n75JXC431veK2scZnrGflijkMP5vE0=; b=OGnwemiORSMvv5oGLJzeULbzXPFi764RRZsS0TJG7QM/c5oBaBKPlI/6m3TRUPnebl g0v7vnartMb8T/X3N/cTW/f7Y1yCxf0rp3bKfKl/DP4E3ytB8kD9olqCQhru75hIv61F pMvQ5Sne8r5SXTCydNC59MGz5N89v6obwywOk+LSUFMqCpkWZepvciSQOLIcH3WJ504q YrcRdfHMXCWmrj3p++LspbcLOS/Z9FZC8FQ7yVZgzRYqHNEIkiON6WLABOlkyx0Lp0WB Pi4tjliD64TChdfxkgD8reQSNRrDnI8ozmG3nrF/XzMDFKvXANxW18ApyWluLzdeMwnB aATw== X-Gm-Message-State: AOAM530MZApaswGz0m+/nHApHawCtYstTejxbp3ogkTG1+AZ3/NVZRQJ BNuZxabOjaLlnn0L0C4EX/w= X-Google-Smtp-Source: ABdhPJypgcHaU1DTZ2y1IDanTJ49ZworgxgovFChPohdimUbrs0QJBkjHn8lPLMH5kqMFotyixE6uQ== X-Received: by 2002:adf:eb88:: with SMTP id t8mr39492070wrn.105.1608126255629; Wed, 16 Dec 2020 05:44:15 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Paul Burton , Richard Henderson , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 09/11] target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3 Date: Wed, 16 Dec 2020 14:43:26 +0100 Message-Id: <20201216134328.851840-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216134328.851840-1-f4bug@amsat.org> References: <20201216134328.851840-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The MIPS ISA release 3 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/mips-defs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 9ef3f517aaa..171d94c16dc 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -24,7 +24,7 @@ #define ISA_MIPS5 0x0000000000000010ULL #define ISA_MIPS_R1 0x0000000000000020ULL #define ISA_MIPS_R2 0x0000000000000040ULL -#define ISA_MIPS32R3 0x0000000000000200ULL +#define ISA_MIPS_R3 0x0000000000000080ULL #define ISA_MIPS32R5 0x0000000000000800ULL #define ISA_MIPS32R6 0x0000000000002000ULL #define ISA_NANOMIPS32 0x0000000000008000ULL @@ -80,7 +80,7 @@ #define CPU_MIPS64R2 (CPU_MIPS64 | ISA_MIPS_R2) =20 /* MIPS Technologies "Release 3" */ -#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) +#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS_R3) #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3) =20 /* MIPS Technologies "Release 5" */ --=20 2.26.2 From nobody Tue Nov 18 05:50:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) client-ip=209.85.128.46; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f46.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1608126263; cv=none; d=zohomail.com; s=zohoarc; b=MWpz0M+vZs7vKOE4RymQs7F+bZU39jHiVuytTJx1lQdTIT6JkYl/aY9+Rnr1sxkZRsju0CGwmVFiL5x1aTyyTO/sqmOcHIX02Cwld3huuq36/rOFeV7hjeyCPBKe+kEoy7dk7OFe9zUPNrl2NivgXVTLOPnvlPbUduEVDNxjfac= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608126263; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wLFcl6Vi44+jgM/M1PEATPZTUeRmUNN1l1qQcgVBAnw=; b=N6OCBWUkuwqyvqEUvMSqcJiAXnMs00lAgIGNgmsgnzx1nmV5RnnTgkz764uBlRSeDaxvauPG/zFapVgkHJ9GUBZ2h8hhYJe1ouvfellrWi5/bwsLP6KPMjzHamnHCx01n75mqyDtd2PAhSDtpJvtz6QSzJ4a2D5To9IxFRBEKME= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) by mx.zohomail.com with SMTPS id 1608126263115749.1782528444049; Wed, 16 Dec 2020 05:44:23 -0800 (PST) Received: by mail-wm1-f46.google.com with SMTP id g185so2490858wmf.3 for ; Wed, 16 Dec 2020 05:44:21 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id z64sm2833660wme.10.2020.12.16.05.44.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 05:44:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wLFcl6Vi44+jgM/M1PEATPZTUeRmUNN1l1qQcgVBAnw=; b=ZWupw9rokBEvovxkaWwo+oDlGRCDQKzYxtv+uf5nYSjI7Z3Ipwz0vWGDDR4Oh49ryt ERTQFzlDSvRHfO3e/OiMYlCBbZlFdkeMpyZ5+vAZ8743fdMwEZEUOCsarOF2fkF7FGN7 aPKjnSwY9GA5wPScEmI5dJCx3tSIMqlKQtXL4mm1c73nloSIL7abHBatlk0jaMnredZU o0SAU928MeMvThW7ysFfFu7/X6mWleezVuzv/lUuZXbm4wi61FBUFT2o833Ipy1u8bfZ 86kifkeblUBKHoMmv+Kv/Cy8mffNEhGUJz/YNxvTta5Uqc4KX1kDKWLA/jIrNFc51O6t SYlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=wLFcl6Vi44+jgM/M1PEATPZTUeRmUNN1l1qQcgVBAnw=; b=UigF2a0N2ZGyBxHZ2D9UPYtSQykdlX33l2/94UmLpptnuJC4jDdhOc4SBL/Jj13K9C L4Q3w6qLBvz1+6K4Zf4KhUWyMiALUs3jQEVRV6l9Z6OlxcBmwxWVhJNNKQ2rY4PzKRjb m/KbfHkuq3LqASOEzojs7MffhTdwu0Dyz07CINFKLKdOrfQvC9ya3ecKxP/Jh2c7uww1 BZUqDWd9nKImF0injxVIuAQ+OFtrtdBp9YnccmVa7oYV2nJy9KZmjoKtkf9tKH1NDqi+ atgBFt0VlTNbOOUQ2IQOkCPvcDNwvh2j4s0INFHcGMEn18peLT77XWqWgERPWPEu/dWW FnNQ== X-Gm-Message-State: AOAM531jFTPsdoEKLa+kngzD9G2PDlZ95IpaEHxljZTqCkqFLR0ihn1H euuj7euqIom28DiIGJhNCtsLgpYb+T0= X-Google-Smtp-Source: ABdhPJwuZHb5FwUtzmbnO7QzQWri7mvN/ji7Qsw+fr85rHkoWn3J0eC4Gg8DYBVryynvN8TGD4I5Ag== X-Received: by 2002:a05:600c:21d5:: with SMTP id x21mr3448500wmj.10.1608126260587; Wed, 16 Dec 2020 05:44:20 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Paul Burton , Richard Henderson , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 10/11] target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5 Date: Wed, 16 Dec 2020 14:43:27 +0100 Message-Id: <20201216134328.851840-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216134328.851840-1-f4bug@amsat.org> References: <20201216134328.851840-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The MIPS ISA release 5 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/mips-defs.h | 4 ++-- target/mips/translate.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 171d94c16dc..068fe9c8a19 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -25,7 +25,7 @@ #define ISA_MIPS_R1 0x0000000000000020ULL #define ISA_MIPS_R2 0x0000000000000040ULL #define ISA_MIPS_R3 0x0000000000000080ULL -#define ISA_MIPS32R5 0x0000000000000800ULL +#define ISA_MIPS_R5 0x0000000000000100ULL #define ISA_MIPS32R6 0x0000000000002000ULL #define ISA_NANOMIPS32 0x0000000000008000ULL /* @@ -84,7 +84,7 @@ #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3) =20 /* MIPS Technologies "Release 5" */ -#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5) +#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS_R5) #define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5) =20 /* MIPS Technologies "Release 6" */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 842db4490ce..6406596293c 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -10588,7 +10588,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext= *ctx, uint32_t opc, if (ctx->opcode & (1 << bit_shift)) { /* OPC_ERETNC */ opn =3D "eretnc"; - check_insn(ctx, ISA_MIPS32R5); + check_insn(ctx, ISA_MIPS_R5); gen_helper_eretnc(cpu_env); } else { /* OPC_ERET */ --=20 2.26.2 From nobody Tue Nov 18 05:50:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.46 as permitted sender) client-ip=209.85.221.46; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f46.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1608126269; cv=none; d=zohomail.com; s=zohoarc; b=UHVu4v1gOE1ruuMraV2yUBXylkutjomQek1dYZy3sKnhEzyl1+WiNeve2V1lMFwDivjg+T7PQ5LQPRMp5hB/icuvZ9k3w/3kIeGBFUGGqSc7PnuIRYb8l/jhteJpe5ouYCfMPJny5lAqT/zOzhteOKyLfYqAiOw/HVXQ+CcCmp4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608126269; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Z5PAwkrsVrNXN4FN/YvmNFpK/gDVQ5j3ObxyQwp9F+A=; b=ZCAIo9FDIi9neS6V6xI4vSeOY3tKznCvdD7a80Vt08x2yzFaPh7vLaehMA/s2nkkgDJzFTgMT+umPbR1ezIxiDjDFXO/n89eBZuyclCik13tPd/xXC7A2hbzkedY7UbMN173Scg3gIXIAPQuMVfdwofJ2hpZeZA+TvYDuO03ymk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) by mx.zohomail.com with SMTPS id 1608126269962320.41583060457685; Wed, 16 Dec 2020 05:44:29 -0800 (PST) Received: by mail-wr1-f46.google.com with SMTP id c5so19579622wrp.6 for ; Wed, 16 Dec 2020 05:44:27 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id z15sm3420028wrv.67.2020.12.16.05.44.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 05:44:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Z5PAwkrsVrNXN4FN/YvmNFpK/gDVQ5j3ObxyQwp9F+A=; b=J0Ys0dH7CZDHoC1ZBKd2jv64TVbWsLhbUkQUneJ771neRG62oe+WGB/SzqjGuHztVM y32cMgiZMHv5T4gTp/Q131rvxF4jtJfJ2jQoIAMBHr4s8R1v0kE7wcGdnBCaCTgjp88+ LiUPs3TzfbUN/YA7h5FgZtAQU+lqRi6eRv2SrC+lH2FOP8tPo/Q41VadToqy5OEje/ll HmT/139r/kVoLMgIXG9NKcFFUzA5nw1Iofpo+nZdx/vYcJ/bQHA1lQY4AsFEX5MPy9I7 aSDExtAlO5AMncM462ArobfrYiRJf5N/6YsCbWS87Ru6/wJz0VNagK6ndiA4WEEBs/BA y9pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Z5PAwkrsVrNXN4FN/YvmNFpK/gDVQ5j3ObxyQwp9F+A=; b=VI/9SQX2aHE++c9Tc6RKE51sYT8HFoxWeHX8ZSPKycUxt+Nc+VQddYpWHfpoclgW1T 8GOJzC2t8dj1dzc2hMmxewOLA/Dlg9zLyomy1BScU37Mni0F+GZb7el2TOz6hsW/BFSo UGTNTi0iQsDexU+jetEu6F1tNBinYTop9kWOvazyEczSjnKr8+o6TZODMrqYaC7+/69L QNdbesz2C8/CM9ZaSvjqs5Rz52TWN0pXVJ/aB63kDX5/L8Nr5YtEAFPNd6mQLjBDaJ9r 9WirfuzpEif8uZrX/u7f8YlXiizflZQ1G5lpyDDJa9nnMNBwyUYaaO+2sLMowjRpfEtb wPHw== X-Gm-Message-State: AOAM530HuFMl7ac3nDKUDRQ9HD0zPskz2AkWvNNKFZ/nj6wKmiH9KBMp uDUd8K1sd5pKB9wdlfTZQUUm9FS89O0= X-Google-Smtp-Source: ABdhPJwDSubfnHMyl2EhQhbbkKaEQTa1aW2iuIsnDkAKoa5nzXMCHONep0/pqHSfjndXI6sn64qSMw== X-Received: by 2002:adf:9cca:: with SMTP id h10mr31228905wre.77.1608126265692; Wed, 16 Dec 2020 05:44:25 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Paul Burton , Richard Henderson , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 11/11] target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6 Date: Wed, 16 Dec 2020 14:43:28 +0100 Message-Id: <20201216134328.851840-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216134328.851840-1-f4bug@amsat.org> References: <20201216134328.851840-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The MIPS ISA release 6 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 4 +- target/mips/mips-defs.h | 4 +- linux-user/elfload.c | 2 +- linux-user/mips/cpu_loop.c | 2 +- target/mips/cp0_helper.c | 18 +- target/mips/cpu.c | 10 +- target/mips/fpu_helper.c | 4 +- target/mips/tlb_helper.c | 6 +- target/mips/translate.c | 426 ++++++++++++++++++------------------- 9 files changed, 238 insertions(+), 238 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index b14671a9a51..5dd17ff7333 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -308,7 +308,7 @@ static inline void compute_hflags(CPUMIPSState *env) } else if (((env->hflags & MIPS_HFLAG_KSU) =3D=3D MIPS_HFLAG_UM) && !(env->CP0_Status & (1 << CP0St_UX))) { env->hflags |=3D MIPS_HFLAG_AWRAP; - } else if (env->insn_flags & ISA_MIPS32R6) { + } else if (env->insn_flags & ISA_MIPS_R6) { /* Address wrapping for Supervisor and Kernel is specified in R6 */ if ((((env->hflags & MIPS_HFLAG_KSU) =3D=3D MIPS_HFLAG_SM) && !(env->CP0_Status & (1 << CP0St_SX))) || @@ -319,7 +319,7 @@ static inline void compute_hflags(CPUMIPSState *env) } #endif if (((env->CP0_Status & (1 << CP0St_CU0)) && - !(env->insn_flags & ISA_MIPS32R6)) || + !(env->insn_flags & ISA_MIPS_R6)) || !(env->hflags & MIPS_HFLAG_KSU)) { env->hflags |=3D MIPS_HFLAG_CP0; } diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 068fe9c8a19..32c4c5cf6c4 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -26,7 +26,7 @@ #define ISA_MIPS_R2 0x0000000000000040ULL #define ISA_MIPS_R3 0x0000000000000080ULL #define ISA_MIPS_R5 0x0000000000000100ULL -#define ISA_MIPS32R6 0x0000000000002000ULL +#define ISA_MIPS_R6 0x0000000000000200ULL #define ISA_NANOMIPS32 0x0000000000008000ULL /* * bits 24-39: MIPS ASEs @@ -88,7 +88,7 @@ #define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5) =20 /* MIPS Technologies "Release 6" */ -#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) +#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS_R6) #define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6) =20 /* Wave Computing: "nanoMIPS" */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index e875a5387cc..5f8bc98e5c5 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -997,7 +997,7 @@ static uint32_t get_elf_hwcap(void) #define GET_FEATURE(flag, hwcap) \ do { if (cpu->env.insn_flags & (flag)) { hwcaps |=3D hwcap; } } while = (0) =20 - GET_FEATURE(ISA_MIPS32R6, HWCAP_MIPS_R6); + GET_FEATURE(ISA_MIPS_R6, HWCAP_MIPS_R6); GET_FEATURE(ASE_MSA, HWCAP_MIPS_MSA); =20 #undef GET_FEATURE diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index fc5446ade37..9d813ece4e7 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -386,7 +386,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct tar= get_pt_regs *regs) prog_req.fre &=3D interp_req.fre; =20 bool cpu_has_mips_r2_r6 =3D env->insn_flags & ISA_MIPS_R2 || - env->insn_flags & ISA_MIPS32R6; + env->insn_flags & ISA_MIPS_R6; =20 if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) { env->CP0_Config5 |=3D (1 << CP0C5_FRE); diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c index 36a92857bfb..aae2af6eccc 100644 --- a/target/mips/cp0_helper.c +++ b/target/mips/cp0_helper.c @@ -527,7 +527,7 @@ void helper_mtc0_index(CPUMIPSState *env, target_ulong = arg1) uint32_t index_p =3D env->CP0_Index & 0x80000000; uint32_t tlb_index =3D arg1 & 0x7fffffff; if (tlb_index < env->tlb->nb_tlb) { - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { index_p |=3D arg1 & 0x80000000; } env->CP0_Index =3D index_p | tlb_index; @@ -960,7 +960,7 @@ void helper_mtc0_pwfield(CPUMIPSState *env, target_ulon= g arg1) uint32_t old_ptei =3D (env->CP0_PWField >> CP0PF_PTEI) & 0x3FULL; uint32_t new_ptei =3D (arg1 >> CP0PF_PTEI) & 0x3FULL; =20 - if ((env->insn_flags & ISA_MIPS32R6)) { + if ((env->insn_flags & ISA_MIPS_R6)) { if (((arg1 >> CP0PF_BDI) & 0x3FULL) < 12) { mask &=3D ~(0x3FULL << CP0PF_BDI); } @@ -980,7 +980,7 @@ void helper_mtc0_pwfield(CPUMIPSState *env, target_ulon= g arg1) env->CP0_PWField =3D arg1 & mask; =20 if ((new_ptei >=3D 32) || - ((env->insn_flags & ISA_MIPS32R6) && + ((env->insn_flags & ISA_MIPS_R6) && (new_ptei =3D=3D 0 || new_ptei =3D=3D 1))) { env->CP0_PWField =3D (env->CP0_PWField & ~0x3FULL) | (old_ptei << CP0PF_PTEI); @@ -990,7 +990,7 @@ void helper_mtc0_pwfield(CPUMIPSState *env, target_ulon= g arg1) uint32_t old_ptew =3D (env->CP0_PWField >> CP0PF_PTEW) & 0x3F; uint32_t new_ptew =3D (arg1 >> CP0PF_PTEW) & 0x3F; =20 - if ((env->insn_flags & ISA_MIPS32R6)) { + if ((env->insn_flags & ISA_MIPS_R6)) { if (((arg1 >> CP0PF_GDW) & 0x3F) < 12) { mask &=3D ~(0x3F << CP0PF_GDW); } @@ -1007,7 +1007,7 @@ void helper_mtc0_pwfield(CPUMIPSState *env, target_ul= ong arg1) env->CP0_PWField =3D arg1 & mask; =20 if ((new_ptew >=3D 32) || - ((env->insn_flags & ISA_MIPS32R6) && + ((env->insn_flags & ISA_MIPS_R6) && (new_ptew =3D=3D 0 || new_ptew =3D=3D 1))) { env->CP0_PWField =3D (env->CP0_PWField & ~0x3F) | (old_ptew << CP0PF_PTEW); @@ -1026,7 +1026,7 @@ void helper_mtc0_pwsize(CPUMIPSState *env, target_ulo= ng arg1) =20 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1) { - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { if (arg1 < env->tlb->nb_tlb) { env->CP0_Wired =3D arg1; } @@ -1075,10 +1075,10 @@ void helper_mtc0_hwrena(CPUMIPSState *env, target_u= long arg1) uint32_t mask =3D 0x0000000F; =20 if ((env->CP0_Config1 & (1 << CP0C1_PC)) && - (env->insn_flags & ISA_MIPS32R6)) { + (env->insn_flags & ISA_MIPS_R6)) { mask |=3D (1 << 4); } - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { mask |=3D (1 << 5); } if (env->CP0_Config3 & (1 << CP0C3_ULRI)) { @@ -1149,7 +1149,7 @@ void helper_mtc0_entryhi(CPUMIPSState *env, target_ul= ong arg1) =20 /* 1k pages not implemented */ #if defined(TARGET_MIPS64) - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { int entryhi_r =3D extract64(arg1, 62, 2); int config0_at =3D extract32(env->CP0_Config0, 13, 2); bool no_supervisor =3D (env->CP0_Status_rw_bitmask & 0x8) =3D=3D 0; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 5c571434134..905772a394b 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -77,7 +77,7 @@ void cpu_mips_store_status(CPUMIPSState *env, target_ulon= g val) uint32_t mask =3D env->CP0_Status_rw_bitmask; target_ulong old =3D env->CP0_Status; =20 - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { bool has_supervisor =3D extract32(mask, CP0St_KSU, 2) =3D=3D 0x3; #if defined(TARGET_MIPS64) uint32_t ksux =3D (1 << CP0St_KX) & val; @@ -114,7 +114,7 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulo= ng val) if (env->insn_flags & ISA_MIPS_R2) { mask |=3D 1 << CP0Ca_DC; } - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { mask &=3D ~((1 << CP0Ca_WP) & val); } =20 @@ -281,7 +281,7 @@ static bool mips_cpu_has_work(CPUState *cs) if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && cpu_mips_hw_interrupts_pending(env)) { if (cpu_mips_hw_interrupts_enabled(env) || - (env->insn_flags & ISA_MIPS32R6)) { + (env->insn_flags & ISA_MIPS_R6)) { has_work =3D true; } } @@ -503,13 +503,13 @@ static void mips_cpu_reset(DeviceState *dev) /* XKPhys (note, SegCtl2.XR =3D 0, so XAM won't be used) */ env->CP0_SegCtl1 |=3D (CP0SC_AM_UK << CP0SC1_XAM); #endif /* !CONFIG_USER_ONLY */ - if ((env->insn_flags & ISA_MIPS32R6) && + if ((env->insn_flags & ISA_MIPS_R6) && (env->active_fpu.fcr0 & (1 << FCR0_F64))) { /* Status.FR =3D 0 mode in 64-bit FPU not allowed in R6 */ env->CP0_Status |=3D (1 << CP0St_FR); } =20 - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { /* PTW =3D 1 */ env->CP0_PWSize =3D 0x40; /* GDI =3D 12 */ diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index a3c05160b35..6dd853259e2 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -146,7 +146,7 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, = uint32_t fs, uint32_t rt) } break; case 25: - if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) { + if ((env->insn_flags & ISA_MIPS_R6) || (arg1 & 0xffffff00)) { return; } env->active_fpu.fcr31 =3D (env->active_fpu.fcr31 & 0x017fffff) | @@ -173,7 +173,7 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, = uint32_t fs, uint32_t rt) (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask= )); break; default: - if (env->insn_flags & ISA_MIPS32R6) { + if (env->insn_flags & ISA_MIPS_R6) { do_raise_exception(env, EXCP_RI, GETPC()); } return; diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c index 68d766f90a3..082c17928d3 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tlb_helper.c @@ -1025,7 +1025,7 @@ void mips_cpu_do_interrupt(CPUState *cs) enter_debug_mode: if (env->insn_flags & ISA_MIPS3) { env->hflags |=3D MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS32R6) || + if (!(env->insn_flags & ISA_MIPS_R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &=3D ~MIPS_HFLAG_AWRAP; } @@ -1054,7 +1054,7 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Status |=3D (1 << CP0St_ERL) | (1 << CP0St_BEV); if (env->insn_flags & ISA_MIPS3) { env->hflags |=3D MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS32R6) || + if (!(env->insn_flags & ISA_MIPS_R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &=3D ~MIPS_HFLAG_AWRAP; } @@ -1240,7 +1240,7 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Status |=3D (1 << CP0St_EXL); if (env->insn_flags & ISA_MIPS3) { env->hflags |=3D MIPS_HFLAG_64; - if (!(env->insn_flags & ISA_MIPS32R6) || + if (!(env->insn_flags & ISA_MIPS_R6) || env->CP0_Status & (1 << CP0St_KX)) { env->hflags &=3D ~MIPS_HFLAG_AWRAP; } diff --git a/target/mips/translate.c b/target/mips/translate.c index 6406596293c..0d27d15eb26 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -3634,7 +3634,7 @@ static void gen_logic_imm(DisasContext *ctx, uint32_t= opc, } break; case OPC_LUI: - if (rs !=3D 0 && (ctx->insn_flags & ISA_MIPS32R6)) { + if (rs !=3D 0 && (ctx->insn_flags & ISA_MIPS_R6)) { /* OPC_AUI */ tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], imm << 16); tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); @@ -6994,7 +6994,7 @@ cp0_unimplemented: =20 static inline void gen_mfc0_unimplemented(DisasContext *ctx, TCGv arg) { - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { tcg_gen_movi_tl(arg, 0); } else { tcg_gen_movi_tl(arg, ~0); @@ -7043,7 +7043,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_01: switch (sel) { case CP0_REG01__RANDOM: - CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); + CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); gen_helper_mfc0_random(arg, cpu_env); register_name =3D "Random"; break; @@ -7559,7 +7559,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_21: /* Officially reserved, but sel 0 is used for R1x000 framemask */ - CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); + CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); switch (sel) { case 0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask)); @@ -8304,7 +8304,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REGISTER_21: /* Officially reserved, but sel 0 is used for R1x000 framemask */ - CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); + CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); switch (sel) { case 0: gen_helper_mtc0_framemask(cpu_env, arg); @@ -8575,7 +8575,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REGISTER_01: switch (sel) { case CP0_REG01__RANDOM: - CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); + CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); gen_helper_mfc0_random(arg, cpu_env); register_name =3D "Random"; break; @@ -9056,7 +9056,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_21: /* Officially reserved, but sel 0 is used for R1x000 framemask */ - CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); + CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); switch (sel) { case 0: gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask)); @@ -9786,7 +9786,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REGISTER_21: /* Officially reserved, but sel 0 is used for R1x000 framemask */ - CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); + CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); switch (sel) { case 0: gen_helper_mtc0_framemask(cpu_env, arg); @@ -10580,7 +10580,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext= *ctx, uint32_t opc, gen_helper_tlbr(cpu_env); break; case OPC_ERET: /* OPC_ERETNC */ - if ((ctx->insn_flags & ISA_MIPS32R6) && + if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { goto die; } else { @@ -10602,7 +10602,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext= *ctx, uint32_t opc, case OPC_DERET: opn =3D "deret"; check_insn(ctx, ISA_MIPS_R1); - if ((ctx->insn_flags & ISA_MIPS32R6) && + if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { goto die; } @@ -10617,7 +10617,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext= *ctx, uint32_t opc, case OPC_WAIT: opn =3D "wait"; check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1); - if ((ctx->insn_flags & ISA_MIPS32R6) && + if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { goto die; } @@ -10645,7 +10645,7 @@ static void gen_compute_branch1(DisasContext *ctx, = uint32_t op, target_ulong btarget; TCGv_i32 t0 =3D tcg_temp_new_i32(); =20 - if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->hflags & MIPS_HFLAG_BMAS= K)) { + if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK= )) { gen_reserved_instruction(ctx); goto out; } @@ -11501,23 +11501,23 @@ static void gen_farith(DisasContext *ctx, enum fo= pcode op1, } break; case OPC_SEL_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_sel_s(ctx, op1, fd, ft, fs); break; case OPC_SELEQZ_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_sel_s(ctx, op1, fd, ft, fs); break; case OPC_SELNEZ_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_sel_s(ctx, op1, fd, ft, fs); break; case OPC_MOVCF_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_movcf_s(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1); break; case OPC_MOVZ_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); { TCGLabel *l1 =3D gen_new_label(); TCGv_i32 fp0; @@ -11533,7 +11533,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MOVN_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); { TCGLabel *l1 =3D gen_new_label(); TCGv_i32 fp0; @@ -11569,7 +11569,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MADDF_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i32 fp0 =3D tcg_temp_new_i32(); TCGv_i32 fp1 =3D tcg_temp_new_i32(); @@ -11585,7 +11585,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MSUBF_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i32 fp0 =3D tcg_temp_new_i32(); TCGv_i32 fp1 =3D tcg_temp_new_i32(); @@ -11601,7 +11601,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_RINT_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i32 fp0 =3D tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, fs); @@ -11611,7 +11611,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_CLASS_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i32 fp0 =3D tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, fs); @@ -11621,7 +11621,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MIN_S: /* OPC_RECIP2_S */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MIN_S */ TCGv_i32 fp0 =3D tcg_temp_new_i32(); TCGv_i32 fp1 =3D tcg_temp_new_i32(); @@ -11650,7 +11650,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MINA_S: /* OPC_RECIP1_S */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MINA_S */ TCGv_i32 fp0 =3D tcg_temp_new_i32(); TCGv_i32 fp1 =3D tcg_temp_new_i32(); @@ -11676,7 +11676,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MAX_S: /* OPC_RSQRT1_S */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MAX_S */ TCGv_i32 fp0 =3D tcg_temp_new_i32(); TCGv_i32 fp1 =3D tcg_temp_new_i32(); @@ -11700,7 +11700,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MAXA_S: /* OPC_RSQRT2_S */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MAXA_S */ TCGv_i32 fp0 =3D tcg_temp_new_i32(); TCGv_i32 fp1 =3D tcg_temp_new_i32(); @@ -11802,7 +11802,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, case OPC_CMP_NGE_S: case OPC_CMP_LE_S: case OPC_CMP_NGT_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->opcode & (1 << 6)) { gen_cmpabs_s(ctx, func - 48, ft, fs, cc); } else { @@ -12045,23 +12045,23 @@ static void gen_farith(DisasContext *ctx, enum fo= pcode op1, } break; case OPC_SEL_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_sel_d(ctx, op1, fd, ft, fs); break; case OPC_SELEQZ_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_sel_d(ctx, op1, fd, ft, fs); break; case OPC_SELNEZ_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_sel_d(ctx, op1, fd, ft, fs); break; case OPC_MOVCF_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_movcf_d(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1); break; case OPC_MOVZ_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); { TCGLabel *l1 =3D gen_new_label(); TCGv_i64 fp0; @@ -12077,7 +12077,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MOVN_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); { TCGLabel *l1 =3D gen_new_label(); TCGv_i64 fp0; @@ -12115,7 +12115,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MADDF_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i64 fp0 =3D tcg_temp_new_i64(); TCGv_i64 fp1 =3D tcg_temp_new_i64(); @@ -12131,7 +12131,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MSUBF_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i64 fp0 =3D tcg_temp_new_i64(); TCGv_i64 fp1 =3D tcg_temp_new_i64(); @@ -12147,7 +12147,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_RINT_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i64 fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); @@ -12157,7 +12157,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_CLASS_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); { TCGv_i64 fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); @@ -12167,7 +12167,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MIN_D: /* OPC_RECIP2_D */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MIN_D */ TCGv_i64 fp0 =3D tcg_temp_new_i64(); TCGv_i64 fp1 =3D tcg_temp_new_i64(); @@ -12194,7 +12194,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MINA_D: /* OPC_RECIP1_D */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MINA_D */ TCGv_i64 fp0 =3D tcg_temp_new_i64(); TCGv_i64 fp1 =3D tcg_temp_new_i64(); @@ -12218,7 +12218,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MAX_D: /* OPC_RSQRT1_D */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MAX_D */ TCGv_i64 fp0 =3D tcg_temp_new_i64(); TCGv_i64 fp1 =3D tcg_temp_new_i64(); @@ -12242,7 +12242,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } break; case OPC_MAXA_D: /* OPC_RSQRT2_D */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_MAXA_D */ TCGv_i64 fp0 =3D tcg_temp_new_i64(); TCGv_i64 fp1 =3D tcg_temp_new_i64(); @@ -12284,7 +12284,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, case OPC_CMP_NGE_D: case OPC_CMP_LE_D: case OPC_CMP_NGT_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->opcode & (1 << 6)) { gen_cmpabs_d(ctx, func - 48, ft, fs, cc); } else { @@ -13080,7 +13080,7 @@ static void gen_rdhwr(DisasContext *ctx, int rt, in= t rd, int sel) gen_store_gpr(t0, rt); break; case 4: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (sel !=3D 0) { /* * Performance counter registers are not implemented other than @@ -13092,7 +13092,7 @@ static void gen_rdhwr(DisasContext *ctx, int rt, in= t rd, int sel) gen_store_gpr(t0, rt); break; case 5: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_helper_rdhwr_xnp(t0, cpu_env); gen_store_gpr(t0, rt); break; @@ -15755,7 +15755,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) case 0x2c: switch (minor) { case BITSWAP: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_bitswap(ctx, OPC_BITSWAP, rs, rt); break; case SEB: @@ -15774,26 +15774,26 @@ static void gen_pool32axf(CPUMIPSState *env, Disa= sContext *ctx, int rt, int rs) gen_cl(ctx, mips32_op, rt, rs); break; case RDHWR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_rdhwr(ctx, rt, rs, 0); break; case WSBH: gen_bshfl(ctx, OPC_WSBH, rs, rt); break; case MULT: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MULT; goto do_mul; case MULTU: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MULTU; goto do_mul; case DIV: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_DIV; goto do_div; case DIVU: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_DIVU; goto do_div; do_div: @@ -15801,19 +15801,19 @@ static void gen_pool32axf(CPUMIPSState *env, Disa= sContext *ctx, int rt, int rs) gen_muldiv(ctx, mips32_op, 0, rs, rt); break; case MADD: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MADD; goto do_mul; case MADDU: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MADDU; goto do_mul; case MSUB: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MSUB; goto do_mul; case MSUBU: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MSUBU; do_mul: check_insn(ctx, ISA_MIPS_R1); @@ -15841,7 +15841,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) switch (minor) { case JALR: /* JALRC */ case JALR_HB: /* JALRC_HB */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* JALRC, JALRC_HB */ gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 0); } else { @@ -15852,7 +15852,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) break; case JALRS: case JALRS_HB: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_JALR, 4, rs, rt, 0, 2); ctx->hflags |=3D MIPS_HFLAG_BDS_STRICT; break; @@ -15995,7 +15995,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) } break; case 0x35: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); switch (minor) { case MFHI32: gen_HILO(ctx, OPC_MFHI, 0, rs); @@ -16269,7 +16269,7 @@ static void gen_pool32fxf(DisasContext *ctx, int rt= , int rs) case COND_FLOAT_MOV(MOVT, 5): case COND_FLOAT_MOV(MOVT, 6): case COND_FLOAT_MOV(MOVT, 7): - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 1); break; case COND_FLOAT_MOV(MOVF, 0): @@ -16280,7 +16280,7 @@ static void gen_pool32fxf(DisasContext *ctx, int rt= , int rs) case COND_FLOAT_MOV(MOVF, 5): case COND_FLOAT_MOV(MOVF, 6): case COND_FLOAT_MOV(MOVF, 7): - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_movci(ctx, rt, rs, (ctx->opcode >> 13) & 0x7, 0); break; default: @@ -16331,15 +16331,15 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) gen_shift_imm(ctx, mips32_op, rt, rs, rd); break; case SELEQZ: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_cond_move(ctx, OPC_SELEQZ, rd, rs, rt); break; case SELNEZ: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_cond_move(ctx, OPC_SELNEZ, rd, rs, rt); break; case R6_RDHWR: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_rdhwr(ctx, rt, rs, extract32(ctx->opcode, 11, 3)); break; default: @@ -16363,7 +16363,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) mips32_op =3D OPC_SUBU; goto do_arith; case MUL: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MUL; do_arith: gen_arith(ctx, mips32_op, rd, rs, rt); @@ -16416,7 +16416,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) switch (minor) { /* Conditional moves */ case MOVN: /* MUL */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* MUL */ gen_r6_muldiv(ctx, R6_OPC_MUL, rd, rs, rt); } else { @@ -16425,7 +16425,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case MOVZ: /* MUH */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* MUH */ gen_r6_muldiv(ctx, R6_OPC_MUH, rd, rs, rt); } else { @@ -16434,15 +16434,15 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) } break; case MULU: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_r6_muldiv(ctx, R6_OPC_MULU, rd, rs, rt); break; case MUHU: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_r6_muldiv(ctx, R6_OPC_MUHU, rd, rs, rt); break; case LWXS: /* DIV */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* DIV */ gen_r6_muldiv(ctx, R6_OPC_DIV, rd, rs, rt); } else { @@ -16451,15 +16451,15 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) } break; case MOD: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_r6_muldiv(ctx, R6_OPC_MOD, rd, rs, rt); break; case R6_DIVU: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_r6_muldiv(ctx, R6_OPC_DIVU, rd, rs, rt); break; case MODU: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_r6_muldiv(ctx, R6_OPC_MODU, rd, rs, rt); break; default: @@ -16470,11 +16470,11 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) gen_bitops(ctx, OPC_INS, rt, rs, rr, rd); return; case LSA: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_LSA(ctx, rd, rs, rt, extract32(ctx->opcode, 9, 2)); break; case ALIGN: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_align(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 9, 2)); break; case EXT: @@ -16487,7 +16487,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) generate_exception_end(ctx, EXCP_BREAK); break; case SIGRIE: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_reserved_instruction(ctx); break; default: @@ -16545,61 +16545,61 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) check_cp1_enabled(ctx); switch (minor) { case ALNV_PS: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_ALNV_PS; goto do_madd; case MADD_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MADD_S; goto do_madd; case MADD_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MADD_D; goto do_madd; case MADD_PS: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MADD_PS; goto do_madd; case MSUB_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MSUB_S; goto do_madd; case MSUB_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MSUB_D; goto do_madd; case MSUB_PS: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_MSUB_PS; goto do_madd; case NMADD_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_NMADD_S; goto do_madd; case NMADD_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_NMADD_D; goto do_madd; case NMADD_PS: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_NMADD_PS; goto do_madd; case NMSUB_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_NMSUB_S; goto do_madd; case NMSUB_D: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_NMSUB_D; goto do_madd; case NMSUB_PS: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_NMSUB_PS; do_madd: gen_flt3_arith(ctx, mips32_op, rd, rr, rs, rt); break; case CABS_COND_FMT: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); cond =3D (ctx->opcode >> 6) & 0xf; cc =3D (ctx->opcode >> 13) & 0x7; fmt =3D (ctx->opcode >> 10) & 0x3; @@ -16618,7 +16618,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case C_COND_FMT: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); cond =3D (ctx->opcode >> 6) & 0xf; cc =3D (ctx->opcode >> 13) & 0x7; fmt =3D (ctx->opcode >> 10) & 0x3; @@ -16637,11 +16637,11 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) } break; case CMP_CONDN_S: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_r6_cmp_s(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd); break; case CMP_CONDN_D: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_r6_cmp_d(ctx, (ctx->opcode >> 6) & 0x1f, rt, rs, rd); break; case POOL32FXF: @@ -16663,7 +16663,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) mips32_op =3D OPC_PUU_PS; goto do_ps; case CVT_PS_S: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_CVT_PS_S; do_ps: gen_farith(ctx, mips32_op, rt, rs, rd, 0); @@ -16673,7 +16673,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case MIN_FMT: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: gen_farith(ctx, OPC_MIN_S, rt, rs, rd, 0); @@ -16689,27 +16689,27 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) /* [LS][WDU]XC1 */ switch ((ctx->opcode >> 6) & 0x7) { case LWXC1: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_LWXC1; goto do_ldst_cp1; case SWXC1: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_SWXC1; goto do_ldst_cp1; case LDXC1: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_LDXC1; goto do_ldst_cp1; case SDXC1: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_SDXC1; goto do_ldst_cp1; case LUXC1: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_LUXC1; goto do_ldst_cp1; case SUXC1: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_SUXC1; do_ldst_cp1: gen_flt3_ldst(ctx, mips32_op, rd, rd, rt, rs); @@ -16719,7 +16719,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case MAX_FMT: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: gen_farith(ctx, OPC_MAX_S, rt, rs, rd, 0); @@ -16733,7 +16733,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) break; case 0x18: /* 3D insns */ - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); fmt =3D (ctx->opcode >> 9) & 0x3; switch ((ctx->opcode >> 6) & 0x7) { case RSQRT2_FMT: @@ -16784,7 +16784,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) fmt =3D (ctx->opcode >> 9) & 0x3; switch ((ctx->opcode >> 6) & 0x7) { case MOVF_FMT: /* RINT_FMT */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* RINT_FMT */ switch (fmt) { case FMT_SDPS_S: @@ -16815,7 +16815,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case MOVT_FMT: /* CLASS_FMT */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* CLASS_FMT */ switch (fmt) { case FMT_SDPS_S: @@ -16846,7 +16846,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case PREFX: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); break; default: goto pool32f_invalid; @@ -16868,7 +16868,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) goto pool32f_invalid; \ } case MINA_FMT: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: gen_farith(ctx, OPC_MINA_S, rt, rs, rd, 0); @@ -16881,7 +16881,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case MAXA_FMT: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: gen_farith(ctx, OPC_MAXA_S, rt, rs, rd, 0); @@ -16923,7 +16923,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) /* cmovs */ switch ((ctx->opcode >> 6) & 0x7) { case MOVN_FMT: /* SELEQZ_FMT */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* SELEQZ_FMT */ switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: @@ -16941,11 +16941,11 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) } break; case MOVN_FMT_04: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); FINSN_3ARG_SDPS(MOVN); break; case MOVZ_FMT: /* SELNEZ_FMT */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* SELNEZ_FMT */ switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: @@ -16963,11 +16963,11 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) } break; case MOVZ_FMT_05: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); FINSN_3ARG_SDPS(MOVZ); break; case SEL_FMT: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: gen_sel_s(ctx, OPC_SEL_S, rd, rt, rs); @@ -16980,7 +16980,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case MADDF_FMT: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: mips32_op =3D OPC_MADDF_S; @@ -16993,7 +16993,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case MSUBF_FMT: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); switch ((ctx->opcode >> 9) & 0x3) { case FMT_SDPS_S: mips32_op =3D OPC_MSUBF_S; @@ -17026,45 +17026,45 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) minor =3D (ctx->opcode >> 21) & 0x1f; switch (minor) { case BLTZ: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BLTZ, 4, rs, -1, imm << 1, 4); break; case BLTZAL: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 4); ctx->hflags |=3D MIPS_HFLAG_BDS_STRICT; break; case BLTZALS: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BLTZAL, 4, rs, -1, imm << 1, 2); ctx->hflags |=3D MIPS_HFLAG_BDS_STRICT; break; case BGEZ: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BGEZ, 4, rs, -1, imm << 1, 4); break; case BGEZAL: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 4); ctx->hflags |=3D MIPS_HFLAG_BDS_STRICT; break; case BGEZALS: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BGEZAL, 4, rs, -1, imm << 1, 2); ctx->hflags |=3D MIPS_HFLAG_BDS_STRICT; break; case BLEZ: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BLEZ, 4, rs, -1, imm << 1, 4); break; case BGTZ: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, OPC_BGTZ, 4, rs, -1, imm << 1, 4); break; =20 /* Traps */ case TLTI: /* BC1EQZC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* BC1EQZC */ check_cp1_enabled(ctx); gen_compute_branch1_r6(ctx, OPC_BC1EQZ, rs, imm << 1, 0); @@ -17075,7 +17075,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case TGEI: /* BC1NEZC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* BC1NEZC */ check_cp1_enabled(ctx); gen_compute_branch1_r6(ctx, OPC_BC1NEZ, rs, imm << 1, 0); @@ -17086,15 +17086,15 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) } break; case TLTIU: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_TLTIU; goto do_trapi; case TGEIU: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_TGEIU; goto do_trapi; case TNEI: /* SYNCI */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* SYNCI */ /* * Break the TB to be able to sync copied instructions @@ -17108,7 +17108,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case TEQI: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_TEQI; do_trapi: gen_trap(ctx, mips32_op, rs, -1, imm); @@ -17116,7 +17116,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) =20 case BNEZC: case BEQZC: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch(ctx, minor =3D=3D BNEZC ? OPC_BNE : OPC_BEQ, 4, rs, 0, imm << 1, 0); /* @@ -17126,11 +17126,11 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) */ break; case LUI: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_logic_imm(ctx, OPC_LUI, rs, 0, imm); break; case SYNCI: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* * Break the TB to be able to sync copied instructions * immediately. @@ -17139,24 +17139,24 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) break; case BC2F: case BC2T: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* COP2: Not implemented. */ generate_exception_err(ctx, EXCP_CpU, 2); break; case BC1F: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D (ctx->opcode & (1 << 16)) ? OPC_BC1FANY2 : OPC_B= C1F; goto do_cp1branch; case BC1T: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D (ctx->opcode & (1 << 16)) ? OPC_BC1TANY2 : OPC_B= C1T; goto do_cp1branch; case BC1ANY4F: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_BC1FANY4; goto do_cp1mips3d; case BC1ANY4T: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_BC1TANY4; do_cp1mips3d: check_cop1x(ctx); @@ -17184,47 +17184,47 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) case POOL32C: minor =3D (ctx->opcode >> 12) & 0xf; offset =3D sextract32(ctx->opcode, 0, - (ctx->insn_flags & ISA_MIPS32R6) ? 9 : 12); + (ctx->insn_flags & ISA_MIPS_R6) ? 9 : 12); switch (minor) { case LWL: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_LWL; goto do_ld_lr; case SWL: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_SWL; goto do_st_lr; case LWR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_LWR; goto do_ld_lr; case SWR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_SWR; goto do_st_lr; #if defined(TARGET_MIPS64) case LDL: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_LDL; goto do_ld_lr; case SDL: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_SDL; goto do_st_lr; case LDR: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_LDR; goto do_ld_lr; case SDR: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_SDR; goto do_st_lr; case LWU: @@ -17275,11 +17275,11 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) mips32_op =3D OPC_LHUE; goto do_ld_lr; case LWLE: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_LWLE; goto do_ld_lr; case LWRE: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_LWRE; goto do_ld_lr; case LBE: @@ -17308,16 +17308,16 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) offset =3D sextract32(ctx->opcode, 0, 9); switch (minor2) { case SWLE: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_SWLE; goto do_st_lr; case SWRE: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); mips32_op =3D OPC_SWRE; goto do_st_lr; case PREFE: /* Treat as no-op */ - if ((ctx->insn_flags & ISA_MIPS32R6) && (rt >=3D 24)) { + if ((ctx->insn_flags & ISA_MIPS_R6) && (rt >=3D 24)) { /* hint codes 24-31 are reserved and signal RI */ generate_exception(ctx, EXCP_RI); } @@ -17344,7 +17344,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) break; case PREF: /* Treat as no-op */ - if ((ctx->insn_flags & ISA_MIPS32R6) && (rt >=3D 24)) { + if ((ctx->insn_flags & ISA_MIPS_R6) && (rt >=3D 24)) { /* hint codes 24-31 are reserved and signal RI */ generate_exception(ctx, EXCP_RI); } @@ -17356,7 +17356,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case ADDI32: /* AUI, LUI */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* AUI, LUI */ gen_logic_imm(ctx, OPC_LUI, rt, rs, imm); } else { @@ -17394,13 +17394,13 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) gen_slt_imm(ctx, mips32_op, rt, rs, imm); break; case JALX32: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); offset =3D (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; gen_compute_branch(ctx, OPC_JALX, 4, rt, rs, offset, 4); ctx->hflags |=3D MIPS_HFLAG_BDS_STRICT; break; case JALS32: /* BOVC, BEQC, BEQZALC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { if (rs >=3D rt) { /* BOVC */ mips32_op =3D OPC_BOVC; @@ -17420,7 +17420,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case BEQ32: /* BC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* BC */ gen_compute_compact_branch(ctx, OPC_BC, 0, 0, sextract32(ctx->opcode << 1, 0, 27)= ); @@ -17430,7 +17430,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case BNE32: /* BALC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* BALC */ gen_compute_compact_branch(ctx, OPC_BALC, 0, 0, sextract32(ctx->opcode << 1, 0, 27)= ); @@ -17440,7 +17440,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case J32: /* BGTZC, BLTZC, BLTC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { if (rs =3D=3D 0 && rt !=3D 0) { /* BGTZC */ mips32_op =3D OPC_BGTZC; @@ -17459,7 +17459,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case JAL32: /* BLEZC, BGEZC, BGEC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { if (rs =3D=3D 0 && rt !=3D 0) { /* BLEZC */ mips32_op =3D OPC_BLEZC; @@ -17494,7 +17494,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) gen_cop1_ldst(ctx, mips32_op, rt, rs, imm); break; case ADDIUPC: /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */ switch ((ctx->opcode >> 16) & 0x1f) { case ADDIUPC_00: @@ -17536,7 +17536,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case BNVC: /* BNEC, BNEZALC */ - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (rs >=3D rt) { /* BNVC */ mips32_op =3D OPC_BNVC; @@ -17550,7 +17550,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1); break; case R6_BNEZC: /* JIALC */ - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (rt !=3D 0) { /* BNEZC */ gen_compute_compact_branch(ctx, OPC_BNEZC, rt, 0, @@ -17561,7 +17561,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case R6_BEQZC: /* JIC */ - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (rt !=3D 0) { /* BEQZC */ gen_compute_compact_branch(ctx, OPC_BEQZC, rt, 0, @@ -17572,7 +17572,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) } break; case BLEZALC: /* BGEZALC, BGEUC */ - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (rs =3D=3D 0 && rt !=3D 0) { /* BLEZALC */ mips32_op =3D OPC_BLEZALC; @@ -17586,7 +17586,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) gen_compute_compact_branch(ctx, mips32_op, rs, rt, imm << 1); break; case BGTZALC: /* BLTZALC, BLTUC */ - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (rs =3D=3D 0 && rt !=3D 0) { /* BGTZALC */ mips32_op =3D OPC_BGTZALC; @@ -17708,7 +17708,7 @@ static int decode_micromips_opc(CPUMIPSState *env, = DisasContext *ctx) opc =3D OPC_SUBU; break; } - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* * In the Release 6, the register number location in * the instruction encoding has changed. @@ -17740,7 +17740,7 @@ static int decode_micromips_opc(CPUMIPSState *env, = DisasContext *ctx) } break; case POOL16C: - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { gen_pool16c_r6_insn(ctx); } else { gen_pool16c_insn(ctx); @@ -17756,7 +17756,7 @@ static int decode_micromips_opc(CPUMIPSState *env, = DisasContext *ctx) } break; case POOL16F: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->opcode & 1) { gen_reserved_instruction(ctx); } else { @@ -17874,14 +17874,14 @@ static int decode_micromips_opc(CPUMIPSState *env= , DisasContext *ctx) case B16: /* BC16 */ gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0, sextract32(ctx->opcode, 0, 10) << 1, - (ctx->insn_flags & ISA_MIPS32R6) ? 0 : 4); + (ctx->insn_flags & ISA_MIPS_R6) ? 0 : 4); break; case BNEZ16: /* BNEZC16 */ case BEQZ16: /* BEQZC16 */ gen_compute_branch(ctx, op =3D=3D BNEZ16 ? OPC_BNE : OPC_BEQ, 2, mmreg(uMIPS_RD(ctx->opcode)), 0, sextract32(ctx->opcode, 0, 7) << 1, - (ctx->insn_flags & ISA_MIPS32R6) ? 0 : 4); + (ctx->insn_flags & ISA_MIPS_R6) ? 0 : 4); =20 break; case LI16: @@ -24563,7 +24563,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) case OPC_SLL: /* Shift with immediate */ if (sa =3D=3D 5 && rd =3D=3D 0 && rs =3D=3D 0 && rt =3D=3D 0) { /* PAUSE */ - if ((ctx->insn_flags & ISA_MIPS32R6) && + if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { gen_reserved_instruction(ctx); break; @@ -24638,7 +24638,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) gen_trap(ctx, op1, rs, rt, -1); break; case OPC_LSA: /* OPC_PMON */ - if ((ctx->insn_flags & ISA_MIPS32R6) || ase_msa_available(env)) { + if ((ctx->insn_flags & ISA_MIPS_R6) || ase_msa_available(env)) { decode_opc_special_r6(env, ctx); } else { /* Pmon entry point, also R4010 selsl */ @@ -24740,13 +24740,13 @@ static void decode_opc_special(CPUMIPSState *env,= DisasContext *ctx) } break; case OPC_DLSA: - if ((ctx->insn_flags & ISA_MIPS32R6) || ase_msa_available(env)) { + if ((ctx->insn_flags & ISA_MIPS_R6) || ase_msa_available(env)) { decode_opc_special_r6(env, ctx); } break; #endif default: - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { decode_opc_special_r6(env, ctx); } else if (ctx->insn_flags & INSN_R5900) { decode_opc_special_tx79(env, ctx); @@ -27156,7 +27156,7 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) int rs, rt, rd; uint32_t op1; =20 - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); =20 rs =3D (ctx->opcode >> 21) & 0x1f; rt =3D (ctx->opcode >> 16) & 0x1f; @@ -28143,7 +28143,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) switch (op1) { case OPC_LWLE: case OPC_LWRE: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* fall through */ case OPC_LBUE: case OPC_LHUE: @@ -28156,7 +28156,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) return; case OPC_SWLE: case OPC_SWRE: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* fall through */ case OPC_SBE: case OPC_SHE: @@ -28196,7 +28196,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) case OPC_ALIGN_2: case OPC_ALIGN_3: case OPC_BITSWAP: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); decode_opc_special3_r6(env, ctx); break; default: @@ -28228,7 +28228,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) case OPC_DALIGN_6: case OPC_DALIGN_7: case OPC_DBITSWAP: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); decode_opc_special3_r6(env, ctx); break; default: @@ -28268,7 +28268,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) } break; default: - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { decode_opc_special3_r6(env, ctx); } else { decode_opc_special3_legacy(env, ctx); @@ -28324,7 +28324,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) case OPC_BLTZALL: case OPC_BGEZALL: check_insn(ctx, ISA_MIPS2); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* Fallthrough */ case OPC_BLTZ: case OPC_BGEZ: @@ -28332,7 +28332,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) break; case OPC_BLTZAL: case OPC_BGEZAL: - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { if (rs =3D=3D 0) { /* OPC_NAL, OPC_BAL */ gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2, 4); @@ -28351,11 +28351,11 @@ static bool decode_opc_legacy(CPUMIPSState *env, = DisasContext *ctx) =20 case OPC_TNEI: check_insn(ctx, ISA_MIPS2); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_trap(ctx, op1, rs, -1, imm); break; case OPC_SIGRIE: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_reserved_instruction(ctx); break; case OPC_SYNCI: @@ -28375,14 +28375,14 @@ static bool decode_opc_legacy(CPUMIPSState *env, = DisasContext *ctx) break; #if defined(TARGET_MIPS64) case OPC_DAHI: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); check_mips_64(ctx); if (rs !=3D 0) { tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << = 32); } break; case OPC_DATI: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); check_mips_64(ctx); if (rs !=3D 0) { tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << = 48); @@ -28462,14 +28462,14 @@ static bool decode_opc_legacy(CPUMIPSState *env, = DisasContext *ctx) gen_store_gpr(t0, rt); break; case OPC_DVP: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (ctx->vp) { gen_helper_dvp(t0, cpu_env); gen_store_gpr(t0, rt); } break; case OPC_EVP: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); if (ctx->vp) { gen_helper_evp(t0, cpu_env); gen_store_gpr(t0, rt); @@ -28522,7 +28522,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) } break; case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC, OPC_ADDI */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_BOVC, OPC_BEQZALC, OPC_BEQC */ gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); } else { @@ -28551,7 +28551,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) break; /* Branch */ case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC, OPC_BLEZL */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { if (rt =3D=3D 0) { gen_reserved_instruction(ctx); break; @@ -28564,7 +28564,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) } break; case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC, OPC_BGTZL */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { if (rt =3D=3D 0) { gen_reserved_instruction(ctx); break; @@ -28581,7 +28581,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) /* OPC_BLEZ */ gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4); } else { - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); /* OPC_BLEZALC, OPC_BGEZALC, OPC_BGEUC */ gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); } @@ -28591,7 +28591,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) /* OPC_BGTZ */ gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4); } else { - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); /* OPC_BGTZALC, OPC_BLTZALC, OPC_BLTUC */ gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); } @@ -28599,7 +28599,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) case OPC_BEQL: case OPC_BNEL: check_insn(ctx, ISA_MIPS2); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* Fallthrough */ case OPC_BEQ: case OPC_BNE: @@ -28613,7 +28613,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) /* Fallthrough */ case OPC_LWL: case OPC_LWR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* Fallthrough */ case OPC_LB: case OPC_LH: @@ -28625,7 +28625,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) break; case OPC_SWL: case OPC_SWR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* fall through */ case OPC_SB: case OPC_SH: @@ -28634,14 +28634,14 @@ static bool decode_opc_legacy(CPUMIPSState *env, = DisasContext *ctx) break; case OPC_SC: check_insn(ctx, ISA_MIPS2); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->insn_flags & INSN_R5900) { check_insn_opc_user_only(ctx, INSN_R5900); } gen_st_cond(ctx, rt, rs, imm, MO_TESL, false); break; case OPC_CACHE: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); check_cp0_enabled(ctx); check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1); if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { @@ -28650,7 +28650,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) /* Treat as NOP. */ break; case OPC_PREF: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->insn_flags & INSN_R5900) { /* Treat as NOP. */ } else { @@ -28694,7 +28694,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) #endif case OPC_BC1EQZ: /* OPC_BC1ANY2 */ check_cp1_enabled(ctx); - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_BC1EQZ */ gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode), rt, imm << 2, 4); @@ -28708,19 +28708,19 @@ static bool decode_opc_legacy(CPUMIPSState *env, = DisasContext *ctx) break; case OPC_BC1NEZ: check_cp1_enabled(ctx); - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode), rt, imm << 2, 4); break; case OPC_BC1ANY4: check_cp1_enabled(ctx); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); check_cop1x(ctx); check_insn(ctx, ASE_MIPS3D); /* fall through */ case OPC_BC1: check_cp1_enabled(ctx); - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); gen_compute_branch1(ctx, MASK_BC1(ctx->opcode), (rt >> 2) & 0x7, imm << 2); break; @@ -28738,7 +28738,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) { int r6_op =3D ctx->opcode & FOP(0x3f, 0x1f); check_cp1_enabled(ctx); - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { switch (r6_op) { case R6_OPC_CMP_AF_S: case R6_OPC_CMP_UN_S: @@ -28810,7 +28810,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) /* Compact branches [R6] and COP2 [non-R6] */ case OPC_BC: /* OPC_LWC2 */ case OPC_BALC: /* OPC_SWC2 */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_BC, OPC_BALC */ gen_compute_compact_branch(ctx, op, 0, 0, sextract32(ctx->opcode << 2, 0, 28)= ); @@ -28824,7 +28824,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) break; case OPC_BEQZC: /* OPC_JIC, OPC_LDC2 */ case OPC_BNEZC: /* OPC_JIALC, OPC_SDC2 */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { if (rs !=3D 0) { /* OPC_BEQZC, OPC_BNEZC */ gen_compute_compact_branch(ctx, op, rs, 0, @@ -28848,7 +28848,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) break; =20 case OPC_CP3: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { check_cp1_enabled(ctx); op1 =3D MASK_CP3(ctx->opcode); @@ -28905,7 +28905,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) /* fall through */ case OPC_LDL: case OPC_LDR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* fall through */ case OPC_LWU: case OPC_LD: @@ -28915,7 +28915,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) break; case OPC_SDL: case OPC_SDR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); /* fall through */ case OPC_SD: check_insn(ctx, ISA_MIPS3); @@ -28923,7 +28923,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) gen_st(ctx, op, rt, rs, imm); break; case OPC_SCD: - check_insn_opc_removed(ctx, ISA_MIPS32R6); + check_insn_opc_removed(ctx, ISA_MIPS_R6); check_insn(ctx, ISA_MIPS3); if (ctx->insn_flags & INSN_R5900) { check_insn_opc_user_only(ctx, INSN_R5900); @@ -28932,7 +28932,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) gen_st_cond(ctx, rt, rs, imm, MO_TEQ, false); break; case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { /* OPC_BNVC, OPC_BNEZALC, OPC_BNEC */ gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); } else { @@ -28949,7 +28949,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) break; #else case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); } else { MIPS_INVAL("major opcode"); @@ -28958,7 +28958,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) break; #endif case OPC_DAUI: /* OPC_JALX */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if (ctx->insn_flags & ISA_MIPS_R6) { #if defined(TARGET_MIPS64) /* OPC_DAUI */ check_mips_64(ctx); @@ -28991,7 +28991,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) } break; case OPC_PCREL: - check_insn(ctx, ISA_MIPS32R6); + check_insn(ctx, ISA_MIPS_R6); gen_pcrel(ctx, ctx->opcode, ctx->base.pc_next, rs); break; default: /* Invalid */ @@ -29078,7 +29078,7 @@ static void mips_tr_init_disas_context(DisasContext= Base *dcbase, CPUState *cs) #else ctx->mem_idx =3D hflags_mmu_index(ctx->hflags); #endif - ctx->default_tcg_memop_mask =3D (ctx->insn_flags & (ISA_MIPS32R6 | + ctx->default_tcg_memop_mask =3D (ctx->insn_flags & (ISA_MIPS_R6 | INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN; =20 LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx, --=20 2.26.2