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Tue, 15 Dec 2020 18:02:54 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 08/15] target/riscv: rvb: single-bit instructions Date: Wed, 16 Dec 2020 10:01:33 +0800 Message-Id: <20201216020150.3157-9-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201216020150.3157-1-frank.chang@sifive.com> References: <20201216020150.3157-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=frank.chang@sifive.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Alistair Francis , Palmer Dabbelt , Kito Cheng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang --- target/riscv/insn32-64.decode | 8 ++ target/riscv/insn32.decode | 9 +++ target/riscv/insn_trans/trans_rvb.c.inc | 90 +++++++++++++++++++++ target/riscv/translate.c | 102 ++++++++++++++++++++++++ 4 files changed, 209 insertions(+) diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index fd7e0492372..e2490f791b7 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -94,3 +94,11 @@ pcntw 0110000 00010 ..... 001 ..... 0011011 @r2 =20 packw 0000100 .......... 100 ..... 0111011 @r packuw 0100100 .......... 100 ..... 0111011 @r +sbsetw 0010100 .......... 001 ..... 0111011 @r +sbclrw 0100100 .......... 001 ..... 0111011 @r +sbinvw 0110100 .......... 001 ..... 0111011 @r +sbextw 0100100 .......... 101 ..... 0111011 @r + +sbsetiw 0010100 .......... 001 ..... 0011011 @sh5 +sbclriw 0100100 .......... 001 ..... 0011011 @sh5 +sbinviw 0110100 .......... 001 ..... 0011011 @sh5 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 4baafed21f1..c697ff5c867 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -611,3 +611,12 @@ min 0000101 .......... 100 ..... 0110011 @r minu 0000101 .......... 101 ..... 0110011 @r max 0000101 .......... 110 ..... 0110011 @r maxu 0000101 .......... 111 ..... 0110011 @r +sbset 0010100 .......... 001 ..... 0110011 @r +sbclr 0100100 .......... 001 ..... 0110011 @r +sbinv 0110100 .......... 001 ..... 0110011 @r +sbext 0100100 .......... 101 ..... 0110011 @r + +sbseti 00101. ........... 001 ..... 0010011 @sh +sbclri 01001. ........... 001 ..... 0010011 @sh +sbinvi 01101. ........... 001 ..... 0010011 @sh +sbexti 01001. ........... 101 ..... 0010011 @sh diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index 5ea0f0ff81c..43e9b670f73 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -107,6 +107,54 @@ static bool trans_sext_h(DisasContext *ctx, arg_sext_h= *a) return gen_unary(ctx, a, &tcg_gen_ext16s_tl); } =20 +static bool trans_sbset(DisasContext *ctx, arg_sbset *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shift(ctx, a, &gen_sbset); +} + +static bool trans_sbseti(DisasContext *ctx, arg_sbseti *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shifti(ctx, a, &gen_sbset); +} + +static bool trans_sbclr(DisasContext *ctx, arg_sbclr *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shift(ctx, a, &gen_sbclr); +} + +static bool trans_sbclri(DisasContext *ctx, arg_sbclri *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shifti(ctx, a, &gen_sbclr); +} + +static bool trans_sbinv(DisasContext *ctx, arg_sbinv *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shift(ctx, a, &gen_sbinv); +} + +static bool trans_sbinvi(DisasContext *ctx, arg_sbinvi *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shifti(ctx, a, &gen_sbinv); +} + +static bool trans_sbext(DisasContext *ctx, arg_sbext *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shift(ctx, a, &gen_sbext); +} + +static bool trans_sbexti(DisasContext *ctx, arg_sbexti *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shifti(ctx, a, &gen_sbext); +} + { /* RV64-only instructions */ #ifdef TARGET_RISCV64 @@ -141,4 +189,46 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw= *a) return gen_arith(ctx, a, &gen_packuw); } =20 +static bool trans_sbsetw(DisasContext *ctx, arg_sbsetw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shiftw(ctx, a, &gen_sbset); +} + +static bool trans_sbsetiw(DisasContext *ctx, arg_sbsetiw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shiftiw(ctx, a, &gen_sbset); +} + +static bool trans_sbclrw(DisasContext *ctx, arg_sbclrw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shiftw(ctx, a, &gen_sbclr); +} + +static bool trans_sbclriw(DisasContext *ctx, arg_sbclriw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shiftiw(ctx, a, &gen_sbclr); +} + +static bool trans_sbinvw(DisasContext *ctx, arg_sbinvw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shiftw(ctx, a, &gen_sbinv); +} + +static bool trans_sbinviw(DisasContext *ctx, arg_sbinviw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shiftiw(ctx, a, &gen_sbinv); +} + +static bool trans_sbextw(DisasContext *ctx, arg_sbextw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shiftw(ctx, a, &gen_sbext); +} + #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 7b427a9caec..ca176709674 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -755,6 +755,48 @@ static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2) tcg_temp_free(t); } =20 +static void gen_sbop_mask(TCGv ret, TCGv shamt) +{ + tcg_gen_movi_tl(ret, 1); + tcg_gen_shl_tl(ret, ret, shamt); +} + +static void gen_sbset(TCGv ret, TCGv arg1, TCGv shamt) +{ + TCGv t =3D tcg_temp_new(); + + gen_sbop_mask(t, shamt); + tcg_gen_or_tl(ret, arg1, t); + + tcg_temp_free(t); +} + +static void gen_sbclr(TCGv ret, TCGv arg1, TCGv shamt) +{ + TCGv t =3D tcg_temp_new(); + + gen_sbop_mask(t, shamt); + tcg_gen_andc_tl(ret, arg1, t); + + tcg_temp_free(t); +} + +static void gen_sbinv(TCGv ret, TCGv arg1, TCGv shamt) +{ + TCGv t =3D tcg_temp_new(); + + gen_sbop_mask(t, shamt); + tcg_gen_xor_tl(ret, arg1, t); + + tcg_temp_free(t); +} + +static void gen_sbext(TCGv ret, TCGv arg1, TCGv shamt) +{ + tcg_gen_shr_tl(ret, arg1, shamt); + tcg_gen_andi_tl(ret, ret, 1); +} + =20 #ifdef TARGET_RISCV64 =20 @@ -832,6 +874,66 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, return true; } =20 +static bool gen_shifti(DisasContext *ctx, arg_shift *a, + void(*func)(TCGv, TCGv, TCGv)) +{ + TCGv source1 =3D tcg_temp_new(); + TCGv source2 =3D tcg_temp_new(); + + gen_get_gpr(source1, a->rs1); + tcg_gen_movi_tl(source2, a->shamt); + + tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1); + (*func)(source1, source1, source2); + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + tcg_temp_free(source2); + return true; +} + +#ifdef TARGET_RISCV64 + +static bool gen_shiftw(DisasContext *ctx, arg_r *a, + void(*func)(TCGv, TCGv, TCGv)) +{ + TCGv source1 =3D tcg_temp_new(); + TCGv source2 =3D tcg_temp_new(); + + gen_get_gpr(source1, a->rs1); + gen_get_gpr(source2, a->rs2); + + tcg_gen_andi_tl(source2, source2, 31); + (*func)(source1, source1, source2); + tcg_gen_ext32s_tl(source1, source1); + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + tcg_temp_free(source2); + return true; +} + +static bool gen_shiftiw(DisasContext *ctx, arg_shift *a, + void(*func)(TCGv, TCGv, TCGv)) +{ + TCGv source1 =3D tcg_temp_new(); + TCGv source2 =3D tcg_temp_new(); + + gen_get_gpr(source1, a->rs1); + tcg_gen_movi_tl(source2, a->shamt); + + tcg_gen_andi_tl(source2, source2, 31); + (*func)(source1, source1, source2); + tcg_gen_ext32s_tl(source1, source1); + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + tcg_temp_free(source2); + return true; +} + +#endif + static void gen_ctz(TCGv ret, TCGv arg1) { tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS); --=20 2.17.1