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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id a13sm289150pfr.59.2020.12.15.18.04.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 18:04:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+CWaIlbPzrY451DhxfSimx4EEc+YfrZK05ZurdY+u+Q=; b=UZUZ+dORZNY7hg4SBRL9soUYrZi/FL6QOT8HmWhInOPAmZU3SnH86t+U8k4X+o5tlu CtTtZsVF9PtRVdMKyFCVq5j9bSBnVYjq2j2/T3mJPPBQDB/dnunbbr2hDkIdLazXk+t4 ndffAirt2E2frIKT5NqmK42SBqq0o71/lIuOlLKJQP77I2cfFrXBfoQamLFcVs21fKFe 3Gzy6SbkvVMw4xKB8b2VYNK2JzbLR1MfeCeG5+vrExGJ9yk/J9BuklimsXX6uKDOBF/4 2TqOLtuG3a0P7mJM7MZgKeQMLxQkHYvtI1ziAomMugfua5+ZHtVDVRBT1jN03ybnCDW0 EizQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+CWaIlbPzrY451DhxfSimx4EEc+YfrZK05ZurdY+u+Q=; b=V9KXXDxHv6AezcGXQPZAAz/1tjEK5Cd4AdCDTfmpZxCAeP7muEWJSlHu9/Z+FYAhGx VcwOWOEkaSoIAQHwlsX1Pxb15wE795JA7vcpA6vLY/hFJ/J7xgInr1H37MDj+6KSX+8O XnIk9lK5a1Bp1neSyxMalU5fvhuOQWyWO3wlFeJn1tc7XW5E218+l/fJAN/3Ow88VWFx O1/7OoRPajz7vpcNubOCUpK0JkFGO21rz4be4F3atlvgy9Iyb9Y8ZvGPUKlkrqmG+q7Q ikyLb3KY/USpRFKJqL3vVotMhrJEqoSUIEgDnXTMhVRfgyAgJr/ZHg+x6pHRdjlKuxNw XvAA== X-Gm-Message-State: AOAM5336QzWyP/H8UA+y8cnNg2QNBjssGn0kobux4uo6Rk5yGXls1pD6 Xwb21ei7O94+N0dkhWihxzGrnbeaz3HrMLXn4F4= X-Google-Smtp-Source: ABdhPJwwQvotbGA0qJVwAgpoKnZU/WiL1oEoLFy/RNH+pNPObuWmwFU4SPlZ3UyQUgSLVJTX6wMppA== X-Received: by 2002:a17:90a:eac5:: with SMTP id ev5mr1205567pjb.65.1608084285859; Tue, 15 Dec 2020 18:04:45 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 15/15] target/riscv: rvb: support and turn on B-extension from command line Date: Wed, 16 Dec 2020 10:01:40 +0800 Message-Id: <20201216020150.3157-16-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201216020150.3157-1-frank.chang@sifive.com> References: <20201216020150.3157-1-frank.chang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Alistair Francis , Palmer Dabbelt , Kito Cheng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Kito Cheng B-extension is default off, use cpu rv32 or rv64 with x-b=3Dtrue to enable B-extension. Signed-off-by: Kito Cheng Signed-off-by: Frank Chang --- target/riscv/cpu.c | 4 ++++ target/riscv/cpu.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6a0264fc6b1..33fa112c4ac 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -441,6 +441,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) if (cpu->cfg.ext_h) { target_misa |=3D RVH; } + if (cpu->cfg.ext_b) { + target_misa |=3D RVB; + } if (cpu->cfg.ext_v) { target_misa |=3D RVV; if (!is_power_of_2(cpu->cfg.vlen)) { @@ -511,6 +514,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), /* This is experimental so mark with 'x-' */ + DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false), DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c0a326c8430..4868f62f32b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -66,6 +66,7 @@ #define RVS RV('S') #define RVU RV('U') #define RVH RV('H') +#define RVB RV('B') =20 /* S extension denotes that Supervisor mode exists, however it is possible to have a core that support S mode but does not have an MMU and there @@ -276,6 +277,7 @@ struct RISCVCPU { bool ext_f; bool ext_d; bool ext_c; + bool ext_b; bool ext_s; bool ext_u; bool ext_h; --=20 2.17.1