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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id f20sm8514210edx.92.2020.12.15.14.58.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 14:58:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nIvvusNJm60WWqveYR8Cj3EE3xSaf0EEqwOHmNBN40o=; b=rE1wg4s+BQFCEk8G4qW/EZvLlvRn6pVxQO3rKh4VPhBKrCVG/5yqEwoiblwqOAVg+s 1jKsfSERkOnk3qfv8sVj922EN1A+gxv1DwbsZUIgZHOBv+BNMQu+6ohBNFP3RnovvOj9 zdyVuynSE1umCq28i/rSVXS5jcEkECpHS2kohBMsXcdYTT8lV+AEga+bmJkpBPnSyWEl y3VaMmRFsjzHzim7xhbqmXib/rnEdeYVp7dPdzpjnLSgh7ViyON5jFRke9Pf8B1deDuj z0dFvMtjfL3QZy1GJxE5hhfYq/jO+10+I6BjV0/xVVDbTYHvVBr90l4FPpqIMxnY9PBn 5atQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=nIvvusNJm60WWqveYR8Cj3EE3xSaf0EEqwOHmNBN40o=; b=eom3eDLjPlzkeeTgsqrTWUE0u+zhux4Nz3jP4QJiwO4+9hkEyCVT4mKS7eLDM92koT jjFsWN+F6RQhIHvZksbjeBLB9m7tO5eVwkWgxbleB9xTdJSXlwoIqAImSl68RwZfHhyN G2Uk38Uk1kY+4G5WuyHRzbi1Opt9oxRHXyQDogAzKGGZOa2wuSB6Z6YHSNjfIr/O1SIY LnyaFNFc9PWgLRIe/AFYQycgnPvJmdCWRsIvjf6Y1nRRAS9pqUb1oOaHlFlDF3g/swvY jh/1Z2Jqg2i5FCKVHK7i9c6ljV4h3IaVaCWK1XzXQrAMUFP8z0WDc+tDBv5SPUMx7NB1 SNuQ== X-Gm-Message-State: AOAM532EA3mzV67nKCVMoaHQ5DUbIoIlb9swtFcejZpA2H3GbPnlmi13 NuwumC6bBCF+5WeV9Knjjk8= X-Google-Smtp-Source: ABdhPJyJfKCLWMingZozHIiLHLT59KgzZqGQr2a+zB0lXaXEIGcuoBun5nXBUlkaB1EB0fOznCztLA== X-Received: by 2002:a17:906:2c54:: with SMTP id f20mr4559736ejh.318.1608073091601; Tue, 15 Dec 2020 14:58:11 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aleksandar Rikalo , Paolo Bonzini , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen Subject: [PATCH v2 02/24] target/mips/translate: Expose check_mips_64() to 32-bit mode Date: Tue, 15 Dec 2020 23:57:35 +0100 Message-Id: <20201215225757.764263-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215225757.764263-1-f4bug@amsat.org> References: <20201215225757.764263-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) To allow compiling 64-bit specific translation code more generically (and removing #ifdef'ry), allow compiling check_mips_64() on 32-bit targets. If ever called on 32-bit, we obviously emit a reserved instruction exception. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jiaxun Yang --- target/mips/translate.h | 2 -- target/mips/translate.c | 8 +++----- 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index a9eab69249f..942d803476c 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -127,9 +127,7 @@ void generate_exception_err(DisasContext *ctx, int excp= , int err); void generate_exception_end(DisasContext *ctx, int excp); void gen_reserved_instruction(DisasContext *ctx); void check_insn(DisasContext *ctx, uint64_t flags); -#ifdef TARGET_MIPS64 void check_mips_64(DisasContext *ctx); -#endif void check_cp1_enabled(DisasContext *ctx); =20 void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offs= et); diff --git a/target/mips/translate.c b/target/mips/translate.c index 5c62b32c6ae..af543d1f375 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2972,18 +2972,16 @@ static inline void check_ps(DisasContext *ctx) check_cp1_64bitmode(ctx); } =20 -#ifdef TARGET_MIPS64 /* - * This code generates a "reserved instruction" exception if 64-bit - * instructions are not enabled. + * This code generates a "reserved instruction" exception if cpu is not + * 64-bit or 64-bit instructions are not enabled. */ void check_mips_64(DisasContext *ctx) { - if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) { + if (unlikely((TARGET_LONG_BITS !=3D 64) || !(ctx->hflags & MIPS_HFLAG_= 64))) { gen_reserved_instruction(ctx); } } -#endif =20 #ifndef CONFIG_USER_ONLY static inline void check_mvh(DisasContext *ctx) --=20 2.26.2