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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id o33sm19828818edd.50.2020.12.15.14.58.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 14:58:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eBR/KP1XMbhrcgssotJd4G/2avIMrBZMV7G4WmoiWo8=; b=YrR0Z5DqkFBEJMEr1NVzef+bcwtTkoahx68HU/I9evKCqeSbblFgtzi4VwkRteuGlB alrA8YVrKnFX+Qmh04SBwbi4UktTCu8JTa5GIZoLuSqedrTqamgZjvge9k/ZMuj6RZv9 0RmgIsSUZFdr60RFQPWxo20uMyRah+OAv4Hg0lBOEJrNCJXPTkVex4JsV7Td9l1UrgH8 18sLjhIGG44a2+kwmIh29I3kxxH6eUDWLFp+NT3KAxoazrkdaDiEpHpw4+vvcikbRRB9 Hpab1AIgsyW6ZGURc5Qrd31/2aT5JgQyU4ESaIVP0R1q+at+GxzUWO0g1NhFgG7SS0xd o/Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=eBR/KP1XMbhrcgssotJd4G/2avIMrBZMV7G4WmoiWo8=; b=qEHCrmx/SUMyQZtIPC7KBoGSRelflOIcBrEtuBYsntDrkt0j8J/qkC4+LtDT2aBaLN scvxf+/typoMcPVyJsvtA44856gZiSwoCfUVKOeqfnvNUPQtO8S2dcX8JtI5WNLLfTXN +eB/aL2pp1MTGN+SLuL+Z0fUgkC/deDdDcoBHLyg1dvhfzZJyKrztaqxqAo30P8zLZd+ AgX0r49oWA+q2lSQpJr5g5JhkoaNQYwWuwXMyx3u+pmxs721nn1Gb1OQCoU3hi5nnyRP dWXDslGZwIzGt7JFi1faI2WzrSKhHz0kBBHypikUtCIzqBEBmSu3G+/6XC13CI5H2myC kU1g== X-Gm-Message-State: AOAM53009giVokosxRbLPPOZR5bKS3gcg1wW5Za9ZKZT0sUnI0Mc8uAT f1+z/7ORWTbpXvYNYFYps9Y= X-Google-Smtp-Source: ABdhPJw8ylReeQsh/8yN74nzFbXTfd16F9/1BaCqotQgh4xKhIEOL+x+fifCJ+4D13ea5/hOaaDSYg== X-Received: by 2002:a17:906:4a4f:: with SMTP id a15mr29198657ejv.541.1608073085939; Tue, 15 Dec 2020 14:58:05 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aleksandar Rikalo , Paolo Bonzini , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen Subject: [PATCH v2 01/24] target/mips/translate: Extract decode_opc_legacy() from decode_opc() Date: Tue, 15 Dec 2020 23:57:34 +0100 Message-Id: <20201215225757.764263-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215225757.764263-1-f4bug@amsat.org> References: <20201215225757.764263-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) As we will slowly move to decodetree generated decoders, extract the legacy decoding from decode_opc(), so new decoders are added in decode_opc() while old code is removed from decode_opc_legacy(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/translate.c | 45 ++++++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 19 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index cc876019bf7..5c62b32c6ae 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -30518,30 +30518,13 @@ static void gen_msa(CPUMIPSState *env, DisasConte= xt *ctx) =20 } =20 -static void decode_opc(CPUMIPSState *env, DisasContext *ctx) +static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) { int32_t offset; int rs, rt, rd, sa; uint32_t op, op1; int16_t imm; =20 - /* make sure instructions are on a word boundary */ - if (ctx->base.pc_next & 0x3) { - env->CP0_BadVAddr =3D ctx->base.pc_next; - generate_exception_err(ctx, EXCP_AdEL, EXCP_INST_NOTAVAIL); - return; - } - - /* Handle blikely not taken case */ - if ((ctx->hflags & MIPS_HFLAG_BMASK_BASE) =3D=3D MIPS_HFLAG_BL) { - TCGLabel *l1 =3D gen_new_label(); - - tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1); - tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK); - gen_goto_tb(ctx, 1, ctx->base.pc_next + 4); - gen_set_label(l1); - } - op =3D MASK_OP_MAJOR(ctx->opcode); rs =3D (ctx->opcode >> 21) & 0x1f; rt =3D (ctx->opcode >> 16) & 0x1f; @@ -31269,8 +31252,32 @@ static void decode_opc(CPUMIPSState *env, DisasCon= text *ctx) break; default: /* Invalid */ MIPS_INVAL("major opcode"); + return false; + } + return true; +} + +static void decode_opc(CPUMIPSState *env, DisasContext *ctx) +{ + /* make sure instructions are on a word boundary */ + if (ctx->base.pc_next & 0x3) { + env->CP0_BadVAddr =3D ctx->base.pc_next; + generate_exception_err(ctx, EXCP_AdEL, EXCP_INST_NOTAVAIL); + return; + } + + /* Handle blikely not taken case */ + if ((ctx->hflags & MIPS_HFLAG_BMASK_BASE) =3D=3D MIPS_HFLAG_BL) { + TCGLabel *l1 =3D gen_new_label(); + + tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1); + tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK); + gen_goto_tb(ctx, 1, ctx->base.pc_next + 4); + gen_set_label(l1); + } + + if (!decode_opc_legacy(env, ctx)) { gen_reserved_instruction(ctx); - break; } } =20 --=20 2.26.2 From nobody Tue May 21 12:06:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.44 as permitted sender) client-ip=209.85.218.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1608073093; cv=none; d=zohomail.com; s=zohoarc; b=fXAzbUlzn7m97YhHFMVcKhmP3Q5WRG+VfOEjpQU2ufO563JqJ1VljFThUXZ3cL7jLOjWoWwaE9u0JuVUMurVdLpJuAfLouyVxg0VHi84HVZb2y4rhKZNlfsBKnfjVfU6RsjMVjZtlaVHQcyPmXoUC+M4k6Z66Zowm+8AfwHnVSw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608073093; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nIvvusNJm60WWqveYR8Cj3EE3xSaf0EEqwOHmNBN40o=; b=Oyq1mCbzxzxCm5mOT48fndXYmMRKlw8ZpOdcwXQgCD/jCLtKj4A8BnqV14vRg8aNy9mpbsCbSxQHQTlNx0L2zpfgTGrLUxMUFaiCTqHAjhKIYZvAYMvKD9ZeSjBLMl0aBnNcAmp7OyUmZw+JUDgckxf7sSgbCgY6yCgXGysCT7k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) by mx.zohomail.com with SMTPS id 160807309340312.58678496945015; Tue, 15 Dec 2020 14:58:13 -0800 (PST) Received: by mail-ej1-f44.google.com with SMTP id x16so30050057ejj.7 for ; Tue, 15 Dec 2020 14:58:12 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id f20sm8514210edx.92.2020.12.15.14.58.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 14:58:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nIvvusNJm60WWqveYR8Cj3EE3xSaf0EEqwOHmNBN40o=; b=rE1wg4s+BQFCEk8G4qW/EZvLlvRn6pVxQO3rKh4VPhBKrCVG/5yqEwoiblwqOAVg+s 1jKsfSERkOnk3qfv8sVj922EN1A+gxv1DwbsZUIgZHOBv+BNMQu+6ohBNFP3RnovvOj9 zdyVuynSE1umCq28i/rSVXS5jcEkECpHS2kohBMsXcdYTT8lV+AEga+bmJkpBPnSyWEl y3VaMmRFsjzHzim7xhbqmXib/rnEdeYVp7dPdzpjnLSgh7ViyON5jFRke9Pf8B1deDuj z0dFvMtjfL3QZy1GJxE5hhfYq/jO+10+I6BjV0/xVVDbTYHvVBr90l4FPpqIMxnY9PBn 5atQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=nIvvusNJm60WWqveYR8Cj3EE3xSaf0EEqwOHmNBN40o=; b=eom3eDLjPlzkeeTgsqrTWUE0u+zhux4Nz3jP4QJiwO4+9hkEyCVT4mKS7eLDM92koT jjFsWN+F6RQhIHvZksbjeBLB9m7tO5eVwkWgxbleB9xTdJSXlwoIqAImSl68RwZfHhyN G2Uk38Uk1kY+4G5WuyHRzbi1Opt9oxRHXyQDogAzKGGZOa2wuSB6Z6YHSNjfIr/O1SIY LnyaFNFc9PWgLRIe/AFYQycgnPvJmdCWRsIvjf6Y1nRRAS9pqUb1oOaHlFlDF3g/swvY jh/1Z2Jqg2i5FCKVHK7i9c6ljV4h3IaVaCWK1XzXQrAMUFP8z0WDc+tDBv5SPUMx7NB1 SNuQ== X-Gm-Message-State: AOAM532EA3mzV67nKCVMoaHQ5DUbIoIlb9swtFcejZpA2H3GbPnlmi13 NuwumC6bBCF+5WeV9Knjjk8= X-Google-Smtp-Source: ABdhPJyJfKCLWMingZozHIiLHLT59KgzZqGQr2a+zB0lXaXEIGcuoBun5nXBUlkaB1EB0fOznCztLA== X-Received: by 2002:a17:906:2c54:: with SMTP id f20mr4559736ejh.318.1608073091601; Tue, 15 Dec 2020 14:58:11 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aleksandar Rikalo , Paolo Bonzini , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen Subject: [PATCH v2 02/24] target/mips/translate: Expose check_mips_64() to 32-bit mode Date: Tue, 15 Dec 2020 23:57:35 +0100 Message-Id: <20201215225757.764263-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215225757.764263-1-f4bug@amsat.org> References: <20201215225757.764263-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) To allow compiling 64-bit specific translation code more generically (and removing #ifdef'ry), allow compiling check_mips_64() on 32-bit targets. If ever called on 32-bit, we obviously emit a reserved instruction exception. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jiaxun Yang --- target/mips/translate.h | 2 -- target/mips/translate.c | 8 +++----- 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index a9eab69249f..942d803476c 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -127,9 +127,7 @@ void generate_exception_err(DisasContext *ctx, int excp= , int err); void generate_exception_end(DisasContext *ctx, int excp); void gen_reserved_instruction(DisasContext *ctx); void check_insn(DisasContext *ctx, uint64_t flags); -#ifdef TARGET_MIPS64 void check_mips_64(DisasContext *ctx); -#endif void check_cp1_enabled(DisasContext *ctx); =20 void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offs= et); diff --git a/target/mips/translate.c b/target/mips/translate.c index 5c62b32c6ae..af543d1f375 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2972,18 +2972,16 @@ static inline void check_ps(DisasContext *ctx) check_cp1_64bitmode(ctx); } =20 -#ifdef TARGET_MIPS64 /* - * This code generates a "reserved instruction" exception if 64-bit - * instructions are not enabled. + * This code generates a "reserved instruction" exception if cpu is not + * 64-bit or 64-bit instructions are not enabled. */ void check_mips_64(DisasContext *ctx) { - if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) { + if (unlikely((TARGET_LONG_BITS !=3D 64) || !(ctx->hflags & MIPS_HFLAG_= 64))) { gen_reserved_instruction(ctx); } } -#endif =20 #ifndef CONFIG_USER_ONLY static inline void check_mvh(DisasContext *ctx) --=20 2.26.2 From nobody Tue May 21 12:06:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.67 as permitted sender) client-ip=209.85.208.67; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f67.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.67 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1608073099; cv=none; d=zohomail.com; s=zohoarc; b=fZdKmOGe6iYRfXyddpVIKle8oTKZ3jcZg7hyRmnHuAT9rfhA84fbg41csVSsk2TR7fPIy3DoSjE3QLxUBB25+QUhAfUMcsTi9LGMANtt2sDMUjUZ3oFRjAOCQ+ggvyW+NTsnCM6u0h1SvIwugZ7CRHiGUmGgfgdq0Ud/R15Drf8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608073099; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gfAK/5l8oepBv1m9fLlqhZZJOh/VztlrVhqk0ziS8jY=; b=XRaWpJJJKWdjaXC/8DAroSde2p9KOR8HXO0vjBJ5UVj2d24ydbLp6SlYHOdmyWeGWmKSYOqdQayRnaUnnkxEWB9uCodt0HoFdh2gN6brQpQoy/zXeX/EqrOQPHNM3AoxGQmehOMF4AQcn/83Ax+/4LLZmru1PHcrOaH5CA5DQqw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.67 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-ed1-f67.google.com (mail-ed1-f67.google.com [209.85.208.67]) by mx.zohomail.com with SMTPS id 1608073099212940.5817933325143; Tue, 15 Dec 2020 14:58:19 -0800 (PST) Received: by mail-ed1-f67.google.com with SMTP id b2so22849062edm.3 for ; Tue, 15 Dec 2020 14:58:18 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id g18sm19135013edt.2.2020.12.15.14.58.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 14:58:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gfAK/5l8oepBv1m9fLlqhZZJOh/VztlrVhqk0ziS8jY=; b=FdLu6d7skwAkLOlWHhnw6CiK9nTmqSFMQ2+f3bQKkxDBeFfIIsep4RJ4VxOZ3Yy17p SGAek2pKHRsx1RZHfY/x/wHRH8f30dESCnX3vmr3QoIk/GXgq/tytDYV8D8tZQHHpEHP 6sl0NKCEuQJoTlEzGwITjQQI3hnDr8e7FSckAnVzfged+2Dv0dtlSlYKPgLd5FLt2fWf icL46mdmQhgYhLDRRRg7AFhiPKLdBTdLWsfb0nEPikLlNnRLt8ANtxLEPeS6IFORnamV Bdd+ZmX04Wlh5Fbu/j7W2Cfhz/g6WuGHhj4JYiT4yzvSx92fmBLqgGw3a5ChUkktz1gP OXXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=gfAK/5l8oepBv1m9fLlqhZZJOh/VztlrVhqk0ziS8jY=; b=B8x7G3WFdNdI1ZkzxDbgyn35RIEppdZMDjc2+KFe1t6UYbWjS22hCPcaRh58bqRuHf CAgAKYCs625qZU8gBxGP/V/IH+hjzHWAEWgIgcvUadzdJTs851ihMGAlRTQiSQuuYLZ5 D3SFL6pGl4TK5WVvU0lxjnG05di1gKn7xXG5xjhJ65cObX7/MN3Frz/o6brh3PC2B4zH LrkY2LlIGMOhF29dP5qarB7a99LWfP9wtWpjZU1ZkUVXIMnYuDxk3cjtP/4ilNtu+h/b WaFKqJIkISKWOfbsRKXC0g+pvzGRGKGHW0rA6A6Ldk9tctk7ewwR+IunTigON0zRqnis LxnQ== X-Gm-Message-State: AOAM5321DYoI1lDY91VCqjfDEBDRiJbfKLH4FE77wSL+HcmXVFL51ySZ HLjWaYEfEhVdKKsiZkZ+VYA= X-Google-Smtp-Source: ABdhPJzMV5ebQ8WKtlqOKKPT4HVLHg+DJtP96dH2LzWIIc/qEDJS0DRMCBuv96y66yLjeOVyXmrpnQ== X-Received: by 2002:a05:6402:30ac:: with SMTP id df12mr32562213edb.175.1608073097456; Tue, 15 Dec 2020 14:58:17 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aleksandar Rikalo , Paolo Bonzini , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen Subject: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper Date: Tue, 15 Dec 2020 23:57:36 +0100 Message-Id: <20201215225757.764263-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215225757.764263-1-f4bug@amsat.org> References: <20201215225757.764263-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Introduce the isa_rel6_available() helper to check if the CPU supports the Release 6 ISA. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/cpu.h | 1 + target/mips/cpu.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 3ac21d0e9c0..c6a556efad5 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1289,6 +1289,7 @@ int cpu_mips_signal_handler(int host_signum, void *pi= nfo, void *puc); bool cpu_type_supports_cps_smp(const char *cpu_type); bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask); bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa); +bool isa_rel6_available(const CPUMIPSState *env); =20 /* Check presence of multi-threading ASE implementation */ static inline bool ase_mt_available(CPUMIPSState *env) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 4191c0741f4..9f082518076 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -789,6 +789,14 @@ bool cpu_supports_isa(const CPUMIPSState *env, uint64_= t isa_mask) return (env->cpu_model->insn_flags & isa_mask) !=3D 0; } =20 +bool isa_rel6_available(const CPUMIPSState *env) +{ + if (TARGET_LONG_BITS =3D=3D 64) { + return cpu_supports_isa(env, ISA_MIPS64R6); + } + return cpu_supports_isa(env, ISA_MIPS32R6); +} + bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa) { const MIPSCPUClass *mcc =3D MIPS_CPU_CLASS(object_class_by_name(cpu_ty= pe)); --=20 2.26.2 From nobody Tue May 21 12:06:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.67 as permitted sender) client-ip=209.85.218.67; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-f67.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.67 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1608073105; cv=none; d=zohomail.com; s=zohoarc; b=OQzS0qBkODrSQJryjIC170KpBdXuWKI5DOfzuIRI672SidZQJUrddy1NQWEIOqPG24d6rnC2u8fwFjoA8vOPydsfHbDiwJMFwfXp5Y6YAveh0OK7uVov4N7v4gNBakWFG6asF4ybX9UVyzqGX0GI0WYz6Nxqi4gWYCGwaxMte2M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608073105; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+wY9Wxdfz8Q05SZXY3w48hyJcCL39vkqVQj5St83H/w=; b=YKaJKzirZFX0TIDS4EB7CqnfuZ87k4vSgXwa758GlSARDUutNhDkzM5uVcI9nqpJlCLlG9NqiPE9EhV6ppwcZ/umWXWoXafmQbEGt2LsLVCXEXfzlC30B9VYIReaeF1f29W+rK1UCDhAvUELXMtGuRfZzHG8MEupTS2c/GuP9dY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.67 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-ej1-f67.google.com (mail-ej1-f67.google.com [209.85.218.67]) by mx.zohomail.com with SMTPS id 16080731054561016.2762977080029; Tue, 15 Dec 2020 14:58:25 -0800 (PST) Received: by mail-ej1-f67.google.com with SMTP id qw4so29992587ejb.12 for ; Tue, 15 Dec 2020 14:58:24 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id dd12sm19502228edb.6.2020.12.15.14.58.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 14:58:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+wY9Wxdfz8Q05SZXY3w48hyJcCL39vkqVQj5St83H/w=; b=GcAigDrbQLzOEAbrwidZpxN3admNCJMSaudn0ivWvxhNktukMBj0fo0yonOBBXDtAn ELcE2tBAf+8gJHst79f+6XryZ6ptaysj5mpNvo448Dk+FYx5onMDZWnUyshkaFP0aeI7 fagA0KEYd53PPDYXjfgDypcgJ4I3Jj3vbZnZ+8VXuMDBkwzEancNWdoVvhOmRUjkLJ3K O37mugRMTBJVK0eW/ywUQiAnzd1sZOFLkw3wMFD5KJu+bp3gbSmFnunP/vlvyW7l79+7 5RUcaNB5rhVTMxV6APoUMSuS3UXhBxG7+RwFe5knb1SAsDiCQx+YmqtvyNi+GZPiHOQn 6Zfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=+wY9Wxdfz8Q05SZXY3w48hyJcCL39vkqVQj5St83H/w=; b=L4o2Cr/VdbgBkBFEBUCs8q+HjVYOzFUlgID865AILL3hy7SNJdpx4ZH6SdLFahfoiB LmxDlFlb6PAvryqUy+tTakh4ElLA1wE7iuiKZTaxnQBAHAaUsKIlUMlcxf99A+fKWhP0 MOS0BKPS3f5ZWQ/S3d2SlY2QnzJMR80WZpVBJXkyGzhoYyuavBomEbnhnZpDpW2iLrqx KAehDLH8IGvBk5AP3I53kuZml75CzQjMKNAkIjM2GJu9SzWUZJkvA6bsXfINhGWASXrC 2CnQHtzdd0ht7UorekYcEIzsJVy3CTEz+r3lBgTwlSxEAv5h/OfRWg5O8bzlNlaPfncT Oqag== X-Gm-Message-State: AOAM530B6bL/4TUeLLPhoeGcbMvzpebFHzhsJsYTInK8kXv4b3pZIzrb dy7Q7A+Gasg2xxWcWyZpAcA= X-Google-Smtp-Source: ABdhPJysJBw/ijI2j8W8zKgKL6O2UflTWr8SqHldf1JMKj1Szq6aQAbJ5n/eI2DBnZIywd1nbmwueA== X-Received: by 2002:a17:906:8051:: with SMTP id x17mr8771161ejw.430.1608073103571; Tue, 15 Dec 2020 14:58:23 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aleksandar Rikalo , Paolo Bonzini , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen Subject: [PATCH v2 04/24] target/mips: Introduce ase_msa_available() helper Date: Tue, 15 Dec 2020 23:57:37 +0100 Message-Id: <20201215225757.764263-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215225757.764263-1-f4bug@amsat.org> References: <20201215225757.764263-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Instead of accessing CP0_Config3 directly and checking the 'MSA Present' bit, introduce an explicit helper, making the code easier to read. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/cpu.h | 6 ++++++ target/mips/cpu.c | 2 +- target/mips/kvm.c | 12 ++++++------ target/mips/translate.c | 6 ++---- 4 files changed, 15 insertions(+), 11 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index c6a556efad5..1d72307c547 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1291,6 +1291,12 @@ bool cpu_supports_isa(const CPUMIPSState *env, uint6= 4_t isa_mask); bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa); bool isa_rel6_available(const CPUMIPSState *env); =20 +/* Check presence of MSA implementation */ +static inline bool ase_msa_available(CPUMIPSState *env) +{ + return env->CP0_Config3 & (1 << CP0C3_MSAP); +} + /* Check presence of multi-threading ASE implementation */ static inline bool ase_mt_available(CPUMIPSState *env) { diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 9f082518076..1b4c13bc972 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -532,7 +532,7 @@ static void mips_cpu_reset(DeviceState *dev) } =20 /* MSA */ - if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { + if (ase_msa_available(env)) { msa_reset(env); } =20 diff --git a/target/mips/kvm.c b/target/mips/kvm.c index a5b6fe35dbc..84fb10ea35d 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -79,7 +79,7 @@ int kvm_arch_init_vcpu(CPUState *cs) } } =20 - if (kvm_mips_msa_cap && env->CP0_Config3 & (1 << CP0C3_MSAP)) { + if (kvm_mips_msa_cap && ase_msa_available(env)) { ret =3D kvm_vcpu_enable_cap(cs, KVM_CAP_MIPS_MSA, 0, 0); if (ret < 0) { /* mark unsupported so it gets disabled on reset */ @@ -105,7 +105,7 @@ void kvm_mips_reset_vcpu(MIPSCPU *cpu) warn_report("KVM does not support FPU, disabling"); env->CP0_Config1 &=3D ~(1 << CP0C1_FP); } - if (!kvm_mips_msa_cap && env->CP0_Config3 & (1 << CP0C3_MSAP)) { + if (!kvm_mips_msa_cap && ase_msa_available(env)) { warn_report("KVM does not support MSA, disabling"); env->CP0_Config3 &=3D ~(1 << CP0C3_MSAP); } @@ -618,7 +618,7 @@ static int kvm_mips_put_fpu_registers(CPUState *cs, int= level) * FPU register state is a subset of MSA vector state, so don't pu= t FPU * registers if we're emulating a CPU with MSA. */ - if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) { + if (!ase_msa_available(env)) { /* Floating point registers */ for (i =3D 0; i < 32; ++i) { if (env->CP0_Status & (1 << CP0St_FR)) { @@ -637,7 +637,7 @@ static int kvm_mips_put_fpu_registers(CPUState *cs, int= level) } =20 /* Only put MSA state if we're emulating a CPU with MSA */ - if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { + if (ase_msa_available(env)) { /* MSA Control Registers */ if (level =3D=3D KVM_PUT_FULL_STATE) { err =3D kvm_mips_put_one_reg(cs, KVM_REG_MIPS_MSA_IR, @@ -698,7 +698,7 @@ static int kvm_mips_get_fpu_registers(CPUState *cs) * FPU register state is a subset of MSA vector state, so don't sa= ve FPU * registers if we're emulating a CPU with MSA. */ - if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) { + if (!ase_msa_available(env)) { /* Floating point registers */ for (i =3D 0; i < 32; ++i) { if (env->CP0_Status & (1 << CP0St_FR)) { @@ -717,7 +717,7 @@ static int kvm_mips_get_fpu_registers(CPUState *cs) } =20 /* Only get MSA state if we're emulating a CPU with MSA */ - if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { + if (ase_msa_available(env)) { /* MSA Control Registers */ err =3D kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_IR, &env->msair); diff --git a/target/mips/translate.c b/target/mips/translate.c index af543d1f375..fc658b3be33 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24920,8 +24920,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) gen_trap(ctx, op1, rs, rt, -1); break; case OPC_LSA: /* OPC_PMON */ - if ((ctx->insn_flags & ISA_MIPS32R6) || - (env->CP0_Config3 & (1 << CP0C3_MSAP))) { + if ((ctx->insn_flags & ISA_MIPS32R6) || ase_msa_available(env)) { decode_opc_special_r6(env, ctx); } else { /* Pmon entry point, also R4010 selsl */ @@ -25023,8 +25022,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) } break; case OPC_DLSA: - if ((ctx->insn_flags & ISA_MIPS32R6) || - (env->CP0_Config3 & (1 << CP0C3_MSAP))) { + if ((ctx->insn_flags & ISA_MIPS32R6) || ase_msa_available(env)) { decode_opc_special_r6(env, ctx); } break; --=20 2.26.2 From nobody Tue May 21 12:06:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.67 as permitted sender) client-ip=209.85.218.67; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id z96sm19329766ede.81.2020.12.15.14.58.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 14:58:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0ud89HtdSyuwzqz0NlT4/PCPOyWmeeMuUKVW0RQc4ak=; b=R8Q/u6+uWuVnK9aH5rSnyo3uq6CPH9LEzjvDfihNcP/Oqy1TpUAulCP7BgTnEaSu4G l+E/Q9AflTdohyTRq2LrpLNOj5c3Hm1PmbOdImn5u8eVBGJXO3zK6L546r9SjcTivbT8 uNKS3mINCH6gJ6HQPW6Ea37Ma/9B+Hqt/Igf/P9CrljRhNBDFze2k1Fprkj8Q2ZF5STN +k9TbVyjUVYNFxPht7VEuoe26q1yTuuiDilT1OX8cJ09eMHdPWQ/viDNbawwCKLMpI81 p64BZ59K/3DLKJnE8lbAIivgAo3tFU9ftiSOyxTwRyiZTiga5uYW4tcrlhMF0wQrm/MN PiXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=0ud89HtdSyuwzqz0NlT4/PCPOyWmeeMuUKVW0RQc4ak=; b=kzPyChNthL0DH7zteBpYl6IYJyTMTMpzgDj5WtQmENkhmZjlw4RPx6BEYyhw1W0dxn Nuub3YuygaJxle5A/p5h0zHN9jLa0rIgwKy1co4GJ0kUcl9Yc6MjXhxdhCDLkYqmYvMF rDR179NG3ELGc0hYJI7RATGz7a8xG3Y0m2Y0CckP78QQqabz4ckh4EWQOCZQGadFKsQM EjtjK9CZTzKB4I0p9sSeBk5BVYBK+qM9loIxl1ByekKyg1SXalSWji1fOgDH8buOf4gV qiBcCpBLTzZVp43Vaip0cslPv9R8/K4uX0bXzPTaz3gQyaZUbtDh7Np8o9vKlVLlUNkR 4giw== X-Gm-Message-State: AOAM532U6wT+gwToavkThRiSnrRZjx5JoSciDWQETK4aNR4U2nhwM6k6 KaXrCjUz9ZSkWHEdmGaP6qw= X-Google-Smtp-Source: ABdhPJz4LrH39C3yWw1Con4fZAHpZ4vpgToMC4Fn3eXoof1muEPI7fFCR+i/YKfY8AYmXD1Csav6+Q== X-Received: by 2002:a17:906:4412:: with SMTP id x18mr6572504ejo.301.1608073109258; Tue, 15 Dec 2020 14:58:29 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aleksandar Rikalo , Paolo Bonzini , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen Subject: [PATCH v2 05/24] target/mips: Simplify msa_reset() Date: Tue, 15 Dec 2020 23:57:38 +0100 Message-Id: <20201215225757.764263-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215225757.764263-1-f4bug@amsat.org> References: <20201215225757.764263-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Call msa_reset() unconditionally, but only reset the MSA registers if MSA is implemented. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/cpu.c | 5 +---- target/mips/cpu-defs.c.inc | 4 ++++ 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 1b4c13bc972..77ebd94c655 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -531,10 +531,7 @@ static void mips_cpu_reset(DeviceState *dev) env->hflags |=3D MIPS_HFLAG_M16; } =20 - /* MSA */ - if (ase_msa_available(env)) { - msa_reset(env); - } + msa_reset(env); =20 compute_hflags(env); restore_fp_status(env); diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index a788f5a6b6d..bf12e91f715 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -976,6 +976,10 @@ static void mvp_init(CPUMIPSState *env) =20 static void msa_reset(CPUMIPSState *env) { + if (!ase_msa_available(env)) { + return; + } + #ifdef CONFIG_USER_ONLY /* MSA access enabled */ env->CP0_Config5 |=3D 1 << CP0C5_MSAEn; --=20 2.26.2 From nobody Tue May 21 12:06:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.67 as permitted sender) client-ip=209.85.218.67; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-f67.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.67 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1608073116; cv=none; d=zohomail.com; s=zohoarc; b=dDgm8oJ1zAR/8rqwjJxEDjCANohjue1Y9JYgcTKk084kmYYyimZUbOSVqWBNcUtdHBwtftStZ+BoACIecfuQfMHgoQh3sk3DsVYRneS4Mzu+LQkUjfzGQ+bSEEDgGvmiFSC3dwnVzzq5w81BJL40yhr7MX5XnpB8iDLMBrHcdsg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608073116; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=74tnrNw+u4pr5iFSEHUsfynOPkwscuzwVbsLeoiPrug=; b=it2JUmWQK7hlxi6wxQb1Jiy2l1b/Z+1YEEYppu/xPT4O+dWYTTzBm6vngkLDJhJc6js4o9018FHg4oUUq94Et5JUCUb+JKa0t7j58yAYszSHBap2rSemRH0IUlMkY8Gh7P739QAdLtVdgZRNN8M/d96iQ0WNTiSZuLI4HmGrMiE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.67 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ej1-f67.google.com (mail-ej1-f67.google.com [209.85.218.67]) by mx.zohomail.com with SMTPS id 1608073116576418.2766340299688; Tue, 15 Dec 2020 14:58:36 -0800 (PST) Received: by mail-ej1-f67.google.com with SMTP id q22so12294453eja.2 for ; Tue, 15 Dec 2020 14:58:36 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id p24sm16660815edr.65.2020.12.15.14.58.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 14:58:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=74tnrNw+u4pr5iFSEHUsfynOPkwscuzwVbsLeoiPrug=; b=RtfvwoVk7Mzw/dylvxtjrTqWQj3l6D3IVMuqLvrBYihy6Ky+DdEmPh7kYq9vx/u4+9 zrpqzx+QC1+jQmK1h6xKi+rxA0kdSPUsmFkcrJjEHsRFgXBy74LRRWKgbd2BlFilLz9b h/KiTiZDcnf+SM/rJ86ct5rK1PkmaltZeKTzz5+HkBObcgtDtMioCzbjhm/f0pKqlD3f JipOCfLPSPCxZ2FkbiQ8isFK1BvJY8Idyl1LHTHppeFLyVUjSjXN3fueMgPcVLssER6o MfdBM69UQgqGzA6zRw8eWV9+QPSP0EteFg6aki6wdZiEh7NjKFCLiGppVEs99VHCFxoG y+XA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=74tnrNw+u4pr5iFSEHUsfynOPkwscuzwVbsLeoiPrug=; b=AvCc2wRC57H11BcRU0LUaZQZPjst51vvcgD8wElHrNhXhI20IGyPNNDXMridPzEjyl 6afhYYXQJ9us0eB6M1QTt28JzMumyoemUeEY/DPED3a6tbn1HqN1vx4/v+GJl9AjWlaS u73gWJ/SZT8NEUbHQWGb9MErMKfA4tucALKxTru6+JPLVCSg7qegXizWsg3LeevnAXAo xQMIXVfMzzYORtSmBe7ylvSUoq0Lk7mnd4otk5NCirrB2lTxNM4J+Ay95l1DK4yrnomi q1ZiUeVDgv2ld47+XEM/o7pzCMDwoNaXoF1aeDFosBFWJ6/T3KZyxTqTv/NJhyx+JEm2 tIOA== X-Gm-Message-State: AOAM530x+KdQlhcjNFZUrqU4wESOXLJU2zJUqwg1G1AnxysFJVeQ8JSj SMiCjXyV8OSdVh1V5DyuSSs= X-Google-Smtp-Source: ABdhPJyHJfU6cpbNmDQETSsJGW3gJhXZe5NIxiaFlY9+UOp46AEFZAvVF2OyKmVq3Soh+D7y3deHsg== X-Received: by 2002:a17:906:814a:: with SMTP id z10mr27884807ejw.96.1608073114782; Tue, 15 Dec 2020 14:58:34 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aleksandar Rikalo , Paolo Bonzini , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen Subject: [PATCH v2 06/24] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA Date: Tue, 15 Dec 2020 23:57:39 +0100 Message-Id: <20201215225757.764263-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215225757.764263-1-f4bug@amsat.org> References: <20201215225757.764263-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) MSA presence is expressed by the MSAP bit of CP0_Config3. We don't need to check anything else. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 968a3a8db8f..1ab2454e61d 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -378,7 +378,7 @@ static inline void compute_hflags(CPUMIPSState *env) env->hflags |=3D MIPS_HFLAG_COP1X; } } - if (env->insn_flags & ASE_MSA) { + if (ase_msa_available(env)) { if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) { env->hflags |=3D MIPS_HFLAG_MSA; } --=20 2.26.2 From nobody Tue May 21 12:06:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.68 as permitted sender) client-ip=209.85.218.68; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-f68.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.68 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1608073121; cv=none; d=zohomail.com; s=zohoarc; b=UH9gLbo4UJw+Ti4m00JqS/bvNAlsubC5pJLWCM4VI6uiOwm6bk0W5QeDtrb+VR4+ZK0iDTPsgPkLfRLPsot1oEmBi/Rd+gABGCMOUtvlcaKvWJL5TYUNNrrbWGvEOEuSGnS3TofRC2AbaJMcitH4isf696iu0buc/0awGGBkX5c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608073121; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BnBuWwu/IR7HzibU0fSLa1btap3ty/kGytf5ZOVzJHw=; b=RI/ug6J7msaVS/3d4lNnGx7n0frNACHny/+MQTK7z84jGJPAXwE7/jkLLM3ZZBYaLWUUbiGoHlbWpCxC4wcRFnbr9popFgwMoZ/op8R4DnnNIzsg7vOQZt72BrsP1rxbvbz8uDMTZlQ7y5sZEqhxxJtB9ZT2w3N/TzxpTweqMmQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.68 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ej1-f68.google.com (mail-ej1-f68.google.com [209.85.218.68]) by mx.zohomail.com with SMTPS id 1608073121976183.02973973995313; Tue, 15 Dec 2020 14:58:41 -0800 (PST) Received: by mail-ej1-f68.google.com with SMTP id b9so5109644ejy.0 for ; Tue, 15 Dec 2020 14:58:41 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id 35sm19174328ede.0.2020.12.15.14.58.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 14:58:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BnBuWwu/IR7HzibU0fSLa1btap3ty/kGytf5ZOVzJHw=; b=US6pT9hkIUe/3Y7u3abkxfxmo+g63uoofHU7oXDwqFCQZm1V3FKeZ5fDXzLgWMR+tz ZUIr8FArsHvKzwdU5ieVduhNmBORH2czavfCNyp2G3DaW1Wx7Y+dAOSt4ViEAcfknR4j NEDgCAFVKk+EIAx5IlI16zjC648EjQDBh+vWLjHPVKgPCIwWemlKmBw9hB648PyqxsGN VdYu36vVvnu1D9nYrydInoLe21pVmk0ZgN067MnXf6abBT+2DG+WabDXSuxUz78F/nNw ztxNkZsRG3MrTs1HcvdY+Er07tfLpecaOC2VF4tD5oP0KgRVvnanghVChVImnzbLu5mN nnig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=BnBuWwu/IR7HzibU0fSLa1btap3ty/kGytf5ZOVzJHw=; b=Q5dZAfBRwHWLGJoy9ZrVIn7bSp6woPxwU0q97IwcCk5wQLlH8XTc0n5JmPAQpOImiG yP3eX9VyzizwEtb3dbKT5NeJE7hIJoRN8LK0Hg1XLCDDS4wHmtm03UIWejb/8ln5+n0C TnThYLuC89DACYzNmmYF9A2Yi4vJskixWz/yqi8M12vhU7HmNrDf5HPNDEQaa7OtahxS Lmy0xyjZu/fGIRvGkxYpDkbFTWzpCE+jNBLtknd+dtWSZAVdH+UpWW3cSGWZSk29VTiH AYGS1/8ENpfSEWHfQ9efXHYMMPIWtYUkpQ+1xR6apIifpZTh0QLjW65aLuE+1cBO06jt aGPA== X-Gm-Message-State: AOAM530eMMqH0guLAb3lyHIoYYe3XGm8BbAR2ii2XQGdoEJgZFytWkMS 4wWKGh7n4+meAShujydxCLU= X-Google-Smtp-Source: ABdhPJwWEmYN+znrgrxMg2p+03mYpoUKLrA8wM858BfPuk+pAWE4X4Nrr/vTEL+NY0y64W3QwD6D1g== X-Received: by 2002:a17:906:705:: with SMTP id y5mr14673838ejb.428.1608073120174; Tue, 15 Dec 2020 14:58:40 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aleksandar Rikalo , Paolo Bonzini , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen Subject: [PATCH v2 07/24] target/mips: Simplify MSA TCG logic Date: Tue, 15 Dec 2020 23:57:40 +0100 Message-Id: <20201215225757.764263-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215225757.764263-1-f4bug@amsat.org> References: <20201215225757.764263-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Only decode MSA opcodes if MSA is present (implemented). Now than check_msa_access() will only be called if MSA is present, the only way to have MIPS_HFLAG_MSA unset is if MSA is disabled (bit CP0C5_MSAEn cleared, see previous commit). Therefore we can remove the 'reserved instruction' exception. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index fc658b3be33..02ea184f9a3 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28568,13 +28568,8 @@ static inline int check_msa_access(DisasContext *c= tx) } =20 if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) { - if (ctx->insn_flags & ASE_MSA) { - generate_exception_end(ctx, EXCP_MSADIS); - return 0; - } else { - gen_reserved_instruction(ctx); - return 0; - } + generate_exception_end(ctx, EXCP_MSADIS); + return 0; } return 1; } @@ -30418,7 +30413,7 @@ static void gen_msa_vec(CPUMIPSState *env, DisasCon= text *ctx) static void gen_msa(CPUMIPSState *env, DisasContext *ctx) { uint32_t opcode =3D ctx->opcode; - check_insn(ctx, ASE_MSA); + check_msa_access(ctx); =20 switch (MASK_MSA_MINOR(opcode)) { @@ -31048,9 +31043,10 @@ static bool decode_opc_legacy(CPUMIPSState *env, D= isasContext *ctx) case OPC_BNZ_H: case OPC_BNZ_W: case OPC_BNZ_D: - check_insn(ctx, ASE_MSA); - gen_msa_branch(env, ctx, op1); - break; + if (ase_msa_available(env)) { + gen_msa_branch(env, ctx, op1); + break; + } default: MIPS_INVAL("cp1"); gen_reserved_instruction(ctx); @@ -31239,7 +31235,9 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) #endif } else { /* MDMX: Not implemented. */ - gen_msa(env, ctx); + if (ase_msa_available(env)) { + gen_msa(env, ctx); + } } break; case OPC_PCREL: --=20 2.26.2 From nobody Tue May 21 12:06:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.42 as permitted sender) client-ip=209.85.208.42; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f42.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1608073127; cv=none; d=zohomail.com; s=zohoarc; b=DyMHu3B9ErvirH2MUD69cKadBuSzqaZn97GbZr7ZZ03FxG13CWZRVd1gNPC/GxLHBtZQsoV2feOgmrqF84zlF4XaeLUWxxdC1J6I+hRcYchgL8ONCuggMLz/exybwlDsAxLrgyesflNz1d9gjxVDvAITL0Aa6tvU0uuC1O8MBy4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608073127; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8J3sFo3k2S1YmV6te7FAq6YGGAxZZACq8K+krD2ja+Y=; b=lncK4aY7/u85DTidi6mku5MxVEHxHkUMcc1bd1dQ04PoRmQc8GVJCqdb1Yc9RC7S4pLFr+wft99Fys+s9pbHue2I/V90NZTTQCDYdM3sH3F8oOHipMsgy3hTrgwEzoPcvjq0Rm4FSZJEouLbcFMAEmrnbyyPGatzeG5b+/Waw1s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ed1-f42.google.com (mail-ed1-f42.google.com [209.85.208.42]) by mx.zohomail.com with SMTPS id 1608073127643324.6329418144463; Tue, 15 Dec 2020 14:58:47 -0800 (PST) Received: by mail-ed1-f42.google.com with SMTP id cw27so22812406edb.5 for ; Tue, 15 Dec 2020 14:58:47 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id e11sm19258366edj.44.2020.12.15.14.58.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 14:58:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8J3sFo3k2S1YmV6te7FAq6YGGAxZZACq8K+krD2ja+Y=; b=BmPmPgRoFcjepulKHlWeXFD97VHMYjpE19Xg5pW/CHYTCfOlgE+pSMvoT1OaoTVV// NQWJK4MoVz31Bj9vjGtYHyuB0MmvCjW29ft1wkKP3nrRpsc/9JVt1oAtG10pgePgMAub KVarmzNxbVMREmVttuG1Wn67oV/2TIJvQBdJ6bfS7goY+RO/PM4jkIvXGYEDd/zZSrjQ /U2Dv/9Z7GR1TxNVgqEzU1zFcpiWZ3PS1XtYbQ66/b9Xg8aOln1scJeVUTjTUEm65OIH rr2QXjRqedtRATJQKsGCFEenWCTs4LhUrXuFQZ9TsDVovRNbYEzGaWsme0LEvY9Dy2Xx dVvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=8J3sFo3k2S1YmV6te7FAq6YGGAxZZACq8K+krD2ja+Y=; b=dLn5qcSYgDGXtmFIqvICUweynqA3FN/YzAvCxHqQmOlwFYamkOPMAuZaqsMkcki1h5 WOlgp7JZLbP42/JzdLmx43PCBeg0xNAsxZEGMSoFcFI33ikWCjzAJU9wPhVnuzQIl6Qb +XGa7lxJuElcelbSB1aLclCC+2+fdOj0k4hHeGAQ1RYvkYzWnvzyZXoz5pEgb8Gg5ixI KHJHTlP38dmfTL8+H51R2ywnRiJOicHtZFV1Lr5RAyZObjwLa+o63xIPI3krXCY0CbQP AqYo8RBs36RwTy3UBBFD4JFBeJlnZPWZi2FNZ01BRDRsjN6AVuGvkc9ZVfQ6YI60a3BB yeLA== X-Gm-Message-State: AOAM531ddD6J6+vX4DBGrmzcdemQn3T9ew1+4vpVgdQHwu9BgLcutVQs YWv+t7YZmMA5sjOgObsqJwY= X-Google-Smtp-Source: ABdhPJxs1anFL48anFvNij5UZqX93iuISG9w1P3EGLDcSda41Z4Do1u27B3fRtD06FML0cUwb7VYQQ== X-Received: by 2002:a05:6402:c4:: with SMTP id i4mr16884467edu.152.1608073125852; Tue, 15 Dec 2020 14:58:45 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aleksandar Rikalo , Paolo Bonzini , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen Subject: [PATCH v2 08/24] target/mips: Remove now unused ASE_MSA definition Date: Tue, 15 Dec 2020 23:57:41 +0100 Message-Id: <20201215225757.764263-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215225757.764263-1-f4bug@amsat.org> References: <20201215225757.764263-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We don't use ASE_MSA anymore (replaced by ase_msa_available() checking MSAP bit from CP0_Config3). Remove it. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/mips-defs.h | 1 - target/mips/cpu-defs.c.inc | 8 ++++---- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index ed6a7a9e545..805034b8956 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -45,7 +45,6 @@ #define ASE_MT 0x0000000040000000ULL #define ASE_SMARTMIPS 0x0000000080000000ULL #define ASE_MICROMIPS 0x0000000100000000ULL -#define ASE_MSA 0x0000000200000000ULL /* * bits 40-51: vendor-specific base instruction sets */ diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index bf12e91f715..325b24b8e2c 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -410,7 +410,7 @@ const mips_def_t mips_defs[] =3D .CP1_fcr31_rw_bitmask =3D 0xFF83FFFF, .SEGBITS =3D 32, .PABITS =3D 40, - .insn_flags =3D CPU_MIPS32R5 | ASE_MSA, + .insn_flags =3D CPU_MIPS32R5, .mmu_type =3D MMU_TYPE_R4000, }, { @@ -721,7 +721,7 @@ const mips_def_t mips_defs[] =3D .MSAIR =3D 0x03 << MSAIR_ProcID, .SEGBITS =3D 48, .PABITS =3D 48, - .insn_flags =3D CPU_MIPS64R6 | ASE_MSA, + .insn_flags =3D CPU_MIPS64R6, .mmu_type =3D MMU_TYPE_R4000, }, { @@ -761,7 +761,7 @@ const mips_def_t mips_defs[] =3D .MSAIR =3D 0x03 << MSAIR_ProcID, .SEGBITS =3D 48, .PABITS =3D 48, - .insn_flags =3D CPU_MIPS64R6 | ASE_MSA, + .insn_flags =3D CPU_MIPS64R6, .mmu_type =3D MMU_TYPE_R4000, }, { @@ -887,7 +887,7 @@ const mips_def_t mips_defs[] =3D .CP1_fcr31_rw_bitmask =3D 0xFF83FFFF, .SEGBITS =3D 48, .PABITS =3D 48, - .insn_flags =3D CPU_LOONGSON3A | ASE_MSA, + .insn_flags =3D CPU_LOONGSON3A, .mmu_type =3D MMU_TYPE_R4000, }, { --=20 2.26.2 From nobody Tue May 21 12:06:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.67 as permitted sender) client-ip=209.85.218.67; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-f67.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.67 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1608073133; cv=none; d=zohomail.com; s=zohoarc; b=gPOIv6btrGEgd0W7vbRHl8ZoqyMWWkiD7peZEAQO1Otysq/Gen6JM6FfK6VBohRetA+lHze7TUNX7BjkfSI1co/b71et9qwNszkjyONfz0Kpc7W7n9d7mXgWhpuylj3lvSGxdeFuuyx4yJPNMXkMrGOxHbGdMs81/CyOywpDcq0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608073133; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kJqpgT5cCXxYnWxKZzDjzqN8ClALR+aWkwE4xRgW0a0=; b=ZrVRrS5KNhqGAX4xI910HEKt7Sbf1II/b1P0js4UI6/L7HXWRBTnVsq/TyrM+ndwEsZIYI4Mz1LRHVE79x2+z7zescSQpnB0QIEqa4xaG2SU2E7M+KDujLoOzORSGnBFvBXoQMfaiGMheDkrzZD0bxlvLQUqIg6+GU6fpZWhpXM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.67 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ej1-f67.google.com (mail-ej1-f67.google.com [209.85.218.67]) by mx.zohomail.com with SMTPS id 1608073133271209.58295414155668; Tue, 15 Dec 2020 14:58:53 -0800 (PST) Received: by mail-ej1-f67.google.com with SMTP id jx16so30021998ejb.10 for ; Tue, 15 Dec 2020 14:58:52 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id bo20sm19594936edb.1.2020.12.15.14.58.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 14:58:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kJqpgT5cCXxYnWxKZzDjzqN8ClALR+aWkwE4xRgW0a0=; b=gTO8VbKJ+idG2rHsFWBqs6EjX1k4dH114g1aphDFM3hLMNDb/c/bqfhzs1q4fu1A6U QSUJQQ6CFv/N4acZmCNDJAwZ+Wl2IXvvTU5/Sgws6RvECY3y8X3EUFjrHZGVSOPGuvzh CdTcqTuGtjy1lhsBqiaWfj23F0E1jCQHjQQcuO+3VVgS0GZ/6MhHuNFSXZVNlCxcgOqQ MRF22jmEa6JnjddJrcDSW00rYOY1mUjoN4Dp8sHLiKNQ+V8GviQ1i0Kcfbjvwo3SAjpX sYp2tadnX+jkOmRCQuBlF9syseKhN8B52YsnTgHdvY1mVbq+6g3JYJ9LzkwzdMjY+GiK 6yCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=kJqpgT5cCXxYnWxKZzDjzqN8ClALR+aWkwE4xRgW0a0=; b=KiGJqz0exfJwq/LFlEhkh5aTVo769ph08tSQTn3Fx+eTBojS/G7O1q8bUd+tTyIV8J MXAarJZSf0fR3MotAwqHRGTkE4ULFwt5kqXZ3Ai5yId+mSmpSGIBpATIHRrUQVUSLT+u sh1zV7y08mxBPpPUvMQ7UxFRVd/jrb095Wu0+Md2Zz71mOyj3Dno51IBQiFr+AVkxL6B OuZt9zAeQA4BbO6JNlSPq1cW7nIIf+yZ1DrDuE+7ZXR2bCkJ8Nj12edKTcZo85hoXK3R dzZj87EtuRrlpfDtOU2/fd/TpzoxJUgCQH3Tkaurm7Yd8pGHik+L6vhruHUiJ6Yjw/OE bZrA== X-Gm-Message-State: AOAM532OtjBMIAJQRzgkVTHxE6ZQuzpTl32ZzLuOBDpo0CfVeRVXxKFr 0kADwN0NblzfBa8b2hyw5tg= X-Google-Smtp-Source: ABdhPJw6mJBdcLNfKfj0SBcmVGdXRaRrc1mUEGLeCBa59IbS65+5glqmmr1YxvxsTtTDqdGRw3btTQ== X-Received: by 2002:a17:906:3a84:: with SMTP id y4mr28571019ejd.425.1608073131484; Tue, 15 Dec 2020 14:58:51 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aleksandar Rikalo , Paolo Bonzini , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen Subject: [PATCH v2 09/24] target/mips: Alias MSA vector registers on FPU scalar registers Date: Tue, 15 Dec 2020 23:57:42 +0100 Message-Id: <20201215225757.764263-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215225757.764263-1-f4bug@amsat.org> References: <20201215225757.764263-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Commits 863f264d10f ("add msa_reset(), global msa register") and cb269f273fd ("fix multiple TCG registers covering same data") removed the FPU scalar registers and replaced them by aliases to the MSA vector registers. It is not very clear to have FPU registers displayed with MSA register names, even if MSA ASE is not present. Instead of aliasing FPU registers to the MSA ones (even when MSA is absent), we now alias the MSA ones to the FPU ones (only when MSA is present). Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 02ea184f9a3..9b5b551b616 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31560,16 +31560,20 @@ void mips_tcg_init(void) offsetof(CPUMIPSState, active_tc.gpr[i]), regnames[i]); - for (i =3D 0; i < 32; i++) { int off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); - msa_wr_d[i * 2] =3D - tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2]); + + fpu_f64[i] =3D tcg_global_mem_new_i64(cpu_env, off, fregnames[i]); + } + /* MSA */ + for (i =3D 0; i < 32; i++) { + int off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); + /* - * The scalar floating-point unit (FPU) registers are mapped on - * the MSA vector registers. + * The MSA vector registers are mapped on the + * scalar floating-point unit (FPU) registers. */ - fpu_f64[i] =3D msa_wr_d[i * 2]; + msa_wr_d[i * 2] =3D fpu_f64[i]; off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); msa_wr_d[i * 2 + 1] =3D tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1= ]); --=20 2.26.2 From nobody Tue May 21 12:06:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.68 as permitted sender) client-ip=209.85.218.68; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-f68.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.68 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1608073139; cv=none; d=zohomail.com; s=zohoarc; b=Qdy/IhCMNVd7Z1YEUNW9NB56boArQ9Nayi7dhEcP3bSuPKRqzHhL3zBmJ13HPZ23RfbI5kJDm3JySSQBOj9cRXoaSuXcq1qwBOzchhm/NNZ3PPXdXI+AeJwGMCHc68pL5MgsACIBE1/33hHbJmxx3gP5xsx2ywUXiy4XJIaVWWk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608073139; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9CkPJcd6xJbMtrAkYBIpDMUHZeAN46ko14KRtiJapA4=; b=kuEc77GB1E7x9iscAETQJI23gh9Z0WLal1ocjCfgHEsknmzIbWB+vuMzdV8woeM4XN7MMR1ihNaGdVVCZYD2SeZdAAo390RLcD+JTJmTpYxREIE5L55Q7UoRNUAsFKD2VDWlihmz1zvLBe340Bv0eD96eiXBcB9Tsxkf0QqTNPA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.68 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ej1-f68.google.com (mail-ej1-f68.google.com [209.85.218.68]) by mx.zohomail.com with SMTPS id 160807313900540.2642420769165; Tue, 15 Dec 2020 14:58:59 -0800 (PST) Received: by mail-ej1-f68.google.com with SMTP id d17so30057941ejy.9 for ; Tue, 15 Dec 2020 14:58:58 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id f11sm20315906edy.59.2020.12.15.14.58.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 14:58:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9CkPJcd6xJbMtrAkYBIpDMUHZeAN46ko14KRtiJapA4=; b=BiQ2ycjsxQHoeJ2ijcxRmvB57TPrTeX5ViuRES6OZFetdzaT9AOzR2TawHUGWuQv8D npUNOkwDu/1Dcys6loUgqcXWYP9mrw1DqBHpDwsNtf00lQqYLqXIatAhGwA8Jp0Alj+2 b/w0mDwRvb5SieQVa6SpAm36h63x3N5//j+CS0xfAH2Fo34wz8bQu1Lxe9sGz5i1mKKk VFXboKx8Llpn5KIa8VLLy2cAn/ma77mM97VtslIJKwbhpFvUMgVRqrsqMleMi427ejAG Rhwn4E1aGvCzu37vOQMqRTckjJpU72dpgaEs5woeDuWsNRZTxY2DfrIlHech18Kj73Eu NO0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=9CkPJcd6xJbMtrAkYBIpDMUHZeAN46ko14KRtiJapA4=; b=GbIqVhpd2iCqhepElT1OubHSM/J7yeVNZJwkGYNItPlCVMcu3kepgxw3GdvmeY9jsv +FMkbNX1ft9SdOJKmfVhXNeizAdvBe/DBPjtZvO4XomrM00Zz5a722PJLeQx6Nze6XJF 8ez1PoI3SkyQt/1eNC18qy4QCGwInlIgSdMyLxPE5l4gFA5LewgPfGH10RqIE6UkJImL EhCz2wsr8ZQNhMchwPjQG7QDNIhbwLG/GjVqvYsAoHBeGLb5S/FKvvO2w/oK5vEcMrmB IZDPium3E8n4/dG0tGf3Yytlz03bW6K/eQ+GaD4cA27gMPvcHVCqIXJ0iFIc3jHw4NmF DG8w== X-Gm-Message-State: AOAM5321yFZiDvlcL0DTfQsCBT01R+GqM5kmFvRB61WGu2lZ49RW5eP6 t3YtQdCh5CtLSB4rBkr/AXRF72lF3xE1GA== X-Google-Smtp-Source: ABdhPJyZlHppOI2Oq3wCyB7RtVd2wgnPpWTwgBne8+vso2vjRRs+QQxQcUYlhx4l3UGpsUSEF85sVQ== X-Received: by 2002:a17:906:26ca:: with SMTP id u10mr15722070ejc.165.1608073137198; Tue, 15 Dec 2020 14:58:57 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aleksandar Rikalo , Paolo Bonzini , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen Subject: [PATCH v2 10/24] target/mips: Extract msa_translate_init() from mips_tcg_init() Date: Tue, 15 Dec 2020 23:57:43 +0100 Message-Id: <20201215225757.764263-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215225757.764263-1-f4bug@amsat.org> References: <20201215225757.764263-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The msa_wr_d[] registers are only initialized/used by MSA. They are declared static. We want to move them to the new 'mod-msa_translate.c' unit in few commits, without having to declare them global (with extern). Extract first the logic initialization of the MSA registers from the generic initialization. We will later move this function along with the MSA registers to the new C unit. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.h | 3 +++ target/mips/translate.c | 33 +++++++++++++++++++-------------- 2 files changed, 22 insertions(+), 14 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index 942d803476c..f7e7037bab8 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -161,4 +161,7 @@ extern TCGv bcond; } = \ } while (0) =20 +/* MSA */ +void msa_translate_init(void); + #endif diff --git a/target/mips/translate.c b/target/mips/translate.c index 9b5b551b616..2dc7b446e9a 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31550,6 +31550,24 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, in= t flags) } } =20 +void msa_translate_init(void) +{ + int i; + + for (i =3D 0; i < 32; i++) { + int off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); + + /* + * The MSA vector registers are mapped on the + * scalar floating-point unit (FPU) registers. + */ + msa_wr_d[i * 2] =3D fpu_f64[i]; + off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); + msa_wr_d[i * 2 + 1] =3D + tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1= ]); + } +} + void mips_tcg_init(void) { int i; @@ -31565,20 +31583,7 @@ void mips_tcg_init(void) =20 fpu_f64[i] =3D tcg_global_mem_new_i64(cpu_env, off, fregnames[i]); } - /* MSA */ - for (i =3D 0; i < 32; i++) { - int off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); - - /* - * The MSA vector registers are mapped on the - * scalar floating-point unit (FPU) registers. - */ - msa_wr_d[i * 2] =3D fpu_f64[i]; - off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); - msa_wr_d[i * 2 + 1] =3D - tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1= ]); - } - + msa_translate_init(); cpu_PC =3D tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, active_tc.PC), "PC"= ); for (i =3D 0; i < MIPS_DSP_ACC; i++) { --=20 2.26.2 From nobody Tue May 21 12:06:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.67 as permitted sender) client-ip=209.85.208.67; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f67.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.67 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1608073144; cv=none; d=zohomail.com; s=zohoarc; b=MIlwPR0/XdeJl2uAHH5S+DkWuTeC5uiOR59qgLiZC3naGEURDR/ZHkfIcywv3Rh0HvTyU6sRMxuONDHzzboFw73UMHOhwvz9gG+mnIlIJ2TS4kpra7Ws0bs9UQxH4STLmbxV34apZVESMk6/s0V2p2fmqQhS5yHywtqpiSl6iCQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608073144; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5zf2zjw7Ua1MQ7xeHvN/Qv9OOVErWs8JxWytfST3iqs=; b=MVG8eFzd5YN19fbl7BS+Vl1AEWLgHp3lRmVUZOU/qGfzah4XexGPaFIhGep00MNKpbjYg5WOGgsH3M1Y84uHi7xu0fg3z5aNb/T78QxLuHJkZ/5EkB9/Dj6V8k08OQPryBMsnyrwPOf3JwPrflnoVozD2L0C/19yeNdyJ5T6TMU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.67 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ed1-f67.google.com (mail-ed1-f67.google.com [209.85.208.67]) by mx.zohomail.com with SMTPS id 1608073144606900.7928870279699; Tue, 15 Dec 2020 14:59:04 -0800 (PST) Received: by mail-ed1-f67.google.com with SMTP id r5so22790283eda.12 for ; Tue, 15 Dec 2020 14:59:03 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id d3sm15992825edt.32.2020.12.15.14.59.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 14:59:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5zf2zjw7Ua1MQ7xeHvN/Qv9OOVErWs8JxWytfST3iqs=; b=bd8VrEaOY0lIeveVRZ5st0UbMIrjDDKj5N77Igo82/CrIopTSTXJQGm0XpqALfBkK5 /c41Zd/4YVXlvBzpsa2yJGHme7YxKnYlj8DofH8CMCAvEKRMhLGnF+JuvnjTOPv6X0lv weWYEhpEjGEW4NztIO8KQkrOj/3gskyV7UCqhACkcHWUYKZCFNGzIjLTfLDyaEViPkG/ FTiiTwXTRCoMZxls8ENq3f3pKZuVYdpXwZl2l7bFglkBT9JeQms2fZxEOxdfWHn/0eyE 0LC4QCHPKb+IU54G8iKN5i2C9LO64KIcmW98dI19HHl3a5i4nilPpusJ7iay1JmSs2iN RC3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=5zf2zjw7Ua1MQ7xeHvN/Qv9OOVErWs8JxWytfST3iqs=; b=U+HCZ/GM+ywEPxBq2XA8/eNqMyzJuzryd41iBkhcYxTtjdqMRdWYi0A7agkncWT9/E NhEJPq1r+htO02DtjMFtBD1ySx9E+eniTk95nUhwniywh4RxAT1exgjs9P5zpMkj0CGE WyH44sq4RROPsamdiWfvTfFxEbkJp50gThr/APYNqMok20UBMyt42qIRm2yTwZndLn4N +STeLVb4YeSXs0tKvHOGuJIJyDP6OFWe+xQ1zm5AKxPyOoJ7M9k81uTYrRyVOsv0/ZJM rUD6dOu6oNBCC4edv97JUlxTwLkx+WjIf8ybWOEeQWROlqrByiqCN1mgNsF4SWPG3DvZ lhzA== X-Gm-Message-State: AOAM531qKoB3ja2bBYD73wNd0OUoLEz47I4pzcqckE4SwFYrknGZm+8d 7ZeinpxeFt/Rvjo/0l6zAuI= X-Google-Smtp-Source: ABdhPJzBXm9mLOTp9OQrBSWtUIaVLcn9f6UKQfa9eXf4LHOuRxZvnMSKdoWoiYQhVbL8L3orffphXg== X-Received: by 2002:a50:955b:: with SMTP id v27mr30892887eda.324.1608073142693; Tue, 15 Dec 2020 14:59:02 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aleksandar Rikalo , Paolo Bonzini , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen Subject: [PATCH v2 11/24] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods Date: Tue, 15 Dec 2020 23:57:44 +0100 Message-Id: <20201215225757.764263-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215225757.764263-1-f4bug@amsat.org> References: <20201215225757.764263-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The gen_msa*() methods don't use the "CPUMIPSState *env" argument. Remove it to simplify. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.c | 57 ++++++++++++++++++++--------------------- 1 file changed, 28 insertions(+), 29 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 2dc7b446e9a..a3618a3beb2 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28615,7 +28615,7 @@ static void gen_check_zero_element(TCGv tresult, ui= nt8_t df, uint8_t wt) tcg_temp_free_i64(t1); } =20 -static void gen_msa_branch(CPUMIPSState *env, DisasContext *ctx, uint32_t = op1) +static void gen_msa_branch(DisasContext *ctx, uint32_t op1) { uint8_t df =3D (ctx->opcode >> 21) & 0x3; uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; @@ -28660,7 +28660,7 @@ static void gen_msa_branch(CPUMIPSState *env, Disas= Context *ctx, uint32_t op1) ctx->hflags |=3D MIPS_HFLAG_BDS32; } =20 -static void gen_msa_i8(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_i8(DisasContext *ctx) { #define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24))) uint8_t i8 =3D (ctx->opcode >> 16) & 0xff; @@ -28718,7 +28718,7 @@ static void gen_msa_i8(CPUMIPSState *env, DisasCont= ext *ctx) tcg_temp_free_i32(ti8); } =20 -static void gen_msa_i5(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_i5(DisasContext *ctx) { #define MASK_MSA_I5(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) uint8_t df =3D (ctx->opcode >> 21) & 0x3; @@ -28791,7 +28791,7 @@ static void gen_msa_i5(CPUMIPSState *env, DisasCont= ext *ctx) tcg_temp_free_i32(timm); } =20 -static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_bit(DisasContext *ctx) { #define MASK_MSA_BIT(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) uint8_t dfm =3D (ctx->opcode >> 16) & 0x7f; @@ -28875,7 +28875,7 @@ static void gen_msa_bit(CPUMIPSState *env, DisasCon= text *ctx) tcg_temp_free_i32(tws); } =20 -static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_3r(DisasContext *ctx) { #define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) uint8_t df =3D (ctx->opcode >> 21) & 0x3; @@ -29857,7 +29857,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) tcg_temp_free_i32(tdf); } =20 -static void gen_msa_elm_3e(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_elm_3e(DisasContext *ctx) { #define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16))) uint8_t source =3D (ctx->opcode >> 11) & 0x1f; @@ -29889,8 +29889,7 @@ static void gen_msa_elm_3e(CPUMIPSState *env, Disas= Context *ctx) tcg_temp_free_i32(tsr); } =20 -static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t = df, - uint32_t n) +static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n) { #define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; @@ -30000,7 +29999,7 @@ static void gen_msa_elm_df(CPUMIPSState *env, Disas= Context *ctx, uint32_t df, tcg_temp_free_i32(tdf); } =20 -static void gen_msa_elm(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_elm(DisasContext *ctx) { uint8_t dfn =3D (ctx->opcode >> 16) & 0x3f; uint32_t df =3D 0, n =3D 0; @@ -30019,17 +30018,17 @@ static void gen_msa_elm(CPUMIPSState *env, DisasC= ontext *ctx) df =3D DF_DOUBLE; } else if (dfn =3D=3D 0x3E) { /* CTCMSA, CFCMSA, MOVE.V */ - gen_msa_elm_3e(env, ctx); + gen_msa_elm_3e(ctx); return; } else { gen_reserved_instruction(ctx); return; } =20 - gen_msa_elm_df(env, ctx, df, n); + gen_msa_elm_df(ctx, df, n); } =20 -static void gen_msa_3rf(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_3rf(DisasContext *ctx) { #define MASK_MSA_3RF(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) uint8_t df =3D (ctx->opcode >> 21) & 0x1; @@ -30187,7 +30186,7 @@ static void gen_msa_3rf(CPUMIPSState *env, DisasCon= text *ctx) tcg_temp_free_i32(tdf); } =20 -static void gen_msa_2r(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_2r(DisasContext *ctx) { #define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \ (op & (0x7 << 18))) @@ -30271,7 +30270,7 @@ static void gen_msa_2r(CPUMIPSState *env, DisasCont= ext *ctx) tcg_temp_free_i32(tdf); } =20 -static void gen_msa_2rf(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_2rf(DisasContext *ctx) { #define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \ (op & (0xf << 17))) @@ -30342,7 +30341,7 @@ static void gen_msa_2rf(CPUMIPSState *env, DisasCon= text *ctx) tcg_temp_free_i32(tdf); } =20 -static void gen_msa_vec_v(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_vec_v(DisasContext *ctx) { #define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21))) uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; @@ -30385,7 +30384,7 @@ static void gen_msa_vec_v(CPUMIPSState *env, DisasC= ontext *ctx) tcg_temp_free_i32(twt); } =20 -static void gen_msa_vec(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_vec(DisasContext *ctx) { switch (MASK_MSA_VEC(ctx->opcode)) { case OPC_AND_V: @@ -30395,13 +30394,13 @@ static void gen_msa_vec(CPUMIPSState *env, DisasC= ontext *ctx) case OPC_BMNZ_V: case OPC_BMZ_V: case OPC_BSEL_V: - gen_msa_vec_v(env, ctx); + gen_msa_vec_v(ctx); break; case OPC_MSA_2R: - gen_msa_2r(env, ctx); + gen_msa_2r(ctx); break; case OPC_MSA_2RF: - gen_msa_2rf(env, ctx); + gen_msa_2rf(ctx); break; default: MIPS_INVAL("MSA instruction"); @@ -30410,7 +30409,7 @@ static void gen_msa_vec(CPUMIPSState *env, DisasCon= text *ctx) } } =20 -static void gen_msa(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa(DisasContext *ctx) { uint32_t opcode =3D ctx->opcode; =20 @@ -30420,15 +30419,15 @@ static void gen_msa(CPUMIPSState *env, DisasConte= xt *ctx) case OPC_MSA_I8_00: case OPC_MSA_I8_01: case OPC_MSA_I8_02: - gen_msa_i8(env, ctx); + gen_msa_i8(ctx); break; case OPC_MSA_I5_06: case OPC_MSA_I5_07: - gen_msa_i5(env, ctx); + gen_msa_i5(ctx); break; case OPC_MSA_BIT_09: case OPC_MSA_BIT_0A: - gen_msa_bit(env, ctx); + gen_msa_bit(ctx); break; case OPC_MSA_3R_0D: case OPC_MSA_3R_0E: @@ -30439,18 +30438,18 @@ static void gen_msa(CPUMIPSState *env, DisasConte= xt *ctx) case OPC_MSA_3R_13: case OPC_MSA_3R_14: case OPC_MSA_3R_15: - gen_msa_3r(env, ctx); + gen_msa_3r(ctx); break; case OPC_MSA_ELM: - gen_msa_elm(env, ctx); + gen_msa_elm(ctx); break; case OPC_MSA_3RF_1A: case OPC_MSA_3RF_1B: case OPC_MSA_3RF_1C: - gen_msa_3rf(env, ctx); + gen_msa_3rf(ctx); break; case OPC_MSA_VEC: - gen_msa_vec(env, ctx); + gen_msa_vec(ctx); break; case OPC_LD_B: case OPC_LD_H: @@ -31044,7 +31043,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) case OPC_BNZ_W: case OPC_BNZ_D: if (ase_msa_available(env)) { - gen_msa_branch(env, ctx, op1); + gen_msa_branch(ctx, op1); break; } default: @@ -31236,7 +31235,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) } else { /* MDMX: Not implemented. */ if (ase_msa_available(env)) { - gen_msa(env, ctx); + gen_msa(ctx); } } break; --=20 2.26.2 From nobody Tue May 21 12:06:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.65 as permitted sender) client-ip=209.85.208.65; envelope-from=philippe.mathieu.daude@gmail.com; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id r16sm19543291edp.43.2020.12.15.14.59.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 14:59:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TYp1kFF/ZgtqaQVDZQD7fDzIxF3789Kks3naiine5GE=; b=YWlPSVWSZefcgqL2OOi4n8nNKyDmAM/Pepw9gPoSE4bCQNU7Tz1a8xMhnOMvaSNhxb rP0U59oLP8X+jkyFKYd//GViJfEscsRsvQHDx+qXGosWQTU5GjfVxk6I75ULh73GWgBc HlyYvm+66XPg8jaiKHCf1JuuN7Q6R5OR1BTIVl94V97NXTGOeRqBZgQ3LRoZDhDUb2BN iPauZaf0aslRCdAuJlf2HRVEv5nOUHfsqvHE45amY7uPwnE1DSI7s8cHNv8eCwWLaqJ2 kDSNP9MFBrKN8K1ptOH3WkUaRBbEX+vrhjm5wMhn6pQRU1gDbZvB77Xf5NAApfqF+9Dy coOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=TYp1kFF/ZgtqaQVDZQD7fDzIxF3789Kks3naiine5GE=; b=dXML6JZDhBEuxEwRQt0cSHjFfdtfFItkwCME971f1HGflC2ZXRwRIOD6gvNRAYeaxd 1ecCRnrUUy30aPv83udtZiVWuEVvbCcJ8d+0spy8X/zC+znjjNVuhvKOJFlJW6qIAx5M d48udyj7rD0bnCPqXsy0LqDDmmmAL6kEuQfaKfFF1jRbxTD1ld7Q4QaNPd32IsveMOhe 2qhFRLZ8sL90Q+LW0zSHyQu0wwZkTmeLHSCBMMWNEQbfc+oCDCmjzCbtkVQrW7N/E/no DJHxsrQ5XkShPOrf3u+Wp5QkDMhKNDEvtZjKc+HzJxhsLaFn3WqZH/rR6e6sRYnwPsUm 0xBQ== X-Gm-Message-State: AOAM532enSi2Z/lzP384n/qV290Jl9FZOeYkYP6bkMyOaLpnbc6Ym/dH 2BCXDZR36CadZUMDJhW9yw0= X-Google-Smtp-Source: ABdhPJxJK5sIiExhW7Lpjype3ogdUyNqClpfMJ8TWGQC/YZBHN1qZavGmRQMlTo+hmfU5hM6CP5Qrg== X-Received: by 2002:aa7:c919:: with SMTP id b25mr30495247edt.108.1608073148427; Tue, 15 Dec 2020 14:59:08 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aleksandar Rikalo , Paolo Bonzini , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen Subject: [PATCH v2 12/24] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() Date: Tue, 15 Dec 2020 23:57:45 +0100 Message-Id: <20201215225757.764263-13-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215225757.764263-1-f4bug@amsat.org> References: <20201215225757.764263-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) In preparation of using the decodetree script, explode gen_msa_branch() as following: - OPC_BZ_V -> BxZ_V(EQ) - OPC_BNZ_V -> BxZ_V(NE) - OPC_BZ_[BHWD] -> BxZ(false) - OPC_BNZ_[BHWD] -> BxZ(true) Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.c | 71 ++++++++++++++++++++++++++++------------- 1 file changed, 49 insertions(+), 22 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index a3618a3beb2..9be946256b3 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28615,49 +28615,76 @@ static void gen_check_zero_element(TCGv tresult, = uint8_t df, uint8_t wt) tcg_temp_free_i64(t1); } =20 +static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond) +{ + TCGv_i64 t0; + + check_msa_access(ctx); + + if (ctx->hflags & MIPS_HFLAG_BMASK) { + gen_reserved_instruction(ctx); + return true; + } + t0 =3D tcg_temp_new_i64(); + tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]); + tcg_gen_setcondi_i64(cond, t0, t0, 0); + tcg_gen_trunc_i64_tl(bcond, t0); + tcg_temp_free_i64(t0); + + ctx->btarget =3D ctx->base.pc_next + (s16 << 2) + 4; + + ctx->hflags |=3D MIPS_HFLAG_BC; + ctx->hflags |=3D MIPS_HFLAG_BDS32; + + return true; +} + +static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool i= f_not) +{ + check_msa_access(ctx); + + if (ctx->hflags & MIPS_HFLAG_BMASK) { + gen_reserved_instruction(ctx); + return true; + } + + gen_check_zero_element(bcond, df, wt); + if (if_not) { + tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0); + } + + ctx->btarget =3D ctx->base.pc_next + (s16 << 2) + 4; + ctx->hflags |=3D MIPS_HFLAG_BC; + ctx->hflags |=3D MIPS_HFLAG_BDS32; + + return true; +} + static void gen_msa_branch(DisasContext *ctx, uint32_t op1) { uint8_t df =3D (ctx->opcode >> 21) & 0x3; uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; int64_t s16 =3D (int16_t)ctx->opcode; =20 - check_msa_access(ctx); - - if (ctx->hflags & MIPS_HFLAG_BMASK) { - gen_reserved_instruction(ctx); - return; - } switch (op1) { case OPC_BZ_V: case OPC_BNZ_V: - { - TCGv_i64 t0 =3D tcg_temp_new_i64(); - tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]); - tcg_gen_setcondi_i64((op1 =3D=3D OPC_BZ_V) ? - TCG_COND_EQ : TCG_COND_NE, t0, t0, 0); - tcg_gen_trunc_i64_tl(bcond, t0); - tcg_temp_free_i64(t0); - } + gen_msa_BxZ_V(ctx, wt, s16, (op1 =3D=3D OPC_BZ_V) ? + TCG_COND_EQ : TCG_COND_NE); break; case OPC_BZ_B: case OPC_BZ_H: case OPC_BZ_W: case OPC_BZ_D: - gen_check_zero_element(bcond, df, wt); + gen_msa_BxZ(ctx, df, wt, s16, false); break; case OPC_BNZ_B: case OPC_BNZ_H: case OPC_BNZ_W: case OPC_BNZ_D: - gen_check_zero_element(bcond, df, wt); - tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0); + gen_msa_BxZ(ctx, df, wt, s16, true); break; } - - ctx->btarget =3D ctx->base.pc_next + (s16 << 2) + 4; - - ctx->hflags |=3D MIPS_HFLAG_BC; - ctx->hflags |=3D MIPS_HFLAG_BDS32; } =20 static void gen_msa_i8(DisasContext *ctx) --=20 2.26.2 From nobody Tue May 21 12:06:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.51 as permitted sender) client-ip=209.85.218.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1608073155; cv=none; d=zohomail.com; s=zohoarc; b=B2TsUeO2xvfz4E3bvaUZUKAN3ouR9mG2fmzmBdu7R8NFb6EDp8XLIYNPewLjIxeFOegG7lnGf5tscztuK0V7KOcEipyhKDARJVcYAo+GvzytizqdlE0VwmMwdAYEl0REbfj0Ro0RYvb38ap7bdPzxeLbJz0Jb9kvFiZkAj9viVU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608073155; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LK9i50FxwiL3rNg7XdhCP+0wnCiZXodjB1KHibKvjIg=; b=RLOHnuUJfQhyufFL3KsuN7TjPEl05Xo4YXuwKTXhZ1aRuG1O+f+fKn4BX+PokqJusVhDVsqFsAnwp/3qNWEHk9lWy3eUHNHzC6B+FuL4f6GyjIlvG86XwGkmJZ874UohNbmaUKl0+Febzzm6VNjRLgv4YpiUaEHkRde/sl2KuxU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ej1-f51.google.com (mail-ej1-f51.google.com [209.85.218.51]) by mx.zohomail.com with SMTPS id 1608073155735416.4681897450496; Tue, 15 Dec 2020 14:59:15 -0800 (PST) Received: by mail-ej1-f51.google.com with SMTP id ce23so30048435ejb.8 for ; Tue, 15 Dec 2020 14:59:15 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id cc8sm20203236edb.17.2020.12.15.14.59.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 14:59:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LK9i50FxwiL3rNg7XdhCP+0wnCiZXodjB1KHibKvjIg=; b=C7+31wk0dn7nvtLlLbxQ4tdyPvFocz+jtQVbV6fd/Exq7EiiI1Vs35cDoR/f5NBMCj RJMJx/qMLe+sSU9/eg6XYz8vQaRJH1URYGtksIlkLf0lNyEYKvAV8w6MF0UhRvYhAzjf q+xXwE9N0zJW7KvCaM4qaJYOEBq6l1DX0UWNa4LNAg4ZKBHKuIm6NNAvD14mZLB5zdbg SoQLlCidIImoZC6Aokyp4xjMQ8kA/hykrPAmqCjOFlYQsTtznNZa8fQvau+NpOOlOeDJ DRRPas9CQnCp/CuW33x/Co5DZUGOXpMZyjJ5WBbPq9V63bMms/ivXFJMki9d8pX0Naab ha/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=LK9i50FxwiL3rNg7XdhCP+0wnCiZXodjB1KHibKvjIg=; b=p6aoJeuZz2q+Wgk3LFYQkhD3Jjz5CCvgnuOIdvWCUF8yvtrQCWmRb1BjG7G6elpTPn 3t4+HQIAuWVm/OcMz+gitkOsoxomF9+QDQ55SZ9owiqoDMiLa4GFg452Ekk0oMTtz5ke 3jMDQSTK7qAFJScZ0zCX6jYiYmLoDXxGG+1VsVjvzS5uUTQDLzjMyPjyxELLuKAF7PuP +sfbrAn4gB2uz3PCL/Hk2nI0OefN5mBteko4Q9/uCDEp/OExfa+nuW9KxLCJuNYat8Ab 8GCtpAWjWsGm5f07Y28Gb89DQ4budbv1dD53lZR+jmAb9HEGozTrtst4bi757/sAEVKq pI5A== X-Gm-Message-State: AOAM5306NGirLZHVNUBaFXpfYp6SAoxlMpzusCFV3lEPu4fqky0b2ihf XNL8RKUzXGjFz761stAL3JI= X-Google-Smtp-Source: ABdhPJwQL9CCQxq3bPS0duIjRuCmTSMfE/3q2UjXzR60heKG3S98TXLkf8U9pAaYKT0+ILnrFYl6pw== X-Received: by 2002:a17:906:9250:: with SMTP id c16mr29307186ejx.355.1608073153983; Tue, 15 Dec 2020 14:59:13 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aleksandar Rikalo , Paolo Bonzini , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen Subject: [PATCH v2 13/24] target/mips: Rename msa_helper.c as mod-msa_helper.c Date: Tue, 15 Dec 2020 23:57:46 +0100 Message-Id: <20201215225757.764263-14-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215225757.764263-1-f4bug@amsat.org> References: <20201215225757.764263-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) MSA means 'MIPS SIMD Architecture' and is defined as a Module by MIPS. To keep the directory sorted, we use the 'mod' prefix for MIPS modules. Rename msa_helper.c as mod-msa_helper.c. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201123204448.3260804-4-f4bug@amsat.org> --- target/mips/{msa_helper.c =3D> mod-msa_helper.c} | 0 target/mips/meson.build | 2 +- 2 files changed, 1 insertion(+), 1 deletion(-) rename target/mips/{msa_helper.c =3D> mod-msa_helper.c} (100%) diff --git a/target/mips/msa_helper.c b/target/mips/mod-msa_helper.c similarity index 100% rename from target/mips/msa_helper.c rename to target/mips/mod-msa_helper.c diff --git a/target/mips/meson.build b/target/mips/meson.build index 596eb1aeeb3..05ed33b75ce 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -7,8 +7,8 @@ 'dsp_helper.c', 'fpu_helper.c', 'lmmi_helper.c', - 'msa_helper.c', 'op_helper.c', + 'mod-msa_helper.c', 'tlb_helper.c', 'translate.c', )) --=20 2.26.2 From nobody Tue May 21 12:06:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.66 as permitted sender) client-ip=209.85.208.66; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f66.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.66 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1608073161; cv=none; d=zohomail.com; s=zohoarc; b=We3Us3OP69TLPdshWcZZeJhi5bz993r5OzqWXpmqGLFExQCw44kero+HvXT7BPDG8/IWh5T0KdRpMXWK/EqKXgxNihohDA630h8/nzOEWQLaqfsYzoElkd57B5h8JbiT/NJaVk5+xSw0KRUBJllvGXLHm5c67ivhaPlWlSfuhy4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608073161; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=r721GGoO1vJJZamWSQ/I62tzPtsotRE5k1CFdAPPmsI=; b=FkqhnGQbf7eaegxFe2GkNrgZoJgic/n1f8Dyc9OvbXBxJNR5+mn5T8ex7qGcGKbbYjchWNCetZuIf8ppCRST9pS1V0bKXnA57ItcyiwKJGU5kioS5DQ3NCk9XyS3L3IWYu6pKHzya6cIi30j4bXqghCYxDWwW3sUwQNKVXiRZy4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.66 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ed1-f66.google.com (mail-ed1-f66.google.com [209.85.208.66]) by mx.zohomail.com with SMTPS id 1608073161297233.2317850531373; Tue, 15 Dec 2020 14:59:21 -0800 (PST) Received: by mail-ed1-f66.google.com with SMTP id v22so22799429edt.9 for ; Tue, 15 Dec 2020 14:59:20 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id f11sm20317375edy.59.2020.12.15.14.59.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 14:59:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=r721GGoO1vJJZamWSQ/I62tzPtsotRE5k1CFdAPPmsI=; b=ksGYyZqUjnjTpQUlnJkwvhrtsTgCJRP3j5mC6OARLNZQF2ZrJ1V+UhVw8CojGWW3/3 WO5B8qupZBGOhKvfYWG4DItmratQ+a/4+qPS1HLXosQWnWKkPc/nkPvCs4l+Jov8kDx/ t8HSxfIh8b5woyVg5KHKoYSQqbU2txnbWYDuKV6NSfRJQ/j+skrIqCkyHWey8VVbqiOM XM9lf20J9/7RHu09BygD1EfvPu3uGCxO3lFf1xFqjRZUCHqPNhVX/Xkxqw6aBL8HTfbW UPhbdt4btRRu8RbClKYwtZcbkLrYPvFR9aadTWTEpUQ0BSzijYdMj1wdVlse/Vx66Doe SxkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=r721GGoO1vJJZamWSQ/I62tzPtsotRE5k1CFdAPPmsI=; b=VkySPJNfdhhj4DAj8osCOiQWPXAYpUeVOvaBKA2Vvp8UI639gyxxxBEn+YlIgDzv7i M+YzYCSigmhRk9YbgEG/B3/bfCTcmHE+RFdZMcwXI5U+3xwhKECVfzJNsX79P02KqVC5 77ONNO+PkNqTM45LFRBrh4H3YC9y5ixQQcIMnokpaWZcWY60U4XQXXEvlQmxd+CWOMBM z20oZyW7VluD5CCGGcCpH+I57y3RT1R9QEfsywtXkyoEYozQ/Sg6WnZY3agD8Y14JFkf 4MgOVK1JI1QKeukmt9zyse+1lMaIAWAekF50mTFGxSNiZvly+w/JrSFakk5EWveRHOIv St0w== X-Gm-Message-State: AOAM533lTd3PHHiel+GCebeXT1BCE2q1OW3xmjnAxBAnZrxhgnJoGyzJ sD8fPnt5/gzbJSQoip6MrqQ= X-Google-Smtp-Source: ABdhPJzDX2qNpMB5rixf8fmszl3M6Xc5Sf7KCB17rbtRfsvmzCRyz1COJgMcmCqIhuY2FxDNAuNTPQ== X-Received: by 2002:aa7:d75a:: with SMTP id a26mr30675115eds.230.1608073159415; Tue, 15 Dec 2020 14:59:19 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aleksandar Rikalo , Paolo Bonzini , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen Subject: [PATCH v2 14/24] target/mips: Move msa_reset() to mod-msa_helper.c Date: Tue, 15 Dec 2020 23:57:47 +0100 Message-Id: <20201215225757.764263-15-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215225757.764263-1-f4bug@amsat.org> References: <20201215225757.764263-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) translate_init.c.inc mostly contains CPU definitions. msa_reset() doesn't belong here, move it with the MSA helpers. One comment style is updated to avoid checkpatch.pl warning. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/internal.h | 2 ++ target/mips/cpu.c | 1 + target/mips/mod-msa_helper.c | 36 ++++++++++++++++++++++++++++++++++++ target/mips/cpu-defs.c.inc | 36 ------------------------------------ 4 files changed, 39 insertions(+), 36 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 1ab2454e61d..76269cfc7bb 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -199,6 +199,8 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMI= PSState *env) =20 void mips_tcg_init(void); =20 +void msa_reset(CPUMIPSState *env); + /* cp0_timer.c */ uint32_t cpu_mips_get_count(CPUMIPSState *env); void cpu_mips_store_count(CPUMIPSState *env, uint32_t value); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 77ebd94c655..26e110b687e 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -33,6 +33,7 @@ #include "hw/qdev-clock.h" #include "hw/semihosting/semihost.h" #include "qapi/qapi-commands-machine-target.h" +#include "fpu_helper.h" =20 #if !defined(CONFIG_USER_ONLY) =20 diff --git a/target/mips/mod-msa_helper.c b/target/mips/mod-msa_helper.c index b89b4c44902..f0d728c03f0 100644 --- a/target/mips/mod-msa_helper.c +++ b/target/mips/mod-msa_helper.c @@ -8201,3 +8201,39 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32= _t df, uint32_t wd, =20 msa_move_v(pwd, pwx); } + +void msa_reset(CPUMIPSState *env) +{ + if (!ase_msa_available(env)) { + return; + } + +#ifdef CONFIG_USER_ONLY + /* MSA access enabled */ + env->CP0_Config5 |=3D 1 << CP0C5_MSAEn; + env->CP0_Status |=3D (1 << CP0St_CU1) | (1 << CP0St_FR); +#endif + + /* + * MSA CSR: + * - non-signaling floating point exception mode off (NX bit is 0) + * - Cause, Enables, and Flags are all 0 + * - round to nearest / ties to even (RM bits are 0) + */ + env->active_tc.msacsr =3D 0; + + restore_msa_fp_status(env); + + /* tininess detected after rounding.*/ + set_float_detect_tininess(float_tininess_after_rounding, + &env->active_tc.msa_fp_status); + + /* clear float_status exception flags */ + set_float_exception_flags(0, &env->active_tc.msa_fp_status); + + /* clear float_status nan mode */ + set_default_nan_mode(0, &env->active_tc.msa_fp_status); + + /* set proper signanling bit meaning ("1" means "quiet") */ + set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); +} diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index 325b24b8e2c..320ebf29f1f 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -18,8 +18,6 @@ * License along with this library; if not, see . */ =20 -#include "fpu_helper.h" - /* CPU / CPU family specific config register values. */ =20 /* Have config1, uncached coherency */ @@ -973,37 +971,3 @@ static void mvp_init(CPUMIPSState *env) (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2= ) | (0x1 << CP0MVPC1_PCP1); } - -static void msa_reset(CPUMIPSState *env) -{ - if (!ase_msa_available(env)) { - return; - } - -#ifdef CONFIG_USER_ONLY - /* MSA access enabled */ - env->CP0_Config5 |=3D 1 << CP0C5_MSAEn; - env->CP0_Status |=3D (1 << CP0St_CU1) | (1 << CP0St_FR); -#endif - - /* MSA CSR: - - non-signaling floating point exception mode off (NX bit is 0) - - Cause, Enables, and Flags are all 0 - - round to nearest / ties to even (RM bits are 0) */ - env->active_tc.msacsr =3D 0; - - restore_msa_fp_status(env); - - /* tininess detected after rounding.*/ - set_float_detect_tininess(float_tininess_after_rounding, - &env->active_tc.msa_fp_status); - - /* clear float_status exception flags */ - set_float_exception_flags(0, &env->active_tc.msa_fp_status); - - /* clear float_status nan mode */ - set_default_nan_mode(0, &env->active_tc.msa_fp_status); - - /* set proper signanling bit meaning ("1" means "quiet") */ - set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); -} --=20 2.26.2 From nobody Tue May 21 12:06:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.48 as permitted sender) client-ip=209.85.218.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1608073168; cv=none; d=zohomail.com; s=zohoarc; b=DdNqXZ28zevs9S4Oooo137Uetf6PE0APKB8y47HOGumnfmAvJ/ISr2pGYm54nWkIUSeNBti5vzOyaHFNZEkDPTRZqoWx7DupSY2r/8lovPGbMHC/esvGkAwOmvsEy0ffJtDhcShuDn/t72NT4Ia/XKXvm1J8rWHJYuDYvMb96/4= ARC-Message-Signature: i=1; a=rsa-sha256; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id c14sm19521003edy.56.2020.12.15.14.59.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 14:59:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6xZ+w3WMxxDlNGoSG1hn/yu43KVZtKsTpEsvr13gWkM=; b=ASUBwU2Bn49X4RoHswzb74viINae58oSJIMDr3KGzdP1w3YX8BxT7UYAC+LjZIy9ys kmvrR4b2eo2YeQnlFQRdZe9WwNtrLD1Pvx3/EXHth3SLWC3RhmygX94s2TPJ39UxPhEh J3CJAbWtwN05+aKDw8RcZVXYk0WmYdk6e8zOUjr7EmftuPvkCCLwvNuYEWE4TA4pp849 6XyFP1rq+/VJLRAXSnO57PG67jIsQuP5tWJYEplRgaIb2SrQxOEoAxYRfcULJVcDPF+h 1lryQJo2sRH63MP8HSz1lbRgy4VwfzHUPhvxsUJPGBU8kEJFwySOCS2glFsZswScCZvX Sy9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=6xZ+w3WMxxDlNGoSG1hn/yu43KVZtKsTpEsvr13gWkM=; b=P0Gc0vAWspoEmuYLR9dtOb9ZuHIvhelym0Y/5xpZgo4JULioMQCIbGORP3XlLArtai Vec1k3Aump6t2jQIepGYJL+vLiLH8VgpNGgkoKQRt7RY41Uc97AFxbkFPgbUGXpH4yxX i7rwwUnZ91ia8vKpjHTyVUfwb615OF9MX7jrPISWE9ZhCh9yDEP8FnSlwqURvZt2IzSQ FpCFs/VT2VAW/tqLfQXJPdzpEm/4+PKy2LhI+e9yUi6icxqxjDd+mwaLoIqKZd0saWMi +Y2hwXOBB3hA3+lc28NEOTYdIlUYCGgZjVTadzVj1c3UK7I9KxtOdBDASeDDeOv+N+Q7 N8Og== X-Gm-Message-State: AOAM531pfAXUmrMv1N0RFUTDctMt26vorm9/PVQep6f+/kQ3n3xmdO3k TiNBbCcNyRfQBlrXJ4vFZAs= X-Google-Smtp-Source: ABdhPJwUZGleQ6C9snTUQ3nVpF+3yM+EuFdgHGRRTCwq1zSSEj/sX3365YXHpVFiX+iLMwvl9GiE+w== X-Received: by 2002:a17:906:c254:: with SMTP id bl20mr7663666ejb.336.1608073164938; Tue, 15 Dec 2020 14:59:24 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aleksandar Rikalo , Paolo Bonzini , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen Subject: [PATCH v2 15/24] target/mips: Extract MSA helpers from op_helper.c Date: Tue, 15 Dec 2020 23:57:48 +0100 Message-Id: <20201215225757.764263-16-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215225757.764263-1-f4bug@amsat.org> References: <20201215225757.764263-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We have ~400 lines of MSA helpers in the generic op_helper.c, move them with the other helpers in 'mod-msa_helper.c'. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201123204448.3260804-5-f4bug@amsat.org> --- target/mips/mod-msa_helper.c | 393 ++++++++++++++++++++++++++++++++++ target/mips/op_helper.c | 394 ----------------------------------- 2 files changed, 393 insertions(+), 394 deletions(-) diff --git a/target/mips/mod-msa_helper.c b/target/mips/mod-msa_helper.c index f0d728c03f0..1298a1917ce 100644 --- a/target/mips/mod-msa_helper.c +++ b/target/mips/mod-msa_helper.c @@ -22,6 +22,7 @@ #include "internal.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" +#include "exec/memop.h" #include "fpu/softfloat.h" #include "fpu_helper.h" =20 @@ -8202,6 +8203,398 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint3= 2_t df, uint32_t wd, msa_move_v(pwd, pwx); } =20 +/* Data format min and max values */ +#define DF_BITS(df) (1 << ((df) + 3)) + +/* Element-by-element access macros */ +#define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df)) + +#if !defined(CONFIG_USER_ONLY) +#define MEMOP_IDX(DF) \ + TCGMemOpIdx oi =3D make_memop_idx(MO_TE | DF | MO_UNALN, \ + cpu_mmu_index(env, false)); +#else +#define MEMOP_IDX(DF) +#endif + +void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + MEMOP_IDX(DF_BYTE) +#if !defined(CONFIG_USER_ONLY) +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->b[0] =3D helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GE= TPC()); + pwd->b[1] =3D helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GE= TPC()); + pwd->b[2] =3D helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GE= TPC()); + pwd->b[3] =3D helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GE= TPC()); + pwd->b[4] =3D helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GE= TPC()); + pwd->b[5] =3D helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GE= TPC()); + pwd->b[6] =3D helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GE= TPC()); + pwd->b[7] =3D helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GE= TPC()); + pwd->b[8] =3D helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GE= TPC()); + pwd->b[9] =3D helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GE= TPC()); + pwd->b[10] =3D helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GE= TPC()); + pwd->b[11] =3D helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GE= TPC()); + pwd->b[12] =3D helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GE= TPC()); + pwd->b[13] =3D helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GE= TPC()); + pwd->b[14] =3D helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GE= TPC()); + pwd->b[15] =3D helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GE= TPC()); +#else + pwd->b[0] =3D helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GE= TPC()); + pwd->b[1] =3D helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GE= TPC()); + pwd->b[2] =3D helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GE= TPC()); + pwd->b[3] =3D helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GE= TPC()); + pwd->b[4] =3D helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GE= TPC()); + pwd->b[5] =3D helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GE= TPC()); + pwd->b[6] =3D helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GE= TPC()); + pwd->b[7] =3D helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GE= TPC()); + pwd->b[8] =3D helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GE= TPC()); + pwd->b[9] =3D helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GE= TPC()); + pwd->b[10] =3D helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GE= TPC()); + pwd->b[11] =3D helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GE= TPC()); + pwd->b[12] =3D helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GE= TPC()); + pwd->b[13] =3D helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GE= TPC()); + pwd->b[14] =3D helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GE= TPC()); + pwd->b[15] =3D helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GE= TPC()); +#endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->b[0] =3D cpu_ldub_data(env, addr + (0 << DF_BYTE)); + pwd->b[1] =3D cpu_ldub_data(env, addr + (1 << DF_BYTE)); + pwd->b[2] =3D cpu_ldub_data(env, addr + (2 << DF_BYTE)); + pwd->b[3] =3D cpu_ldub_data(env, addr + (3 << DF_BYTE)); + pwd->b[4] =3D cpu_ldub_data(env, addr + (4 << DF_BYTE)); + pwd->b[5] =3D cpu_ldub_data(env, addr + (5 << DF_BYTE)); + pwd->b[6] =3D cpu_ldub_data(env, addr + (6 << DF_BYTE)); + pwd->b[7] =3D cpu_ldub_data(env, addr + (7 << DF_BYTE)); + pwd->b[8] =3D cpu_ldub_data(env, addr + (8 << DF_BYTE)); + pwd->b[9] =3D cpu_ldub_data(env, addr + (9 << DF_BYTE)); + pwd->b[10] =3D cpu_ldub_data(env, addr + (10 << DF_BYTE)); + pwd->b[11] =3D cpu_ldub_data(env, addr + (11 << DF_BYTE)); + pwd->b[12] =3D cpu_ldub_data(env, addr + (12 << DF_BYTE)); + pwd->b[13] =3D cpu_ldub_data(env, addr + (13 << DF_BYTE)); + pwd->b[14] =3D cpu_ldub_data(env, addr + (14 << DF_BYTE)); + pwd->b[15] =3D cpu_ldub_data(env, addr + (15 << DF_BYTE)); +#else + pwd->b[0] =3D cpu_ldub_data(env, addr + (7 << DF_BYTE)); + pwd->b[1] =3D cpu_ldub_data(env, addr + (6 << DF_BYTE)); + pwd->b[2] =3D cpu_ldub_data(env, addr + (5 << DF_BYTE)); + pwd->b[3] =3D cpu_ldub_data(env, addr + (4 << DF_BYTE)); + pwd->b[4] =3D cpu_ldub_data(env, addr + (3 << DF_BYTE)); + pwd->b[5] =3D cpu_ldub_data(env, addr + (2 << DF_BYTE)); + pwd->b[6] =3D cpu_ldub_data(env, addr + (1 << DF_BYTE)); + pwd->b[7] =3D cpu_ldub_data(env, addr + (0 << DF_BYTE)); + pwd->b[8] =3D cpu_ldub_data(env, addr + (15 << DF_BYTE)); + pwd->b[9] =3D cpu_ldub_data(env, addr + (14 << DF_BYTE)); + pwd->b[10] =3D cpu_ldub_data(env, addr + (13 << DF_BYTE)); + pwd->b[11] =3D cpu_ldub_data(env, addr + (12 << DF_BYTE)); + pwd->b[12] =3D cpu_ldub_data(env, addr + (11 << DF_BYTE)); + pwd->b[13] =3D cpu_ldub_data(env, addr + (10 << DF_BYTE)); + pwd->b[14] =3D cpu_ldub_data(env, addr + (9 << DF_BYTE)); + pwd->b[15] =3D cpu_ldub_data(env, addr + (8 << DF_BYTE)); +#endif +#endif +} + +void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + MEMOP_IDX(DF_HALF) +#if !defined(CONFIG_USER_ONLY) +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->h[0] =3D helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETP= C()); + pwd->h[1] =3D helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETP= C()); + pwd->h[2] =3D helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETP= C()); + pwd->h[3] =3D helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETP= C()); + pwd->h[4] =3D helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETP= C()); + pwd->h[5] =3D helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETP= C()); + pwd->h[6] =3D helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETP= C()); + pwd->h[7] =3D helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETP= C()); +#else + pwd->h[0] =3D helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETP= C()); + pwd->h[1] =3D helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETP= C()); + pwd->h[2] =3D helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETP= C()); + pwd->h[3] =3D helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETP= C()); + pwd->h[4] =3D helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETP= C()); + pwd->h[5] =3D helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETP= C()); + pwd->h[6] =3D helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETP= C()); + pwd->h[7] =3D helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETP= C()); +#endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->h[0] =3D cpu_lduw_data(env, addr + (0 << DF_HALF)); + pwd->h[1] =3D cpu_lduw_data(env, addr + (1 << DF_HALF)); + pwd->h[2] =3D cpu_lduw_data(env, addr + (2 << DF_HALF)); + pwd->h[3] =3D cpu_lduw_data(env, addr + (3 << DF_HALF)); + pwd->h[4] =3D cpu_lduw_data(env, addr + (4 << DF_HALF)); + pwd->h[5] =3D cpu_lduw_data(env, addr + (5 << DF_HALF)); + pwd->h[6] =3D cpu_lduw_data(env, addr + (6 << DF_HALF)); + pwd->h[7] =3D cpu_lduw_data(env, addr + (7 << DF_HALF)); +#else + pwd->h[0] =3D cpu_lduw_data(env, addr + (3 << DF_HALF)); + pwd->h[1] =3D cpu_lduw_data(env, addr + (2 << DF_HALF)); + pwd->h[2] =3D cpu_lduw_data(env, addr + (1 << DF_HALF)); + pwd->h[3] =3D cpu_lduw_data(env, addr + (0 << DF_HALF)); + pwd->h[4] =3D cpu_lduw_data(env, addr + (7 << DF_HALF)); + pwd->h[5] =3D cpu_lduw_data(env, addr + (6 << DF_HALF)); + pwd->h[6] =3D cpu_lduw_data(env, addr + (5 << DF_HALF)); + pwd->h[7] =3D cpu_lduw_data(env, addr + (4 << DF_HALF)); +#endif +#endif +} + +void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + MEMOP_IDX(DF_WORD) +#if !defined(CONFIG_USER_ONLY) +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->w[0] =3D helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETP= C()); + pwd->w[1] =3D helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETP= C()); + pwd->w[2] =3D helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETP= C()); + pwd->w[3] =3D helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETP= C()); +#else + pwd->w[0] =3D helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETP= C()); + pwd->w[1] =3D helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETP= C()); + pwd->w[2] =3D helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETP= C()); + pwd->w[3] =3D helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETP= C()); +#endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->w[0] =3D cpu_ldl_data(env, addr + (0 << DF_WORD)); + pwd->w[1] =3D cpu_ldl_data(env, addr + (1 << DF_WORD)); + pwd->w[2] =3D cpu_ldl_data(env, addr + (2 << DF_WORD)); + pwd->w[3] =3D cpu_ldl_data(env, addr + (3 << DF_WORD)); +#else + pwd->w[0] =3D cpu_ldl_data(env, addr + (1 << DF_WORD)); + pwd->w[1] =3D cpu_ldl_data(env, addr + (0 << DF_WORD)); + pwd->w[2] =3D cpu_ldl_data(env, addr + (3 << DF_WORD)); + pwd->w[3] =3D cpu_ldl_data(env, addr + (2 << DF_WORD)); +#endif +#endif +} + +void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + MEMOP_IDX(DF_DOUBLE) +#if !defined(CONFIG_USER_ONLY) + pwd->d[0] =3D helper_ret_ldq_mmu(env, addr + (0 << DF_DOUBLE), oi, GET= PC()); + pwd->d[1] =3D helper_ret_ldq_mmu(env, addr + (1 << DF_DOUBLE), oi, GET= PC()); +#else + pwd->d[0] =3D cpu_ldq_data(env, addr + (0 << DF_DOUBLE)); + pwd->d[1] =3D cpu_ldq_data(env, addr + (1 << DF_DOUBLE)); +#endif +} + +#define MSA_PAGESPAN(x) \ + ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN / 8 - 1) >=3D TARGET_PAGE_= SIZE) + +static inline void ensure_writable_pages(CPUMIPSState *env, + target_ulong addr, + int mmu_idx, + uintptr_t retaddr) +{ + /* FIXME: Probe the actual accesses (pass and use a size) */ + if (unlikely(MSA_PAGESPAN(addr))) { + /* first page */ + probe_write(env, addr, 0, mmu_idx, retaddr); + /* second page */ + addr =3D (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; + probe_write(env, addr, 0, mmu_idx, retaddr); + } +} + +void helper_msa_st_b(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + int mmu_idx =3D cpu_mmu_index(env, false); + + MEMOP_IDX(DF_BYTE) + ensure_writable_pages(env, addr, mmu_idx, GETPC()); +#if !defined(CONFIG_USER_ONLY) +#if !defined(HOST_WORDS_BIGENDIAN) + helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[0], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[1], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[2], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[3], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[4], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[5], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[6], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[7], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[8], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[9], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[10], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[11], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[12], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[13], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[14], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[15], oi, GETPC(= )); +#else + helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[0], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[1], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[2], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[3], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[4], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[5], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[6], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[7], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[8], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[9], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[10], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[11], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[12], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[13], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[14], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[15], oi, GETPC(= )); +#endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[0]); + cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[1]); + cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[2]); + cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[3]); + cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[4]); + cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[5]); + cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[6]); + cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[7]); + cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[8]); + cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[9]); + cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[10]); + cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[11]); + cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[12]); + cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[13]); + cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[14]); + cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[15]); +#else + cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[0]); + cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[1]); + cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[2]); + cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[3]); + cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[4]); + cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[5]); + cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[6]); + cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[7]); + cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[8]); + cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[9]); + cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[10]); + cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[11]); + cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[12]); + cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[13]); + cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[14]); + cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[15]); +#endif +#endif +} + +void helper_msa_st_h(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + int mmu_idx =3D cpu_mmu_index(env, false); + + MEMOP_IDX(DF_HALF) + ensure_writable_pages(env, addr, mmu_idx, GETPC()); +#if !defined(CONFIG_USER_ONLY) +#if !defined(HOST_WORDS_BIGENDIAN) + helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[0], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[1], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[2], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[3], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[4], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[5], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[6], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[7], oi, GETPC()); +#else + helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[0], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[1], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[2], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[3], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[4], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[5], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[6], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[7], oi, GETPC()); +#endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[0]); + cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[1]); + cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[2]); + cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[3]); + cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[4]); + cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[5]); + cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[6]); + cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[7]); +#else + cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[0]); + cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[1]); + cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[2]); + cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[3]); + cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[4]); + cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[5]); + cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[6]); + cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[7]); +#endif +#endif +} + +void helper_msa_st_w(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + int mmu_idx =3D cpu_mmu_index(env, false); + + MEMOP_IDX(DF_WORD) + ensure_writable_pages(env, addr, mmu_idx, GETPC()); +#if !defined(CONFIG_USER_ONLY) +#if !defined(HOST_WORDS_BIGENDIAN) + helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[0], oi, GETPC()); + helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[1], oi, GETPC()); + helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[2], oi, GETPC()); + helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[3], oi, GETPC()); +#else + helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[0], oi, GETPC()); + helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[1], oi, GETPC()); + helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[2], oi, GETPC()); + helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[3], oi, GETPC()); +#endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[0]); + cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[1]); + cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[2]); + cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[3]); +#else + cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[0]); + cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[1]); + cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[2]); + cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[3]); +#endif +#endif +} + +void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + int mmu_idx =3D cpu_mmu_index(env, false); + + MEMOP_IDX(DF_DOUBLE) + ensure_writable_pages(env, addr, mmu_idx, GETPC()); +#if !defined(CONFIG_USER_ONLY) + helper_ret_stq_mmu(env, addr + (0 << DF_DOUBLE), pwd->d[0], oi, GETPC(= )); + helper_ret_stq_mmu(env, addr + (1 << DF_DOUBLE), pwd->d[1], oi, GETPC(= )); +#else + cpu_stq_data(env, addr + (0 << DF_DOUBLE), pwd->d[0]); + cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]); +#endif +} + void msa_reset(CPUMIPSState *env) { if (!ase_msa_available(env)) { diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 3386b8228e9..89c7d4556a0 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -1173,400 +1173,6 @@ void mips_cpu_do_transaction_failed(CPUState *cs, h= waddr physaddr, } #endif /* !CONFIG_USER_ONLY */ =20 - -/* MSA */ -/* Data format min and max values */ -#define DF_BITS(df) (1 << ((df) + 3)) - -/* Element-by-element access macros */ -#define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df)) - -#if !defined(CONFIG_USER_ONLY) -#define MEMOP_IDX(DF) \ - TCGMemOpIdx oi =3D make_memop_idx(MO_TE | DF | MO_UNALN, \ - cpu_mmu_index(env, false)); -#else -#define MEMOP_IDX(DF) -#endif - -void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - MEMOP_IDX(DF_BYTE) -#if !defined(CONFIG_USER_ONLY) -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->b[0] =3D helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GE= TPC()); - pwd->b[1] =3D helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GE= TPC()); - pwd->b[2] =3D helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GE= TPC()); - pwd->b[3] =3D helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GE= TPC()); - pwd->b[4] =3D helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GE= TPC()); - pwd->b[5] =3D helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GE= TPC()); - pwd->b[6] =3D helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GE= TPC()); - pwd->b[7] =3D helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GE= TPC()); - pwd->b[8] =3D helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GE= TPC()); - pwd->b[9] =3D helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GE= TPC()); - pwd->b[10] =3D helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GE= TPC()); - pwd->b[11] =3D helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GE= TPC()); - pwd->b[12] =3D helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GE= TPC()); - pwd->b[13] =3D helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GE= TPC()); - pwd->b[14] =3D helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GE= TPC()); - pwd->b[15] =3D helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GE= TPC()); -#else - pwd->b[0] =3D helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GE= TPC()); - pwd->b[1] =3D helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GE= TPC()); - pwd->b[2] =3D helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GE= TPC()); - pwd->b[3] =3D helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GE= TPC()); - pwd->b[4] =3D helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GE= TPC()); - pwd->b[5] =3D helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GE= TPC()); - pwd->b[6] =3D helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GE= TPC()); - pwd->b[7] =3D helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GE= TPC()); - pwd->b[8] =3D helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GE= TPC()); - pwd->b[9] =3D helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GE= TPC()); - pwd->b[10] =3D helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GE= TPC()); - pwd->b[11] =3D helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GE= TPC()); - pwd->b[12] =3D helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GE= TPC()); - pwd->b[13] =3D helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GE= TPC()); - pwd->b[14] =3D helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GE= TPC()); - pwd->b[15] =3D helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GE= TPC()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->b[0] =3D cpu_ldub_data(env, addr + (0 << DF_BYTE)); - pwd->b[1] =3D cpu_ldub_data(env, addr + (1 << DF_BYTE)); - pwd->b[2] =3D cpu_ldub_data(env, addr + (2 << DF_BYTE)); - pwd->b[3] =3D cpu_ldub_data(env, addr + (3 << DF_BYTE)); - pwd->b[4] =3D cpu_ldub_data(env, addr + (4 << DF_BYTE)); - pwd->b[5] =3D cpu_ldub_data(env, addr + (5 << DF_BYTE)); - pwd->b[6] =3D cpu_ldub_data(env, addr + (6 << DF_BYTE)); - pwd->b[7] =3D cpu_ldub_data(env, addr + (7 << DF_BYTE)); - pwd->b[8] =3D cpu_ldub_data(env, addr + (8 << DF_BYTE)); - pwd->b[9] =3D cpu_ldub_data(env, addr + (9 << DF_BYTE)); - pwd->b[10] =3D cpu_ldub_data(env, addr + (10 << DF_BYTE)); - pwd->b[11] =3D cpu_ldub_data(env, addr + (11 << DF_BYTE)); - pwd->b[12] =3D cpu_ldub_data(env, addr + (12 << DF_BYTE)); - pwd->b[13] =3D cpu_ldub_data(env, addr + (13 << DF_BYTE)); - pwd->b[14] =3D cpu_ldub_data(env, addr + (14 << DF_BYTE)); - pwd->b[15] =3D cpu_ldub_data(env, addr + (15 << DF_BYTE)); -#else - pwd->b[0] =3D cpu_ldub_data(env, addr + (7 << DF_BYTE)); - pwd->b[1] =3D cpu_ldub_data(env, addr + (6 << DF_BYTE)); - pwd->b[2] =3D cpu_ldub_data(env, addr + (5 << DF_BYTE)); - pwd->b[3] =3D cpu_ldub_data(env, addr + (4 << DF_BYTE)); - pwd->b[4] =3D cpu_ldub_data(env, addr + (3 << DF_BYTE)); - pwd->b[5] =3D cpu_ldub_data(env, addr + (2 << DF_BYTE)); - pwd->b[6] =3D cpu_ldub_data(env, addr + (1 << DF_BYTE)); - pwd->b[7] =3D cpu_ldub_data(env, addr + (0 << DF_BYTE)); - pwd->b[8] =3D cpu_ldub_data(env, addr + (15 << DF_BYTE)); - pwd->b[9] =3D cpu_ldub_data(env, addr + (14 << DF_BYTE)); - pwd->b[10] =3D cpu_ldub_data(env, addr + (13 << DF_BYTE)); - pwd->b[11] =3D cpu_ldub_data(env, addr + (12 << DF_BYTE)); - pwd->b[12] =3D cpu_ldub_data(env, addr + (11 << DF_BYTE)); - pwd->b[13] =3D cpu_ldub_data(env, addr + (10 << DF_BYTE)); - pwd->b[14] =3D cpu_ldub_data(env, addr + (9 << DF_BYTE)); - pwd->b[15] =3D cpu_ldub_data(env, addr + (8 << DF_BYTE)); -#endif -#endif -} - -void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - MEMOP_IDX(DF_HALF) -#if !defined(CONFIG_USER_ONLY) -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->h[0] =3D helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETP= C()); - pwd->h[1] =3D helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETP= C()); - pwd->h[2] =3D helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETP= C()); - pwd->h[3] =3D helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETP= C()); - pwd->h[4] =3D helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETP= C()); - pwd->h[5] =3D helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETP= C()); - pwd->h[6] =3D helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETP= C()); - pwd->h[7] =3D helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETP= C()); -#else - pwd->h[0] =3D helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETP= C()); - pwd->h[1] =3D helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETP= C()); - pwd->h[2] =3D helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETP= C()); - pwd->h[3] =3D helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETP= C()); - pwd->h[4] =3D helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETP= C()); - pwd->h[5] =3D helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETP= C()); - pwd->h[6] =3D helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETP= C()); - pwd->h[7] =3D helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETP= C()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->h[0] =3D cpu_lduw_data(env, addr + (0 << DF_HALF)); - pwd->h[1] =3D cpu_lduw_data(env, addr + (1 << DF_HALF)); - pwd->h[2] =3D cpu_lduw_data(env, addr + (2 << DF_HALF)); - pwd->h[3] =3D cpu_lduw_data(env, addr + (3 << DF_HALF)); - pwd->h[4] =3D cpu_lduw_data(env, addr + (4 << DF_HALF)); - pwd->h[5] =3D cpu_lduw_data(env, addr + (5 << DF_HALF)); - pwd->h[6] =3D cpu_lduw_data(env, addr + (6 << DF_HALF)); - pwd->h[7] =3D cpu_lduw_data(env, addr + (7 << DF_HALF)); -#else - pwd->h[0] =3D cpu_lduw_data(env, addr + (3 << DF_HALF)); - pwd->h[1] =3D cpu_lduw_data(env, addr + (2 << DF_HALF)); - pwd->h[2] =3D cpu_lduw_data(env, addr + (1 << DF_HALF)); - pwd->h[3] =3D cpu_lduw_data(env, addr + (0 << DF_HALF)); - pwd->h[4] =3D cpu_lduw_data(env, addr + (7 << DF_HALF)); - pwd->h[5] =3D cpu_lduw_data(env, addr + (6 << DF_HALF)); - pwd->h[6] =3D cpu_lduw_data(env, addr + (5 << DF_HALF)); - pwd->h[7] =3D cpu_lduw_data(env, addr + (4 << DF_HALF)); -#endif -#endif -} - -void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - MEMOP_IDX(DF_WORD) -#if !defined(CONFIG_USER_ONLY) -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->w[0] =3D helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETP= C()); - pwd->w[1] =3D helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETP= C()); - pwd->w[2] =3D helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETP= C()); - pwd->w[3] =3D helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETP= C()); -#else - pwd->w[0] =3D helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETP= C()); - pwd->w[1] =3D helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETP= C()); - pwd->w[2] =3D helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETP= C()); - pwd->w[3] =3D helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETP= C()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->w[0] =3D cpu_ldl_data(env, addr + (0 << DF_WORD)); - pwd->w[1] =3D cpu_ldl_data(env, addr + (1 << DF_WORD)); - pwd->w[2] =3D cpu_ldl_data(env, addr + (2 << DF_WORD)); - pwd->w[3] =3D cpu_ldl_data(env, addr + (3 << DF_WORD)); -#else - pwd->w[0] =3D cpu_ldl_data(env, addr + (1 << DF_WORD)); - pwd->w[1] =3D cpu_ldl_data(env, addr + (0 << DF_WORD)); - pwd->w[2] =3D cpu_ldl_data(env, addr + (3 << DF_WORD)); - pwd->w[3] =3D cpu_ldl_data(env, addr + (2 << DF_WORD)); -#endif -#endif -} - -void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - MEMOP_IDX(DF_DOUBLE) -#if !defined(CONFIG_USER_ONLY) - pwd->d[0] =3D helper_ret_ldq_mmu(env, addr + (0 << DF_DOUBLE), oi, GET= PC()); - pwd->d[1] =3D helper_ret_ldq_mmu(env, addr + (1 << DF_DOUBLE), oi, GET= PC()); -#else - pwd->d[0] =3D cpu_ldq_data(env, addr + (0 << DF_DOUBLE)); - pwd->d[1] =3D cpu_ldq_data(env, addr + (1 << DF_DOUBLE)); -#endif -} - -#define MSA_PAGESPAN(x) \ - ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN / 8 - 1) >=3D TARGET_PAGE_= SIZE) - -static inline void ensure_writable_pages(CPUMIPSState *env, - target_ulong addr, - int mmu_idx, - uintptr_t retaddr) -{ - /* FIXME: Probe the actual accesses (pass and use a size) */ - if (unlikely(MSA_PAGESPAN(addr))) { - /* first page */ - probe_write(env, addr, 0, mmu_idx, retaddr); - /* second page */ - addr =3D (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; - probe_write(env, addr, 0, mmu_idx, retaddr); - } -} - -void helper_msa_st_b(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - int mmu_idx =3D cpu_mmu_index(env, false); - - MEMOP_IDX(DF_BYTE) - ensure_writable_pages(env, addr, mmu_idx, GETPC()); -#if !defined(CONFIG_USER_ONLY) -#if !defined(HOST_WORDS_BIGENDIAN) - helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[0], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[1], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[2], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[3], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[4], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[5], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[6], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[7], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[8], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[9], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[10], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[11], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[12], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[13], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[14], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[15], oi, GETPC(= )); -#else - helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[0], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[1], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[2], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[3], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[4], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[5], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[6], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[7], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[8], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[9], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[10], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[11], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[12], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[13], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[14], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[15], oi, GETPC(= )); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[0]); - cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[1]); - cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[2]); - cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[3]); - cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[4]); - cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[5]); - cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[6]); - cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[7]); - cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[8]); - cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[9]); - cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[10]); - cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[11]); - cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[12]); - cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[13]); - cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[14]); - cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[15]); -#else - cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[0]); - cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[1]); - cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[2]); - cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[3]); - cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[4]); - cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[5]); - cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[6]); - cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[7]); - cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[8]); - cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[9]); - cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[10]); - cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[11]); - cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[12]); - cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[13]); - cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[14]); - cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[15]); -#endif -#endif -} - -void helper_msa_st_h(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - int mmu_idx =3D cpu_mmu_index(env, false); - - MEMOP_IDX(DF_HALF) - ensure_writable_pages(env, addr, mmu_idx, GETPC()); -#if !defined(CONFIG_USER_ONLY) -#if !defined(HOST_WORDS_BIGENDIAN) - helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[0], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[1], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[2], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[3], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[4], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[5], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[6], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[7], oi, GETPC()); -#else - helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[0], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[1], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[2], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[3], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[4], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[5], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[6], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[7], oi, GETPC()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[0]); - cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[1]); - cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[2]); - cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[3]); - cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[4]); - cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[5]); - cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[6]); - cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[7]); -#else - cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[0]); - cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[1]); - cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[2]); - cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[3]); - cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[4]); - cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[5]); - cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[6]); - cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[7]); -#endif -#endif -} - -void helper_msa_st_w(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - int mmu_idx =3D cpu_mmu_index(env, false); - - MEMOP_IDX(DF_WORD) - ensure_writable_pages(env, addr, mmu_idx, GETPC()); -#if !defined(CONFIG_USER_ONLY) -#if !defined(HOST_WORDS_BIGENDIAN) - helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[0], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[1], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[2], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[3], oi, GETPC()); -#else - helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[0], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[1], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[2], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[3], oi, GETPC()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[0]); - cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[1]); - cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[2]); - cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[3]); -#else - cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[0]); - cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[1]); - cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[2]); - cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[3]); -#endif -#endif -} - -void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - int mmu_idx =3D cpu_mmu_index(env, false); - - MEMOP_IDX(DF_DOUBLE) - ensure_writable_pages(env, addr, mmu_idx, GETPC()); -#if !defined(CONFIG_USER_ONLY) - helper_ret_stq_mmu(env, addr + (0 << DF_DOUBLE), pwd->d[0], oi, GETPC(= )); - helper_ret_stq_mmu(env, addr + (1 << DF_DOUBLE), pwd->d[1], oi, GETPC(= )); -#else - cpu_stq_data(env, addr + (0 << DF_DOUBLE), pwd->d[0]); - cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]); -#endif -} - void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op) { #ifndef CONFIG_USER_ONLY --=20 2.26.2 From nobody Tue May 21 12:06:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.43 as permitted sender) client-ip=209.85.208.43; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id z26sm19667194edl.71.2020.12.15.14.59.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 14:59:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4LRz+2kXa1G+kvmW7hNaI1eqoy4+tVkf4TaV4Xk9Z+E=; b=FZJG2lYs2/+YEr8Z4/KcMp/Xc1D33CIUwCLuMwj2StSsV0ZOfV0cB9+/lVQJfygQbW 6745W4niJeq5xMWAW/uM3EWk1QP6OXIWtj9sfHttRVH3VQICCocCV13NTy8C/jLVknws MbGy4whEEt18fNi9CV5qqs6FGpSSXO+a8TmCP0xZP6XyrbAnFaauxZBSP3o22luu2/9o RjLLJ2Fya/r5voHz0scbQjvdd3VbUjL1SdbmtZvIAlGC0Sie/X91QJcR2iiOSd+TP5Md plKTeCoR9TDK/EK/uk4FVuuvB5jEc0ubRo9Up5MsYFPgSkuV/lT94967mqmNXw+JFrUS sCpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=4LRz+2kXa1G+kvmW7hNaI1eqoy4+tVkf4TaV4Xk9Z+E=; b=Soe9qEGVo2d7waqWhMK1kbCBr8++NG8heAHmv1Dx37gy59QTw42D8IQWYlWxIgZf2c vxC0aYfMz7i6Q7lvsh9OmmDQOnv7UbqqbPfuio2c9AdGwdtwBIKoY42+OB6tU5BDxdYM SDp1GIqqfA8utFLAwP0musfDvlEnhZfYZlU2g5fVaS8i+6hyKGMbnksNjqNH4Lb2UoC+ 5FeMJ0zJKPHM1qyD2iQ1ds7FscizTjZClo6R5yGPbO0MP4/emyVtFeGJlEePOyiLSUwH mdCVvu4Tfr6EZaDW6D0SW3D8mPfnJeVN7l29wkFr03ljowdfCxOuiKXhNl2YtYNwUJ1K P/Mg== X-Gm-Message-State: AOAM531rpUrivHAN1DF/hHtGXddhEojaBYomC0tKYUNspzMjp3pI/do8 CIM3Ha5CnqSZIah8uIZrmaw= X-Google-Smtp-Source: ABdhPJza2mXk7TsG5FD/FjJyvFWXexw8qnwI4U9UqPKhFQTAPuRI9Zz/1Eb9A1pjrwDJO8SD6xzzkg== X-Received: by 2002:a50:d491:: with SMTP id s17mr13057861edi.169.1608073170436; Tue, 15 Dec 2020 14:59:30 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aleksandar Rikalo , Paolo Bonzini , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen Subject: [PATCH v2 16/24] target/mips: Extract MSA helper definitions Date: Tue, 15 Dec 2020 23:57:49 +0100 Message-Id: <20201215225757.764263-17-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215225757.764263-1-f4bug@amsat.org> References: <20201215225757.764263-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Keep all MSA-related code altogether. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20201120210844.2625602-4-f4bug@amsat.org> --- target/mips/helper.h | 436 +----------------------------- target/mips/mod-msa_helper.h.inc | 443 +++++++++++++++++++++++++++++++ 2 files changed, 445 insertions(+), 434 deletions(-) create mode 100644 target/mips/mod-msa_helper.h.inc diff --git a/target/mips/helper.h b/target/mips/helper.h index e97655dc0eb..80eb675fa64 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -781,438 +781,6 @@ DEF_HELPER_FLAGS_3(dmthlip, 0, void, tl, tl, env) DEF_HELPER_FLAGS_3(wrdsp, 0, void, tl, tl, env) DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env) =20 -/* MIPS SIMD Architecture */ - -DEF_HELPER_3(msa_nloc_b, void, env, i32, i32) -DEF_HELPER_3(msa_nloc_h, void, env, i32, i32) -DEF_HELPER_3(msa_nloc_w, void, env, i32, i32) -DEF_HELPER_3(msa_nloc_d, void, env, i32, i32) - -DEF_HELPER_3(msa_nlzc_b, void, env, i32, i32) -DEF_HELPER_3(msa_nlzc_h, void, env, i32, i32) -DEF_HELPER_3(msa_nlzc_w, void, env, i32, i32) -DEF_HELPER_3(msa_nlzc_d, void, env, i32, i32) - -DEF_HELPER_3(msa_pcnt_b, void, env, i32, i32) -DEF_HELPER_3(msa_pcnt_h, void, env, i32, i32) -DEF_HELPER_3(msa_pcnt_w, void, env, i32, i32) -DEF_HELPER_3(msa_pcnt_d, void, env, i32, i32) - -DEF_HELPER_4(msa_binsl_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_binsl_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_binsl_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_binsl_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_binsr_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_binsr_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_binsr_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_binsr_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_bmnz_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_bclr_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bclr_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bclr_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bclr_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_bneg_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bneg_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bneg_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bneg_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_bset_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bset_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bset_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bset_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_add_a_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_add_a_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_add_a_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_add_a_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_adds_a_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_adds_a_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_adds_a_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_adds_a_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_adds_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_adds_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_adds_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_adds_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_adds_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_adds_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_adds_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_adds_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_addv_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_addv_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_addv_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_addv_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_hadd_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_hadd_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_hadd_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_hadd_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_hadd_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_hadd_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_ave_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ave_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ave_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ave_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_ave_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ave_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ave_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ave_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_aver_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_aver_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_aver_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_aver_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_aver_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_aver_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_aver_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_aver_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_ceq_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ceq_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ceq_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ceq_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_cle_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_cle_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_cle_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_cle_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_cle_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_cle_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_cle_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_cle_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_clt_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_clt_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_clt_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_clt_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_clt_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_clt_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_clt_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_clt_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_div_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_div_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_div_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_div_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_div_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_div_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_div_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_div_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_max_a_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_a_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_a_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_a_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_s_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_u_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_a_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_a_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_a_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_a_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_s_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_mod_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_mod_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_mod_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_mod_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_mod_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_mod_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_mod_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_mod_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_maddv_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_maddv_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_maddv_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_maddv_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_msubv_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_msubv_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_msubv_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_msubv_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_mulv_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_mulv_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_mulv_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_mulv_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_asub_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_asub_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_asub_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_asub_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_asub_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_asub_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_asub_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_asub_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_hsub_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_hsub_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_hsub_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_hsub_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_hsub_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_hsub_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_subs_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subs_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subs_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subs_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_subs_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subs_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subs_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subs_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_subsus_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subsus_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subsus_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subsus_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_subsuu_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subsuu_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subsuu_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subsuu_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_subv_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subv_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subv_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subv_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_ilvev_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvev_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvev_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvev_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvod_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvod_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvod_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvod_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvl_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvl_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvl_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvl_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvr_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvr_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvr_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvr_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_and_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_xor_v, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_pckev_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_pckev_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_pckev_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_pckev_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_pckod_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_pckod_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_pckod_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_pckod_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_sll_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_sll_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_sll_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_sll_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_sra_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_sra_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_sra_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_sra_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_srar_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_srar_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_srar_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_srar_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_srl_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_srl_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_srl_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_srl_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_srlr_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_srlr_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_srlr_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_srlr_d, void, env, i32, i32, i32) - -DEF_HELPER_3(msa_move_v, void, env, i32, i32) - -DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_nori_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_xori_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bmnzi_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bmzi_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bseli_b, void, env, i32, i32, i32) -DEF_HELPER_5(msa_shf_df, void, env, i32, i32, i32, i32) - -DEF_HELPER_5(msa_addvi_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_subvi_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_maxi_s_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_maxi_u_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_mini_s_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_mini_u_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_ceqi_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_clti_s_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_clti_u_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_clei_s_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_clei_u_df, void, env, i32, i32, i32, s32) -DEF_HELPER_4(msa_ldi_df, void, env, i32, i32, s32) - -DEF_HELPER_5(msa_slli_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_srai_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_srli_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_bclri_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_bseti_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_bnegi_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_binsli_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_binsri_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_sat_s_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_sat_u_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_srari_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_srlri_df, void, env, i32, i32, i32, i32) - -DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32) - -DEF_HELPER_4(msa_dotp_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dotp_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dotp_s_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dotp_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dotp_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dotp_u_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpadd_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpadd_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpadd_s_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpadd_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpadd_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpadd_u_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpsub_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpsub_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpsub_s_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpsub_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpsub_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpsub_u_d, void, env, i32, i32, i32) -DEF_HELPER_5(msa_sld_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_splat_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32) - -DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32) - -DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32) -DEF_HELPER_3(msa_ctcmsa, void, env, tl, i32) -DEF_HELPER_2(msa_cfcmsa, tl, env, i32) - -DEF_HELPER_5(msa_fcaf_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fcun_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fceq_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fcueq_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fclt_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fcult_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fcle_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fcule_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsaf_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsun_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fseq_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsueq_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fslt_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsult_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsle_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsule_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fadd_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsub_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fmul_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fdiv_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fmadd_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fmsub_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fexp2_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fexdo_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_ftq_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fmin_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fmin_a_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fmax_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fmax_a_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fcor_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fcune_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fcne_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_mul_q_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_madd_q_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_msub_q_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsor_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsune_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsne_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_mulr_q_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_maddr_q_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_msubr_q_df, void, env, i32, i32, i32, i32) - -DEF_HELPER_4(msa_fill_df, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_copy_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_copy_s_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_copy_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_copy_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_copy_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_insert_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_insert_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_insert_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_insert_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ftrunc_u_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_fsqrt_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_frsqrt_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_frcp_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_frint_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_flog2_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_fexupl_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_fexupr_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ffql_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ffqr_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ftint_s_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ftint_u_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ffint_s_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ffint_u_df, void, env, i32, i32, i32) - -#define MSALDST_PROTO(type) \ -DEF_HELPER_3(msa_ld_ ## type, void, env, i32, tl) \ -DEF_HELPER_3(msa_st_ ## type, void, env, i32, tl) -MSALDST_PROTO(b) -MSALDST_PROTO(h) -MSALDST_PROTO(w) -MSALDST_PROTO(d) -#undef MSALDST_PROTO - DEF_HELPER_3(cache, void, env, tl, i32) + +#include "mod-msa_helper.h.inc" diff --git a/target/mips/mod-msa_helper.h.inc b/target/mips/mod-msa_helper.= h.inc new file mode 100644 index 00000000000..4963d1553a0 --- /dev/null +++ b/target/mips/mod-msa_helper.h.inc @@ -0,0 +1,443 @@ +/* + * MIPS SIMD Architecture Module (MSA) helpers for QEMU. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * Copyright (c) 2006 Marius Groeger (FPU operations) + * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) + * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) + * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support) + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +DEF_HELPER_3(msa_nloc_b, void, env, i32, i32) +DEF_HELPER_3(msa_nloc_h, void, env, i32, i32) +DEF_HELPER_3(msa_nloc_w, void, env, i32, i32) +DEF_HELPER_3(msa_nloc_d, void, env, i32, i32) + +DEF_HELPER_3(msa_nlzc_b, void, env, i32, i32) +DEF_HELPER_3(msa_nlzc_h, void, env, i32, i32) +DEF_HELPER_3(msa_nlzc_w, void, env, i32, i32) +DEF_HELPER_3(msa_nlzc_d, void, env, i32, i32) + +DEF_HELPER_3(msa_pcnt_b, void, env, i32, i32) +DEF_HELPER_3(msa_pcnt_h, void, env, i32, i32) +DEF_HELPER_3(msa_pcnt_w, void, env, i32, i32) +DEF_HELPER_3(msa_pcnt_d, void, env, i32, i32) + +DEF_HELPER_4(msa_binsl_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsl_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsl_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsl_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_binsr_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsr_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsr_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsr_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_bmnz_v, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_bclr_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bclr_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bclr_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bclr_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_bneg_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bneg_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bneg_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bneg_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_bset_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bset_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bset_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bset_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_add_a_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_add_a_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_add_a_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_add_a_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_adds_a_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_a_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_a_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_a_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_adds_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_adds_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_addv_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_addv_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_addv_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_addv_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_hadd_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hadd_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hadd_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_hadd_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hadd_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hadd_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_ave_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ave_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ave_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ave_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_ave_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ave_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ave_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ave_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_aver_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_aver_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_ceq_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ceq_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ceq_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ceq_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_cle_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_cle_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_cle_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_cle_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_cle_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_cle_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_cle_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_cle_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_clt_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_clt_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_div_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_div_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_div_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_div_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_div_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_div_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_div_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_div_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_max_a_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_a_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_a_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_a_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_s_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_u_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_a_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_a_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_a_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_a_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_s_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_mod_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_mod_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_maddv_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_maddv_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_maddv_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_maddv_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_msubv_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_msubv_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_msubv_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_msubv_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_mulv_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mulv_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mulv_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mulv_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_asub_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_asub_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_asub_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_asub_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_asub_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_asub_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_asub_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_asub_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_hsub_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hsub_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hsub_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_hsub_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hsub_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hsub_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_subs_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subs_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subs_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subs_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_subs_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subs_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subs_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subs_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_subsus_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subsus_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subsus_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subsus_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_subsuu_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subsuu_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subsuu_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subsuu_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_subv_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subv_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subv_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subv_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_ilvev_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvev_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvev_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvev_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvod_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvod_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvod_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvod_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvl_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvl_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvl_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvl_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvr_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvr_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvr_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvr_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_and_v, void, env, i32, i32, i32) +DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32) +DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32) +DEF_HELPER_4(msa_xor_v, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_pckev_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckev_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckev_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckev_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckod_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckod_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckod_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckod_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_sll_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_sll_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_sll_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_sll_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_sra_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_sra_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_sra_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_sra_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_srar_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srar_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srar_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srar_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_srl_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srl_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srl_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srl_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_srlr_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srlr_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srlr_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srlr_d, void, env, i32, i32, i32) + +DEF_HELPER_3(msa_move_v, void, env, i32, i32) + +DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_nori_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_xori_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bmnzi_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bmzi_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bseli_b, void, env, i32, i32, i32) +DEF_HELPER_5(msa_shf_df, void, env, i32, i32, i32, i32) + +DEF_HELPER_5(msa_addvi_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_subvi_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_maxi_s_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_maxi_u_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_mini_s_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_mini_u_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_ceqi_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_clti_s_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_clti_u_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_clei_s_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_clei_u_df, void, env, i32, i32, i32, s32) +DEF_HELPER_4(msa_ldi_df, void, env, i32, i32, s32) + +DEF_HELPER_5(msa_slli_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_srai_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_srli_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_bclri_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_bseti_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_bnegi_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_binsli_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_binsri_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_sat_s_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_sat_u_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_srari_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_srlri_df, void, env, i32, i32, i32, i32) + +DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32) + +DEF_HELPER_4(msa_dotp_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dotp_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dotp_s_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dotp_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dotp_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dotp_u_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpadd_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpadd_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpadd_s_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpadd_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpadd_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpadd_u_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpsub_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpsub_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpsub_s_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpsub_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpsub_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpsub_u_d, void, env, i32, i32, i32) +DEF_HELPER_5(msa_sld_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_splat_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32) + +DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32) + +DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32) +DEF_HELPER_3(msa_ctcmsa, void, env, tl, i32) +DEF_HELPER_2(msa_cfcmsa, tl, env, i32) + +DEF_HELPER_5(msa_fcaf_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fcun_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fceq_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fcueq_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fclt_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fcult_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fcle_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fcule_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsaf_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsun_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fseq_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsueq_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fslt_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsult_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsle_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsule_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fadd_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsub_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fmul_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fdiv_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fmadd_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fmsub_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fexp2_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fexdo_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_ftq_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fmin_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fmin_a_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fmax_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fmax_a_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fcor_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fcune_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fcne_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_mul_q_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_madd_q_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_msub_q_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsor_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsune_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsne_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_mulr_q_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_maddr_q_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_msubr_q_df, void, env, i32, i32, i32, i32) + +DEF_HELPER_4(msa_fill_df, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_s_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_insert_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_insert_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_insert_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_insert_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ftrunc_u_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_fsqrt_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_frsqrt_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_frcp_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_frint_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_flog2_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_fexupl_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_fexupr_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ffql_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ffqr_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ftint_s_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ftint_u_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ffint_s_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ffint_u_df, void, env, i32, i32, i32) + +#define MSALDST_PROTO(type) \ +DEF_HELPER_3(msa_ld_ ## type, void, env, i32, tl) \ +DEF_HELPER_3(msa_st_ ## type, void, env, i32, tl) +MSALDST_PROTO(b) +MSALDST_PROTO(h) +MSALDST_PROTO(w) +MSALDST_PROTO(d) +#undef MSALDST_PROTO --=20 2.26.2 From nobody Tue May 21 12:06:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.68 as permitted sender) client-ip=209.85.218.68; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-f68.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.68 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1608073177; cv=none; d=zohomail.com; s=zohoarc; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id s12sm19874597edu.28.2020.12.15.14.59.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 14:59:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=e0eQHnWDCrjwoYyD2yN62FwRsv+ZXJP/kwuNsrV3YJo=; b=F7NZPZDcUD7tQQF+lbqopiHIMiK0uojWbK5lxme/6/QwRVdisEFjXjK30abUTagZXW MAaXJ+db8S92MqrPy5QO3u0hGHbUFtwKXJ6BHpi1jNULSWpvzQ0IhCLIpD/iI5WxRxGM c+MlCtM3XmsTpdqXphE/Tj4bPAk90PXAZbGCnhtNHTMxiJ+k05G0I/kW49VCBccTMOLp 8/H0CXssXcWyuchAPMNZN0cdOujx5+0Kimv/iJ7Y8l78p60InnmSokUwR2aFXnOymFu9 Twpb+jiUkSxKSbi22WC5cz0yTqIF5KWGan9n9eFhwx6EM9mQPm4coPvCiskhjLIGrYOR gnOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=e0eQHnWDCrjwoYyD2yN62FwRsv+ZXJP/kwuNsrV3YJo=; b=Yt5SznnrM6ZJANCzHFYJGhsC1unpx+Iu7pmUxidkcLikGPE3EwfxHpYf1UTXx56MFg ATt9QrAPOd1OC9jxj+nwMbHSYiS5oGWFmYfBOXPMR8bCos6Qz+5EY5nvr+DU/ri+YiQa 5K99OLjPcYDsbIykldelzO2u2CZFKQlDX5wN71sPYml95aPRa7bCNjI09X0LMz2H0XC8 nKNZtgF9wFZJW+EbS2IETHE4lh91M5JmnjiwTJydd2CZNFBJ/XLotltA7vRxk9+hJDvj 55RcwLlibqE9oRFEZ6s2ldLYh6fDkwhnhE1GtePqiMiV1DP0cjww+awTlCxmeo7c9QRu QSBw== X-Gm-Message-State: AOAM531ncjWr+bCzlMIZ1qPd0R+t3hKCOx4FLXMljdehbWg/tUmSZEL0 jr9FlRExtM20megzwahufOo= X-Google-Smtp-Source: ABdhPJwPcNZNoZhcI0FGmQqk+wdxQUMkkCOBpxFi85HJfy6say6TGZ/z07taAzNCIIXoMUj0zpr8VA== X-Received: by 2002:a17:906:aeda:: with SMTP id me26mr3583681ejb.11.1608073175960; Tue, 15 Dec 2020 14:59:35 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aleksandar Rikalo , Paolo Bonzini , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen Subject: [PATCH v2 17/24] target/mips: Declare gen_msa/_branch() in 'translate.h' Date: Tue, 15 Dec 2020 23:57:50 +0100 Message-Id: <20201215225757.764263-18-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215225757.764263-1-f4bug@amsat.org> References: <20201215225757.764263-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Make gen_msa() and gen_msa_branch() public declarations so we can keep calling them once extracted from the big translate.c in the next commit. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/translate.h | 2 ++ target/mips/translate.c | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index f7e7037bab8..77dfec98792 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -163,5 +163,7 @@ extern TCGv bcond; =20 /* MSA */ void msa_translate_init(void); +void gen_msa(DisasContext *ctx); +void gen_msa_branch(DisasContext *ctx, uint32_t op1); =20 #endif diff --git a/target/mips/translate.c b/target/mips/translate.c index 9be946256b3..20174c4aa57 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28660,7 +28660,7 @@ static bool gen_msa_BxZ(DisasContext *ctx, int df, = int wt, int s16, bool if_not) return true; } =20 -static void gen_msa_branch(DisasContext *ctx, uint32_t op1) +void gen_msa_branch(DisasContext *ctx, uint32_t op1) { uint8_t df =3D (ctx->opcode >> 21) & 0x3; uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; @@ -30436,7 +30436,7 @@ static void gen_msa_vec(DisasContext *ctx) } } =20 -static void gen_msa(DisasContext *ctx) +void gen_msa(DisasContext *ctx) { uint32_t opcode =3D ctx->opcode; =20 --=20 2.26.2 From nobody Tue May 21 12:06:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.48 as permitted sender) client-ip=209.85.208.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1608073184; cv=none; d=zohomail.com; s=zohoarc; b=g0h3Zvp0nu/MJAZPgxPOy+NubRxXKWEyCoVdaRZvC4WG0/+5XfmkzYQ+V99HFneTCD+eMsv2+J5nhn4IzP5cQAzTmG1KMVDieRAjIUV3zjQ2GSb90cVEYL+sKgZplLX1XLsHZ7GfyV19aIgX5UGwdshd6/dFUwlxBlrrmLCYSN0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608073184; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pWR4Z77HkduBwXs1UraURNVcJWo7rkpcM8ya6uAvkhk=; b=BENbxfvvmfAz8vwv5rT+bvC01YZYpFi7y3h1Gp0bXTLAH9hUxihPvOAOm5Zj0C9MdATix/WwO/jVXnkbl96PfkNRrmEarmFPz1a1ak6t+cKRN9KKHjs8+0rC4CTpIimRna/R1haS+CfmgM0x4VPqMhJPSBFVNUrEv00YqJRdUqU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-ed1-f48.google.com (mail-ed1-f48.google.com [209.85.208.48]) by mx.zohomail.com with SMTPS id 1608073184774503.77869286935504; Tue, 15 Dec 2020 14:59:44 -0800 (PST) Received: by mail-ed1-f48.google.com with SMTP id c7so22809840edv.6 for ; Tue, 15 Dec 2020 14:59:43 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id c23sm19790858eds.88.2020.12.15.14.59.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 14:59:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pWR4Z77HkduBwXs1UraURNVcJWo7rkpcM8ya6uAvkhk=; b=kvTCAGaZDglE6oxNbFIfiMA7V6QQ3/fNr1miPuf3VFMJhGZEPCNfDO/ZAllcFGN3Go kefu5NJfqF3pdTne1THlrXL3Xf5EvRWGefkdmFcrBAOlNiUD8Cz3qnI5fa1Kyic9VLsM CZs3MNoAgLneLiY2pS0XFPW9vA3nsHdUpOVe7VxuNbm42pZ3VAWYeZklQToGoSiHxBpv sxZbhplwdfLzIKCZCoxYfsL6KRvE2XR2bzWgOXV523aFEfQcoG3ljwhg/9MnWIZ+3zQf 9qN3OZFMaytayyFJ7QOlkhPbs7FH7Hw/8vP4Zm6/0HyxGOIPn6DQwuQEjgHjgaFEyS/B GHzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=pWR4Z77HkduBwXs1UraURNVcJWo7rkpcM8ya6uAvkhk=; b=O/3z7ju/gQSoTg2daC8fDsiPUX5sNWC0aMT4yX/eIadNgGutBINPqph2YVdL4i0wF2 qD3U2OdLJPNg4R1NpkNexVelwBkR6ybNG+Z0C2qe/021bO62R7QkJm4dtYfPmcLLqj1K grALlY3jBAYnbkQeFeA8ZmFTAof5qNj0NxkcU+hCvukCjxDvXTa5jjaGFsPDPZpDpVn7 d0BYSD0XaUDcRE5UoXUVVPe6W5Mr3A+MTB6t7rWTmKaZX4mw3IJ14BYYluDNWu1ZHqsh aikemqyVH0fCPjmiQU7n3KcsabLkQ0y3TF/q79U0gRVFt+GNeVyMgEItiL6Mz2fV6iAz ymHA== X-Gm-Message-State: AOAM533vkWtPlr2zC9i7SmyNqf9Q/bztXRjFfTvwUfmyI3AzwuvTPUg3 QdOjZWiPXhUyoIGPxjIuIK8= X-Google-Smtp-Source: ABdhPJwRk0SGj0PS/YsHX2dsb6vqTiMuKoqvdJUGiTWEH2OjiFDNyj2I3FNAO52C9WyfhT2u8HldBQ== X-Received: by 2002:a05:6402:1816:: with SMTP id g22mr4343227edy.80.1608073181944; Tue, 15 Dec 2020 14:59:41 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aleksandar Rikalo , Paolo Bonzini , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen Subject: [PATCH v2 18/24] target/mips: Extract MSA translation routines Date: Tue, 15 Dec 2020 23:57:51 +0100 Message-Id: <20201215225757.764263-19-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215225757.764263-1-f4bug@amsat.org> References: <20201215225757.764263-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Extract 2200 lines from the huge translate.c to a new file, 'mod-msa_translate.c'. As there are too many inter-dependencies we don't compile it as another object yet, but keep including it in the big translate.o. We gain in code maintainability. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201120210844.2625602-5-f4bug@amsat.org> --- target/mips/mod-msa_translate.c | 2266 +++++++++++++++++++++++++++++++ target/mips/translate.c | 2248 ------------------------------ target/mips/meson.build | 1 + 3 files changed, 2267 insertions(+), 2248 deletions(-) create mode 100644 target/mips/mod-msa_translate.c diff --git a/target/mips/mod-msa_translate.c b/target/mips/mod-msa_translat= e.c new file mode 100644 index 00000000000..63feedcb7ca --- /dev/null +++ b/target/mips/mod-msa_translate.c @@ -0,0 +1,2266 @@ +/* + * MIPS SIMD Architecture Module (MSA) translation routines + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * Copyright (c) 2006 Marius Groeger (FPU operations) + * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) + * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) + * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support) + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#include "qemu/osdep.h" +#include "tcg/tcg-op.h" +#include "exec/helper-gen.h" +#include "translate.h" +#include "fpu_translate.h" +#include "fpu_helper.h" +#include "internal.h" + +#define OPC_MSA (0x1E << 26) + +#define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) +enum { + OPC_MSA_I8_00 =3D 0x00 | OPC_MSA, + OPC_MSA_I8_01 =3D 0x01 | OPC_MSA, + OPC_MSA_I8_02 =3D 0x02 | OPC_MSA, + OPC_MSA_I5_06 =3D 0x06 | OPC_MSA, + OPC_MSA_I5_07 =3D 0x07 | OPC_MSA, + OPC_MSA_BIT_09 =3D 0x09 | OPC_MSA, + OPC_MSA_BIT_0A =3D 0x0A | OPC_MSA, + OPC_MSA_3R_0D =3D 0x0D | OPC_MSA, + OPC_MSA_3R_0E =3D 0x0E | OPC_MSA, + OPC_MSA_3R_0F =3D 0x0F | OPC_MSA, + OPC_MSA_3R_10 =3D 0x10 | OPC_MSA, + OPC_MSA_3R_11 =3D 0x11 | OPC_MSA, + OPC_MSA_3R_12 =3D 0x12 | OPC_MSA, + OPC_MSA_3R_13 =3D 0x13 | OPC_MSA, + OPC_MSA_3R_14 =3D 0x14 | OPC_MSA, + OPC_MSA_3R_15 =3D 0x15 | OPC_MSA, + OPC_MSA_ELM =3D 0x19 | OPC_MSA, + OPC_MSA_3RF_1A =3D 0x1A | OPC_MSA, + OPC_MSA_3RF_1B =3D 0x1B | OPC_MSA, + OPC_MSA_3RF_1C =3D 0x1C | OPC_MSA, + OPC_MSA_VEC =3D 0x1E | OPC_MSA, + + /* MI10 instruction */ + OPC_LD_B =3D (0x20) | OPC_MSA, + OPC_LD_H =3D (0x21) | OPC_MSA, + OPC_LD_W =3D (0x22) | OPC_MSA, + OPC_LD_D =3D (0x23) | OPC_MSA, + OPC_ST_B =3D (0x24) | OPC_MSA, + OPC_ST_H =3D (0x25) | OPC_MSA, + OPC_ST_W =3D (0x26) | OPC_MSA, + OPC_ST_D =3D (0x27) | OPC_MSA, +}; + +enum { + /* I5 instruction df(bits 22..21) =3D _b, _h, _w, _d */ + OPC_ADDVI_df =3D (0x0 << 23) | OPC_MSA_I5_06, + OPC_CEQI_df =3D (0x0 << 23) | OPC_MSA_I5_07, + OPC_SUBVI_df =3D (0x1 << 23) | OPC_MSA_I5_06, + OPC_MAXI_S_df =3D (0x2 << 23) | OPC_MSA_I5_06, + OPC_CLTI_S_df =3D (0x2 << 23) | OPC_MSA_I5_07, + OPC_MAXI_U_df =3D (0x3 << 23) | OPC_MSA_I5_06, + OPC_CLTI_U_df =3D (0x3 << 23) | OPC_MSA_I5_07, + OPC_MINI_S_df =3D (0x4 << 23) | OPC_MSA_I5_06, + OPC_CLEI_S_df =3D (0x4 << 23) | OPC_MSA_I5_07, + OPC_MINI_U_df =3D (0x5 << 23) | OPC_MSA_I5_06, + OPC_CLEI_U_df =3D (0x5 << 23) | OPC_MSA_I5_07, + OPC_LDI_df =3D (0x6 << 23) | OPC_MSA_I5_07, + + /* I8 instruction */ + OPC_ANDI_B =3D (0x0 << 24) | OPC_MSA_I8_00, + OPC_BMNZI_B =3D (0x0 << 24) | OPC_MSA_I8_01, + OPC_SHF_B =3D (0x0 << 24) | OPC_MSA_I8_02, + OPC_ORI_B =3D (0x1 << 24) | OPC_MSA_I8_00, + OPC_BMZI_B =3D (0x1 << 24) | OPC_MSA_I8_01, + OPC_SHF_H =3D (0x1 << 24) | OPC_MSA_I8_02, + OPC_NORI_B =3D (0x2 << 24) | OPC_MSA_I8_00, + OPC_BSELI_B =3D (0x2 << 24) | OPC_MSA_I8_01, + OPC_SHF_W =3D (0x2 << 24) | OPC_MSA_I8_02, + OPC_XORI_B =3D (0x3 << 24) | OPC_MSA_I8_00, + + /* VEC/2R/2RF instruction */ + OPC_AND_V =3D (0x00 << 21) | OPC_MSA_VEC, + OPC_OR_V =3D (0x01 << 21) | OPC_MSA_VEC, + OPC_NOR_V =3D (0x02 << 21) | OPC_MSA_VEC, + OPC_XOR_V =3D (0x03 << 21) | OPC_MSA_VEC, + OPC_BMNZ_V =3D (0x04 << 21) | OPC_MSA_VEC, + OPC_BMZ_V =3D (0x05 << 21) | OPC_MSA_VEC, + OPC_BSEL_V =3D (0x06 << 21) | OPC_MSA_VEC, + + OPC_MSA_2R =3D (0x18 << 21) | OPC_MSA_VEC, + OPC_MSA_2RF =3D (0x19 << 21) | OPC_MSA_VEC, + + /* 2R instruction df(bits 17..16) =3D _b, _h, _w, _d */ + OPC_FILL_df =3D (0x00 << 18) | OPC_MSA_2R, + OPC_PCNT_df =3D (0x01 << 18) | OPC_MSA_2R, + OPC_NLOC_df =3D (0x02 << 18) | OPC_MSA_2R, + OPC_NLZC_df =3D (0x03 << 18) | OPC_MSA_2R, + + /* 2RF instruction df(bit 16) =3D _w, _d */ + OPC_FCLASS_df =3D (0x00 << 17) | OPC_MSA_2RF, + OPC_FTRUNC_S_df =3D (0x01 << 17) | OPC_MSA_2RF, + OPC_FTRUNC_U_df =3D (0x02 << 17) | OPC_MSA_2RF, + OPC_FSQRT_df =3D (0x03 << 17) | OPC_MSA_2RF, + OPC_FRSQRT_df =3D (0x04 << 17) | OPC_MSA_2RF, + OPC_FRCP_df =3D (0x05 << 17) | OPC_MSA_2RF, + OPC_FRINT_df =3D (0x06 << 17) | OPC_MSA_2RF, + OPC_FLOG2_df =3D (0x07 << 17) | OPC_MSA_2RF, + OPC_FEXUPL_df =3D (0x08 << 17) | OPC_MSA_2RF, + OPC_FEXUPR_df =3D (0x09 << 17) | OPC_MSA_2RF, + OPC_FFQL_df =3D (0x0A << 17) | OPC_MSA_2RF, + OPC_FFQR_df =3D (0x0B << 17) | OPC_MSA_2RF, + OPC_FTINT_S_df =3D (0x0C << 17) | OPC_MSA_2RF, + OPC_FTINT_U_df =3D (0x0D << 17) | OPC_MSA_2RF, + OPC_FFINT_S_df =3D (0x0E << 17) | OPC_MSA_2RF, + OPC_FFINT_U_df =3D (0x0F << 17) | OPC_MSA_2RF, + + /* 3R instruction df(bits 22..21) =3D _b, _h, _w, d */ + OPC_SLL_df =3D (0x0 << 23) | OPC_MSA_3R_0D, + OPC_ADDV_df =3D (0x0 << 23) | OPC_MSA_3R_0E, + OPC_CEQ_df =3D (0x0 << 23) | OPC_MSA_3R_0F, + OPC_ADD_A_df =3D (0x0 << 23) | OPC_MSA_3R_10, + OPC_SUBS_S_df =3D (0x0 << 23) | OPC_MSA_3R_11, + OPC_MULV_df =3D (0x0 << 23) | OPC_MSA_3R_12, + OPC_DOTP_S_df =3D (0x0 << 23) | OPC_MSA_3R_13, + OPC_SLD_df =3D (0x0 << 23) | OPC_MSA_3R_14, + OPC_VSHF_df =3D (0x0 << 23) | OPC_MSA_3R_15, + OPC_SRA_df =3D (0x1 << 23) | OPC_MSA_3R_0D, + OPC_SUBV_df =3D (0x1 << 23) | OPC_MSA_3R_0E, + OPC_ADDS_A_df =3D (0x1 << 23) | OPC_MSA_3R_10, + OPC_SUBS_U_df =3D (0x1 << 23) | OPC_MSA_3R_11, + OPC_MADDV_df =3D (0x1 << 23) | OPC_MSA_3R_12, + OPC_DOTP_U_df =3D (0x1 << 23) | OPC_MSA_3R_13, + OPC_SPLAT_df =3D (0x1 << 23) | OPC_MSA_3R_14, + OPC_SRAR_df =3D (0x1 << 23) | OPC_MSA_3R_15, + OPC_SRL_df =3D (0x2 << 23) | OPC_MSA_3R_0D, + OPC_MAX_S_df =3D (0x2 << 23) | OPC_MSA_3R_0E, + OPC_CLT_S_df =3D (0x2 << 23) | OPC_MSA_3R_0F, + OPC_ADDS_S_df =3D (0x2 << 23) | OPC_MSA_3R_10, + OPC_SUBSUS_U_df =3D (0x2 << 23) | OPC_MSA_3R_11, + OPC_MSUBV_df =3D (0x2 << 23) | OPC_MSA_3R_12, + OPC_DPADD_S_df =3D (0x2 << 23) | OPC_MSA_3R_13, + OPC_PCKEV_df =3D (0x2 << 23) | OPC_MSA_3R_14, + OPC_SRLR_df =3D (0x2 << 23) | OPC_MSA_3R_15, + OPC_BCLR_df =3D (0x3 << 23) | OPC_MSA_3R_0D, + OPC_MAX_U_df =3D (0x3 << 23) | OPC_MSA_3R_0E, + OPC_CLT_U_df =3D (0x3 << 23) | OPC_MSA_3R_0F, + OPC_ADDS_U_df =3D (0x3 << 23) | OPC_MSA_3R_10, + OPC_SUBSUU_S_df =3D (0x3 << 23) | OPC_MSA_3R_11, + OPC_DPADD_U_df =3D (0x3 << 23) | OPC_MSA_3R_13, + OPC_PCKOD_df =3D (0x3 << 23) | OPC_MSA_3R_14, + OPC_BSET_df =3D (0x4 << 23) | OPC_MSA_3R_0D, + OPC_MIN_S_df =3D (0x4 << 23) | OPC_MSA_3R_0E, + OPC_CLE_S_df =3D (0x4 << 23) | OPC_MSA_3R_0F, + OPC_AVE_S_df =3D (0x4 << 23) | OPC_MSA_3R_10, + OPC_ASUB_S_df =3D (0x4 << 23) | OPC_MSA_3R_11, + OPC_DIV_S_df =3D (0x4 << 23) | OPC_MSA_3R_12, + OPC_DPSUB_S_df =3D (0x4 << 23) | OPC_MSA_3R_13, + OPC_ILVL_df =3D (0x4 << 23) | OPC_MSA_3R_14, + OPC_HADD_S_df =3D (0x4 << 23) | OPC_MSA_3R_15, + OPC_BNEG_df =3D (0x5 << 23) | OPC_MSA_3R_0D, + OPC_MIN_U_df =3D (0x5 << 23) | OPC_MSA_3R_0E, + OPC_CLE_U_df =3D (0x5 << 23) | OPC_MSA_3R_0F, + OPC_AVE_U_df =3D (0x5 << 23) | OPC_MSA_3R_10, + OPC_ASUB_U_df =3D (0x5 << 23) | OPC_MSA_3R_11, + OPC_DIV_U_df =3D (0x5 << 23) | OPC_MSA_3R_12, + OPC_DPSUB_U_df =3D (0x5 << 23) | OPC_MSA_3R_13, + OPC_ILVR_df =3D (0x5 << 23) | OPC_MSA_3R_14, + OPC_HADD_U_df =3D (0x5 << 23) | OPC_MSA_3R_15, + OPC_BINSL_df =3D (0x6 << 23) | OPC_MSA_3R_0D, + OPC_MAX_A_df =3D (0x6 << 23) | OPC_MSA_3R_0E, + OPC_AVER_S_df =3D (0x6 << 23) | OPC_MSA_3R_10, + OPC_MOD_S_df =3D (0x6 << 23) | OPC_MSA_3R_12, + OPC_ILVEV_df =3D (0x6 << 23) | OPC_MSA_3R_14, + OPC_HSUB_S_df =3D (0x6 << 23) | OPC_MSA_3R_15, + OPC_BINSR_df =3D (0x7 << 23) | OPC_MSA_3R_0D, + OPC_MIN_A_df =3D (0x7 << 23) | OPC_MSA_3R_0E, + OPC_AVER_U_df =3D (0x7 << 23) | OPC_MSA_3R_10, + OPC_MOD_U_df =3D (0x7 << 23) | OPC_MSA_3R_12, + OPC_ILVOD_df =3D (0x7 << 23) | OPC_MSA_3R_14, + OPC_HSUB_U_df =3D (0x7 << 23) | OPC_MSA_3R_15, + + /* ELM instructions df(bits 21..16) =3D _b, _h, _w, _d */ + OPC_SLDI_df =3D (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM, + OPC_CTCMSA =3D (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM, + OPC_SPLATI_df =3D (0x1 << 22) | (0x00 << 16) | OPC_MSA_ELM, + OPC_CFCMSA =3D (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM, + OPC_COPY_S_df =3D (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM, + OPC_MOVE_V =3D (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM, + OPC_COPY_U_df =3D (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM, + OPC_INSERT_df =3D (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM, + OPC_INSVE_df =3D (0x5 << 22) | (0x00 << 16) | OPC_MSA_ELM, + + /* 3RF instruction _df(bit 21) =3D _w, _d */ + OPC_FCAF_df =3D (0x0 << 22) | OPC_MSA_3RF_1A, + OPC_FADD_df =3D (0x0 << 22) | OPC_MSA_3RF_1B, + OPC_FCUN_df =3D (0x1 << 22) | OPC_MSA_3RF_1A, + OPC_FSUB_df =3D (0x1 << 22) | OPC_MSA_3RF_1B, + OPC_FCOR_df =3D (0x1 << 22) | OPC_MSA_3RF_1C, + OPC_FCEQ_df =3D (0x2 << 22) | OPC_MSA_3RF_1A, + OPC_FMUL_df =3D (0x2 << 22) | OPC_MSA_3RF_1B, + OPC_FCUNE_df =3D (0x2 << 22) | OPC_MSA_3RF_1C, + OPC_FCUEQ_df =3D (0x3 << 22) | OPC_MSA_3RF_1A, + OPC_FDIV_df =3D (0x3 << 22) | OPC_MSA_3RF_1B, + OPC_FCNE_df =3D (0x3 << 22) | OPC_MSA_3RF_1C, + OPC_FCLT_df =3D (0x4 << 22) | OPC_MSA_3RF_1A, + OPC_FMADD_df =3D (0x4 << 22) | OPC_MSA_3RF_1B, + OPC_MUL_Q_df =3D (0x4 << 22) | OPC_MSA_3RF_1C, + OPC_FCULT_df =3D (0x5 << 22) | OPC_MSA_3RF_1A, + OPC_FMSUB_df =3D (0x5 << 22) | OPC_MSA_3RF_1B, + OPC_MADD_Q_df =3D (0x5 << 22) | OPC_MSA_3RF_1C, + OPC_FCLE_df =3D (0x6 << 22) | OPC_MSA_3RF_1A, + OPC_MSUB_Q_df =3D (0x6 << 22) | OPC_MSA_3RF_1C, + OPC_FCULE_df =3D (0x7 << 22) | OPC_MSA_3RF_1A, + OPC_FEXP2_df =3D (0x7 << 22) | OPC_MSA_3RF_1B, + OPC_FSAF_df =3D (0x8 << 22) | OPC_MSA_3RF_1A, + OPC_FEXDO_df =3D (0x8 << 22) | OPC_MSA_3RF_1B, + OPC_FSUN_df =3D (0x9 << 22) | OPC_MSA_3RF_1A, + OPC_FSOR_df =3D (0x9 << 22) | OPC_MSA_3RF_1C, + OPC_FSEQ_df =3D (0xA << 22) | OPC_MSA_3RF_1A, + OPC_FTQ_df =3D (0xA << 22) | OPC_MSA_3RF_1B, + OPC_FSUNE_df =3D (0xA << 22) | OPC_MSA_3RF_1C, + OPC_FSUEQ_df =3D (0xB << 22) | OPC_MSA_3RF_1A, + OPC_FSNE_df =3D (0xB << 22) | OPC_MSA_3RF_1C, + OPC_FSLT_df =3D (0xC << 22) | OPC_MSA_3RF_1A, + OPC_FMIN_df =3D (0xC << 22) | OPC_MSA_3RF_1B, + OPC_MULR_Q_df =3D (0xC << 22) | OPC_MSA_3RF_1C, + OPC_FSULT_df =3D (0xD << 22) | OPC_MSA_3RF_1A, + OPC_FMIN_A_df =3D (0xD << 22) | OPC_MSA_3RF_1B, + OPC_MADDR_Q_df =3D (0xD << 22) | OPC_MSA_3RF_1C, + OPC_FSLE_df =3D (0xE << 22) | OPC_MSA_3RF_1A, + OPC_FMAX_df =3D (0xE << 22) | OPC_MSA_3RF_1B, + OPC_MSUBR_Q_df =3D (0xE << 22) | OPC_MSA_3RF_1C, + OPC_FSULE_df =3D (0xF << 22) | OPC_MSA_3RF_1A, + OPC_FMAX_A_df =3D (0xF << 22) | OPC_MSA_3RF_1B, + + /* BIT instruction df(bits 22..16) =3D _B _H _W _D */ + OPC_SLLI_df =3D (0x0 << 23) | OPC_MSA_BIT_09, + OPC_SAT_S_df =3D (0x0 << 23) | OPC_MSA_BIT_0A, + OPC_SRAI_df =3D (0x1 << 23) | OPC_MSA_BIT_09, + OPC_SAT_U_df =3D (0x1 << 23) | OPC_MSA_BIT_0A, + OPC_SRLI_df =3D (0x2 << 23) | OPC_MSA_BIT_09, + OPC_SRARI_df =3D (0x2 << 23) | OPC_MSA_BIT_0A, + OPC_BCLRI_df =3D (0x3 << 23) | OPC_MSA_BIT_09, + OPC_SRLRI_df =3D (0x3 << 23) | OPC_MSA_BIT_0A, + OPC_BSETI_df =3D (0x4 << 23) | OPC_MSA_BIT_09, + OPC_BNEGI_df =3D (0x5 << 23) | OPC_MSA_BIT_09, + OPC_BINSLI_df =3D (0x6 << 23) | OPC_MSA_BIT_09, + OPC_BINSRI_df =3D (0x7 << 23) | OPC_MSA_BIT_09, +}; + +static const char * const msaregnames[] =3D { + "w0.d0", "w0.d1", "w1.d0", "w1.d1", + "w2.d0", "w2.d1", "w3.d0", "w3.d1", + "w4.d0", "w4.d1", "w5.d0", "w5.d1", + "w6.d0", "w6.d1", "w7.d0", "w7.d1", + "w8.d0", "w8.d1", "w9.d0", "w9.d1", + "w10.d0", "w10.d1", "w11.d0", "w11.d1", + "w12.d0", "w12.d1", "w13.d0", "w13.d1", + "w14.d0", "w14.d1", "w15.d0", "w15.d1", + "w16.d0", "w16.d1", "w17.d0", "w17.d1", + "w18.d0", "w18.d1", "w19.d0", "w19.d1", + "w20.d0", "w20.d1", "w21.d0", "w21.d1", + "w22.d0", "w22.d1", "w23.d0", "w23.d1", + "w24.d0", "w24.d1", "w25.d0", "w25.d1", + "w26.d0", "w26.d1", "w27.d0", "w27.d1", + "w28.d0", "w28.d1", "w29.d0", "w29.d1", + "w30.d0", "w30.d1", "w31.d0", "w31.d1", +}; + +static TCGv_i64 msa_wr_d[64]; + +void msa_translate_init(void) +{ + int i; + + for (i =3D 0; i < 32; i++) { + int off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); + + /* + * The MSA vector registers are mapped on the + * scalar floating-point unit (FPU) registers. + */ + msa_wr_d[i * 2] =3D fpu_f64[i]; + off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); + msa_wr_d[i * 2 + 1] =3D + tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1= ]); + } +} + +static inline int check_msa_access(DisasContext *ctx) +{ + if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) && + !(ctx->hflags & MIPS_HFLAG_F64))) { + gen_reserved_instruction(ctx); + return 0; + } + + if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) { + generate_exception_end(ctx, EXCP_MSADIS); + return 0; + } + return 1; +} + +static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt) +{ + /* generates tcg ops to check if any element is 0 */ + /* Note this function only works with MSA_WRLEN =3D 128 */ + uint64_t eval_zero_or_big =3D 0; + uint64_t eval_big =3D 0; + TCGv_i64 t0 =3D tcg_temp_new_i64(); + TCGv_i64 t1 =3D tcg_temp_new_i64(); + switch (df) { + case DF_BYTE: + eval_zero_or_big =3D 0x0101010101010101ULL; + eval_big =3D 0x8080808080808080ULL; + break; + case DF_HALF: + eval_zero_or_big =3D 0x0001000100010001ULL; + eval_big =3D 0x8000800080008000ULL; + break; + case DF_WORD: + eval_zero_or_big =3D 0x0000000100000001ULL; + eval_big =3D 0x8000000080000000ULL; + break; + case DF_DOUBLE: + eval_zero_or_big =3D 0x0000000000000001ULL; + eval_big =3D 0x8000000000000000ULL; + break; + } + tcg_gen_subi_i64(t0, msa_wr_d[wt << 1], eval_zero_or_big); + tcg_gen_andc_i64(t0, t0, msa_wr_d[wt << 1]); + tcg_gen_andi_i64(t0, t0, eval_big); + tcg_gen_subi_i64(t1, msa_wr_d[(wt << 1) + 1], eval_zero_or_big); + tcg_gen_andc_i64(t1, t1, msa_wr_d[(wt << 1) + 1]); + tcg_gen_andi_i64(t1, t1, eval_big); + tcg_gen_or_i64(t0, t0, t1); + /* if all bits are zero then all elements are not zero */ + /* if some bit is non-zero then some element is zero */ + tcg_gen_setcondi_i64(TCG_COND_NE, t0, t0, 0); + tcg_gen_trunc_i64_tl(tresult, t0); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); +} + +static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond) +{ + TCGv_i64 t0; + + check_msa_access(ctx); + + if (ctx->hflags & MIPS_HFLAG_BMASK) { + gen_reserved_instruction(ctx); + return true; + } + t0 =3D tcg_temp_new_i64(); + tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]); + tcg_gen_setcondi_i64(cond, t0, t0, 0); + tcg_gen_trunc_i64_tl(bcond, t0); + tcg_temp_free_i64(t0); + + ctx->btarget =3D ctx->base.pc_next + (s16 << 2) + 4; + + ctx->hflags |=3D MIPS_HFLAG_BC; + ctx->hflags |=3D MIPS_HFLAG_BDS32; + + return true; +} + +static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool i= f_not) +{ + check_msa_access(ctx); + + if (ctx->hflags & MIPS_HFLAG_BMASK) { + gen_reserved_instruction(ctx); + return true; + } + + gen_check_zero_element(bcond, df, wt); + if (if_not) { + tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0); + } + + ctx->btarget =3D ctx->base.pc_next + (s16 << 2) + 4; + ctx->hflags |=3D MIPS_HFLAG_BC; + ctx->hflags |=3D MIPS_HFLAG_BDS32; + + return true; +} + +void gen_msa_branch(DisasContext *ctx, uint32_t op1) +{ + uint8_t df =3D (ctx->opcode >> 21) & 0x3; + uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; + int64_t s16 =3D (int16_t)ctx->opcode; + + switch (op1) { + case OPC_BZ_V: + case OPC_BNZ_V: + gen_msa_BxZ_V(ctx, wt, s16, (op1 =3D=3D OPC_BZ_V) ? + TCG_COND_EQ : TCG_COND_NE); + break; + case OPC_BZ_B: + case OPC_BZ_H: + case OPC_BZ_W: + case OPC_BZ_D: + gen_msa_BxZ(ctx, df, wt, s16, false); + break; + case OPC_BNZ_B: + case OPC_BNZ_H: + case OPC_BNZ_W: + case OPC_BNZ_D: + gen_msa_BxZ(ctx, df, wt, s16, true); + break; + } +} + +static void gen_msa_i8(DisasContext *ctx) +{ +#define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24))) + uint8_t i8 =3D (ctx->opcode >> 16) & 0xff; + uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + + TCGv_i32 twd =3D tcg_const_i32(wd); + TCGv_i32 tws =3D tcg_const_i32(ws); + TCGv_i32 ti8 =3D tcg_const_i32(i8); + + switch (MASK_MSA_I8(ctx->opcode)) { + case OPC_ANDI_B: + gen_helper_msa_andi_b(cpu_env, twd, tws, ti8); + break; + case OPC_ORI_B: + gen_helper_msa_ori_b(cpu_env, twd, tws, ti8); + break; + case OPC_NORI_B: + gen_helper_msa_nori_b(cpu_env, twd, tws, ti8); + break; + case OPC_XORI_B: + gen_helper_msa_xori_b(cpu_env, twd, tws, ti8); + break; + case OPC_BMNZI_B: + gen_helper_msa_bmnzi_b(cpu_env, twd, tws, ti8); + break; + case OPC_BMZI_B: + gen_helper_msa_bmzi_b(cpu_env, twd, tws, ti8); + break; + case OPC_BSELI_B: + gen_helper_msa_bseli_b(cpu_env, twd, tws, ti8); + break; + case OPC_SHF_B: + case OPC_SHF_H: + case OPC_SHF_W: + { + uint8_t df =3D (ctx->opcode >> 24) & 0x3; + if (df =3D=3D DF_DOUBLE) { + gen_reserved_instruction(ctx); + } else { + TCGv_i32 tdf =3D tcg_const_i32(df); + gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, ti8); + tcg_temp_free_i32(tdf); + } + } + break; + default: + MIPS_INVAL("MSA instruction"); + gen_reserved_instruction(ctx); + break; + } + + tcg_temp_free_i32(twd); + tcg_temp_free_i32(tws); + tcg_temp_free_i32(ti8); +} + +static void gen_msa_i5(DisasContext *ctx) +{ +#define MASK_MSA_I5(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) + uint8_t df =3D (ctx->opcode >> 21) & 0x3; + int8_t s5 =3D (int8_t) sextract32(ctx->opcode, 16, 5); + uint8_t u5 =3D (ctx->opcode >> 16) & 0x1f; + uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + + TCGv_i32 tdf =3D tcg_const_i32(df); + TCGv_i32 twd =3D tcg_const_i32(wd); + TCGv_i32 tws =3D tcg_const_i32(ws); + TCGv_i32 timm =3D tcg_temp_new_i32(); + tcg_gen_movi_i32(timm, u5); + + switch (MASK_MSA_I5(ctx->opcode)) { + case OPC_ADDVI_df: + gen_helper_msa_addvi_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_SUBVI_df: + gen_helper_msa_subvi_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_MAXI_S_df: + tcg_gen_movi_i32(timm, s5); + gen_helper_msa_maxi_s_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_MAXI_U_df: + gen_helper_msa_maxi_u_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_MINI_S_df: + tcg_gen_movi_i32(timm, s5); + gen_helper_msa_mini_s_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_MINI_U_df: + gen_helper_msa_mini_u_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_CEQI_df: + tcg_gen_movi_i32(timm, s5); + gen_helper_msa_ceqi_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_CLTI_S_df: + tcg_gen_movi_i32(timm, s5); + gen_helper_msa_clti_s_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_CLTI_U_df: + gen_helper_msa_clti_u_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_CLEI_S_df: + tcg_gen_movi_i32(timm, s5); + gen_helper_msa_clei_s_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_CLEI_U_df: + gen_helper_msa_clei_u_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_LDI_df: + { + int32_t s10 =3D sextract32(ctx->opcode, 11, 10); + tcg_gen_movi_i32(timm, s10); + gen_helper_msa_ldi_df(cpu_env, tdf, twd, timm); + } + break; + default: + MIPS_INVAL("MSA instruction"); + gen_reserved_instruction(ctx); + break; + } + + tcg_temp_free_i32(tdf); + tcg_temp_free_i32(twd); + tcg_temp_free_i32(tws); + tcg_temp_free_i32(timm); +} + +static void gen_msa_bit(DisasContext *ctx) +{ +#define MASK_MSA_BIT(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) + uint8_t dfm =3D (ctx->opcode >> 16) & 0x7f; + uint32_t df =3D 0, m =3D 0; + uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + + TCGv_i32 tdf; + TCGv_i32 tm; + TCGv_i32 twd; + TCGv_i32 tws; + + if ((dfm & 0x40) =3D=3D 0x00) { + m =3D dfm & 0x3f; + df =3D DF_DOUBLE; + } else if ((dfm & 0x60) =3D=3D 0x40) { + m =3D dfm & 0x1f; + df =3D DF_WORD; + } else if ((dfm & 0x70) =3D=3D 0x60) { + m =3D dfm & 0x0f; + df =3D DF_HALF; + } else if ((dfm & 0x78) =3D=3D 0x70) { + m =3D dfm & 0x7; + df =3D DF_BYTE; + } else { + gen_reserved_instruction(ctx); + return; + } + + tdf =3D tcg_const_i32(df); + tm =3D tcg_const_i32(m); + twd =3D tcg_const_i32(wd); + tws =3D tcg_const_i32(ws); + + switch (MASK_MSA_BIT(ctx->opcode)) { + case OPC_SLLI_df: + gen_helper_msa_slli_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_SRAI_df: + gen_helper_msa_srai_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_SRLI_df: + gen_helper_msa_srli_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_BCLRI_df: + gen_helper_msa_bclri_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_BSETI_df: + gen_helper_msa_bseti_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_BNEGI_df: + gen_helper_msa_bnegi_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_BINSLI_df: + gen_helper_msa_binsli_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_BINSRI_df: + gen_helper_msa_binsri_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_SAT_S_df: + gen_helper_msa_sat_s_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_SAT_U_df: + gen_helper_msa_sat_u_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_SRARI_df: + gen_helper_msa_srari_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_SRLRI_df: + gen_helper_msa_srlri_df(cpu_env, tdf, twd, tws, tm); + break; + default: + MIPS_INVAL("MSA instruction"); + gen_reserved_instruction(ctx); + break; + } + + tcg_temp_free_i32(tdf); + tcg_temp_free_i32(tm); + tcg_temp_free_i32(twd); + tcg_temp_free_i32(tws); +} + +static void gen_msa_3r(DisasContext *ctx) +{ +#define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) + uint8_t df =3D (ctx->opcode >> 21) & 0x3; + uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; + uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + + TCGv_i32 tdf =3D tcg_const_i32(df); + TCGv_i32 twd =3D tcg_const_i32(wd); + TCGv_i32 tws =3D tcg_const_i32(ws); + TCGv_i32 twt =3D tcg_const_i32(wt); + + switch (MASK_MSA_3R(ctx->opcode)) { + case OPC_BINSL_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_binsl_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_binsl_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_binsl_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_binsl_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_BINSR_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_binsr_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_binsr_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_binsr_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_binsr_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_BCLR_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_bclr_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_bclr_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_bclr_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_bclr_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_BNEG_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_bneg_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_bneg_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_bneg_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_bneg_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_BSET_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_bset_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_bset_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_bset_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_bset_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ADD_A_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_add_a_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_add_a_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_add_a_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_add_a_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ADDS_A_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_adds_a_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_adds_a_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_adds_a_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_adds_a_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ADDS_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_adds_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_adds_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_adds_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_adds_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ADDS_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_adds_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_adds_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_adds_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_adds_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ADDV_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_addv_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_addv_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_addv_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_addv_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_AVE_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ave_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ave_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ave_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ave_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_AVE_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ave_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ave_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ave_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ave_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_AVER_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_aver_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_aver_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_aver_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_aver_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_AVER_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_aver_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_aver_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_aver_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_aver_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_CEQ_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ceq_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ceq_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ceq_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ceq_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_CLE_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_cle_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_cle_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_cle_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_cle_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_CLE_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_cle_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_cle_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_cle_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_cle_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_CLT_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_clt_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_clt_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_clt_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_clt_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_CLT_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_clt_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_clt_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_clt_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_clt_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_DIV_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_div_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_div_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_div_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_div_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_DIV_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_div_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_div_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_div_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_div_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MAX_A_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_max_a_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_max_a_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_max_a_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_max_a_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MAX_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_max_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_max_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_max_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_max_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MAX_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_max_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_max_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_max_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_max_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MIN_A_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_min_a_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_min_a_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_min_a_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_min_a_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MIN_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_min_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_min_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_min_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_min_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MIN_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_min_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_min_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_min_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_min_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MOD_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_mod_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_mod_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_mod_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_mod_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MOD_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_mod_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_mod_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_mod_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_mod_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MADDV_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_maddv_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_maddv_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_maddv_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_maddv_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MSUBV_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_msubv_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_msubv_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_msubv_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_msubv_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ASUB_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_asub_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_asub_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_asub_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_asub_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ASUB_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_asub_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_asub_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_asub_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_asub_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ILVEV_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ilvev_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ilvev_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ilvev_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ilvev_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ILVOD_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ilvod_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ilvod_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ilvod_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ilvod_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ILVL_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ilvl_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ilvl_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ilvl_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ilvl_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ILVR_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ilvr_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ilvr_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ilvr_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ilvr_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_PCKEV_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_pckev_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_pckev_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_pckev_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_pckev_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_PCKOD_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_pckod_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_pckod_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_pckod_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_pckod_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SLL_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_sll_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_sll_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_sll_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_sll_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SRA_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_sra_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_sra_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_sra_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_sra_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SRAR_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_srar_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_srar_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_srar_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_srar_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SRL_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_srl_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_srl_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_srl_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_srl_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SRLR_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_srlr_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_srlr_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_srlr_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_srlr_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SUBS_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_subs_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_subs_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_subs_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_subs_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MULV_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_mulv_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_mulv_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_mulv_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_mulv_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SLD_df: + gen_helper_msa_sld_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_VSHF_df: + gen_helper_msa_vshf_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_SUBV_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_subv_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_subv_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_subv_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_subv_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SUBS_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_subs_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_subs_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_subs_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_subs_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SPLAT_df: + gen_helper_msa_splat_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_SUBSUS_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_subsus_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_subsus_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_subsus_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_subsus_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SUBSUU_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_subsuu_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_subsuu_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_subsuu_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_subsuu_s_d(cpu_env, twd, tws, twt); + break; + } + break; + + case OPC_DOTP_S_df: + case OPC_DOTP_U_df: + case OPC_DPADD_S_df: + case OPC_DPADD_U_df: + case OPC_DPSUB_S_df: + case OPC_HADD_S_df: + case OPC_DPSUB_U_df: + case OPC_HADD_U_df: + case OPC_HSUB_S_df: + case OPC_HSUB_U_df: + if (df =3D=3D DF_BYTE) { + gen_reserved_instruction(ctx); + break; + } + switch (MASK_MSA_3R(ctx->opcode)) { + case OPC_HADD_S_df: + switch (df) { + case DF_HALF: + gen_helper_msa_hadd_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_hadd_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_hadd_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_HADD_U_df: + switch (df) { + case DF_HALF: + gen_helper_msa_hadd_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_hadd_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_hadd_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_HSUB_S_df: + switch (df) { + case DF_HALF: + gen_helper_msa_hsub_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_hsub_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_hsub_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_HSUB_U_df: + switch (df) { + case DF_HALF: + gen_helper_msa_hsub_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_hsub_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_hsub_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_DOTP_S_df: + switch (df) { + case DF_HALF: + gen_helper_msa_dotp_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_dotp_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_dotp_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_DOTP_U_df: + switch (df) { + case DF_HALF: + gen_helper_msa_dotp_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_dotp_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_dotp_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_DPADD_S_df: + switch (df) { + case DF_HALF: + gen_helper_msa_dpadd_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_dpadd_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_dpadd_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_DPADD_U_df: + switch (df) { + case DF_HALF: + gen_helper_msa_dpadd_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_dpadd_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_dpadd_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_DPSUB_S_df: + switch (df) { + case DF_HALF: + gen_helper_msa_dpsub_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_dpsub_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_dpsub_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_DPSUB_U_df: + switch (df) { + case DF_HALF: + gen_helper_msa_dpsub_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_dpsub_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_dpsub_u_d(cpu_env, twd, tws, twt); + break; + } + break; + } + break; + default: + MIPS_INVAL("MSA instruction"); + gen_reserved_instruction(ctx); + break; + } + tcg_temp_free_i32(twd); + tcg_temp_free_i32(tws); + tcg_temp_free_i32(twt); + tcg_temp_free_i32(tdf); +} + +static void gen_msa_elm_3e(DisasContext *ctx) +{ +#define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16))) + uint8_t source =3D (ctx->opcode >> 11) & 0x1f; + uint8_t dest =3D (ctx->opcode >> 6) & 0x1f; + TCGv telm =3D tcg_temp_new(); + TCGv_i32 tsr =3D tcg_const_i32(source); + TCGv_i32 tdt =3D tcg_const_i32(dest); + + switch (MASK_MSA_ELM_DF3E(ctx->opcode)) { + case OPC_CTCMSA: + gen_load_gpr(telm, source); + gen_helper_msa_ctcmsa(cpu_env, telm, tdt); + break; + case OPC_CFCMSA: + gen_helper_msa_cfcmsa(telm, cpu_env, tsr); + gen_store_gpr(telm, dest); + break; + case OPC_MOVE_V: + gen_helper_msa_move_v(cpu_env, tdt, tsr); + break; + default: + MIPS_INVAL("MSA instruction"); + gen_reserved_instruction(ctx); + break; + } + + tcg_temp_free(telm); + tcg_temp_free_i32(tdt); + tcg_temp_free_i32(tsr); +} + +static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n) +{ +#define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) + uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + + TCGv_i32 tws =3D tcg_const_i32(ws); + TCGv_i32 twd =3D tcg_const_i32(wd); + TCGv_i32 tn =3D tcg_const_i32(n); + TCGv_i32 tdf =3D tcg_const_i32(df); + + switch (MASK_MSA_ELM(ctx->opcode)) { + case OPC_SLDI_df: + gen_helper_msa_sldi_df(cpu_env, tdf, twd, tws, tn); + break; + case OPC_SPLATI_df: + gen_helper_msa_splati_df(cpu_env, tdf, twd, tws, tn); + break; + case OPC_INSVE_df: + gen_helper_msa_insve_df(cpu_env, tdf, twd, tws, tn); + break; + case OPC_COPY_S_df: + case OPC_COPY_U_df: + case OPC_INSERT_df: +#if !defined(TARGET_MIPS64) + /* Double format valid only for MIPS64 */ + if (df =3D=3D DF_DOUBLE) { + gen_reserved_instruction(ctx); + break; + } + if ((MASK_MSA_ELM(ctx->opcode) =3D=3D OPC_COPY_U_df) && + (df =3D=3D DF_WORD)) { + gen_reserved_instruction(ctx); + break; + } +#endif + switch (MASK_MSA_ELM(ctx->opcode)) { + case OPC_COPY_S_df: + if (likely(wd !=3D 0)) { + switch (df) { + case DF_BYTE: + gen_helper_msa_copy_s_b(cpu_env, twd, tws, tn); + break; + case DF_HALF: + gen_helper_msa_copy_s_h(cpu_env, twd, tws, tn); + break; + case DF_WORD: + gen_helper_msa_copy_s_w(cpu_env, twd, tws, tn); + break; +#if defined(TARGET_MIPS64) + case DF_DOUBLE: + gen_helper_msa_copy_s_d(cpu_env, twd, tws, tn); + break; +#endif + default: + assert(0); + } + } + break; + case OPC_COPY_U_df: + if (likely(wd !=3D 0)) { + switch (df) { + case DF_BYTE: + gen_helper_msa_copy_u_b(cpu_env, twd, tws, tn); + break; + case DF_HALF: + gen_helper_msa_copy_u_h(cpu_env, twd, tws, tn); + break; +#if defined(TARGET_MIPS64) + case DF_WORD: + gen_helper_msa_copy_u_w(cpu_env, twd, tws, tn); + break; +#endif + default: + assert(0); + } + } + break; + case OPC_INSERT_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_insert_b(cpu_env, twd, tws, tn); + break; + case DF_HALF: + gen_helper_msa_insert_h(cpu_env, twd, tws, tn); + break; + case DF_WORD: + gen_helper_msa_insert_w(cpu_env, twd, tws, tn); + break; +#if defined(TARGET_MIPS64) + case DF_DOUBLE: + gen_helper_msa_insert_d(cpu_env, twd, tws, tn); + break; +#endif + default: + assert(0); + } + break; + } + break; + default: + MIPS_INVAL("MSA instruction"); + gen_reserved_instruction(ctx); + } + tcg_temp_free_i32(twd); + tcg_temp_free_i32(tws); + tcg_temp_free_i32(tn); + tcg_temp_free_i32(tdf); +} + +static void gen_msa_elm(DisasContext *ctx) +{ + uint8_t dfn =3D (ctx->opcode >> 16) & 0x3f; + uint32_t df =3D 0, n =3D 0; + + if ((dfn & 0x30) =3D=3D 0x00) { + n =3D dfn & 0x0f; + df =3D DF_BYTE; + } else if ((dfn & 0x38) =3D=3D 0x20) { + n =3D dfn & 0x07; + df =3D DF_HALF; + } else if ((dfn & 0x3c) =3D=3D 0x30) { + n =3D dfn & 0x03; + df =3D DF_WORD; + } else if ((dfn & 0x3e) =3D=3D 0x38) { + n =3D dfn & 0x01; + df =3D DF_DOUBLE; + } else if (dfn =3D=3D 0x3E) { + /* CTCMSA, CFCMSA, MOVE.V */ + gen_msa_elm_3e(ctx); + return; + } else { + gen_reserved_instruction(ctx); + return; + } + + gen_msa_elm_df(ctx, df, n); +} + +static void gen_msa_3rf(DisasContext *ctx) +{ +#define MASK_MSA_3RF(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) + uint8_t df =3D (ctx->opcode >> 21) & 0x1; + uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; + uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + + TCGv_i32 twd =3D tcg_const_i32(wd); + TCGv_i32 tws =3D tcg_const_i32(ws); + TCGv_i32 twt =3D tcg_const_i32(wt); + TCGv_i32 tdf =3D tcg_temp_new_i32(); + + /* adjust df value for floating-point instruction */ + tcg_gen_movi_i32(tdf, df + 2); + + switch (MASK_MSA_3RF(ctx->opcode)) { + case OPC_FCAF_df: + gen_helper_msa_fcaf_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FADD_df: + gen_helper_msa_fadd_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCUN_df: + gen_helper_msa_fcun_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSUB_df: + gen_helper_msa_fsub_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCOR_df: + gen_helper_msa_fcor_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCEQ_df: + gen_helper_msa_fceq_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FMUL_df: + gen_helper_msa_fmul_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCUNE_df: + gen_helper_msa_fcune_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCUEQ_df: + gen_helper_msa_fcueq_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FDIV_df: + gen_helper_msa_fdiv_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCNE_df: + gen_helper_msa_fcne_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCLT_df: + gen_helper_msa_fclt_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FMADD_df: + gen_helper_msa_fmadd_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_MUL_Q_df: + tcg_gen_movi_i32(tdf, df + 1); + gen_helper_msa_mul_q_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCULT_df: + gen_helper_msa_fcult_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FMSUB_df: + gen_helper_msa_fmsub_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_MADD_Q_df: + tcg_gen_movi_i32(tdf, df + 1); + gen_helper_msa_madd_q_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCLE_df: + gen_helper_msa_fcle_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_MSUB_Q_df: + tcg_gen_movi_i32(tdf, df + 1); + gen_helper_msa_msub_q_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCULE_df: + gen_helper_msa_fcule_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FEXP2_df: + gen_helper_msa_fexp2_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSAF_df: + gen_helper_msa_fsaf_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FEXDO_df: + gen_helper_msa_fexdo_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSUN_df: + gen_helper_msa_fsun_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSOR_df: + gen_helper_msa_fsor_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSEQ_df: + gen_helper_msa_fseq_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FTQ_df: + gen_helper_msa_ftq_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSUNE_df: + gen_helper_msa_fsune_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSUEQ_df: + gen_helper_msa_fsueq_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSNE_df: + gen_helper_msa_fsne_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSLT_df: + gen_helper_msa_fslt_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FMIN_df: + gen_helper_msa_fmin_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_MULR_Q_df: + tcg_gen_movi_i32(tdf, df + 1); + gen_helper_msa_mulr_q_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSULT_df: + gen_helper_msa_fsult_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FMIN_A_df: + gen_helper_msa_fmin_a_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_MADDR_Q_df: + tcg_gen_movi_i32(tdf, df + 1); + gen_helper_msa_maddr_q_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSLE_df: + gen_helper_msa_fsle_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FMAX_df: + gen_helper_msa_fmax_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_MSUBR_Q_df: + tcg_gen_movi_i32(tdf, df + 1); + gen_helper_msa_msubr_q_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSULE_df: + gen_helper_msa_fsule_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FMAX_A_df: + gen_helper_msa_fmax_a_df(cpu_env, tdf, twd, tws, twt); + break; + default: + MIPS_INVAL("MSA instruction"); + gen_reserved_instruction(ctx); + break; + } + + tcg_temp_free_i32(twd); + tcg_temp_free_i32(tws); + tcg_temp_free_i32(twt); + tcg_temp_free_i32(tdf); +} + +static void gen_msa_2r(DisasContext *ctx) +{ +#define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \ + (op & (0x7 << 18))) + uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; + uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + uint8_t df =3D (ctx->opcode >> 16) & 0x3; + TCGv_i32 twd =3D tcg_const_i32(wd); + TCGv_i32 tws =3D tcg_const_i32(ws); + TCGv_i32 twt =3D tcg_const_i32(wt); + TCGv_i32 tdf =3D tcg_const_i32(df); + + switch (MASK_MSA_2R(ctx->opcode)) { + case OPC_FILL_df: +#if !defined(TARGET_MIPS64) + /* Double format valid only for MIPS64 */ + if (df =3D=3D DF_DOUBLE) { + gen_reserved_instruction(ctx); + break; + } +#endif + gen_helper_msa_fill_df(cpu_env, tdf, twd, tws); /* trs */ + break; + case OPC_NLOC_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_nloc_b(cpu_env, twd, tws); + break; + case DF_HALF: + gen_helper_msa_nloc_h(cpu_env, twd, tws); + break; + case DF_WORD: + gen_helper_msa_nloc_w(cpu_env, twd, tws); + break; + case DF_DOUBLE: + gen_helper_msa_nloc_d(cpu_env, twd, tws); + break; + } + break; + case OPC_NLZC_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_nlzc_b(cpu_env, twd, tws); + break; + case DF_HALF: + gen_helper_msa_nlzc_h(cpu_env, twd, tws); + break; + case DF_WORD: + gen_helper_msa_nlzc_w(cpu_env, twd, tws); + break; + case DF_DOUBLE: + gen_helper_msa_nlzc_d(cpu_env, twd, tws); + break; + } + break; + case OPC_PCNT_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_pcnt_b(cpu_env, twd, tws); + break; + case DF_HALF: + gen_helper_msa_pcnt_h(cpu_env, twd, tws); + break; + case DF_WORD: + gen_helper_msa_pcnt_w(cpu_env, twd, tws); + break; + case DF_DOUBLE: + gen_helper_msa_pcnt_d(cpu_env, twd, tws); + break; + } + break; + default: + MIPS_INVAL("MSA instruction"); + gen_reserved_instruction(ctx); + break; + } + + tcg_temp_free_i32(twd); + tcg_temp_free_i32(tws); + tcg_temp_free_i32(twt); + tcg_temp_free_i32(tdf); +} + +static void gen_msa_2rf(DisasContext *ctx) +{ +#define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \ + (op & (0xf << 17))) + uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; + uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + uint8_t df =3D (ctx->opcode >> 16) & 0x1; + TCGv_i32 twd =3D tcg_const_i32(wd); + TCGv_i32 tws =3D tcg_const_i32(ws); + TCGv_i32 twt =3D tcg_const_i32(wt); + /* adjust df value for floating-point instruction */ + TCGv_i32 tdf =3D tcg_const_i32(df + 2); + + switch (MASK_MSA_2RF(ctx->opcode)) { + case OPC_FCLASS_df: + gen_helper_msa_fclass_df(cpu_env, tdf, twd, tws); + break; + case OPC_FTRUNC_S_df: + gen_helper_msa_ftrunc_s_df(cpu_env, tdf, twd, tws); + break; + case OPC_FTRUNC_U_df: + gen_helper_msa_ftrunc_u_df(cpu_env, tdf, twd, tws); + break; + case OPC_FSQRT_df: + gen_helper_msa_fsqrt_df(cpu_env, tdf, twd, tws); + break; + case OPC_FRSQRT_df: + gen_helper_msa_frsqrt_df(cpu_env, tdf, twd, tws); + break; + case OPC_FRCP_df: + gen_helper_msa_frcp_df(cpu_env, tdf, twd, tws); + break; + case OPC_FRINT_df: + gen_helper_msa_frint_df(cpu_env, tdf, twd, tws); + break; + case OPC_FLOG2_df: + gen_helper_msa_flog2_df(cpu_env, tdf, twd, tws); + break; + case OPC_FEXUPL_df: + gen_helper_msa_fexupl_df(cpu_env, tdf, twd, tws); + break; + case OPC_FEXUPR_df: + gen_helper_msa_fexupr_df(cpu_env, tdf, twd, tws); + break; + case OPC_FFQL_df: + gen_helper_msa_ffql_df(cpu_env, tdf, twd, tws); + break; + case OPC_FFQR_df: + gen_helper_msa_ffqr_df(cpu_env, tdf, twd, tws); + break; + case OPC_FTINT_S_df: + gen_helper_msa_ftint_s_df(cpu_env, tdf, twd, tws); + break; + case OPC_FTINT_U_df: + gen_helper_msa_ftint_u_df(cpu_env, tdf, twd, tws); + break; + case OPC_FFINT_S_df: + gen_helper_msa_ffint_s_df(cpu_env, tdf, twd, tws); + break; + case OPC_FFINT_U_df: + gen_helper_msa_ffint_u_df(cpu_env, tdf, twd, tws); + break; + } + + tcg_temp_free_i32(twd); + tcg_temp_free_i32(tws); + tcg_temp_free_i32(twt); + tcg_temp_free_i32(tdf); +} + +static void gen_msa_vec_v(DisasContext *ctx) +{ +#define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21))) + uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; + uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + TCGv_i32 twd =3D tcg_const_i32(wd); + TCGv_i32 tws =3D tcg_const_i32(ws); + TCGv_i32 twt =3D tcg_const_i32(wt); + + switch (MASK_MSA_VEC(ctx->opcode)) { + case OPC_AND_V: + gen_helper_msa_and_v(cpu_env, twd, tws, twt); + break; + case OPC_OR_V: + gen_helper_msa_or_v(cpu_env, twd, tws, twt); + break; + case OPC_NOR_V: + gen_helper_msa_nor_v(cpu_env, twd, tws, twt); + break; + case OPC_XOR_V: + gen_helper_msa_xor_v(cpu_env, twd, tws, twt); + break; + case OPC_BMNZ_V: + gen_helper_msa_bmnz_v(cpu_env, twd, tws, twt); + break; + case OPC_BMZ_V: + gen_helper_msa_bmz_v(cpu_env, twd, tws, twt); + break; + case OPC_BSEL_V: + gen_helper_msa_bsel_v(cpu_env, twd, tws, twt); + break; + default: + MIPS_INVAL("MSA instruction"); + gen_reserved_instruction(ctx); + break; + } + + tcg_temp_free_i32(twd); + tcg_temp_free_i32(tws); + tcg_temp_free_i32(twt); +} + +static void gen_msa_vec(DisasContext *ctx) +{ + switch (MASK_MSA_VEC(ctx->opcode)) { + case OPC_AND_V: + case OPC_OR_V: + case OPC_NOR_V: + case OPC_XOR_V: + case OPC_BMNZ_V: + case OPC_BMZ_V: + case OPC_BSEL_V: + gen_msa_vec_v(ctx); + break; + case OPC_MSA_2R: + gen_msa_2r(ctx); + break; + case OPC_MSA_2RF: + gen_msa_2rf(ctx); + break; + default: + MIPS_INVAL("MSA instruction"); + gen_reserved_instruction(ctx); + break; + } +} + +void gen_msa(DisasContext *ctx) +{ + uint32_t opcode =3D ctx->opcode; + + check_msa_access(ctx); + + switch (MASK_MSA_MINOR(opcode)) { + case OPC_MSA_I8_00: + case OPC_MSA_I8_01: + case OPC_MSA_I8_02: + gen_msa_i8(ctx); + break; + case OPC_MSA_I5_06: + case OPC_MSA_I5_07: + gen_msa_i5(ctx); + break; + case OPC_MSA_BIT_09: + case OPC_MSA_BIT_0A: + gen_msa_bit(ctx); + break; + case OPC_MSA_3R_0D: + case OPC_MSA_3R_0E: + case OPC_MSA_3R_0F: + case OPC_MSA_3R_10: + case OPC_MSA_3R_11: + case OPC_MSA_3R_12: + case OPC_MSA_3R_13: + case OPC_MSA_3R_14: + case OPC_MSA_3R_15: + gen_msa_3r(ctx); + break; + case OPC_MSA_ELM: + gen_msa_elm(ctx); + break; + case OPC_MSA_3RF_1A: + case OPC_MSA_3RF_1B: + case OPC_MSA_3RF_1C: + gen_msa_3rf(ctx); + break; + case OPC_MSA_VEC: + gen_msa_vec(ctx); + break; + case OPC_LD_B: + case OPC_LD_H: + case OPC_LD_W: + case OPC_LD_D: + case OPC_ST_B: + case OPC_ST_H: + case OPC_ST_W: + case OPC_ST_D: + { + int32_t s10 =3D sextract32(ctx->opcode, 16, 10); + uint8_t rs =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + uint8_t df =3D (ctx->opcode >> 0) & 0x3; + + TCGv_i32 twd =3D tcg_const_i32(wd); + TCGv taddr =3D tcg_temp_new(); + gen_base_offset_addr(ctx, taddr, rs, s10 << df); + + switch (MASK_MSA_MINOR(opcode)) { + case OPC_LD_B: + gen_helper_msa_ld_b(cpu_env, twd, taddr); + break; + case OPC_LD_H: + gen_helper_msa_ld_h(cpu_env, twd, taddr); + break; + case OPC_LD_W: + gen_helper_msa_ld_w(cpu_env, twd, taddr); + break; + case OPC_LD_D: + gen_helper_msa_ld_d(cpu_env, twd, taddr); + break; + case OPC_ST_B: + gen_helper_msa_st_b(cpu_env, twd, taddr); + break; + case OPC_ST_H: + gen_helper_msa_st_h(cpu_env, twd, taddr); + break; + case OPC_ST_W: + gen_helper_msa_st_w(cpu_env, twd, taddr); + break; + case OPC_ST_D: + gen_helper_msa_st_d(cpu_env, twd, taddr); + break; + } + + tcg_temp_free_i32(twd); + tcg_temp_free(taddr); + } + break; + default: + MIPS_INVAL("MSA instruction"); + gen_reserved_instruction(ctx); + break; + } +} diff --git a/target/mips/translate.c b/target/mips/translate.c index 20174c4aa57..1e20d426388 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1133,240 +1133,6 @@ enum { OPC_NMSUB_PS =3D 0x3E | OPC_CP3, }; =20 -/* MSA Opcodes */ -#define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) -enum { - OPC_MSA_I8_00 =3D 0x00 | OPC_MSA, - OPC_MSA_I8_01 =3D 0x01 | OPC_MSA, - OPC_MSA_I8_02 =3D 0x02 | OPC_MSA, - OPC_MSA_I5_06 =3D 0x06 | OPC_MSA, - OPC_MSA_I5_07 =3D 0x07 | OPC_MSA, - OPC_MSA_BIT_09 =3D 0x09 | OPC_MSA, - OPC_MSA_BIT_0A =3D 0x0A | OPC_MSA, - OPC_MSA_3R_0D =3D 0x0D | OPC_MSA, - OPC_MSA_3R_0E =3D 0x0E | OPC_MSA, - OPC_MSA_3R_0F =3D 0x0F | OPC_MSA, - OPC_MSA_3R_10 =3D 0x10 | OPC_MSA, - OPC_MSA_3R_11 =3D 0x11 | OPC_MSA, - OPC_MSA_3R_12 =3D 0x12 | OPC_MSA, - OPC_MSA_3R_13 =3D 0x13 | OPC_MSA, - OPC_MSA_3R_14 =3D 0x14 | OPC_MSA, - OPC_MSA_3R_15 =3D 0x15 | OPC_MSA, - OPC_MSA_ELM =3D 0x19 | OPC_MSA, - OPC_MSA_3RF_1A =3D 0x1A | OPC_MSA, - OPC_MSA_3RF_1B =3D 0x1B | OPC_MSA, - OPC_MSA_3RF_1C =3D 0x1C | OPC_MSA, - OPC_MSA_VEC =3D 0x1E | OPC_MSA, - - /* MI10 instruction */ - OPC_LD_B =3D (0x20) | OPC_MSA, - OPC_LD_H =3D (0x21) | OPC_MSA, - OPC_LD_W =3D (0x22) | OPC_MSA, - OPC_LD_D =3D (0x23) | OPC_MSA, - OPC_ST_B =3D (0x24) | OPC_MSA, - OPC_ST_H =3D (0x25) | OPC_MSA, - OPC_ST_W =3D (0x26) | OPC_MSA, - OPC_ST_D =3D (0x27) | OPC_MSA, -}; - -enum { - /* I5 instruction df(bits 22..21) =3D _b, _h, _w, _d */ - OPC_ADDVI_df =3D (0x0 << 23) | OPC_MSA_I5_06, - OPC_CEQI_df =3D (0x0 << 23) | OPC_MSA_I5_07, - OPC_SUBVI_df =3D (0x1 << 23) | OPC_MSA_I5_06, - OPC_MAXI_S_df =3D (0x2 << 23) | OPC_MSA_I5_06, - OPC_CLTI_S_df =3D (0x2 << 23) | OPC_MSA_I5_07, - OPC_MAXI_U_df =3D (0x3 << 23) | OPC_MSA_I5_06, - OPC_CLTI_U_df =3D (0x3 << 23) | OPC_MSA_I5_07, - OPC_MINI_S_df =3D (0x4 << 23) | OPC_MSA_I5_06, - OPC_CLEI_S_df =3D (0x4 << 23) | OPC_MSA_I5_07, - OPC_MINI_U_df =3D (0x5 << 23) | OPC_MSA_I5_06, - OPC_CLEI_U_df =3D (0x5 << 23) | OPC_MSA_I5_07, - OPC_LDI_df =3D (0x6 << 23) | OPC_MSA_I5_07, - - /* I8 instruction */ - OPC_ANDI_B =3D (0x0 << 24) | OPC_MSA_I8_00, - OPC_BMNZI_B =3D (0x0 << 24) | OPC_MSA_I8_01, - OPC_SHF_B =3D (0x0 << 24) | OPC_MSA_I8_02, - OPC_ORI_B =3D (0x1 << 24) | OPC_MSA_I8_00, - OPC_BMZI_B =3D (0x1 << 24) | OPC_MSA_I8_01, - OPC_SHF_H =3D (0x1 << 24) | OPC_MSA_I8_02, - OPC_NORI_B =3D (0x2 << 24) | OPC_MSA_I8_00, - OPC_BSELI_B =3D (0x2 << 24) | OPC_MSA_I8_01, - OPC_SHF_W =3D (0x2 << 24) | OPC_MSA_I8_02, - OPC_XORI_B =3D (0x3 << 24) | OPC_MSA_I8_00, - - /* VEC/2R/2RF instruction */ - OPC_AND_V =3D (0x00 << 21) | OPC_MSA_VEC, - OPC_OR_V =3D (0x01 << 21) | OPC_MSA_VEC, - OPC_NOR_V =3D (0x02 << 21) | OPC_MSA_VEC, - OPC_XOR_V =3D (0x03 << 21) | OPC_MSA_VEC, - OPC_BMNZ_V =3D (0x04 << 21) | OPC_MSA_VEC, - OPC_BMZ_V =3D (0x05 << 21) | OPC_MSA_VEC, - OPC_BSEL_V =3D (0x06 << 21) | OPC_MSA_VEC, - - OPC_MSA_2R =3D (0x18 << 21) | OPC_MSA_VEC, - OPC_MSA_2RF =3D (0x19 << 21) | OPC_MSA_VEC, - - /* 2R instruction df(bits 17..16) =3D _b, _h, _w, _d */ - OPC_FILL_df =3D (0x00 << 18) | OPC_MSA_2R, - OPC_PCNT_df =3D (0x01 << 18) | OPC_MSA_2R, - OPC_NLOC_df =3D (0x02 << 18) | OPC_MSA_2R, - OPC_NLZC_df =3D (0x03 << 18) | OPC_MSA_2R, - - /* 2RF instruction df(bit 16) =3D _w, _d */ - OPC_FCLASS_df =3D (0x00 << 17) | OPC_MSA_2RF, - OPC_FTRUNC_S_df =3D (0x01 << 17) | OPC_MSA_2RF, - OPC_FTRUNC_U_df =3D (0x02 << 17) | OPC_MSA_2RF, - OPC_FSQRT_df =3D (0x03 << 17) | OPC_MSA_2RF, - OPC_FRSQRT_df =3D (0x04 << 17) | OPC_MSA_2RF, - OPC_FRCP_df =3D (0x05 << 17) | OPC_MSA_2RF, - OPC_FRINT_df =3D (0x06 << 17) | OPC_MSA_2RF, - OPC_FLOG2_df =3D (0x07 << 17) | OPC_MSA_2RF, - OPC_FEXUPL_df =3D (0x08 << 17) | OPC_MSA_2RF, - OPC_FEXUPR_df =3D (0x09 << 17) | OPC_MSA_2RF, - OPC_FFQL_df =3D (0x0A << 17) | OPC_MSA_2RF, - OPC_FFQR_df =3D (0x0B << 17) | OPC_MSA_2RF, - OPC_FTINT_S_df =3D (0x0C << 17) | OPC_MSA_2RF, - OPC_FTINT_U_df =3D (0x0D << 17) | OPC_MSA_2RF, - OPC_FFINT_S_df =3D (0x0E << 17) | OPC_MSA_2RF, - OPC_FFINT_U_df =3D (0x0F << 17) | OPC_MSA_2RF, - - /* 3R instruction df(bits 22..21) =3D _b, _h, _w, d */ - OPC_SLL_df =3D (0x0 << 23) | OPC_MSA_3R_0D, - OPC_ADDV_df =3D (0x0 << 23) | OPC_MSA_3R_0E, - OPC_CEQ_df =3D (0x0 << 23) | OPC_MSA_3R_0F, - OPC_ADD_A_df =3D (0x0 << 23) | OPC_MSA_3R_10, - OPC_SUBS_S_df =3D (0x0 << 23) | OPC_MSA_3R_11, - OPC_MULV_df =3D (0x0 << 23) | OPC_MSA_3R_12, - OPC_DOTP_S_df =3D (0x0 << 23) | OPC_MSA_3R_13, - OPC_SLD_df =3D (0x0 << 23) | OPC_MSA_3R_14, - OPC_VSHF_df =3D (0x0 << 23) | OPC_MSA_3R_15, - OPC_SRA_df =3D (0x1 << 23) | OPC_MSA_3R_0D, - OPC_SUBV_df =3D (0x1 << 23) | OPC_MSA_3R_0E, - OPC_ADDS_A_df =3D (0x1 << 23) | OPC_MSA_3R_10, - OPC_SUBS_U_df =3D (0x1 << 23) | OPC_MSA_3R_11, - OPC_MADDV_df =3D (0x1 << 23) | OPC_MSA_3R_12, - OPC_DOTP_U_df =3D (0x1 << 23) | OPC_MSA_3R_13, - OPC_SPLAT_df =3D (0x1 << 23) | OPC_MSA_3R_14, - OPC_SRAR_df =3D (0x1 << 23) | OPC_MSA_3R_15, - OPC_SRL_df =3D (0x2 << 23) | OPC_MSA_3R_0D, - OPC_MAX_S_df =3D (0x2 << 23) | OPC_MSA_3R_0E, - OPC_CLT_S_df =3D (0x2 << 23) | OPC_MSA_3R_0F, - OPC_ADDS_S_df =3D (0x2 << 23) | OPC_MSA_3R_10, - OPC_SUBSUS_U_df =3D (0x2 << 23) | OPC_MSA_3R_11, - OPC_MSUBV_df =3D (0x2 << 23) | OPC_MSA_3R_12, - OPC_DPADD_S_df =3D (0x2 << 23) | OPC_MSA_3R_13, - OPC_PCKEV_df =3D (0x2 << 23) | OPC_MSA_3R_14, - OPC_SRLR_df =3D (0x2 << 23) | OPC_MSA_3R_15, - OPC_BCLR_df =3D (0x3 << 23) | OPC_MSA_3R_0D, - OPC_MAX_U_df =3D (0x3 << 23) | OPC_MSA_3R_0E, - OPC_CLT_U_df =3D (0x3 << 23) | OPC_MSA_3R_0F, - OPC_ADDS_U_df =3D (0x3 << 23) | OPC_MSA_3R_10, - OPC_SUBSUU_S_df =3D (0x3 << 23) | OPC_MSA_3R_11, - OPC_DPADD_U_df =3D (0x3 << 23) | OPC_MSA_3R_13, - OPC_PCKOD_df =3D (0x3 << 23) | OPC_MSA_3R_14, - OPC_BSET_df =3D (0x4 << 23) | OPC_MSA_3R_0D, - OPC_MIN_S_df =3D (0x4 << 23) | OPC_MSA_3R_0E, - OPC_CLE_S_df =3D (0x4 << 23) | OPC_MSA_3R_0F, - OPC_AVE_S_df =3D (0x4 << 23) | OPC_MSA_3R_10, - OPC_ASUB_S_df =3D (0x4 << 23) | OPC_MSA_3R_11, - OPC_DIV_S_df =3D (0x4 << 23) | OPC_MSA_3R_12, - OPC_DPSUB_S_df =3D (0x4 << 23) | OPC_MSA_3R_13, - OPC_ILVL_df =3D (0x4 << 23) | OPC_MSA_3R_14, - OPC_HADD_S_df =3D (0x4 << 23) | OPC_MSA_3R_15, - OPC_BNEG_df =3D (0x5 << 23) | OPC_MSA_3R_0D, - OPC_MIN_U_df =3D (0x5 << 23) | OPC_MSA_3R_0E, - OPC_CLE_U_df =3D (0x5 << 23) | OPC_MSA_3R_0F, - OPC_AVE_U_df =3D (0x5 << 23) | OPC_MSA_3R_10, - OPC_ASUB_U_df =3D (0x5 << 23) | OPC_MSA_3R_11, - OPC_DIV_U_df =3D (0x5 << 23) | OPC_MSA_3R_12, - OPC_DPSUB_U_df =3D (0x5 << 23) | OPC_MSA_3R_13, - OPC_ILVR_df =3D (0x5 << 23) | OPC_MSA_3R_14, - OPC_HADD_U_df =3D (0x5 << 23) | OPC_MSA_3R_15, - OPC_BINSL_df =3D (0x6 << 23) | OPC_MSA_3R_0D, - OPC_MAX_A_df =3D (0x6 << 23) | OPC_MSA_3R_0E, - OPC_AVER_S_df =3D (0x6 << 23) | OPC_MSA_3R_10, - OPC_MOD_S_df =3D (0x6 << 23) | OPC_MSA_3R_12, - OPC_ILVEV_df =3D (0x6 << 23) | OPC_MSA_3R_14, - OPC_HSUB_S_df =3D (0x6 << 23) | OPC_MSA_3R_15, - OPC_BINSR_df =3D (0x7 << 23) | OPC_MSA_3R_0D, - OPC_MIN_A_df =3D (0x7 << 23) | OPC_MSA_3R_0E, - OPC_AVER_U_df =3D (0x7 << 23) | OPC_MSA_3R_10, - OPC_MOD_U_df =3D (0x7 << 23) | OPC_MSA_3R_12, - OPC_ILVOD_df =3D (0x7 << 23) | OPC_MSA_3R_14, - OPC_HSUB_U_df =3D (0x7 << 23) | OPC_MSA_3R_15, - - /* ELM instructions df(bits 21..16) =3D _b, _h, _w, _d */ - OPC_SLDI_df =3D (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM, - OPC_CTCMSA =3D (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM, - OPC_SPLATI_df =3D (0x1 << 22) | (0x00 << 16) | OPC_MSA_ELM, - OPC_CFCMSA =3D (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM, - OPC_COPY_S_df =3D (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM, - OPC_MOVE_V =3D (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM, - OPC_COPY_U_df =3D (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM, - OPC_INSERT_df =3D (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM, - OPC_INSVE_df =3D (0x5 << 22) | (0x00 << 16) | OPC_MSA_ELM, - - /* 3RF instruction _df(bit 21) =3D _w, _d */ - OPC_FCAF_df =3D (0x0 << 22) | OPC_MSA_3RF_1A, - OPC_FADD_df =3D (0x0 << 22) | OPC_MSA_3RF_1B, - OPC_FCUN_df =3D (0x1 << 22) | OPC_MSA_3RF_1A, - OPC_FSUB_df =3D (0x1 << 22) | OPC_MSA_3RF_1B, - OPC_FCOR_df =3D (0x1 << 22) | OPC_MSA_3RF_1C, - OPC_FCEQ_df =3D (0x2 << 22) | OPC_MSA_3RF_1A, - OPC_FMUL_df =3D (0x2 << 22) | OPC_MSA_3RF_1B, - OPC_FCUNE_df =3D (0x2 << 22) | OPC_MSA_3RF_1C, - OPC_FCUEQ_df =3D (0x3 << 22) | OPC_MSA_3RF_1A, - OPC_FDIV_df =3D (0x3 << 22) | OPC_MSA_3RF_1B, - OPC_FCNE_df =3D (0x3 << 22) | OPC_MSA_3RF_1C, - OPC_FCLT_df =3D (0x4 << 22) | OPC_MSA_3RF_1A, - OPC_FMADD_df =3D (0x4 << 22) | OPC_MSA_3RF_1B, - OPC_MUL_Q_df =3D (0x4 << 22) | OPC_MSA_3RF_1C, - OPC_FCULT_df =3D (0x5 << 22) | OPC_MSA_3RF_1A, - OPC_FMSUB_df =3D (0x5 << 22) | OPC_MSA_3RF_1B, - OPC_MADD_Q_df =3D (0x5 << 22) | OPC_MSA_3RF_1C, - OPC_FCLE_df =3D (0x6 << 22) | OPC_MSA_3RF_1A, - OPC_MSUB_Q_df =3D (0x6 << 22) | OPC_MSA_3RF_1C, - OPC_FCULE_df =3D (0x7 << 22) | OPC_MSA_3RF_1A, - OPC_FEXP2_df =3D (0x7 << 22) | OPC_MSA_3RF_1B, - OPC_FSAF_df =3D (0x8 << 22) | OPC_MSA_3RF_1A, - OPC_FEXDO_df =3D (0x8 << 22) | OPC_MSA_3RF_1B, - OPC_FSUN_df =3D (0x9 << 22) | OPC_MSA_3RF_1A, - OPC_FSOR_df =3D (0x9 << 22) | OPC_MSA_3RF_1C, - OPC_FSEQ_df =3D (0xA << 22) | OPC_MSA_3RF_1A, - OPC_FTQ_df =3D (0xA << 22) | OPC_MSA_3RF_1B, - OPC_FSUNE_df =3D (0xA << 22) | OPC_MSA_3RF_1C, - OPC_FSUEQ_df =3D (0xB << 22) | OPC_MSA_3RF_1A, - OPC_FSNE_df =3D (0xB << 22) | OPC_MSA_3RF_1C, - OPC_FSLT_df =3D (0xC << 22) | OPC_MSA_3RF_1A, - OPC_FMIN_df =3D (0xC << 22) | OPC_MSA_3RF_1B, - OPC_MULR_Q_df =3D (0xC << 22) | OPC_MSA_3RF_1C, - OPC_FSULT_df =3D (0xD << 22) | OPC_MSA_3RF_1A, - OPC_FMIN_A_df =3D (0xD << 22) | OPC_MSA_3RF_1B, - OPC_MADDR_Q_df =3D (0xD << 22) | OPC_MSA_3RF_1C, - OPC_FSLE_df =3D (0xE << 22) | OPC_MSA_3RF_1A, - OPC_FMAX_df =3D (0xE << 22) | OPC_MSA_3RF_1B, - OPC_MSUBR_Q_df =3D (0xE << 22) | OPC_MSA_3RF_1C, - OPC_FSULE_df =3D (0xF << 22) | OPC_MSA_3RF_1A, - OPC_FMAX_A_df =3D (0xF << 22) | OPC_MSA_3RF_1B, - - /* BIT instruction df(bits 22..16) =3D _B _H _W _D */ - OPC_SLLI_df =3D (0x0 << 23) | OPC_MSA_BIT_09, - OPC_SAT_S_df =3D (0x0 << 23) | OPC_MSA_BIT_0A, - OPC_SRAI_df =3D (0x1 << 23) | OPC_MSA_BIT_09, - OPC_SAT_U_df =3D (0x1 << 23) | OPC_MSA_BIT_0A, - OPC_SRLI_df =3D (0x2 << 23) | OPC_MSA_BIT_09, - OPC_SRARI_df =3D (0x2 << 23) | OPC_MSA_BIT_0A, - OPC_BCLRI_df =3D (0x3 << 23) | OPC_MSA_BIT_09, - OPC_SRLRI_df =3D (0x3 << 23) | OPC_MSA_BIT_0A, - OPC_BSETI_df =3D (0x4 << 23) | OPC_MSA_BIT_09, - OPC_BNEGI_df =3D (0x5 << 23) | OPC_MSA_BIT_09, - OPC_BINSLI_df =3D (0x6 << 23) | OPC_MSA_BIT_09, - OPC_BINSRI_df =3D (0x7 << 23) | OPC_MSA_BIT_09, -}; - - /* * * AN OVERVIEW OF MXU EXTENSION INSTRUCTION SET @@ -2506,25 +2272,6 @@ static const char * const fregnames[] =3D { "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", }; =20 -static const char * const msaregnames[] =3D { - "w0.d0", "w0.d1", "w1.d0", "w1.d1", - "w2.d0", "w2.d1", "w3.d0", "w3.d1", - "w4.d0", "w4.d1", "w5.d0", "w5.d1", - "w6.d0", "w6.d1", "w7.d0", "w7.d1", - "w8.d0", "w8.d1", "w9.d0", "w9.d1", - "w10.d0", "w10.d1", "w11.d0", "w11.d1", - "w12.d0", "w12.d1", "w13.d0", "w13.d1", - "w14.d0", "w14.d1", "w15.d0", "w15.d1", - "w16.d0", "w16.d1", "w17.d0", "w17.d1", - "w18.d0", "w18.d1", "w19.d0", "w19.d1", - "w20.d0", "w20.d1", "w21.d0", "w21.d1", - "w22.d0", "w22.d1", "w23.d0", "w23.d1", - "w24.d0", "w24.d1", "w25.d0", "w25.d1", - "w26.d0", "w26.d1", "w27.d0", "w27.d1", - "w28.d0", "w28.d1", "w29.d0", "w29.d1", - "w30.d0", "w30.d1", "w31.d0", "w31.d1", -}; - #if !defined(TARGET_MIPS64) static const char * const mxuregnames[] =3D { "XR1", "XR2", "XR3", "XR4", "XR5", "XR6", "XR7", "XR8", @@ -28558,1983 +28305,6 @@ static void decode_opc_special3(CPUMIPSState *en= v, DisasContext *ctx) } } =20 -/* MIPS SIMD Architecture (MSA) */ -static inline int check_msa_access(DisasContext *ctx) -{ - if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) && - !(ctx->hflags & MIPS_HFLAG_F64))) { - gen_reserved_instruction(ctx); - return 0; - } - - if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) { - generate_exception_end(ctx, EXCP_MSADIS); - return 0; - } - return 1; -} - -static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt) -{ - /* generates tcg ops to check if any element is 0 */ - /* Note this function only works with MSA_WRLEN =3D 128 */ - uint64_t eval_zero_or_big =3D 0; - uint64_t eval_big =3D 0; - TCGv_i64 t0 =3D tcg_temp_new_i64(); - TCGv_i64 t1 =3D tcg_temp_new_i64(); - switch (df) { - case DF_BYTE: - eval_zero_or_big =3D 0x0101010101010101ULL; - eval_big =3D 0x8080808080808080ULL; - break; - case DF_HALF: - eval_zero_or_big =3D 0x0001000100010001ULL; - eval_big =3D 0x8000800080008000ULL; - break; - case DF_WORD: - eval_zero_or_big =3D 0x0000000100000001ULL; - eval_big =3D 0x8000000080000000ULL; - break; - case DF_DOUBLE: - eval_zero_or_big =3D 0x0000000000000001ULL; - eval_big =3D 0x8000000000000000ULL; - break; - } - tcg_gen_subi_i64(t0, msa_wr_d[wt << 1], eval_zero_or_big); - tcg_gen_andc_i64(t0, t0, msa_wr_d[wt << 1]); - tcg_gen_andi_i64(t0, t0, eval_big); - tcg_gen_subi_i64(t1, msa_wr_d[(wt << 1) + 1], eval_zero_or_big); - tcg_gen_andc_i64(t1, t1, msa_wr_d[(wt << 1) + 1]); - tcg_gen_andi_i64(t1, t1, eval_big); - tcg_gen_or_i64(t0, t0, t1); - /* if all bits are zero then all elements are not zero */ - /* if some bit is non-zero then some element is zero */ - tcg_gen_setcondi_i64(TCG_COND_NE, t0, t0, 0); - tcg_gen_trunc_i64_tl(tresult, t0); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); -} - -static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond) -{ - TCGv_i64 t0; - - check_msa_access(ctx); - - if (ctx->hflags & MIPS_HFLAG_BMASK) { - gen_reserved_instruction(ctx); - return true; - } - t0 =3D tcg_temp_new_i64(); - tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]); - tcg_gen_setcondi_i64(cond, t0, t0, 0); - tcg_gen_trunc_i64_tl(bcond, t0); - tcg_temp_free_i64(t0); - - ctx->btarget =3D ctx->base.pc_next + (s16 << 2) + 4; - - ctx->hflags |=3D MIPS_HFLAG_BC; - ctx->hflags |=3D MIPS_HFLAG_BDS32; - - return true; -} - -static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool i= f_not) -{ - check_msa_access(ctx); - - if (ctx->hflags & MIPS_HFLAG_BMASK) { - gen_reserved_instruction(ctx); - return true; - } - - gen_check_zero_element(bcond, df, wt); - if (if_not) { - tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0); - } - - ctx->btarget =3D ctx->base.pc_next + (s16 << 2) + 4; - ctx->hflags |=3D MIPS_HFLAG_BC; - ctx->hflags |=3D MIPS_HFLAG_BDS32; - - return true; -} - -void gen_msa_branch(DisasContext *ctx, uint32_t op1) -{ - uint8_t df =3D (ctx->opcode >> 21) & 0x3; - uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; - int64_t s16 =3D (int16_t)ctx->opcode; - - switch (op1) { - case OPC_BZ_V: - case OPC_BNZ_V: - gen_msa_BxZ_V(ctx, wt, s16, (op1 =3D=3D OPC_BZ_V) ? - TCG_COND_EQ : TCG_COND_NE); - break; - case OPC_BZ_B: - case OPC_BZ_H: - case OPC_BZ_W: - case OPC_BZ_D: - gen_msa_BxZ(ctx, df, wt, s16, false); - break; - case OPC_BNZ_B: - case OPC_BNZ_H: - case OPC_BNZ_W: - case OPC_BNZ_D: - gen_msa_BxZ(ctx, df, wt, s16, true); - break; - } -} - -static void gen_msa_i8(DisasContext *ctx) -{ -#define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24))) - uint8_t i8 =3D (ctx->opcode >> 16) & 0xff; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 ti8 =3D tcg_const_i32(i8); - - switch (MASK_MSA_I8(ctx->opcode)) { - case OPC_ANDI_B: - gen_helper_msa_andi_b(cpu_env, twd, tws, ti8); - break; - case OPC_ORI_B: - gen_helper_msa_ori_b(cpu_env, twd, tws, ti8); - break; - case OPC_NORI_B: - gen_helper_msa_nori_b(cpu_env, twd, tws, ti8); - break; - case OPC_XORI_B: - gen_helper_msa_xori_b(cpu_env, twd, tws, ti8); - break; - case OPC_BMNZI_B: - gen_helper_msa_bmnzi_b(cpu_env, twd, tws, ti8); - break; - case OPC_BMZI_B: - gen_helper_msa_bmzi_b(cpu_env, twd, tws, ti8); - break; - case OPC_BSELI_B: - gen_helper_msa_bseli_b(cpu_env, twd, tws, ti8); - break; - case OPC_SHF_B: - case OPC_SHF_H: - case OPC_SHF_W: - { - uint8_t df =3D (ctx->opcode >> 24) & 0x3; - if (df =3D=3D DF_DOUBLE) { - gen_reserved_instruction(ctx); - } else { - TCGv_i32 tdf =3D tcg_const_i32(df); - gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, ti8); - tcg_temp_free_i32(tdf); - } - } - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } - - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(ti8); -} - -static void gen_msa_i5(DisasContext *ctx) -{ -#define MASK_MSA_I5(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) - uint8_t df =3D (ctx->opcode >> 21) & 0x3; - int8_t s5 =3D (int8_t) sextract32(ctx->opcode, 16, 5); - uint8_t u5 =3D (ctx->opcode >> 16) & 0x1f; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - - TCGv_i32 tdf =3D tcg_const_i32(df); - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 timm =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(timm, u5); - - switch (MASK_MSA_I5(ctx->opcode)) { - case OPC_ADDVI_df: - gen_helper_msa_addvi_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_SUBVI_df: - gen_helper_msa_subvi_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_MAXI_S_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_maxi_s_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_MAXI_U_df: - gen_helper_msa_maxi_u_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_MINI_S_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_mini_s_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_MINI_U_df: - gen_helper_msa_mini_u_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CEQI_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_ceqi_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CLTI_S_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_clti_s_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CLTI_U_df: - gen_helper_msa_clti_u_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CLEI_S_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_clei_s_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CLEI_U_df: - gen_helper_msa_clei_u_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_LDI_df: - { - int32_t s10 =3D sextract32(ctx->opcode, 11, 10); - tcg_gen_movi_i32(timm, s10); - gen_helper_msa_ldi_df(cpu_env, tdf, twd, timm); - } - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } - - tcg_temp_free_i32(tdf); - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(timm); -} - -static void gen_msa_bit(DisasContext *ctx) -{ -#define MASK_MSA_BIT(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) - uint8_t dfm =3D (ctx->opcode >> 16) & 0x7f; - uint32_t df =3D 0, m =3D 0; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - - TCGv_i32 tdf; - TCGv_i32 tm; - TCGv_i32 twd; - TCGv_i32 tws; - - if ((dfm & 0x40) =3D=3D 0x00) { - m =3D dfm & 0x3f; - df =3D DF_DOUBLE; - } else if ((dfm & 0x60) =3D=3D 0x40) { - m =3D dfm & 0x1f; - df =3D DF_WORD; - } else if ((dfm & 0x70) =3D=3D 0x60) { - m =3D dfm & 0x0f; - df =3D DF_HALF; - } else if ((dfm & 0x78) =3D=3D 0x70) { - m =3D dfm & 0x7; - df =3D DF_BYTE; - } else { - gen_reserved_instruction(ctx); - return; - } - - tdf =3D tcg_const_i32(df); - tm =3D tcg_const_i32(m); - twd =3D tcg_const_i32(wd); - tws =3D tcg_const_i32(ws); - - switch (MASK_MSA_BIT(ctx->opcode)) { - case OPC_SLLI_df: - gen_helper_msa_slli_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SRAI_df: - gen_helper_msa_srai_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SRLI_df: - gen_helper_msa_srli_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BCLRI_df: - gen_helper_msa_bclri_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BSETI_df: - gen_helper_msa_bseti_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BNEGI_df: - gen_helper_msa_bnegi_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BINSLI_df: - gen_helper_msa_binsli_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BINSRI_df: - gen_helper_msa_binsri_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SAT_S_df: - gen_helper_msa_sat_s_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SAT_U_df: - gen_helper_msa_sat_u_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SRARI_df: - gen_helper_msa_srari_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SRLRI_df: - gen_helper_msa_srlri_df(cpu_env, tdf, twd, tws, tm); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } - - tcg_temp_free_i32(tdf); - tcg_temp_free_i32(tm); - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); -} - -static void gen_msa_3r(DisasContext *ctx) -{ -#define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) - uint8_t df =3D (ctx->opcode >> 21) & 0x3; - uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - - TCGv_i32 tdf =3D tcg_const_i32(df); - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 twt =3D tcg_const_i32(wt); - - switch (MASK_MSA_3R(ctx->opcode)) { - case OPC_BINSL_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_binsl_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_binsl_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_binsl_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_binsl_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_BINSR_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_binsr_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_binsr_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_binsr_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_binsr_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_BCLR_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_bclr_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_bclr_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_bclr_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_bclr_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_BNEG_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_bneg_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_bneg_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_bneg_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_bneg_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_BSET_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_bset_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_bset_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_bset_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_bset_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ADD_A_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_add_a_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_add_a_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_add_a_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_add_a_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ADDS_A_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_adds_a_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_adds_a_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_adds_a_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_adds_a_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ADDS_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_adds_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_adds_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_adds_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_adds_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ADDS_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_adds_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_adds_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_adds_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_adds_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ADDV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_addv_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_addv_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_addv_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_addv_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_AVE_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ave_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ave_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ave_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ave_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_AVE_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ave_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ave_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ave_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ave_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_AVER_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_aver_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_aver_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_aver_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_aver_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_AVER_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_aver_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_aver_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_aver_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_aver_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_CEQ_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ceq_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ceq_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ceq_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ceq_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_CLE_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_cle_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_cle_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_cle_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_cle_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_CLE_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_cle_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_cle_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_cle_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_cle_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_CLT_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_clt_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_clt_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_clt_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_clt_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_CLT_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_clt_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_clt_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_clt_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_clt_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DIV_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_div_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_div_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_div_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_div_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DIV_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_div_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_div_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_div_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_div_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MAX_A_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_max_a_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_max_a_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_max_a_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_max_a_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MAX_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_max_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_max_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_max_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_max_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MAX_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_max_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_max_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_max_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_max_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MIN_A_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_min_a_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_min_a_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_min_a_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_min_a_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MIN_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_min_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_min_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_min_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_min_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MIN_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_min_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_min_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_min_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_min_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MOD_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_mod_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_mod_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_mod_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_mod_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MOD_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_mod_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_mod_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_mod_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_mod_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MADDV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_maddv_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_maddv_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_maddv_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_maddv_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MSUBV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_msubv_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_msubv_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_msubv_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_msubv_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ASUB_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_asub_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_asub_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_asub_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_asub_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ASUB_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_asub_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_asub_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_asub_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_asub_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ILVEV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ilvev_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ilvev_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ilvev_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ilvev_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ILVOD_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ilvod_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ilvod_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ilvod_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ilvod_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ILVL_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ilvl_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ilvl_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ilvl_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ilvl_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ILVR_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ilvr_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ilvr_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ilvr_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ilvr_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_PCKEV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_pckev_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_pckev_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_pckev_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_pckev_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_PCKOD_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_pckod_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_pckod_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_pckod_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_pckod_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SLL_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_sll_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_sll_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_sll_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_sll_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SRA_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_sra_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_sra_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_sra_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_sra_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SRAR_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_srar_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_srar_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_srar_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_srar_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SRL_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_srl_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_srl_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_srl_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_srl_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SRLR_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_srlr_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_srlr_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_srlr_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_srlr_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SUBS_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_subs_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_subs_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_subs_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_subs_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MULV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_mulv_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_mulv_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_mulv_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_mulv_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SLD_df: - gen_helper_msa_sld_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_VSHF_df: - gen_helper_msa_vshf_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_SUBV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_subv_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_subv_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_subv_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_subv_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SUBS_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_subs_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_subs_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_subs_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_subs_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SPLAT_df: - gen_helper_msa_splat_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_SUBSUS_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_subsus_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_subsus_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_subsus_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_subsus_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SUBSUU_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_subsuu_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_subsuu_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_subsuu_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_subsuu_s_d(cpu_env, twd, tws, twt); - break; - } - break; - - case OPC_DOTP_S_df: - case OPC_DOTP_U_df: - case OPC_DPADD_S_df: - case OPC_DPADD_U_df: - case OPC_DPSUB_S_df: - case OPC_HADD_S_df: - case OPC_DPSUB_U_df: - case OPC_HADD_U_df: - case OPC_HSUB_S_df: - case OPC_HSUB_U_df: - if (df =3D=3D DF_BYTE) { - gen_reserved_instruction(ctx); - break; - } - switch (MASK_MSA_3R(ctx->opcode)) { - case OPC_HADD_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_hadd_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_hadd_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_hadd_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_HADD_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_hadd_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_hadd_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_hadd_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_HSUB_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_hsub_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_hsub_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_hsub_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_HSUB_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_hsub_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_hsub_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_hsub_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DOTP_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dotp_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dotp_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dotp_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DOTP_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dotp_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dotp_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dotp_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DPADD_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dpadd_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dpadd_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dpadd_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DPADD_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dpadd_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dpadd_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dpadd_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DPSUB_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dpsub_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dpsub_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dpsub_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DPSUB_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dpsub_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dpsub_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dpsub_u_d(cpu_env, twd, tws, twt); - break; - } - break; - } - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(twt); - tcg_temp_free_i32(tdf); -} - -static void gen_msa_elm_3e(DisasContext *ctx) -{ -#define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16))) - uint8_t source =3D (ctx->opcode >> 11) & 0x1f; - uint8_t dest =3D (ctx->opcode >> 6) & 0x1f; - TCGv telm =3D tcg_temp_new(); - TCGv_i32 tsr =3D tcg_const_i32(source); - TCGv_i32 tdt =3D tcg_const_i32(dest); - - switch (MASK_MSA_ELM_DF3E(ctx->opcode)) { - case OPC_CTCMSA: - gen_load_gpr(telm, source); - gen_helper_msa_ctcmsa(cpu_env, telm, tdt); - break; - case OPC_CFCMSA: - gen_helper_msa_cfcmsa(telm, cpu_env, tsr); - gen_store_gpr(telm, dest); - break; - case OPC_MOVE_V: - gen_helper_msa_move_v(cpu_env, tdt, tsr); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } - - tcg_temp_free(telm); - tcg_temp_free_i32(tdt); - tcg_temp_free_i32(tsr); -} - -static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n) -{ -#define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tn =3D tcg_const_i32(n); - TCGv_i32 tdf =3D tcg_const_i32(df); - - switch (MASK_MSA_ELM(ctx->opcode)) { - case OPC_SLDI_df: - gen_helper_msa_sldi_df(cpu_env, tdf, twd, tws, tn); - break; - case OPC_SPLATI_df: - gen_helper_msa_splati_df(cpu_env, tdf, twd, tws, tn); - break; - case OPC_INSVE_df: - gen_helper_msa_insve_df(cpu_env, tdf, twd, tws, tn); - break; - case OPC_COPY_S_df: - case OPC_COPY_U_df: - case OPC_INSERT_df: -#if !defined(TARGET_MIPS64) - /* Double format valid only for MIPS64 */ - if (df =3D=3D DF_DOUBLE) { - gen_reserved_instruction(ctx); - break; - } - if ((MASK_MSA_ELM(ctx->opcode) =3D=3D OPC_COPY_U_df) && - (df =3D=3D DF_WORD)) { - gen_reserved_instruction(ctx); - break; - } -#endif - switch (MASK_MSA_ELM(ctx->opcode)) { - case OPC_COPY_S_df: - if (likely(wd !=3D 0)) { - switch (df) { - case DF_BYTE: - gen_helper_msa_copy_s_b(cpu_env, twd, tws, tn); - break; - case DF_HALF: - gen_helper_msa_copy_s_h(cpu_env, twd, tws, tn); - break; - case DF_WORD: - gen_helper_msa_copy_s_w(cpu_env, twd, tws, tn); - break; -#if defined(TARGET_MIPS64) - case DF_DOUBLE: - gen_helper_msa_copy_s_d(cpu_env, twd, tws, tn); - break; -#endif - default: - assert(0); - } - } - break; - case OPC_COPY_U_df: - if (likely(wd !=3D 0)) { - switch (df) { - case DF_BYTE: - gen_helper_msa_copy_u_b(cpu_env, twd, tws, tn); - break; - case DF_HALF: - gen_helper_msa_copy_u_h(cpu_env, twd, tws, tn); - break; -#if defined(TARGET_MIPS64) - case DF_WORD: - gen_helper_msa_copy_u_w(cpu_env, twd, tws, tn); - break; -#endif - default: - assert(0); - } - } - break; - case OPC_INSERT_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_insert_b(cpu_env, twd, tws, tn); - break; - case DF_HALF: - gen_helper_msa_insert_h(cpu_env, twd, tws, tn); - break; - case DF_WORD: - gen_helper_msa_insert_w(cpu_env, twd, tws, tn); - break; -#if defined(TARGET_MIPS64) - case DF_DOUBLE: - gen_helper_msa_insert_d(cpu_env, twd, tws, tn); - break; -#endif - default: - assert(0); - } - break; - } - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - } - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(tn); - tcg_temp_free_i32(tdf); -} - -static void gen_msa_elm(DisasContext *ctx) -{ - uint8_t dfn =3D (ctx->opcode >> 16) & 0x3f; - uint32_t df =3D 0, n =3D 0; - - if ((dfn & 0x30) =3D=3D 0x00) { - n =3D dfn & 0x0f; - df =3D DF_BYTE; - } else if ((dfn & 0x38) =3D=3D 0x20) { - n =3D dfn & 0x07; - df =3D DF_HALF; - } else if ((dfn & 0x3c) =3D=3D 0x30) { - n =3D dfn & 0x03; - df =3D DF_WORD; - } else if ((dfn & 0x3e) =3D=3D 0x38) { - n =3D dfn & 0x01; - df =3D DF_DOUBLE; - } else if (dfn =3D=3D 0x3E) { - /* CTCMSA, CFCMSA, MOVE.V */ - gen_msa_elm_3e(ctx); - return; - } else { - gen_reserved_instruction(ctx); - return; - } - - gen_msa_elm_df(ctx, df, n); -} - -static void gen_msa_3rf(DisasContext *ctx) -{ -#define MASK_MSA_3RF(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) - uint8_t df =3D (ctx->opcode >> 21) & 0x1; - uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 twt =3D tcg_const_i32(wt); - TCGv_i32 tdf =3D tcg_temp_new_i32(); - - /* adjust df value for floating-point instruction */ - tcg_gen_movi_i32(tdf, df + 2); - - switch (MASK_MSA_3RF(ctx->opcode)) { - case OPC_FCAF_df: - gen_helper_msa_fcaf_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FADD_df: - gen_helper_msa_fadd_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCUN_df: - gen_helper_msa_fcun_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSUB_df: - gen_helper_msa_fsub_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCOR_df: - gen_helper_msa_fcor_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCEQ_df: - gen_helper_msa_fceq_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMUL_df: - gen_helper_msa_fmul_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCUNE_df: - gen_helper_msa_fcune_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCUEQ_df: - gen_helper_msa_fcueq_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FDIV_df: - gen_helper_msa_fdiv_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCNE_df: - gen_helper_msa_fcne_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCLT_df: - gen_helper_msa_fclt_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMADD_df: - gen_helper_msa_fmadd_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_MUL_Q_df: - tcg_gen_movi_i32(tdf, df + 1); - gen_helper_msa_mul_q_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCULT_df: - gen_helper_msa_fcult_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMSUB_df: - gen_helper_msa_fmsub_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_MADD_Q_df: - tcg_gen_movi_i32(tdf, df + 1); - gen_helper_msa_madd_q_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCLE_df: - gen_helper_msa_fcle_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_MSUB_Q_df: - tcg_gen_movi_i32(tdf, df + 1); - gen_helper_msa_msub_q_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCULE_df: - gen_helper_msa_fcule_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FEXP2_df: - gen_helper_msa_fexp2_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSAF_df: - gen_helper_msa_fsaf_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FEXDO_df: - gen_helper_msa_fexdo_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSUN_df: - gen_helper_msa_fsun_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSOR_df: - gen_helper_msa_fsor_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSEQ_df: - gen_helper_msa_fseq_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FTQ_df: - gen_helper_msa_ftq_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSUNE_df: - gen_helper_msa_fsune_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSUEQ_df: - gen_helper_msa_fsueq_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSNE_df: - gen_helper_msa_fsne_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSLT_df: - gen_helper_msa_fslt_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMIN_df: - gen_helper_msa_fmin_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_MULR_Q_df: - tcg_gen_movi_i32(tdf, df + 1); - gen_helper_msa_mulr_q_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSULT_df: - gen_helper_msa_fsult_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMIN_A_df: - gen_helper_msa_fmin_a_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_MADDR_Q_df: - tcg_gen_movi_i32(tdf, df + 1); - gen_helper_msa_maddr_q_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSLE_df: - gen_helper_msa_fsle_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMAX_df: - gen_helper_msa_fmax_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_MSUBR_Q_df: - tcg_gen_movi_i32(tdf, df + 1); - gen_helper_msa_msubr_q_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSULE_df: - gen_helper_msa_fsule_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMAX_A_df: - gen_helper_msa_fmax_a_df(cpu_env, tdf, twd, tws, twt); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } - - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(twt); - tcg_temp_free_i32(tdf); -} - -static void gen_msa_2r(DisasContext *ctx) -{ -#define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \ - (op & (0x7 << 18))) - uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - uint8_t df =3D (ctx->opcode >> 16) & 0x3; - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 twt =3D tcg_const_i32(wt); - TCGv_i32 tdf =3D tcg_const_i32(df); - - switch (MASK_MSA_2R(ctx->opcode)) { - case OPC_FILL_df: -#if !defined(TARGET_MIPS64) - /* Double format valid only for MIPS64 */ - if (df =3D=3D DF_DOUBLE) { - gen_reserved_instruction(ctx); - break; - } -#endif - gen_helper_msa_fill_df(cpu_env, tdf, twd, tws); /* trs */ - break; - case OPC_NLOC_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_nloc_b(cpu_env, twd, tws); - break; - case DF_HALF: - gen_helper_msa_nloc_h(cpu_env, twd, tws); - break; - case DF_WORD: - gen_helper_msa_nloc_w(cpu_env, twd, tws); - break; - case DF_DOUBLE: - gen_helper_msa_nloc_d(cpu_env, twd, tws); - break; - } - break; - case OPC_NLZC_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_nlzc_b(cpu_env, twd, tws); - break; - case DF_HALF: - gen_helper_msa_nlzc_h(cpu_env, twd, tws); - break; - case DF_WORD: - gen_helper_msa_nlzc_w(cpu_env, twd, tws); - break; - case DF_DOUBLE: - gen_helper_msa_nlzc_d(cpu_env, twd, tws); - break; - } - break; - case OPC_PCNT_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_pcnt_b(cpu_env, twd, tws); - break; - case DF_HALF: - gen_helper_msa_pcnt_h(cpu_env, twd, tws); - break; - case DF_WORD: - gen_helper_msa_pcnt_w(cpu_env, twd, tws); - break; - case DF_DOUBLE: - gen_helper_msa_pcnt_d(cpu_env, twd, tws); - break; - } - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } - - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(twt); - tcg_temp_free_i32(tdf); -} - -static void gen_msa_2rf(DisasContext *ctx) -{ -#define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \ - (op & (0xf << 17))) - uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - uint8_t df =3D (ctx->opcode >> 16) & 0x1; - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 twt =3D tcg_const_i32(wt); - /* adjust df value for floating-point instruction */ - TCGv_i32 tdf =3D tcg_const_i32(df + 2); - - switch (MASK_MSA_2RF(ctx->opcode)) { - case OPC_FCLASS_df: - gen_helper_msa_fclass_df(cpu_env, tdf, twd, tws); - break; - case OPC_FTRUNC_S_df: - gen_helper_msa_ftrunc_s_df(cpu_env, tdf, twd, tws); - break; - case OPC_FTRUNC_U_df: - gen_helper_msa_ftrunc_u_df(cpu_env, tdf, twd, tws); - break; - case OPC_FSQRT_df: - gen_helper_msa_fsqrt_df(cpu_env, tdf, twd, tws); - break; - case OPC_FRSQRT_df: - gen_helper_msa_frsqrt_df(cpu_env, tdf, twd, tws); - break; - case OPC_FRCP_df: - gen_helper_msa_frcp_df(cpu_env, tdf, twd, tws); - break; - case OPC_FRINT_df: - gen_helper_msa_frint_df(cpu_env, tdf, twd, tws); - break; - case OPC_FLOG2_df: - gen_helper_msa_flog2_df(cpu_env, tdf, twd, tws); - break; - case OPC_FEXUPL_df: - gen_helper_msa_fexupl_df(cpu_env, tdf, twd, tws); - break; - case OPC_FEXUPR_df: - gen_helper_msa_fexupr_df(cpu_env, tdf, twd, tws); - break; - case OPC_FFQL_df: - gen_helper_msa_ffql_df(cpu_env, tdf, twd, tws); - break; - case OPC_FFQR_df: - gen_helper_msa_ffqr_df(cpu_env, tdf, twd, tws); - break; - case OPC_FTINT_S_df: - gen_helper_msa_ftint_s_df(cpu_env, tdf, twd, tws); - break; - case OPC_FTINT_U_df: - gen_helper_msa_ftint_u_df(cpu_env, tdf, twd, tws); - break; - case OPC_FFINT_S_df: - gen_helper_msa_ffint_s_df(cpu_env, tdf, twd, tws); - break; - case OPC_FFINT_U_df: - gen_helper_msa_ffint_u_df(cpu_env, tdf, twd, tws); - break; - } - - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(twt); - tcg_temp_free_i32(tdf); -} - -static void gen_msa_vec_v(DisasContext *ctx) -{ -#define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21))) - uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 twt =3D tcg_const_i32(wt); - - switch (MASK_MSA_VEC(ctx->opcode)) { - case OPC_AND_V: - gen_helper_msa_and_v(cpu_env, twd, tws, twt); - break; - case OPC_OR_V: - gen_helper_msa_or_v(cpu_env, twd, tws, twt); - break; - case OPC_NOR_V: - gen_helper_msa_nor_v(cpu_env, twd, tws, twt); - break; - case OPC_XOR_V: - gen_helper_msa_xor_v(cpu_env, twd, tws, twt); - break; - case OPC_BMNZ_V: - gen_helper_msa_bmnz_v(cpu_env, twd, tws, twt); - break; - case OPC_BMZ_V: - gen_helper_msa_bmz_v(cpu_env, twd, tws, twt); - break; - case OPC_BSEL_V: - gen_helper_msa_bsel_v(cpu_env, twd, tws, twt); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } - - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(twt); -} - -static void gen_msa_vec(DisasContext *ctx) -{ - switch (MASK_MSA_VEC(ctx->opcode)) { - case OPC_AND_V: - case OPC_OR_V: - case OPC_NOR_V: - case OPC_XOR_V: - case OPC_BMNZ_V: - case OPC_BMZ_V: - case OPC_BSEL_V: - gen_msa_vec_v(ctx); - break; - case OPC_MSA_2R: - gen_msa_2r(ctx); - break; - case OPC_MSA_2RF: - gen_msa_2rf(ctx); - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } -} - -void gen_msa(DisasContext *ctx) -{ - uint32_t opcode =3D ctx->opcode; - - check_msa_access(ctx); - - switch (MASK_MSA_MINOR(opcode)) { - case OPC_MSA_I8_00: - case OPC_MSA_I8_01: - case OPC_MSA_I8_02: - gen_msa_i8(ctx); - break; - case OPC_MSA_I5_06: - case OPC_MSA_I5_07: - gen_msa_i5(ctx); - break; - case OPC_MSA_BIT_09: - case OPC_MSA_BIT_0A: - gen_msa_bit(ctx); - break; - case OPC_MSA_3R_0D: - case OPC_MSA_3R_0E: - case OPC_MSA_3R_0F: - case OPC_MSA_3R_10: - case OPC_MSA_3R_11: - case OPC_MSA_3R_12: - case OPC_MSA_3R_13: - case OPC_MSA_3R_14: - case OPC_MSA_3R_15: - gen_msa_3r(ctx); - break; - case OPC_MSA_ELM: - gen_msa_elm(ctx); - break; - case OPC_MSA_3RF_1A: - case OPC_MSA_3RF_1B: - case OPC_MSA_3RF_1C: - gen_msa_3rf(ctx); - break; - case OPC_MSA_VEC: - gen_msa_vec(ctx); - break; - case OPC_LD_B: - case OPC_LD_H: - case OPC_LD_W: - case OPC_LD_D: - case OPC_ST_B: - case OPC_ST_H: - case OPC_ST_W: - case OPC_ST_D: - { - int32_t s10 =3D sextract32(ctx->opcode, 16, 10); - uint8_t rs =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - uint8_t df =3D (ctx->opcode >> 0) & 0x3; - - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv taddr =3D tcg_temp_new(); - gen_base_offset_addr(ctx, taddr, rs, s10 << df); - - switch (MASK_MSA_MINOR(opcode)) { - case OPC_LD_B: - gen_helper_msa_ld_b(cpu_env, twd, taddr); - break; - case OPC_LD_H: - gen_helper_msa_ld_h(cpu_env, twd, taddr); - break; - case OPC_LD_W: - gen_helper_msa_ld_w(cpu_env, twd, taddr); - break; - case OPC_LD_D: - gen_helper_msa_ld_d(cpu_env, twd, taddr); - break; - case OPC_ST_B: - gen_helper_msa_st_b(cpu_env, twd, taddr); - break; - case OPC_ST_H: - gen_helper_msa_st_h(cpu_env, twd, taddr); - break; - case OPC_ST_W: - gen_helper_msa_st_w(cpu_env, twd, taddr); - break; - case OPC_ST_D: - gen_helper_msa_st_d(cpu_env, twd, taddr); - break; - } - - tcg_temp_free_i32(twd); - tcg_temp_free(taddr); - } - break; - default: - MIPS_INVAL("MSA instruction"); - gen_reserved_instruction(ctx); - break; - } - -} - static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) { int32_t offset; @@ -31576,24 +29346,6 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, in= t flags) } } =20 -void msa_translate_init(void) -{ - int i; - - for (i =3D 0; i < 32; i++) { - int off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); - - /* - * The MSA vector registers are mapped on the - * scalar floating-point unit (FPU) registers. - */ - msa_wr_d[i * 2] =3D fpu_f64[i]; - off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); - msa_wr_d[i * 2 + 1] =3D - tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1= ]); - } -} - void mips_tcg_init(void) { int i; diff --git a/target/mips/meson.build b/target/mips/meson.build index 05ed33b75ce..41c3fe7c5bb 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -11,6 +11,7 @@ 'mod-msa_helper.c', 'tlb_helper.c', 'translate.c', + 'mod-msa_translate.c', )) mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 --=20 2.26.2 From nobody Tue May 21 12:06:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id k3sm6045015eds.87.2020.12.15.14.59.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 14:59:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ugX7vu8E1u5hECC/REMJKzNtvhnIJCt4SGmKDATm7G0=; b=B19fvyYF31auU1m7HeEgEY4427wbbGjGtpQR9PZ8ScXLyvFekkxTe98jsbXiPEJLf9 MlP/1oUignkLt8kCih3uMMxB/GLcXfeuRzsQggqQsAb2/I/AtD8w+o5EVy38yOFtN2Yg uXqmY7eXMkhu5BcRiYyCJTjUoYXxSOSCRzGOJ04Y7KB48RP9vl9cEEOpasi8UZ6d7U65 ogPx70l+fFIfRrnyPE0/7R9iAwigWInFpfo1b/r3KjUGhSbgQRDYqsYuYn4P4ak7xxT9 gBZULq/2huNepteDMonXevcNmRN/mGT86c6LEUsM+Cpes2J/maQ1op3iVOl9oMY5U9Lj yQUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ugX7vu8E1u5hECC/REMJKzNtvhnIJCt4SGmKDATm7G0=; b=D0NhMIJj/iR+kA6BDCyHMpW7sBqofH1QpaixKVm77e3Lxm3vrQ2lKlPMnbwUWyIIa8 b4VByWbBkdtKQ1w+RIqKMcmRZn1m59UCSyKptvIdWKMaH5rp3RQtbwpaHyvNba5hN5a6 eHQ9jFfM97TnqKYEv45QiZZrGL5iDZDY36ZppRcwEc5MAbzGOf/ami5aJHcENrcd3f66 VUcsFvsutHhLVB+8WKpQDpA9XRwl2iRDXuXQjPQxGZdMfGgimzIjU1/pVq0fe+HlnsOt xYP6GMNGiN2SCW/0SRJZTzBQm7n65DT3q79cF2gJpFY5tIdJQFmalM9PwLoDHYw67vYe rQ0g== X-Gm-Message-State: AOAM532k1r9sQCQ4JSKQcnYixV/V1Jgzw3LQV+EuALo8vRBEWUSxWqEb OTmb9V+D5lP2IhTAzKT47u8= X-Google-Smtp-Source: ABdhPJwNLlkALJwGE7A5peSMRHL5rEpwGLTnyYq766LxGTdxyKRhuasqM41nOZ1u6Wg4GyjZOiq6+A== X-Received: by 2002:a17:906:c254:: with SMTP id bl20mr7663991ejb.336.1608073187404; Tue, 15 Dec 2020 14:59:47 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aleksandar Rikalo , Paolo Bonzini , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen Subject: [PATCH v2 19/24] target/mips: Introduce decode tree bindings for MSA opcodes Date: Tue, 15 Dec 2020 23:57:52 +0100 Message-Id: <20201215225757.764263-20-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215225757.764263-1-f4bug@amsat.org> References: <20201215225757.764263-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Introduce the 'mod-msa32' decodetree config for the 32-bit MSA ASE. We decode the branch instructions, and all instructions based on the MSA opcode. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/translate.h | 3 +++ target/mips/mod-msa32.decode | 24 +++++++++++++++++++++ target/mips/mod-msa_translate.c | 37 ++++++++++++++++++++++++++++++++- target/mips/translate.c | 1 - target/mips/meson.build | 5 +++++ 5 files changed, 68 insertions(+), 2 deletions(-) create mode 100644 target/mips/mod-msa32.decode diff --git a/target/mips/translate.h b/target/mips/translate.h index 77dfec98792..7ca92bd6beb 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -166,4 +166,7 @@ void msa_translate_init(void); void gen_msa(DisasContext *ctx); void gen_msa_branch(DisasContext *ctx, uint32_t op1); =20 +/* decodetree generated */ +bool decode_ase_msa(DisasContext *ctx, uint32_t insn); + #endif diff --git a/target/mips/mod-msa32.decode b/target/mips/mod-msa32.decode new file mode 100644 index 00000000000..d69675132b8 --- /dev/null +++ b/target/mips/mod-msa32.decode @@ -0,0 +1,24 @@ +# MIPS SIMD Architecture Module instruction set +# +# Copyright (C) 2020 Philippe Mathieu-Daud=C3=A9 +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: +# MIPS Architecture for Programmers Volume IV-j +# The MIPS32 SIMD Architecture Module, Revision 1.12 +# (Document Number: MD00866-2B-MSA32-AFP-01.12) +# + +&msa_bz df wt s16 + +@bz ...... ... .. wt:5 s16:16 &msa_bz df=3D3 +@bz_df ...... ... df:2 wt:5 s16:16 &msa_bz + +BZ_V 010001 01011 ..... ................ @bz +BNZ_V 010001 01111 ..... ................ @bz + +BZ_x 010001 110 .. ..... ................ @bz_df +BNZ_x 010001 111 .. ..... ................ @bz_df + +MSA 011110 -------------------------- diff --git a/target/mips/mod-msa_translate.c b/target/mips/mod-msa_translat= e.c index 63feedcb7ca..d0e393a6831 100644 --- a/target/mips/mod-msa_translate.c +++ b/target/mips/mod-msa_translate.c @@ -6,6 +6,7 @@ * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support) + * Copyright (c) 2020 Philippe Mathieu-Daud=C3=A9 * * SPDX-License-Identifier: LGPL-2.1-or-later */ @@ -13,10 +14,12 @@ #include "tcg/tcg-op.h" #include "exec/helper-gen.h" #include "translate.h" -#include "fpu_translate.h" #include "fpu_helper.h" #include "internal.h" =20 +/* Include the auto-generated decoder. */ +#include "decode-mod-msa32.c.inc" + #define OPC_MSA (0x1E << 26) =20 #define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) @@ -370,6 +373,16 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, i= nt s16, TCGCond cond) return true; } =20 +static bool trans_BZ_V(DisasContext *ctx, arg_msa_bz *a) +{ + return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_EQ); +} + +static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a) +{ + return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_NE); +} + static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool i= f_not) { check_msa_access(ctx); @@ -391,6 +404,16 @@ static bool gen_msa_BxZ(DisasContext *ctx, int df, int= wt, int s16, bool if_not) return true; } =20 +static bool trans_BZ_x(DisasContext *ctx, arg_msa_bz *a) +{ + return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, false); +} + +static bool trans_BNZ_x(DisasContext *ctx, arg_msa_bz *a) +{ + return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, true); +} + void gen_msa_branch(DisasContext *ctx, uint32_t op1) { uint8_t df =3D (ctx->opcode >> 21) & 0x3; @@ -2264,3 +2287,15 @@ void gen_msa(DisasContext *ctx) break; } } + +static bool trans_MSA(DisasContext *ctx, arg_MSA *a) +{ + gen_msa(ctx); + + return true; +} + +bool decode_ase_msa(DisasContext *ctx, uint32_t insn) +{ + return decode_msa32(ctx, insn); +} diff --git a/target/mips/translate.c b/target/mips/translate.c index 1e20d426388..f36255f073a 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2190,7 +2190,6 @@ static TCGv cpu_lladdr, cpu_llval; static TCGv_i32 hflags; TCGv_i32 fpu_fcr0, fpu_fcr31; TCGv_i64 fpu_f64[32]; -static TCGv_i64 msa_wr_d[64]; =20 #if defined(TARGET_MIPS64) /* Upper halves of R5900's 128-bit registers: MMRs (multimedia registers) = */ diff --git a/target/mips/meson.build b/target/mips/meson.build index 41c3fe7c5bb..5ccc9ddc6b8 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -1,4 +1,9 @@ +gen =3D [ + decodetree.process('mod-msa32.decode', extra_args: [ '--static-decode=3D= decode_msa32' ]), +] + mips_ss =3D ss.source_set() +mips_ss.add(gen) mips_ss.add(files( 'cpu.c', 'gdbstub.c', --=20 2.26.2 From nobody Tue May 21 12:06:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.46 as permitted sender) client-ip=209.85.208.46; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id w20sm19937008edi.12.2020.12.15.14.59.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 14:59:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YiCWC0K0BpPtxSsBugnUMdi5L646sG0eSz98PXvsG6o=; b=Kf4y9LhBkewDzJQ+65mUKnwTqwCVxZRL88BKSVzrUSgOprshgYVL5eFH6g7OJYXUii fsu1oUPyCvQHTMaQmfRjkWHzm/8CnJmysMv5jgPr16OrKxNK7bkERELxLPbb1mqVnkAJ /vTQpRTycqWWjr3RvNCqgEl7iN+2S2jaMheJtW8LtCfwcV3OiA7VuQztp8YUXhMubLul /dNdrQgqKr6R09ubRN7DdPH8Y+4y+KnzzHYOZOqg9PjMp7nneynAUjGz453GDBTSCa4g d4eq8hr4dp9DAbKzbXFv56JCI4iou7c73XU8Yht7scPfQ5C32pgas6Fc/6j4j+M/NUo0 iRfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=YiCWC0K0BpPtxSsBugnUMdi5L646sG0eSz98PXvsG6o=; b=kjcxulVPN07QANgVDKk6nhV2w6dMaTOYMkyXBAoFAwIzmMxjiq7coP5yffDh16m8kk iXGUlzoBqu32H/84cdL4tMo2tnsu+UiU+PJQr/NGGDrHFUUNk5Q7FcUdzp5Gxo+ZNi6H KgaQ8kIQYV0WhPx3ubIwCsoDde2J0PO0eD+cgWJc723edUxODdSkJTPFH556f7AAQUeq iHyGZ5puRSbXt/za9eqctRNfzqgHbqbQFzQcqf5wIRjwxq6R0FxOPQKJlTIqAzmhnq2M xLGhRuCz+ziIQnXn1V6Z/fU5hVVavdnBcHOOnFqRi3IjT3NINYWR+2XeQe12Rqp7Z4p/ CdkA== X-Gm-Message-State: AOAM532Pvxy9Y5qUiAZd7LcGfDqHnTzIsgLrRodpm/IyyCUyUKUZx+vE j6p1wXIUj74Nu+A0f7S4ss4+tsgI81zhXA== X-Google-Smtp-Source: ABdhPJy7G+MixB/CP0tzpA6lyu2mwvF/wF9LYIcPPlO3BTa38GHeef+LM0daH+IODqs+NauCk0ysTQ== X-Received: by 2002:a50:bb44:: with SMTP id y62mr31377675ede.103.1608073192913; Tue, 15 Dec 2020 14:59:52 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aleksandar Rikalo , Paolo Bonzini , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen Subject: [PATCH v2 20/24] target/mips: Use decode_ase_msa() generated from decodetree Date: Tue, 15 Dec 2020 23:57:53 +0100 Message-Id: <20201215225757.764263-21-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215225757.764263-1-f4bug@amsat.org> References: <20201215225757.764263-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Now that we can decode the MSA ASE opcodes with decode_msa32(), use it and remove the unreachable code. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/translate.h | 12 ------------ target/mips/mod-msa_translate.c | 29 +---------------------------- target/mips/translate.c | 31 ++++++++++--------------------- 3 files changed, 11 insertions(+), 61 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index 7ca92bd6beb..8d84e0c254d 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -82,8 +82,6 @@ enum { OPC_BC1 =3D (0x08 << 21) | OPC_CP1, /* bc */ OPC_BC1ANY2 =3D (0x09 << 21) | OPC_CP1, OPC_BC1ANY4 =3D (0x0A << 21) | OPC_CP1, - OPC_BZ_V =3D (0x0B << 21) | OPC_CP1, - OPC_BNZ_V =3D (0x0F << 21) | OPC_CP1, OPC_S_FMT =3D (FMT_S << 21) | OPC_CP1, OPC_D_FMT =3D (FMT_D << 21) | OPC_CP1, OPC_E_FMT =3D (FMT_E << 21) | OPC_CP1, @@ -93,14 +91,6 @@ enum { OPC_PS_FMT =3D (FMT_PS << 21) | OPC_CP1, OPC_BC1EQZ =3D (0x09 << 21) | OPC_CP1, OPC_BC1NEZ =3D (0x0D << 21) | OPC_CP1, - OPC_BZ_B =3D (0x18 << 21) | OPC_CP1, - OPC_BZ_H =3D (0x19 << 21) | OPC_CP1, - OPC_BZ_W =3D (0x1A << 21) | OPC_CP1, - OPC_BZ_D =3D (0x1B << 21) | OPC_CP1, - OPC_BNZ_B =3D (0x1C << 21) | OPC_CP1, - OPC_BNZ_H =3D (0x1D << 21) | OPC_CP1, - OPC_BNZ_W =3D (0x1E << 21) | OPC_CP1, - OPC_BNZ_D =3D (0x1F << 21) | OPC_CP1, }; =20 #define MASK_CP1_FUNC(op) (MASK_CP1(op) | (op & 0x3F)) @@ -163,8 +153,6 @@ extern TCGv bcond; =20 /* MSA */ void msa_translate_init(void); -void gen_msa(DisasContext *ctx); -void gen_msa_branch(DisasContext *ctx, uint32_t op1); =20 /* decodetree generated */ bool decode_ase_msa(DisasContext *ctx, uint32_t insn); diff --git a/target/mips/mod-msa_translate.c b/target/mips/mod-msa_translat= e.c index d0e393a6831..d1a8a95e62e 100644 --- a/target/mips/mod-msa_translate.c +++ b/target/mips/mod-msa_translate.c @@ -414,33 +414,6 @@ static bool trans_BNZ_x(DisasContext *ctx, arg_msa_bz = *a) return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, true); } =20 -void gen_msa_branch(DisasContext *ctx, uint32_t op1) -{ - uint8_t df =3D (ctx->opcode >> 21) & 0x3; - uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; - int64_t s16 =3D (int16_t)ctx->opcode; - - switch (op1) { - case OPC_BZ_V: - case OPC_BNZ_V: - gen_msa_BxZ_V(ctx, wt, s16, (op1 =3D=3D OPC_BZ_V) ? - TCG_COND_EQ : TCG_COND_NE); - break; - case OPC_BZ_B: - case OPC_BZ_H: - case OPC_BZ_W: - case OPC_BZ_D: - gen_msa_BxZ(ctx, df, wt, s16, false); - break; - case OPC_BNZ_B: - case OPC_BNZ_H: - case OPC_BNZ_W: - case OPC_BNZ_D: - gen_msa_BxZ(ctx, df, wt, s16, true); - break; - } -} - static void gen_msa_i8(DisasContext *ctx) { #define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24))) @@ -2190,7 +2163,7 @@ static void gen_msa_vec(DisasContext *ctx) } } =20 -void gen_msa(DisasContext *ctx) +static void gen_msa(DisasContext *ctx) { uint32_t opcode =3D ctx->opcode; =20 diff --git a/target/mips/translate.c b/target/mips/translate.c index f36255f073a..2ce3dc10dfb 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -6,6 +6,7 @@ * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support) + * Copyright (c) 2020 Philippe Mathieu-Daud=C3=A9 * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public @@ -135,8 +136,6 @@ enum { OPC_JIALC =3D (0x3E << 26), /* MDMX ASE specific */ OPC_MDMX =3D (0x1E << 26), - /* MSA ASE, same as MDMX */ - OPC_MSA =3D OPC_MDMX, /* Cache and prefetch */ OPC_CACHE =3D (0x2F << 26), OPC_PREF =3D (0x33 << 26), @@ -28828,20 +28827,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, D= isasContext *ctx) } break; } - case OPC_BZ_V: - case OPC_BNZ_V: - case OPC_BZ_B: - case OPC_BZ_H: - case OPC_BZ_W: - case OPC_BZ_D: - case OPC_BNZ_B: - case OPC_BNZ_H: - case OPC_BNZ_W: - case OPC_BNZ_D: - if (ase_msa_available(env)) { - gen_msa_branch(ctx, op1); - break; - } default: MIPS_INVAL("cp1"); gen_reserved_instruction(ctx); @@ -29023,16 +29008,13 @@ static bool decode_opc_legacy(CPUMIPSState *env, = DisasContext *ctx) gen_compute_branch(ctx, op, 4, rs, rt, offset, 4); } break; - case OPC_MSA: /* OPC_MDMX */ + case OPC_MDMX: /* MMI_OPC_LQ */ if (ctx->insn_flags & INSN_R5900) { #if defined(TARGET_MIPS64) - gen_mmi_lq(env, ctx); /* MMI_OPC_LQ */ + gen_mmi_lq(env, ctx); #endif } else { /* MDMX: Not implemented. */ - if (ase_msa_available(env)) { - gen_msa(ctx); - } } break; case OPC_PCREL: @@ -29065,6 +29047,13 @@ static void decode_opc(CPUMIPSState *env, DisasCon= text *ctx) gen_set_label(l1); } =20 + /* Transition to the auto-generated decoder. */ + + /* ISA Extensions */ + if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) { + return; + } + if (!decode_opc_legacy(env, ctx)) { gen_reserved_instruction(ctx); } --=20 2.26.2 From nobody Tue May 21 12:06:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.65 as permitted sender) client-ip=209.85.218.65; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-f65.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.65 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1608073200; cv=none; d=zohomail.com; s=zohoarc; b=MDxypP/lBhz0r7owV1EDYDCSXQglZ83oD4DbhiFD8nMRcSiv7kDlH9LwoODsmcEnq+/2y5qySu1oAsoHDii+SAuZdLzCnENBJNI/bRKD/yjG6QzNyiH8PIUHzkuFkF3kJ2r8QN5m8il9bM3dZwUVslEEq4qeACbG4egO9tJrMLI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608073200; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RTK7vnM8yZ9pd7ko0y63TgIf7i/lwwx22Mz5QVVeyms=; b=J+DRuaV9DkFmQlS5HoM1BvBQNNX+Pd8qijltJiYY1zhdEWZqENac+wlcI5DTftvBH8ZbClHVgHIuxRunAW3dt2K0Nwkf6N8MY1iBo7fXdbh50GWZBuXto5OMooZMvO2rMRsYvELzjp9/FEyRVhVcDgomGXMmXBZ70JfvfKEVyQI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.65 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-ej1-f65.google.com (mail-ej1-f65.google.com [209.85.218.65]) by mx.zohomail.com with SMTPS id 1608073200291537.9471327187241; Tue, 15 Dec 2020 15:00:00 -0800 (PST) Received: by mail-ej1-f65.google.com with SMTP id d17so30060503ejy.9 for ; Tue, 15 Dec 2020 14:59:59 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id g18sm19140308edt.2.2020.12.15.14.59.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 14:59:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RTK7vnM8yZ9pd7ko0y63TgIf7i/lwwx22Mz5QVVeyms=; b=mNDsCxxVkA38BJJ4dFTHZ5i4yiqLD5ltE5zPeBuh79tnEF2Q1mbSTUzlorrcgrk9A/ pQLL5DSdO2USHXfm+rMPndWmabYivHkzMamGvsqtc2lxhnCxAg2upF65GXnjQTKaptwo RX0lyWJiCqzLGi7S8V+Vtz1FT+om9Iqh79ucEfe09h0t5zzYXpbRwhk2jG86ZHkdTW4L fD+Ll5pYJfbqARP7Nmfb9rOsAZSnivQbgiNRLpL93fLX4fTGgcnlHho3iRff/MQi9bHn wTyE3WDjafOG+OpMy+rdkDylSKjpccPFfsAyW0yrnRk+YlAVMbMDJP1CMVglYteA3TRp z53Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=RTK7vnM8yZ9pd7ko0y63TgIf7i/lwwx22Mz5QVVeyms=; b=bt0VZHhHMQuI6XVkk0gWI9oJAjRKulNW6EVdNKcGYhJFka+MPtFGj32FBtjLHsFFGJ Slzw2mqe7+Ai699Rzy+cYcWT6LFwkPmoKtlFDDlvH/Ixpo5JNCuLHFBcQKUpgNzPG6xZ pnBjIFnCB4qo0GdN3rCYeQ899WE+0S9KKiuCQyMoM3i7lgJWlpGVwpV0tu+pgDOR6FAh PKNqWxllzTTpD8IiS2r1xgBf4MBiUUB//9H6MI6X1jhL3RNuOQi2/6MmqiI4/s5daHvA vzbaDOCv05QRqKLb62xHLlImptzz4mxtdPADf48k+cvwnV8rqYD+tzexbyP2k28ULCT9 +YUA== X-Gm-Message-State: AOAM533UIWEhz4I2x7qJajStwWxDswGXu5TKveOX2nbVLhIPTLtTnxGr QitxuY8x1c11+XJntbUQyD0= X-Google-Smtp-Source: ABdhPJx6VLQ5b5Wq+eHCClr3sqEYcaE/VngDekbuTBbX2Bi6JiMo+wLolfnX46abCl0XDrkibiOSdQ== X-Received: by 2002:a17:907:3e85:: with SMTP id hs5mr7927654ejc.548.1608073198420; Tue, 15 Dec 2020 14:59:58 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aleksandar Rikalo , Paolo Bonzini , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen Subject: [PATCH v2 21/24] target/mips: Extract LSA/DLSA translation generators Date: Tue, 15 Dec 2020 23:57:54 +0100 Message-Id: <20201215225757.764263-22-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215225757.764263-1-f4bug@amsat.org> References: <20201215225757.764263-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Extract gen_lsa() from translate.c and explode it as gen_LSA() and gen_DLSA(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/translate.h | 6 ++++ target/mips/translate.c | 35 +++----------------- target/mips/translate_addr_const.c | 52 ++++++++++++++++++++++++++++++ target/mips/meson.build | 1 + 4 files changed, 63 insertions(+), 31 deletions(-) create mode 100644 target/mips/translate_addr_const.c diff --git a/target/mips/translate.h b/target/mips/translate.h index 8d84e0c254d..47129de81d9 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -128,6 +128,12 @@ void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int= reg); void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg); int get_fp_bit(int cc); =20 +/* + * Address Computation and Large Constant Instructions + */ +bool gen_LSA(DisasContext *ctx, int rd, int rt, int rs, int sa); +bool gen_DLSA(DisasContext *ctx, int rd, int rt, int rs, int sa); + extern TCGv cpu_gpr[32], cpu_PC; extern TCGv_i32 fpu_fcr0, fpu_fcr31; extern TCGv_i64 fpu_f64[32]; diff --git a/target/mips/translate.c b/target/mips/translate.c index 2ce3dc10dfb..e0439ba92d8 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -6616,31 +6616,6 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op= 2, int rt, int rd) tcg_temp_free(t0); } =20 -static void gen_lsa(DisasContext *ctx, int opc, int rd, int rs, int rt, - int imm2) -{ - TCGv t0; - TCGv t1; - if (rd =3D=3D 0) { - /* Treat as NOP. */ - return; - } - t0 =3D tcg_temp_new(); - t1 =3D tcg_temp_new(); - gen_load_gpr(t0, rs); - gen_load_gpr(t1, rt); - tcg_gen_shli_tl(t0, t0, imm2 + 1); - tcg_gen_add_tl(cpu_gpr[rd], t0, t1); - if (opc =3D=3D OPC_LSA) { - tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - } - - tcg_temp_free(t1); - tcg_temp_free(t0); - - return; -} - static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs, int rt, int bits) { @@ -16496,8 +16471,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) return; case LSA: check_insn(ctx, ISA_MIPS32R6); - gen_lsa(ctx, OPC_LSA, rd, rs, rt, - extract32(ctx->opcode, 9, 2)); + gen_LSA(ctx, rd, rs, rt, extract32(ctx->opcode, 9, 2)); break; case ALIGN: check_insn(ctx, ISA_MIPS32R6); @@ -21460,8 +21434,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) * amount, meaning that the supported shift values are in * the range 0 to 3 (instead of 1 to 4 in MIPSR6). */ - gen_lsa(ctx, OPC_LSA, rd, rs, rt, - extract32(ctx->opcode, 9, 2) - 1); + gen_LSA(ctx, rd, rs, rt, extract32(ctx->opcode, 9, 2) - 1); break; case NM_EXTW: gen_ext(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 6, 5)); @@ -24347,7 +24320,7 @@ static void decode_opc_special_r6(CPUMIPSState *env= , DisasContext *ctx) op1 =3D MASK_SPECIAL(ctx->opcode); switch (op1) { case OPC_LSA: - gen_lsa(ctx, op1, rd, rs, rt, extract32(ctx->opcode, 6, 2)); + gen_LSA(ctx, rd, rs, rt, extract32(ctx->opcode, 6, 2)); break; case OPC_MULT: case OPC_MULTU: @@ -24401,7 +24374,7 @@ static void decode_opc_special_r6(CPUMIPSState *env= , DisasContext *ctx) #if defined(TARGET_MIPS64) case OPC_DLSA: check_mips_64(ctx); - gen_lsa(ctx, op1, rd, rs, rt, extract32(ctx->opcode, 6, 2)); + gen_DLSA(ctx, rd, rs, rt, extract32(ctx->opcode, 6, 2)); break; case R6_OPC_DCLO: case R6_OPC_DCLZ: diff --git a/target/mips/translate_addr_const.c b/target/mips/translate_add= r_const.c new file mode 100644 index 00000000000..84662933d49 --- /dev/null +++ b/target/mips/translate_addr_const.c @@ -0,0 +1,52 @@ +/* + * Address Computation and Large Constant Instructions + */ +#include "qemu/osdep.h" +#include "tcg/tcg-op.h" +#include "translate.h" + +bool gen_LSA(DisasContext *ctx, int rd, int rt, int rs, int sa) +{ + TCGv t0; + TCGv t1; + + if (rd =3D=3D 0) { + /* Treat as NOP. */ + return true; + } + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + tcg_gen_shli_tl(t0, t0, sa + 1); + tcg_gen_add_tl(cpu_gpr[rd], t0, t1); + tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); + + tcg_temp_free(t1); + tcg_temp_free(t0); + + return true; +} + +bool gen_DLSA(DisasContext *ctx, int rd, int rt, int rs, int sa) +{ + TCGv t0; + TCGv t1; + + check_mips_64(ctx); + + if (rd =3D=3D 0) { + /* Treat as NOP. */ + return true; + } + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + tcg_gen_shli_tl(t0, t0, sa + 1); + tcg_gen_add_tl(cpu_gpr[rd], t0, t1); + tcg_temp_free(t1); + tcg_temp_free(t0); + + return true; +} diff --git a/target/mips/meson.build b/target/mips/meson.build index 5ccc9ddc6b8..dce0ca96527 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -16,6 +16,7 @@ 'mod-msa_helper.c', 'tlb_helper.c', 'translate.c', + 'translate_addr_const.c', 'mod-msa_translate.c', )) mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) --=20 2.26.2 From nobody Tue May 21 12:06:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.45 as permitted sender) client-ip=209.85.208.45; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f45.google.com; Authentication-Results: mx.zohomail.com; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id v16sm19120925eds.64.2020.12.15.15.00.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 15:00:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qhCr51gZzmCyhfb9yAybvFXb3H9tr37qgZdUgiwOt1k=; b=DU0zSBFj/RMVXWs8OhS0o+DuJ6AcJiRFIB8npmjbOIkvcNs3XsVXLPX1qOB/uVGfLT ZW38qaWpj7Xs0kAkp81wUSK7F+PF88TlKDKF1A5wmUiTCE+Uu+aWba0eT1nyvonOi11u iMpCecYUP6ZbZGuKJwvQe+5QJt91nRUUGf09Z5zT5HWsDTfm7jbjwNws6ZUa5bEWjYuy DHExeNr6sHkQJFwVCLD7V9drOYr6O4KpF5DxUDW8vdlZAyuwALeTuzCBkFAkFkuPQEwN kbhKYAs6zlQnQitEi0j/OULmfJWmsEFSrDx26MrVl3621TQDCLp2/x8JKEpMh+9gicqS N+KA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=qhCr51gZzmCyhfb9yAybvFXb3H9tr37qgZdUgiwOt1k=; b=a/gHkWAoQ9CJRPvTXR17YslGrSKik4WFzWN8aFuhnURYYEGtguFbMoym/b0AbsEZ6y UAfOkZOACAkHlpYbYyt/7NvEckfCDL6QHxgSZ2ADXh4K83jw2HyAlmq3LcMPrP8aela9 RgdQTMzgLiZm8TxHxfctVnO4ZhMt5vwjHiXOhs95WR8OoP0RuJcKWDEbtg4/kUxq7UvB C8oUkYaPS6TxocY5htbngGHeWGHfw0HAnoo7WkTR0tJevJeqUPUXGF2QdsnWA+6eYo+M Fy1IwPlWT/0i4OULbCEgp6IRm6E+pkj0zCLLkyo1RtS/RaOMC5lP0zRSFGApX+XTd1cH V+mw== X-Gm-Message-State: AOAM532RztQNstDDqWR4IElu+zNRuAux5AcFX9dZvvefTOUYtd4p0yfh cNhh1bU6yBIPKOqrvHzSxzc= X-Google-Smtp-Source: ABdhPJwAw/3qzdrXTqpeeUEUWGq0bTt6nV1n5heKOXy582bqGD3WN1pilgWUPaMuIGw9eYMAorR4Aw== X-Received: by 2002:aa7:d94e:: with SMTP id l14mr4310053eds.98.1608073203992; Tue, 15 Dec 2020 15:00:03 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aleksandar Rikalo , Paolo Bonzini , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen Subject: [PATCH v2 22/24] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes Date: Tue, 15 Dec 2020 23:57:55 +0100 Message-Id: <20201215225757.764263-23-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215225757.764263-1-f4bug@amsat.org> References: <20201215225757.764263-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Add the LSA opcode to the MSA32 decodetree config, add DLSA to a new config for the MSA64 ASE, and call decode_msa64() in the main decode_opc() loop. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/mod-msa32.decode | 4 ++++ target/mips/mod-msa64.decode | 17 +++++++++++++++++ target/mips/mod-msa_translate.c | 14 ++++++++++++++ target/mips/meson.build | 2 ++ 4 files changed, 37 insertions(+) create mode 100644 target/mips/mod-msa64.decode diff --git a/target/mips/mod-msa32.decode b/target/mips/mod-msa32.decode index d69675132b8..0b2f0863251 100644 --- a/target/mips/mod-msa32.decode +++ b/target/mips/mod-msa32.decode @@ -10,11 +10,15 @@ # (Document Number: MD00866-2B-MSA32-AFP-01.12) # =20 +&lsa rd rt rs sa &msa_bz df wt s16 =20 +@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &lsa @bz ...... ... .. wt:5 s16:16 &msa_bz df=3D3 @bz_df ...... ... df:2 wt:5 s16:16 &msa_bz =20 +LSA 000000 ..... ..... ..... 000 .. 000101 @lsa + BZ_V 010001 01011 ..... ................ @bz BNZ_V 010001 01111 ..... ................ @bz =20 diff --git a/target/mips/mod-msa64.decode b/target/mips/mod-msa64.decode new file mode 100644 index 00000000000..8dcbbcd8538 --- /dev/null +++ b/target/mips/mod-msa64.decode @@ -0,0 +1,17 @@ +# MIPS SIMD Architecture Module instruction set +# +# Copyright (C) 2020 Philippe Mathieu-Daud=C3=A9 +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: +# MIPS Architecture for Programmers Volume IV-j +# The MIPS64 SIMD Architecture Module, Revision 1.12 +# (Document Number: MD00868-1D-MSA64-AFP-01.12) +# + +&lsa rd rt rs sa !extern + +@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &lsa + +DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa diff --git a/target/mips/mod-msa_translate.c b/target/mips/mod-msa_translat= e.c index d1a8a95e62e..f139ba784dc 100644 --- a/target/mips/mod-msa_translate.c +++ b/target/mips/mod-msa_translate.c @@ -19,6 +19,7 @@ =20 /* Include the auto-generated decoder. */ #include "decode-mod-msa32.c.inc" +#include "decode-mod-msa64.c.inc" =20 #define OPC_MSA (0x1E << 26) =20 @@ -2268,7 +2269,20 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) return true; } =20 +static bool trans_LSA(DisasContext *ctx, arg_LSA *a) +{ + return gen_LSA(ctx, a->rd, a->rt, a->rs, a->sa); +} + +static bool trans_DLSA(DisasContext *ctx, arg_LSA *a) +{ + return gen_DLSA(ctx, a->rd, a->rt, a->rs, a->sa); +} + bool decode_ase_msa(DisasContext *ctx, uint32_t insn) { + if (TARGET_LONG_BITS =3D=3D 64 && decode_msa64(ctx, insn)) { + return true; + } return decode_msa32(ctx, insn); } diff --git a/target/mips/meson.build b/target/mips/meson.build index dce0ca96527..8e2e5fa40b8 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -1,5 +1,6 @@ gen =3D [ decodetree.process('mod-msa32.decode', extra_args: [ '--static-decode=3D= decode_msa32' ]), + decodetree.process('mod-msa64.decode', extra_args: [ '--static-decode=3D= decode_msa64' ]), ] =20 mips_ss =3D ss.source_set() @@ -19,6 +20,7 @@ 'translate_addr_const.c', 'mod-msa_translate.c', )) + mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 mips_softmmu_ss =3D ss.source_set() --=20 2.26.2 From nobody Tue May 21 12:06:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.45 as permitted sender) client-ip=209.85.218.45; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-f45.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1608073213; cv=none; d=zohomail.com; s=zohoarc; b=Empu32ohnV15r07P4DDTM4+sHv3HdPwzHm28CuhRwPkVKeEgQYKdD5MDCJ3atmPdkNgAsD63XA8vvtgIqQsa0fq2umksHCBMyBX1j77Qgr6ZAsvIXaZ982tOR1on8XtBveHbzKNyxrg6H3h+xh0bvMwBZMZRnRVjlmxWjh+xYOY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608073213; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4FByo0luaRsj+aLeL9XTS/vkQm9Li61qyHi3C9wh89E=; b=Wi/aL6F4OqSAP1lre+SI6Ij09ouhk4Md8jvLlVlkcoSOF16OZdoeiPOOtRvSNLPdP7A5G9iDST7EOGocM6/8vWplnLlt2xTtLlRfWKH2NuIBuYbeqh1f8FaNXmE9uUEqWxQILFwFAhxTxIi2hgLT/HnnpC/gz1Ts+tac0mBpuOo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) by mx.zohomail.com with SMTPS id 1608073213510895.1206749842956; Tue, 15 Dec 2020 15:00:13 -0800 (PST) Received: by mail-ej1-f45.google.com with SMTP id j22so12053163eja.13 for ; Tue, 15 Dec 2020 15:00:10 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id h15sm19497149edz.95.2020.12.15.15.00.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 15:00:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4FByo0luaRsj+aLeL9XTS/vkQm9Li61qyHi3C9wh89E=; b=qbkqTfIDUlwvWOW7Gd7einDqrUc20NC6J69WdA//sX2fo8TGhuEXTmkdAH/RZtkQTb MytpnmKRDJ2G3biodDRUNJsm4o2wsUZKKPfrOp9aA2U7ePCJq2nogPiRf7NwhgSC6J5I VxoQxzii3zg6w0RPO8fKylTunHuMfAnetvaZD1PE/CPBNe7y9IXnzT1oSIXiMWZK7hyZ jTPN568DPQA2XPrg5MRhen2iiHE7wvPlKAtrsO45gOHgbHTnLSpgQzFsYUHNwwRNe4CY t7fEqmVjRymZegCRGsKFl6xLMw0pDtbWoJuNd66Y2EkTqcUQAAyDLxkfgy9MQpH/4b93 yQzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=4FByo0luaRsj+aLeL9XTS/vkQm9Li61qyHi3C9wh89E=; b=LX9akjirT3lnGk+1S9BCgpYUf8l8iByL4iLuKr+68eeKH9JTOYPSaB03965wdr+1ro GuXnqfbSe57KMQKQ7k+c58dQcAozcb2SAr6S0e6EPDnE71EsmwEExG2esJ9+AFgztPsk 1wbo/hFrhyAtSDaBulDqlVfO049Y7+YmFGvinfyxMPXD3+ldxBkXUx9TAUghyByG055d dMAmXRFnKYWfWezBcVM5czFdyyEuHt3YvaAHFCHQyYslLxv1QbnLcY6nFcIALpqE3lrj OozH8amppWb0jOEfRGJVz0DZp2F7fvPRzAd3RqjFHMnYgEAi/owmQT9n+WjHu5ohrJN6 nSGg== X-Gm-Message-State: AOAM530Bo1vCMaETW2ukc6hEw1Bn7fbp9uCNrokNR8j6vSwHNn4j0ktJ rCXbwKVoLPQpkwlxxU1CZeg= X-Google-Smtp-Source: ABdhPJwDVfUkiC184zELa5kw8x1BW2v7eil7oduSJGx+lW/j20b1aOWUnA0EMRSvgjtAUsGKyYriMg== X-Received: by 2002:a17:906:b793:: with SMTP id dt19mr28515625ejb.120.1608073209280; Tue, 15 Dec 2020 15:00:09 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aleksandar Rikalo , Paolo Bonzini , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen Subject: [PATCH v2 23/24] target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes Date: Tue, 15 Dec 2020 23:57:56 +0100 Message-Id: <20201215225757.764263-24-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215225757.764263-1-f4bug@amsat.org> References: <20201215225757.764263-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) LSA and LDSA opcodes are also available with MIPS release 6. Introduce the decodetree config files and call the decode() helpers in the main decode_opc() loop. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/translate.h | 1 + target/mips/isa-mips32r6.decode | 17 ++++++++++++ target/mips/isa-mips64r6.decode | 17 ++++++++++++ target/mips/isa-mips_rel6_translate.c | 37 +++++++++++++++++++++++++++ target/mips/translate.c | 5 ++++ target/mips/meson.build | 3 +++ 6 files changed, 80 insertions(+) create mode 100644 target/mips/isa-mips32r6.decode create mode 100644 target/mips/isa-mips64r6.decode create mode 100644 target/mips/isa-mips_rel6_translate.c diff --git a/target/mips/translate.h b/target/mips/translate.h index 47129de81d9..cbaef53b958 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -161,6 +161,7 @@ extern TCGv bcond; void msa_translate_init(void); =20 /* decodetree generated */ +bool decode_isa_rel6(DisasContext *ctx, uint32_t insn); bool decode_ase_msa(DisasContext *ctx, uint32_t insn); =20 #endif diff --git a/target/mips/isa-mips32r6.decode b/target/mips/isa-mips32r6.dec= ode new file mode 100644 index 00000000000..027585ee042 --- /dev/null +++ b/target/mips/isa-mips32r6.decode @@ -0,0 +1,17 @@ +# MIPS32 Release 6 instruction set +# +# Copyright (C) 2020 Philippe Mathieu-Daud=C3=A9 +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: +# MIPS Architecture for Programmers Volume II-A +# The MIPS32 Instruction Set Reference Manual, Revision 6.06 +# (Document Number: MD00086-2B-MIPS32BIS-AFP-06.06) +# + +&lsa rd rt rs sa + +@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &lsa + +LSA 000000 ..... ..... ..... 000 .. 000101 @lsa diff --git a/target/mips/isa-mips64r6.decode b/target/mips/isa-mips64r6.dec= ode new file mode 100644 index 00000000000..e812224341e --- /dev/null +++ b/target/mips/isa-mips64r6.decode @@ -0,0 +1,17 @@ +# MIPS64 Release 6 instruction set +# +# Copyright (C) 2020 Philippe Mathieu-Daud=C3=A9 +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: +# MIPS Architecture for Programmers Volume II-A +# The MIPS64 Instruction Set Reference Manual, Revision 6.06 +# (Document Number: MD00087-2B-MIPS64BIS-AFP-6.06) +# + +&lsa rd rt rs sa !extern + +@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &lsa + +DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa diff --git a/target/mips/isa-mips_rel6_translate.c b/target/mips/isa-mips_r= el6_translate.c new file mode 100644 index 00000000000..d5872bbf8fc --- /dev/null +++ b/target/mips/isa-mips_rel6_translate.c @@ -0,0 +1,37 @@ +/* + * MIPS emulation for QEMU - # Release 6 translation routines + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * Copyright (c) 2006 Marius Groeger (FPU operations) + * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) + * Copyright (c) 2020 Philippe Mathieu-Daud=C3=A9 + * + * This code is licensed under the GNU GPLv2 and later. + */ + +#include "qemu/osdep.h" +#include "tcg/tcg-op.h" +#include "exec/helper-gen.h" +#include "translate.h" + +/* Include the auto-generated decoder. */ +#include "decode-isa-mips32r6.c.inc" +#include "decode-isa-mips64r6.c.inc" + +static bool trans_LSA(DisasContext *ctx, arg_LSA *a) +{ + return gen_LSA(ctx, a->rd, a->rt, a->rs, a->sa); +} + +static bool trans_DLSA(DisasContext *ctx, arg_LSA *a) +{ + return gen_DLSA(ctx, a->rd, a->rt, a->rs, a->sa); +} + +bool decode_isa_rel6(DisasContext *ctx, uint32_t insn) +{ + if (TARGET_LONG_BITS =3D=3D 64 && decode_mips64r6(ctx, insn)) { + return true; + } + return decode_mips32r6(ctx, insn); +} diff --git a/target/mips/translate.c b/target/mips/translate.c index e0439ba92d8..125b2aac848 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -29027,6 +29027,11 @@ static void decode_opc(CPUMIPSState *env, DisasCon= text *ctx) return; } =20 + /* ISA */ + if (isa_rel6_available(env) && decode_isa_rel6(ctx, ctx->opcode)) { + return; + } + if (!decode_opc_legacy(env, ctx)) { gen_reserved_instruction(ctx); } diff --git a/target/mips/meson.build b/target/mips/meson.build index 8e2e5fa40b8..2d62288d604 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -1,4 +1,6 @@ gen =3D [ + decodetree.process('isa-mips32r6.decode', extra_args: [ '--static-decode= =3Ddecode_mips32r6' ]), + decodetree.process('isa-mips64r6.decode', extra_args: [ '--static-decode= =3Ddecode_mips64r6' ]), decodetree.process('mod-msa32.decode', extra_args: [ '--static-decode=3D= decode_msa32' ]), decodetree.process('mod-msa64.decode', extra_args: [ '--static-decode=3D= decode_msa64' ]), ] @@ -12,6 +14,7 @@ mips_ss.add(when: 'CONFIG_TCG', if_true: files( 'dsp_helper.c', 'fpu_helper.c', + 'isa-mips_rel6_translate.c', 'lmmi_helper.c', 'op_helper.c', 'mod-msa_helper.c', --=20 2.26.2 From nobody Tue May 21 12:06:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.66 as permitted sender) client-ip=209.85.218.66; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id f11sm20320776edy.59.2020.12.15.15.00.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 15:00:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DTZIrFlHcNm9YcGLkUm/8b5t2eShtDyueJmi4bfarso=; b=o/Lg9AW6RsdSbatw9ZvZiaqGAphftza4xV+qx2aTN7AIRuAThHpFz8i03HC30uKif4 k09ZCCY9ml9P9upy+m6AILYY/L92yYpHq6eo071QIX5MR2XFCcw1tpcKSFq0Beh5kBFZ eKuGpJf3YtIbB+EBHr94w4ud4pJuvCmbR5HK2mjoL1KsceIV2cYIwLjkL4P2WdxN7xH1 7df04zElquESuERW5RwQxmyaw6EG/LLy+y0CDF2GlnYq4Rkd2jxAIN8Ee/ajZh/6bxN2 gRZNrILg4ZZK8S//9V52n0Ty1QvOpXo2VFq6XbSTeEgotNf9yw3JM8JO37yUKdAdf80o muow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=DTZIrFlHcNm9YcGLkUm/8b5t2eShtDyueJmi4bfarso=; b=VGPhKxyMzgv1nsHX3jQIk7SW6w1cG36aAjS7U1MYhbhrEy5Wx13CUZn4Yot6SCKQ+a Zyucpo8PQuItraCjfD97hg46p+jw0GTLuijk9IT1veFZdT8K0pnm5llz0Man35cwz+A0 2qwQpbP/F4RCkF59fsAZyI7pt5F9kqJjyTqFbyqZLpZaWHMWerJSOj/mopSLFEQzsLQC KayDFN5DAJYv/t0OS30Kf4BHILv/1AOS9dTvp1ywtA36pDIU/FpGxJSsyob9Z590Rvt3 I3GROvkmeHLlX2bNWKCaXmt78ebLjF+ExMo7oAF96ReuPcuhJ4OfEqJUH66pMeq3MszB K9MA== X-Gm-Message-State: AOAM532GXq6euvtx4ur0UJEbw1G1W4XYjYH3QIxaj7BGcCrb8/JOsav6 RQFDfMGoP3kG3YfLuwzaKZ8= X-Google-Smtp-Source: ABdhPJwwyM69vtNujuLHaxpzJ3Xo4kw4/9pTA0EnBDUB6BwcABn54DD4EgmC3yUoZ3BDWepNBGrQAw== X-Received: by 2002:a17:907:94c6:: with SMTP id dn6mr29085549ejc.13.1608073214898; Tue, 15 Dec 2020 15:00:14 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aleksandar Rikalo , Paolo Bonzini , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen Subject: [RFC PATCH v2 24/24] target/mips/mod-msa: Pass TCGCond argument to gen_check_zero_element() Date: Tue, 15 Dec 2020 23:57:57 +0100 Message-Id: <20201215225757.764263-25-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215225757.764263-1-f4bug@amsat.org> References: <20201215225757.764263-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Simplify gen_check_zero_element() by passing the TCGCond argument along. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- Maybe this can be named 'msa_translate.c' after all... --- target/mips/mod-msa_translate.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/target/mips/mod-msa_translate.c b/target/mips/mod-msa_translat= e.c index f139ba784dc..7ad14b19b0c 100644 --- a/target/mips/mod-msa_translate.c +++ b/target/mips/mod-msa_translate.c @@ -309,7 +309,8 @@ static inline int check_msa_access(DisasContext *ctx) return 1; } =20 -static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt) +static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt, + TCGCond cond) { /* generates tcg ops to check if any element is 0 */ /* Note this function only works with MSA_WRLEN =3D 128 */ @@ -344,7 +345,7 @@ static void gen_check_zero_element(TCGv tresult, uint8_= t df, uint8_t wt) tcg_gen_or_i64(t0, t0, t1); /* if all bits are zero then all elements are not zero */ /* if some bit is non-zero then some element is zero */ - tcg_gen_setcondi_i64(TCG_COND_NE, t0, t0, 0); + tcg_gen_setcondi_i64(cond, t0, t0, 0); tcg_gen_trunc_i64_tl(tresult, t0); tcg_temp_free_i64(t0); tcg_temp_free_i64(t1); @@ -393,10 +394,7 @@ static bool gen_msa_BxZ(DisasContext *ctx, int df, int= wt, int s16, bool if_not) return true; } =20 - gen_check_zero_element(bcond, df, wt); - if (if_not) { - tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0); - } + gen_check_zero_element(bcond, df, wt, if_not ? TCG_COND_EQ : TCG_COND_= NE); =20 ctx->btarget =3D ctx->base.pc_next + (s16 << 2) + 4; ctx->hflags |=3D MIPS_HFLAG_BC; --=20 2.26.2