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Tue, 15 Dec 2020 12:48:28 -0500 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-222-k2Fij3x0OUikQCCCHRJFMQ-1; Tue, 15 Dec 2020 12:48:19 -0500 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 5CA3810054FF; Tue, 15 Dec 2020 17:48:18 +0000 (UTC) Received: from kamzik.brq.redhat.com (ovpn-113-73.ams2.redhat.com [10.36.113.73]) by smtp.corp.redhat.com (Postfix) with ESMTP id D03BE10023B7; Tue, 15 Dec 2020 17:48:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1608054504; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=sT7McfMnj3aA9Tkx3FqU+o+8cYD3dAIbywRJYxT0XdA=; b=dsFARaweT1ajBmZUoUB+/U1HpdaNqFWDaxPWrnMNnemUz66kqYbCBReipR2ScMzAiJ7sHu lAeiDrpI7DhJprzzG0aIb5Wjt9PLALH2E77utFwnI9qXsUXz0QcEhjv3r5Zd1ZXfvwrYD0 5jZlQpwpSvRrtXdQXdm/Iee5vkGSdCg= X-MC-Unique: k2Fij3x0OUikQCCCHRJFMQ-1 From: Andrew Jones To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: [PATCH] hw/arm/virt: Remove virt machine state 'smp_cpus' Date: Tue, 15 Dec 2020 18:48:15 +0100 Message-Id: <20201215174815.51520-1-drjones@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=drjones@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=63.128.21.124; envelope-from=drjones@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: fangying1@huawei.com, peter.maydell@linaro.org, salil.mehta@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" virt machine's 'smp_cpus' and machine->smp.cpus must always have the same value. And, anywhere we have virt machine state we have machine state. So let's remove the redundancy. Also, to make it easier to see that machine->smp is the true source for "smp_cpus" and "max_cpus", avoid passing them in function parameters, preferring instead to get them from the state. No functional change intended. Signed-off-by: Andrew Jones Reviewed-by: David Edmondson Reviewed-by: Ying Fang --- hw/arm/virt-acpi-build.c | 9 +++++---- hw/arm/virt.c | 24 +++++++++++------------- include/hw/arm/virt.h | 3 +-- 3 files changed, 17 insertions(+), 19 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 711cf2069fe8..9d9ee2405345 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -59,11 +59,12 @@ =20 #define ACPI_BUILD_TABLE_SIZE 0x20000 =20 -static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) +static void acpi_dsdt_add_cpus(Aml *scope, VirtMachineState *vms) { + MachineState *ms =3D MACHINE(vms); uint16_t i; =20 - for (i =3D 0; i < smp_cpus; i++) { + for (i =3D 0; i < ms->smp.cpus; i++) { Aml *dev =3D aml_device("C%.03X", i); aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); aml_append(dev, aml_name_decl("_UID", aml_int(i))); @@ -484,7 +485,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) gicd->base_address =3D cpu_to_le64(memmap[VIRT_GIC_DIST].base); gicd->version =3D vms->gic_version; =20 - for (i =3D 0; i < vms->smp_cpus; i++) { + for (i =3D 0; i < MACHINE(vms)->smp.cpus; i++) { AcpiMadtGenericCpuInterface *gicc =3D acpi_data_push(table_data, sizeof(*gicc)); ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(i)); @@ -603,7 +604,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) * the RTC ACPI device at all when using UEFI. */ scope =3D aml_scope("\\_SB"); - acpi_dsdt_add_cpus(scope, vms->smp_cpus); + acpi_dsdt_add_cpus(scope, vms); acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], (irqmap[VIRT_UART] + ARM_SPI_BASE)); if (vmc->acpi_expose_flash) { diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 556592012ee0..534d306f3104 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -323,7 +323,7 @@ static void fdt_add_timer_nodes(const VirtMachineState = *vms) if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { irqflags =3D deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, GIC_FDT_IRQ_PPI_CPU_WIDTH, - (1 << vms->smp_cpus) - 1); + (1 << MACHINE(vms)->smp.cpus) - 1); } =20 qemu_fdt_add_subnode(vms->fdt, "/timer"); @@ -347,9 +347,9 @@ static void fdt_add_timer_nodes(const VirtMachineState = *vms) =20 static void fdt_add_cpu_nodes(const VirtMachineState *vms) { - int cpu; - int addr_cells =3D 1; const MachineState *ms =3D MACHINE(vms); + int smp_cpus =3D ms->smp.cpus, cpu; + int addr_cells =3D 1; =20 /* * From Documentation/devicetree/bindings/arm/cpus.txt @@ -364,7 +364,7 @@ static void fdt_add_cpu_nodes(const VirtMachineState *v= ms) * The simplest way to go is to examine affinity IDs of all our CPUs.= If * at least one of them has Aff3 populated, we set #address-cells to = 2. */ - for (cpu =3D 0; cpu < vms->smp_cpus; cpu++) { + for (cpu =3D 0; cpu < smp_cpus; cpu++) { ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu)); =20 if (armcpu->mp_affinity & ARM_AFF3_MASK) { @@ -377,7 +377,7 @@ static void fdt_add_cpu_nodes(const VirtMachineState *v= ms) qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells); qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0); =20 - for (cpu =3D vms->smp_cpus - 1; cpu >=3D 0; cpu--) { + for (cpu =3D smp_cpus - 1; cpu >=3D 0; cpu--) { char *nodename =3D g_strdup_printf("/cpus/cpu@%d", cpu); ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu)); CPUState *cs =3D CPU(armcpu); @@ -387,8 +387,7 @@ static void fdt_add_cpu_nodes(const VirtMachineState *v= ms) qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", armcpu->dtb_compatible); =20 - if (vms->psci_conduit !=3D QEMU_PSCI_CONDUIT_DISABLED - && vms->smp_cpus > 1) { + if (vms->psci_conduit !=3D QEMU_PSCI_CONDUIT_DISABLED && smp_cpus = > 1) { qemu_fdt_setprop_string(vms->fdt, nodename, "enable-method", "psci"); } @@ -534,7 +533,7 @@ static void fdt_add_pmu_nodes(const VirtMachineState *v= ms) if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { irqflags =3D deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, GIC_FDT_IRQ_PPI_CPU_WIDTH, - (1 << vms->smp_cpus) - 1); + (1 << MACHINE(vms)->smp.cpus) - 1); } =20 qemu_fdt_add_subnode(vms->fdt, "/pmu"); @@ -1673,9 +1672,9 @@ static void finalize_gic_version(VirtMachineState *vm= s) * virt_cpu_post_init() must be called after the CPUs have * been realized and the GIC has been created. */ -static void virt_cpu_post_init(VirtMachineState *vms, int max_cpus, - MemoryRegion *sysmem) +static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem) { + int max_cpus =3D MACHINE(vms)->smp.max_cpus; bool aarch64, pmu, steal_time; CPUState *cpu; =20 @@ -1828,8 +1827,6 @@ static void machvirt_init(MachineState *machine) exit(1); } =20 - vms->smp_cpus =3D smp_cpus; - if (vms->virt && kvm_enabled()) { error_report("mach-virt: KVM does not support providing " "Virtualization extensions to the guest CPU"); @@ -1845,6 +1842,7 @@ static void machvirt_init(MachineState *machine) create_fdt(vms); =20 possible_cpus =3D mc->possible_cpu_arch_ids(machine); + assert(possible_cpus->len =3D=3D max_cpus); for (n =3D 0; n < possible_cpus->len; n++) { Object *cpuobj; CPUState *cs; @@ -1965,7 +1963,7 @@ static void machvirt_init(MachineState *machine) =20 create_gic(vms); =20 - virt_cpu_post_init(vms, possible_cpus->len, sysmem); + virt_cpu_post_init(vms, sysmem); =20 fdt_add_pmu_nodes(vms); =20 diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index abf54fab4981..e4a2d216420f 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -151,7 +151,6 @@ struct VirtMachineState { MemMapEntry *memmap; char *pciehb_nodename; const int *irqmap; - int smp_cpus; void *fdt; int fdt_size; uint32_t clock_phandle; @@ -182,7 +181,7 @@ static inline int virt_gicv3_redist_region_count(VirtMa= chineState *vms) =20 assert(vms->gic_version =3D=3D VIRT_GIC_VERSION_3); =20 - return vms->smp_cpus > redist0_capacity ? 2 : 1; + return MACHINE(vms)->smp.cpus > redist0_capacity ? 2 : 1; } =20 #endif /* QEMU_ARM_VIRT_H */ --=20 2.26.2