From nobody Thu Dec 18 13:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608065933; cv=none; d=zohomail.com; s=zohoarc; b=DhFkkegjUZBNPLW6MSUalf/TIxpbawDWLqcLiqBPM33j7RIjeG5mfapHqinHY/q/QzNaRZxps0HyNiOY0GGPZ2TpkVI33i++1L5zKDBdyEMCuz6U4CWgULMKHL8cPj2enHQwURyCeOJ86a5J7YkDOBTm54z+dEKAbl+Mwr3UM4k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608065933; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lv9BxTsnVMI28ncB29ZUXQqJSkKOizde5SVuW6MLg8M=; b=dOgWKbYpNDeoy2vI7g4L2LDKqymv2cCtROVIMpbuw8fIlv2buXBy8zvazrmXc+tk32Fwvkn7mEIqhs0dnS0bniNFiYduVdlxEBBjTZr7oCb1Hqg2g0Rv4UDhui/PFtk9NIEnWvE/9bqnVm9peihfNfMkxQJSgL6bUb6QC+stw5M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 160806593324240.04563666681452; Tue, 15 Dec 2020 12:58:53 -0800 (PST) Received: from localhost ([::1]:49484 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kpBFZ-0008M4-Ja for importer@patchew.org; Tue, 15 Dec 2020 09:24:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34036) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kpB4W-0001Vr-JL for qemu-devel@nongnu.org; Tue, 15 Dec 2020 09:13:00 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:36194) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kpB4I-00076N-2v for qemu-devel@nongnu.org; Tue, 15 Dec 2020 09:12:56 -0500 Received: by mail-wm1-x336.google.com with SMTP id y23so18654455wmi.1 for ; Tue, 15 Dec 2020 06:12:42 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w21sm19667319wmi.45.2020.12.15.06.12.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 06:12:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=lv9BxTsnVMI28ncB29ZUXQqJSkKOizde5SVuW6MLg8M=; b=CQnacXQtLN6dcn0iTm11ShOWW4AOpLpv8mQdqnf4vMtH7cOx59IlTVvg+lpnlgf1aO utMUn/8tWlHn2d/AmIoDBtPSVjGzhy+nKzWdvgj5SJhwMHIFcP71rme9JiM5CqKYbhOv Y4v/25X6WA88Hsjx0NaNihRsmPAOn6v+0ZBWQ6KpS5rSHpBVisMFLdmaKdu5pglEyKuw Y79mJBc144VDvDr83o/dRgR+ZcG4groNkVYE0OU5Mck/wibDUT7/+fGLV8w1iGMCmSrU Qo51Csdq7GYeiOLeKhGb7OHxGiQ130DtDpL+y73XllvVRQ+R9yB7c0O1QyvEs4TQ+ZP2 LT+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lv9BxTsnVMI28ncB29ZUXQqJSkKOizde5SVuW6MLg8M=; b=l8ydmX9IsrhuASbQyxGSa0roybpNVNLcJOhaptVv6f9U7h+liGaYnDZIWh8Yp8W7GZ s2++Q1qhZQHEw1zUsjrPfsCVpKTqszV54ZlEGt0MZWluU9y7Yx3EN9xOv3PtVVrHafkh b2bLfEJJXo8H7ylHsusYPe6fZQen9wYI4KdycIyr6/uf0TLxck0U5DjYNRrGkwfTMGnM /5Z92UpqWb7pdCSjwAdPtcT58UIvRrfoSoqqSeWEvjrC0uWwImpSESeE61QCdety0kk5 aqTPHPSEq+yu2i/q8MDEu8jK0BPvE6zrhcZ9UvAcBypqcVoSoNc/a4LGuojAgsPWxVYR nWXQ== X-Gm-Message-State: AOAM5306E5FBa+dz/5bA6+P5ntoYEsy9R5cqgqJkC5W52MEHTDjzzj04 arLRfkFmxYZ9xeLp8HMGVTPMXpKN8zpxig== X-Google-Smtp-Source: ABdhPJxeDcU/223Xj4nN+PFLHYQB8Tx662qNvJoYN1UoI1EjRopRvhR+WzH4dzqrPoI/3uHouxArxA== X-Received: by 2002:a7b:c19a:: with SMTP id y26mr32064064wmi.20.1608041561181; Tue, 15 Dec 2020 06:12:41 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/20] gdbstub: Correct misparsing of vCont C/S requests Date: Tue, 15 Dec 2020 14:12:18 +0000 Message-Id: <20201215141237.17868-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201215141237.17868-1-peter.maydell@linaro.org> References: <20201215141237.17868-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) In the vCont packet, two of the command actions (C and S) take an argument specifying the signal to be sent to the process/thread, which is sent as an ASCII string of two hex digits which immediately follow the 'C' or 'S' character. Our code for parsing this packet accidentally skipped the first of the two bytes of the signal value, because it started parsing the hex string at 'p + 1' when the preceding code had already moved past the 'C' or 'S' with "cur_action =3D *p++". This meant that we would only do the right thing for signals below 10, and would misinterpret the rest. For instance, when the debugger wants to send the process a SIGPROF (27 on x86-64) we mangle this into a SIGSEGV (11). Remove the accidental double increment. Fixes: https://bugs.launchpad.net/qemu/+bug/1773743 Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Message-id: 20201121210342.10089-1-peter.maydell@linaro.org --- gdbstub.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gdbstub.c b/gdbstub.c index f19f98ab1ab..d99bc0bf2ea 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1243,7 +1243,7 @@ static int gdb_handle_vcont(const char *p) cur_action =3D *p++; if (cur_action =3D=3D 'C' || cur_action =3D=3D 'S') { cur_action =3D qemu_tolower(cur_action); - res =3D qemu_strtoul(p + 1, &p, 16, &tmp); + res =3D qemu_strtoul(p, &p, 16, &tmp); if (res) { goto out; } --=20 2.20.1 From nobody Thu Dec 18 13:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608064131; cv=none; d=zohomail.com; s=zohoarc; b=LHJK3JoonlIjzXSPKRMUm/1N3pKOo9GeyvtIXdhOjnWR/J9KJW1xmEydlCm+ZnjcfVV2r/JuycUoNqcXSWrK0IbCUyKlQkBFTJAyDM+fA0Sh36eXHv0CBlz8W/bYytiF/yf/bnhYZUEakLVN5ap2ufrVkgexl3/AcFZ4LusAPIk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608064131; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NgipyMtEahMK7WxKAqWo98jTa4SOUfBt1SZmHI5R7Fw=; b=VoWEcBb4B7DYpI6cQz7bzz+iRtnM+n5Dm5yIW0JCDRACAgm5Uw/PFsAAdk8ThQa9ww1Km7+28F/bDIV6jGQ/NAf6d48i/G8+xmmSA7VFhjlt5idj1pomHtBE384UGrAZaQuJ9TkC7LWG3/5BiQe8nrWL6e9QwIoQ/i7V6rxLmEE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1608064131008172.44899560696; Tue, 15 Dec 2020 12:28:51 -0800 (PST) Received: from localhost ([::1]:60978 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kpBBa-0001Y3-CU for importer@patchew.org; Tue, 15 Dec 2020 09:20:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33972) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kpB4Q-0001Rg-66 for qemu-devel@nongnu.org; Tue, 15 Dec 2020 09:12:54 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:43634) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kpB4J-00076m-73 for qemu-devel@nongnu.org; Tue, 15 Dec 2020 09:12:53 -0500 Received: by mail-wr1-x441.google.com with SMTP id y17so19971531wrr.10 for ; Tue, 15 Dec 2020 06:12:43 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w21sm19667319wmi.45.2020.12.15.06.12.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 06:12:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=NgipyMtEahMK7WxKAqWo98jTa4SOUfBt1SZmHI5R7Fw=; b=XuSKzX/Hy3pB1XRsWdwppe3yH982icl+v/tGQ7nNoJ+Z4/DGAlL6V/rY2fRC/mpcAY w5nZqaavfYcZym0n6D6dHE5xysBNVQLcxrpyADlHXFAupSsP3lBbirSpyMhoTweMDAQF ptWR/mZKzsRwM86PYCoDvgrJ6jz40bmf7RWOSW2hFsslO2xzrtDyW+wp1Qjw8PRz+wnU VExVbhWcIWA0uAbyNLw992USM3aWF3aCuQxPqzeWuJq2Iz2N4sYAPyPxHqWItVrMAOkr meRTc8CYp68J2pDhAqphIGf+YAxUM2lgg+xg8N+F/GzImXaHUTU8Dpo2MFlknXYdpz1o GdjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NgipyMtEahMK7WxKAqWo98jTa4SOUfBt1SZmHI5R7Fw=; b=caj6ZggTOPlD9U4U3/WRErmGDvroXVJVWux9TAXTaomcH7UFdg/CtoDW9CGmBuSwoj bW81InXVUwelFr9dzc5i8Yvne4ans4+M0OTvq9vRl8+uOU+39dHtbWgGTRVB2nF5+aZr 3RhSc33+KXu8eqzVzmPgkkbzT8pIPvPFDbnn7C+m69j28ms65Bd30SHBhZuEtZCikdLS 3NkJ7bcgeoCETAXMHoIbUUQv5suEE+hCr1dqWpvVXxSeQpnlF8NMuolevSPdWwnD2qMh BHPja8D9q2oMu1UxNjHdoJ77+d417GrDXI/vv1oOfy1FSwDE2TNtj6gQVva8QJ6o5V4S g3bQ== X-Gm-Message-State: AOAM531glAnCU9NCZN8eAfwxneO3EOBaw1vhWV4vqpdiLGMI7yot3RD7 /r/F92my0t6Fm4kmCDlYs//Zzdx/kRFAZg== X-Google-Smtp-Source: ABdhPJzh/g0zgBUoNOj/0/PwVAtTiHB57PHGLeK+MaNLYYBZZJsAS/1XmtMOnL/lAwnAXeZn8Bqg+A== X-Received: by 2002:adf:fd05:: with SMTP id e5mr34704896wrr.225.1608041562286; Tue, 15 Dec 2020 06:12:42 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/20] hw/openrisc/openrisc_sim: Use IRQ splitter when connecting IRQ to multiple CPUs Date: Tue, 15 Dec 2020 14:12:19 +0000 Message-Id: <20201215141237.17868-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201215141237.17868-1-peter.maydell@linaro.org> References: <20201215141237.17868-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x441.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" openrisc_sim_net_init() attempts to connect the IRQ line from the ethernet device to both CPUs in an SMP configuration by simply caling sysbus_connect_irq() for it twice. This doesn't work, because the second connection simply overrides the first. Fix this by creating a TYPE_SPLIT_IRQ to split the IRQ in the SMP case. Signed-off-by: Peter Maydell Reviewed-by: Stafford Horne Message-id: 20201127225127.14770-2-peter.maydell@linaro.org --- hw/openrisc/openrisc_sim.c | 13 +++++++++++-- hw/openrisc/Kconfig | 1 + 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index d752282e675..a8adf6b70d7 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -34,6 +34,7 @@ #include "hw/sysbus.h" #include "sysemu/qtest.h" #include "sysemu/reset.h" +#include "hw/core/split-irq.h" =20 #define KERNEL_LOAD_ADDR 0x100 =20 @@ -64,8 +65,16 @@ static void openrisc_sim_net_init(hwaddr base, hwaddr de= scriptors, =20 s =3D SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(s, &error_fatal); - for (i =3D 0; i < num_cpus; i++) { - sysbus_connect_irq(s, 0, cpu_irqs[i][irq_pin]); + if (num_cpus > 1) { + DeviceState *splitter =3D qdev_new(TYPE_SPLIT_IRQ); + qdev_prop_set_uint32(splitter, "num-lines", num_cpus); + qdev_realize_and_unref(splitter, NULL, &error_fatal); + for (i =3D 0; i < num_cpus; i++) { + qdev_connect_gpio_out(splitter, i, cpu_irqs[i][irq_pin]); + } + sysbus_connect_irq(s, 0, qdev_get_gpio_in(splitter, 0)); + } else { + sysbus_connect_irq(s, 0, cpu_irqs[0][irq_pin]); } sysbus_mmio_map(s, 0, base); sysbus_mmio_map(s, 1, descriptors); diff --git a/hw/openrisc/Kconfig b/hw/openrisc/Kconfig index 6c1e86884e2..8f284f3ba04 100644 --- a/hw/openrisc/Kconfig +++ b/hw/openrisc/Kconfig @@ -3,3 +3,4 @@ config OR1K_SIM select SERIAL select OPENCORES_ETH select OMPIC + select SPLIT_IRQ --=20 2.20.1 From nobody Thu Dec 18 13:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608054954; cv=none; d=zohomail.com; s=zohoarc; b=buSjEhDhaHY0PTDI2tBGdjzU7oYMn/8epARbxOy/+kaphiyiZ12HyNuNCZWzGBohGlWC7ErXXRHa2ewbjxUyGfmxRBIx4jkQ4XP/Cdxl78RPW8zWZXlFPAinMxJDTcxjDAhMf81TL+gQ8GUca+UyIlbllJ9EXahOvxUR5H9jmWw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608054954; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9UlecDaR2TH7Y40McyC04bsmJGq7HwQNtSBVe+3WirE=; b=cnXpxLyHxAGDsBoV269xaflf64H0e1zxEKAmKzyJ+KFBs3qfffUl89VBjJARIj+1mYfqQLvP1+sqMsct/XQX065O5MMZl4/GV2AxnzxS6xmUrM0TJyDVXSmdaP/nBmpu4BiU/0jTspOifSX5R29h7NpsW506hApchOzJHU3hvZI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1608054952609723.3369256353566; Tue, 15 Dec 2020 09:55:52 -0800 (PST) Received: from localhost ([::1]:53134 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kpB9E-0006kf-J6 for importer@patchew.org; Tue, 15 Dec 2020 09:17:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34002) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kpB4R-0001Sf-Ny for qemu-devel@nongnu.org; Tue, 15 Dec 2020 09:12:58 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:55580) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kpB4J-00076r-6r for qemu-devel@nongnu.org; Tue, 15 Dec 2020 09:12:55 -0500 Received: by mail-wm1-x342.google.com with SMTP id x22so17001898wmc.5 for ; Tue, 15 Dec 2020 06:12:44 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w21sm19667319wmi.45.2020.12.15.06.12.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 06:12:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=9UlecDaR2TH7Y40McyC04bsmJGq7HwQNtSBVe+3WirE=; b=IMtkcb6OQjGa4xlnf6Pte3F6UrPDcaKsV6UDt1t4Sq3ftVvvRql5PIQ5tHsbn5KtFA kg0SYf4BhrHjj7sAZQYP+qPDw2NuEI/0UITVF7RbkevG4o9s5qzLztlUkzARpSgwwCej T/bAZgLq2aFq7pbrBB9qSaeIHhHD2Pep7uGgVx09sBHK9d+S1bUhrq1ek+wLMSp7Qb3O wVXLtpbSFt7Q7fdN+iAZXA8GdkiSNXLfWlecL034uqddjH72wQ5yH8CRgAOAhEs6RD/H ymlTwKofaW5i38+HXGpjN8x2pIcrwAFyk8T7Bsfj1u2DFkrJa8Bn5Oot7gxkfc8oHxyp 2Paw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9UlecDaR2TH7Y40McyC04bsmJGq7HwQNtSBVe+3WirE=; b=jz6gKe9t0gnVQcSuhbH8DtYi2IRGLfCoPdkGvY+HSceAbBObxCnrer3fXy1SsEiqEN e5r6HPQFytRePCMeVVxOPffNe6CC8IaaBA9EFuGLHjVqwrCrgysB9T4GAFjeUy3+YZsG 1if8DvJNjNeN6d+R59iG3HXAqmDaUdp53T5me4k6hMtgXD8lVf4aW+NqFhwMe4dsieMd Td1KPLHmlwFanuSvfB6CX4R+TYDg5PmSqxv9G4cQbirBYd+YeYu3+40DLTbNhdxruWVc f6MI/dZ2bG8Mz8tUTXPZa6VQmSkLaimjNDdhy+cYaKNNIrhmT1MjkN/PgAtOxJbS3Euz t9kg== X-Gm-Message-State: AOAM532MCI8j9SE2uJx+zvi/RZeRqAE9Ash/P6O9qaRtIPDL3W741Jkg JFhPZTp12c/BEs4bgF9TDWhkgLgiTNZV2g== X-Google-Smtp-Source: ABdhPJzr9cieubB+kBKcKeY04Q0NOoJIfjJx4T2R2pZC2uf1b31t3OhOW6X2htdhAAW7Xkb2KJc2MA== X-Received: by 2002:a1c:3c09:: with SMTP id j9mr33200906wma.180.1608041563515; Tue, 15 Dec 2020 06:12:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/20] hw/openrisc/openrisc_sim: Abstract out "get IRQ x of CPU y" Date: Tue, 15 Dec 2020 14:12:20 +0000 Message-Id: <20201215141237.17868-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201215141237.17868-1-peter.maydell@linaro.org> References: <20201215141237.17868-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x342.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We're about to refactor the OpenRISC pic_cpu code in a way that means that just grabbing the whole qemu_irq[] array of inbound IRQs for a CPU won't be possible any more. Abstract out a function for "return the qemu_irq for IRQ x input of CPU y" so we can more easily replace the implementation. Signed-off-by: Peter Maydell Reviewed-by: Stafford Horne Message-id: 20201127225127.14770-3-peter.maydell@linaro.org --- hw/openrisc/openrisc_sim.c | 38 +++++++++++++++++++++----------------- 1 file changed, 21 insertions(+), 17 deletions(-) diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index a8adf6b70d7..75ba0f47444 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -52,8 +52,13 @@ static void main_cpu_reset(void *opaque) cpu_set_pc(cs, boot_info.bootstrap_pc); } =20 +static qemu_irq get_cpu_irq(OpenRISCCPU *cpus[], int cpunum, int irq_pin) +{ + return cpus[cpunum]->env.irq[irq_pin]; +} + static void openrisc_sim_net_init(hwaddr base, hwaddr descriptors, - int num_cpus, qemu_irq **cpu_irqs, + int num_cpus, OpenRISCCPU *cpus[], int irq_pin, NICInfo *nd) { DeviceState *dev; @@ -70,18 +75,18 @@ static void openrisc_sim_net_init(hwaddr base, hwaddr d= escriptors, qdev_prop_set_uint32(splitter, "num-lines", num_cpus); qdev_realize_and_unref(splitter, NULL, &error_fatal); for (i =3D 0; i < num_cpus; i++) { - qdev_connect_gpio_out(splitter, i, cpu_irqs[i][irq_pin]); + qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pi= n)); } sysbus_connect_irq(s, 0, qdev_get_gpio_in(splitter, 0)); } else { - sysbus_connect_irq(s, 0, cpu_irqs[0][irq_pin]); + sysbus_connect_irq(s, 0, get_cpu_irq(cpus, 0, irq_pin)); } sysbus_mmio_map(s, 0, base); sysbus_mmio_map(s, 1, descriptors); } =20 static void openrisc_sim_ompic_init(hwaddr base, int num_cpus, - qemu_irq **cpu_irqs, int irq_pin) + OpenRISCCPU *cpus[], int irq_pin) { DeviceState *dev; SysBusDevice *s; @@ -93,7 +98,7 @@ static void openrisc_sim_ompic_init(hwaddr base, int num_= cpus, s =3D SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(s, &error_fatal); for (i =3D 0; i < num_cpus; i++) { - sysbus_connect_irq(s, i, cpu_irqs[i][irq_pin]); + sysbus_connect_irq(s, i, get_cpu_irq(cpus, i, irq_pin)); } sysbus_mmio_map(s, 0, base); } @@ -136,26 +141,24 @@ static void openrisc_sim_init(MachineState *machine) { ram_addr_t ram_size =3D machine->ram_size; const char *kernel_filename =3D machine->kernel_filename; - OpenRISCCPU *cpu =3D NULL; + OpenRISCCPU *cpus[2] =3D {}; MemoryRegion *ram; - qemu_irq *cpu_irqs[2]; qemu_irq serial_irq; int n; unsigned int smp_cpus =3D machine->smp.cpus; =20 assert(smp_cpus >=3D 1 && smp_cpus <=3D 2); for (n =3D 0; n < smp_cpus; n++) { - cpu =3D OPENRISC_CPU(cpu_create(machine->cpu_type)); - if (cpu =3D=3D NULL) { + cpus[n] =3D OPENRISC_CPU(cpu_create(machine->cpu_type)); + if (cpus[n] =3D=3D NULL) { fprintf(stderr, "Unable to find CPU definition!\n"); exit(1); } - cpu_openrisc_pic_init(cpu); - cpu_irqs[n] =3D (qemu_irq *) cpu->env.irq; + cpu_openrisc_pic_init(cpus[n]); =20 - cpu_openrisc_clock_init(cpu); + cpu_openrisc_clock_init(cpus[n]); =20 - qemu_register_reset(main_cpu_reset, cpu); + qemu_register_reset(main_cpu_reset, cpus[n]); } =20 ram =3D g_malloc(sizeof(*ram)); @@ -164,15 +167,16 @@ static void openrisc_sim_init(MachineState *machine) =20 if (nd_table[0].used) { openrisc_sim_net_init(0x92000000, 0x92000400, smp_cpus, - cpu_irqs, 4, nd_table); + cpus, 4, nd_table); } =20 if (smp_cpus > 1) { - openrisc_sim_ompic_init(0x98000000, smp_cpus, cpu_irqs, 1); + openrisc_sim_ompic_init(0x98000000, smp_cpus, cpus, 1); =20 - serial_irq =3D qemu_irq_split(cpu_irqs[0][2], cpu_irqs[1][2]); + serial_irq =3D qemu_irq_split(get_cpu_irq(cpus, 0, 2), + get_cpu_irq(cpus, 1, 2)); } else { - serial_irq =3D cpu_irqs[0][2]; + serial_irq =3D get_cpu_irq(cpus, 0, 2); } =20 serial_mm_init(get_system_memory(), 0x90000000, 0, serial_irq, --=20 2.20.1 From nobody Thu Dec 18 13:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608064081; cv=none; d=zohomail.com; s=zohoarc; b=jZI38Bv8r/YnUD1a7y+wZwW2WwETzqxVQ6XDVrgSLlR2c6jxvhwLOD99xdDHPayz2cJmSHEXfYPewpr1bzDpM5UfNYYMeFhdLmNWhsTTl+N5eU6+1j0mg1gWu19/DOeZZC32lNON3pm38xj1RQy0Dgnf/Ku+HYlXkTLDf/VVCVc= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w21sm19667319wmi.45.2020.12.15.06.12.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 06:12:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=0uGh6rZn+TxuLffZhBCIg1+EbECxHviBy9gau+xw4MA=; b=p5tQYOA+uQ2zl5KKTz/velFlp6r3haa+zaXdDj0xTXR8JT+U99FwD3JqjFF4ibuf3+ rryzOXuAYm4sZfRAGaEFtUZpaDAeU7xnJrloFbPCA3OhVKiecKKk0JWXgDJ0sif5NTLH GLgnplJh+qVcjMqi9chEurKGDUF3+GsTbEQU1tQUfBYwPaEh1W9kp0qi7zN9ndiqjO30 ccl9qTeyfLAfhoOR+QPVx4cYup7crEiByKsDLwm+PnS2b+Vq7D8lY4a0GiaDRJQsFW6W ln0LjvHZzOYMj0t/i6SEgJsIJtwLEaiEI6kCAz8Zw23Ayh8F0V/WlmoQm99ZkH/dJNJ5 1UwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0uGh6rZn+TxuLffZhBCIg1+EbECxHviBy9gau+xw4MA=; b=LFWM7mdqEgN0a3YrU/Riv+WeNY8BfDLs6U24Qab/WN+esf15EDZ9TXKgUBmKKeVrsG 0QbjCnUkAP8g3r/34dBTVheDuIWQxpQce2NpcekGPKgJlddbku1bu/zRGzpcVinvrOd/ jT/8PZAJh5Uc2x4LKyVDtg8MuVf0R4Znl8qwGRX+LCnVPfGPf3gz3zp9ycYVqWjMx2Mt dou0lJUUWkA+EfHgUtuKJoQHXq5MtzELQAsUIbSvQIXrJoDAFOvZNlb6pxmRyYOnmLT/ 6BcEEXh7al1kbXdidzBDcYxnYOzuSFki6ylqVyajyWBb/iYOJXWGbISSOnF152M5l7i5 PUGg== X-Gm-Message-State: AOAM530JDopwOr0ydyrVuYaeEeAnerl21AQ1RrG2GLllFLr86QZM8maD 0et7zjihPeJoVGX3XKdmKpbZxkQfGXev+Q== X-Google-Smtp-Source: ABdhPJzjjJW/mk3CCOeC2taH79ifVp1w1ns0sg16kZDZDVFbrrS0G9IBJimhIZPo1tKjnW17tQE9Yw== X-Received: by 2002:adf:8b09:: with SMTP id n9mr33276662wra.180.1608041564720; Tue, 15 Dec 2020 06:12:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/20] target/openrisc: Move pic_cpu code into CPU object proper Date: Tue, 15 Dec 2020 14:12:21 +0000 Message-Id: <20201215141237.17868-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201215141237.17868-1-peter.maydell@linaro.org> References: <20201215141237.17868-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The openrisc code uses an old style of interrupt handling, where a separate standalone set of qemu_irqs invoke a function openrisc_pic_cpu_handler() which signals the interrupt to the CPU proper by directly calling cpu_interrupt() and cpu_reset_interrupt(). Because CPU objects now inherit (indirectly) from TYPE_DEVICE, they can have GPIO input lines themselves, and the neater modern way to implement this is to simply have the CPU object itself provide the input IRQ lines. Create GPIO inputs to the OpenRISC CPU object, and make the only user of cpu_openrisc_pic_init() wire up directly to those instead. This allows us to delete the hw/openrisc/pic_cpu.c file entirely. This fixes a trivial memory leak reported by Coverity of the IRQs allocated in cpu_openrisc_pic_init(). Fixes: Coverity CID 1421934 Signed-off-by: Peter Maydell Reviewed-by: Stafford Horne Message-id: 20201127225127.14770-4-peter.maydell@linaro.org --- target/openrisc/cpu.h | 1 - hw/openrisc/openrisc_sim.c | 3 +- hw/openrisc/pic_cpu.c | 61 -------------------------------------- target/openrisc/cpu.c | 32 ++++++++++++++++++++ hw/openrisc/meson.build | 2 +- 5 files changed, 34 insertions(+), 65 deletions(-) delete mode 100644 hw/openrisc/pic_cpu.c diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index bd42faf144f..82cbaeb4f84 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -293,7 +293,6 @@ typedef struct CPUOpenRISCState { uint32_t picmr; /* Interrupt mask register */ uint32_t picsr; /* Interrupt contrl register*/ #endif - void *irq[32]; /* Interrupt irq input */ } CPUOpenRISCState; =20 /** diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index 75ba0f47444..39f1d344ae9 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -54,7 +54,7 @@ static void main_cpu_reset(void *opaque) =20 static qemu_irq get_cpu_irq(OpenRISCCPU *cpus[], int cpunum, int irq_pin) { - return cpus[cpunum]->env.irq[irq_pin]; + return qdev_get_gpio_in_named(DEVICE(cpus[cpunum]), "IRQ", irq_pin); } =20 static void openrisc_sim_net_init(hwaddr base, hwaddr descriptors, @@ -154,7 +154,6 @@ static void openrisc_sim_init(MachineState *machine) fprintf(stderr, "Unable to find CPU definition!\n"); exit(1); } - cpu_openrisc_pic_init(cpus[n]); =20 cpu_openrisc_clock_init(cpus[n]); =20 diff --git a/hw/openrisc/pic_cpu.c b/hw/openrisc/pic_cpu.c deleted file mode 100644 index 36f93508309..00000000000 --- a/hw/openrisc/pic_cpu.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * OpenRISC Programmable Interrupt Controller support. - * - * Copyright (c) 2011-2012 Jia Liu - * Feng Gao - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ - -#include "qemu/osdep.h" -#include "hw/irq.h" -#include "cpu.h" - -/* OpenRISC pic handler */ -static void openrisc_pic_cpu_handler(void *opaque, int irq, int level) -{ - OpenRISCCPU *cpu =3D (OpenRISCCPU *)opaque; - CPUState *cs =3D CPU(cpu); - uint32_t irq_bit; - - if (irq > 31 || irq < 0) { - return; - } - - irq_bit =3D 1U << irq; - - if (level) { - cpu->env.picsr |=3D irq_bit; - } else { - cpu->env.picsr &=3D ~irq_bit; - } - - if (cpu->env.picsr & cpu->env.picmr) { - cpu_interrupt(cs, CPU_INTERRUPT_HARD); - } else { - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - cpu->env.picsr =3D 0; - } -} - -void cpu_openrisc_pic_init(OpenRISCCPU *cpu) -{ - int i; - qemu_irq *qi; - qi =3D qemu_allocate_irqs(openrisc_pic_cpu_handler, cpu, NR_IRQS); - - for (i =3D 0; i < NR_IRQS; i++) { - cpu->env.irq[i] =3D qi[i]; - } -} diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 5528c0918f4..b0bdfbe4fe2 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -65,6 +65,34 @@ static void openrisc_cpu_reset(DeviceState *dev) #endif } =20 +#ifndef CONFIG_USER_ONLY +static void openrisc_cpu_set_irq(void *opaque, int irq, int level) +{ + OpenRISCCPU *cpu =3D (OpenRISCCPU *)opaque; + CPUState *cs =3D CPU(cpu); + uint32_t irq_bit; + + if (irq > 31 || irq < 0) { + return; + } + + irq_bit =3D 1U << irq; + + if (level) { + cpu->env.picsr |=3D irq_bit; + } else { + cpu->env.picsr &=3D ~irq_bit; + } + + if (cpu->env.picsr & cpu->env.picmr) { + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + cpu->env.picsr =3D 0; + } +} +#endif + static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -88,6 +116,10 @@ static void openrisc_cpu_initfn(Object *obj) OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); =20 cpu_set_cpustate_pointers(cpu); + +#ifndef CONFIG_USER_ONLY + qdev_init_gpio_in_named(DEVICE(cpu), openrisc_cpu_set_irq, "IRQ", NR_I= RQS); +#endif } =20 /* CPU models */ diff --git a/hw/openrisc/meson.build b/hw/openrisc/meson.build index 57c42558e18..947f63ee087 100644 --- a/hw/openrisc/meson.build +++ b/hw/openrisc/meson.build @@ -1,5 +1,5 @@ openrisc_ss =3D ss.source_set() -openrisc_ss.add(files('pic_cpu.c', 'cputimer.c')) +openrisc_ss.add(files('cputimer.c')) openrisc_ss.add(when: 'CONFIG_OR1K_SIM', if_true: files('openrisc_sim.c')) =20 hw_arch +=3D {'openrisc': openrisc_ss} --=20 2.20.1 From nobody Thu Dec 18 13:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608041693; cv=none; d=zohomail.com; s=zohoarc; b=f3zn3kLXbwt6/09Natzxxojgp4BTSJqN4tGMke/raTKKoSw0LqC6eMnD3FwYaUmKnZU1mmTn+8T/I9f9vHb8kKcNKKycRjArH8TOBs3kaR8tjDDznFi3QGwTn0vDzhpeEtPrhVdy4RXDiyryZwcUl0HhHZNTRopeiVhQ8iQaZUg= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w21sm19667319wmi.45.2020.12.15.06.12.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 06:12:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=YmzmWI7qeCjylLL96J2HXl5KV2fYM+123qW0myuYRfc=; b=XDGvEzgFuY2yrz+YWQiH4lASfgVJnhh5slc/vc8NAegDk4iLvvo+24K4lqAAapisL7 0Pwbn4MHZ7XrNFh+/j02sb0bB30i9qvCO5yeHqG874aR/U2FfZO2QH11SW+xtmmtLenR wsNmO44546EDJxG7UYd37hgteOX3AbVbv2LDMU8fzKCK0eVvtrugPlj9ya51H6AhEBts a86NtbHXsNanl/D+6QIHin2s33osIwLbNNU87nDd+tRSI++TNWkQcdhxjQ9dGtPweFew tTQJPseT/vEBCWT7FiXOgtccZHRIIeHU/p6rL1p9Rv83jnu7ugOQjfP8mG2o4IVbuKDu iIMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YmzmWI7qeCjylLL96J2HXl5KV2fYM+123qW0myuYRfc=; b=XkL/oannFKCmhnw9FRJAMBsRa0zRT9clG5CFKe/nRKLVunOCs+JuCYdh2qhpWI2byO yLn5ZcIsvQ6veRWtJLiJxdv39adUdbYB1uwgFxjXk/Yqj1ftRn2WonXuJ4wtvCKkVtur UckrbU8RTq1YkUxOT8KXwqP0BuOt14fF2LkbGK7VA5wNBlFNDwETWCio/VhcIxX/JAK/ QOL78nBFpvS4EX917AZAYM+sBDG0vcLyKwIUImQzVJ7Dfa/AT8MZMcppDT/nhCXKSn+3 l2YkGgBNxOwuWh33MKGHVT7m5VGcsJQz6pIw3O63QirHf7/JcHdQlp+B1y7j5o+KV3ed Tv+g== X-Gm-Message-State: AOAM532ELlTKtEdyEGRK+uL/nDHPUiY7B+QWGIvUhcuaz0vT+52r4NUE OzIfbv/RSaE0uz2QVb8pSmI8SQEq1LWnSw== X-Google-Smtp-Source: ABdhPJzqH7Y+llG1pfOMLZ5qCvpL9VrsU4SM+pi8+/tkgdORvYymbi6eG4tC4hFmAVAQcUwx1B3y7w== X-Received: by 2002:a1c:3d55:: with SMTP id k82mr32465176wma.57.1608041565892; Tue, 15 Dec 2020 06:12:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/20] target/nios2: Move IIC code into CPU object proper Date: Tue, 15 Dec 2020 14:12:22 +0000 Message-Id: <20201215141237.17868-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201215141237.17868-1-peter.maydell@linaro.org> References: <20201215141237.17868-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) The Nios2 architecture supports two different interrupt controller options: * The IIC (Internal Interrupt Controller) is part of the CPU itself; it has 32 IRQ input lines and no NMI support. Interrupt status is queried and controlled via the CPU's ipending and istatus registers. * The EIC (External Interrupt Controller) interface allows the CPU to connect to an external interrupt controller. The interface allows the interrupt controller to present a packet of information containing: - handler address - interrupt level - register set - NMI mode QEMU does not model an EIC currently. We do model the IIC, but its implementation is split across code in hw/nios2/cpu_pic.c and hw/intc/nios2_iic.c. The code in those two files has no state of its own -- the IIC state is in the Nios2CPU state struct. Because CPU objects now inherit (indirectly) from TYPE_DEVICE, they can have GPIO input lines themselves, so we can implement the IIC directly in the CPU object the same way that real hardware does. Create named "IRQ" GPIO inputs to the Nios2 CPU object, and make the only user of the IIC wire up directly to those instead. Note that the old code had an "NMI" concept which was entirely unused and also as far as I can see not architecturally correct, since only the EIC has a concept of an NMI. This fixes a Coverity-reported trivial memory leak of the IRQ array allocated in nios2_cpu_pic_init(). Fixes: Coverity CID 1421916 Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20201129174022.26530-2-peter.maydell@linaro.org Reviewed-by: Wentong Wu Tested-by: Wentong Wu --- target/nios2/cpu.h | 1 - hw/intc/nios2_iic.c | 95 --------------------------------------- hw/nios2/10m50_devboard.c | 13 +----- hw/nios2/cpu_pic.c | 31 ------------- target/nios2/cpu.c | 30 +++++++++++++ MAINTAINERS | 1 - hw/intc/meson.build | 1 - 7 files changed, 32 insertions(+), 140 deletions(-) delete mode 100644 hw/intc/nios2_iic.c diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 86bbe1d8670..b7efb54ba7e 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -201,7 +201,6 @@ void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr= addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); =20 -qemu_irq *nios2_cpu_pic_init(Nios2CPU *cpu); void nios2_check_interrupts(CPUNios2State *env); =20 void do_nios2_semihosting(CPUNios2State *env); diff --git a/hw/intc/nios2_iic.c b/hw/intc/nios2_iic.c deleted file mode 100644 index 216db670594..00000000000 --- a/hw/intc/nios2_iic.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * QEMU Altera Internal Interrupt Controller. - * - * Copyright (c) 2012 Chris Wulff - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see - * - */ - -#include "qemu/osdep.h" -#include "qemu/module.h" -#include "qapi/error.h" - -#include "hw/irq.h" -#include "hw/sysbus.h" -#include "cpu.h" -#include "qom/object.h" - -#define TYPE_ALTERA_IIC "altera,iic" -OBJECT_DECLARE_SIMPLE_TYPE(AlteraIIC, ALTERA_IIC) - -struct AlteraIIC { - SysBusDevice parent_obj; - void *cpu; - qemu_irq parent_irq; -}; - -static void update_irq(AlteraIIC *pv) -{ - CPUNios2State *env =3D &((Nios2CPU *)(pv->cpu))->env; - - qemu_set_irq(pv->parent_irq, - env->regs[CR_IPENDING] & env->regs[CR_IENABLE]); -} - -static void irq_handler(void *opaque, int irq, int level) -{ - AlteraIIC *pv =3D opaque; - CPUNios2State *env =3D &((Nios2CPU *)(pv->cpu))->env; - - env->regs[CR_IPENDING] &=3D ~(1 << irq); - env->regs[CR_IPENDING] |=3D !!level << irq; - - update_irq(pv); -} - -static void altera_iic_init(Object *obj) -{ - AlteraIIC *pv =3D ALTERA_IIC(obj); - - qdev_init_gpio_in(DEVICE(pv), irq_handler, 32); - sysbus_init_irq(SYS_BUS_DEVICE(obj), &pv->parent_irq); -} - -static void altera_iic_realize(DeviceState *dev, Error **errp) -{ - struct AlteraIIC *pv =3D ALTERA_IIC(dev); - - pv->cpu =3D object_property_get_link(OBJECT(dev), "cpu", &error_abort); -} - -static void altera_iic_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(klass); - - /* Reason: needs to be wired up, e.g. by nios2_10m50_ghrd_init() */ - dc->user_creatable =3D false; - dc->realize =3D altera_iic_realize; -} - -static TypeInfo altera_iic_info =3D { - .name =3D TYPE_ALTERA_IIC, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(AlteraIIC), - .instance_init =3D altera_iic_init, - .class_init =3D altera_iic_class_init, -}; - -static void altera_iic_register(void) -{ - type_register_static(&altera_iic_info); -} - -type_init(altera_iic_register) diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c index 5c13b74306f..a14fc31e86b 100644 --- a/hw/nios2/10m50_devboard.c +++ b/hw/nios2/10m50_devboard.c @@ -52,7 +52,7 @@ static void nios2_10m50_ghrd_init(MachineState *machine) ram_addr_t tcm_size =3D 0x1000; /* 1 kiB, but QEMU limit is 4 kiB */ ram_addr_t ram_base =3D 0x08000000; ram_addr_t ram_size =3D 0x08000000; - qemu_irq *cpu_irq, irq[32]; + qemu_irq irq[32]; int i; =20 /* Physical TCM (tb_ram_1k) with alias at 0xc0000000 */ @@ -75,17 +75,8 @@ static void nios2_10m50_ghrd_init(MachineState *machine) =20 /* Create CPU -- FIXME */ cpu =3D NIOS2_CPU(cpu_create(TYPE_NIOS2_CPU)); - - /* Register: CPU interrupt controller (PIC) */ - cpu_irq =3D nios2_cpu_pic_init(cpu); - - /* Register: Internal Interrupt Controller (IIC) */ - dev =3D qdev_new("altera,iic"); - object_property_add_const_link(OBJECT(dev), "cpu", OBJECT(cpu)); - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]); for (i =3D 0; i < 32; i++) { - irq[i] =3D qdev_get_gpio_in(dev, i); + irq[i] =3D qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", i); } =20 /* Register: Altera 16550 UART */ diff --git a/hw/nios2/cpu_pic.c b/hw/nios2/cpu_pic.c index 5ea7e52ab83..3fb621c5c85 100644 --- a/hw/nios2/cpu_pic.c +++ b/hw/nios2/cpu_pic.c @@ -26,32 +26,6 @@ =20 #include "boot.h" =20 -static void nios2_pic_cpu_handler(void *opaque, int irq, int level) -{ - Nios2CPU *cpu =3D opaque; - CPUNios2State *env =3D &cpu->env; - CPUState *cs =3D CPU(cpu); - int type =3D irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD; - - if (type =3D=3D CPU_INTERRUPT_HARD) { - env->irq_pending =3D level; - - if (level && (env->regs[CR_STATUS] & CR_STATUS_PIE)) { - env->irq_pending =3D 0; - cpu_interrupt(cs, type); - } else if (!level) { - env->irq_pending =3D 0; - cpu_reset_interrupt(cs, type); - } - } else { - if (level) { - cpu_interrupt(cs, type); - } else { - cpu_reset_interrupt(cs, type); - } - } -} - void nios2_check_interrupts(CPUNios2State *env) { if (env->irq_pending && @@ -60,8 +34,3 @@ void nios2_check_interrupts(CPUNios2State *env) cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HARD); } } - -qemu_irq *nios2_cpu_pic_init(Nios2CPU *cpu) -{ - return qemu_allocate_irqs(nios2_pic_cpu_handler, cpu, 2); -} diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 8f7011fcb92..52ebda89ca7 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -64,6 +64,27 @@ static void nios2_cpu_reset(DeviceState *dev) #endif } =20 +#ifndef CONFIG_USER_ONLY +static void nios2_cpu_set_irq(void *opaque, int irq, int level) +{ + Nios2CPU *cpu =3D opaque; + CPUNios2State *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); + + env->regs[CR_IPENDING] &=3D ~(1 << irq); + env->regs[CR_IPENDING] |=3D !!level << irq; + + env->irq_pending =3D env->regs[CR_IPENDING] & env->regs[CR_IENABLE]; + + if (env->irq_pending && (env->regs[CR_STATUS] & CR_STATUS_PIE)) { + env->irq_pending =3D 0; + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } else if (!env->irq_pending) { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } +} +#endif + static void nios2_cpu_initfn(Object *obj) { Nios2CPU *cpu =3D NIOS2_CPU(obj); @@ -72,6 +93,15 @@ static void nios2_cpu_initfn(Object *obj) =20 #if !defined(CONFIG_USER_ONLY) mmu_init(&cpu->env); + + /* + * These interrupt lines model the IIC (internal interrupt + * controller). QEMU does not currently support the EIC + * (external interrupt controller) -- if we did it would be + * a separate device in hw/intc with a custom interface to + * the CPU, and boards using it would not wire up these IRQ lines. + */ + qdev_init_gpio_in_named(DEVICE(cpu), nios2_cpu_set_irq, "IRQ", 32); #endif } =20 diff --git a/MAINTAINERS b/MAINTAINERS index 062074e47cd..99293a5e027 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -259,7 +259,6 @@ M: Marek Vasut S: Maintained F: target/nios2/ F: hw/nios2/ -F: hw/intc/nios2_iic.c F: disas/nios2.c F: default-configs/nios2-softmmu.mak =20 diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 3f82cc230ad..7c3e9daf586 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -37,7 +37,6 @@ specific_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex= _plic.c')) specific_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic.c')) specific_ss.add(when: 'CONFIG_LOONGSON_LIOINTC', if_true: files('loongson_= liointc.c')) specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_gic.c')) -specific_ss.add(when: 'CONFIG_NIOS2', if_true: files('nios2_iic.c')) specific_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_intc.c')) specific_ss.add(when: 'CONFIG_OMPIC', if_true: files('ompic.c')) specific_ss.add(when: 'CONFIG_OPENPIC_KVM', if_true: files('openpic_kvm.c'= )) --=20 2.20.1 From nobody Thu Dec 18 13:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608067692; cv=none; d=zohomail.com; s=zohoarc; b=Q8LmuRFUsY0QCQEYIv6OkkyUgBoS6+qhZUrIbcFxgZnTTAOPyhOHaXpBlnquDw28e+Yx9wOslJB42XjISqZM3nhc0zGZiG50qyzbXjzrqaeIaqm2FtmiPXViHxAZ8vtIhWnfrgpfBXJwbiiufEA/oP2H/sOUwjKDGmWssJqwk8c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608067692; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0KcOmRFODdzl37ZYt1is0h9nvS6eEXO8j+QkYIiR94Y=; b=N4DdWdT3Hrw72AeuWl1aDXHQU0J3nHVlRWcsa1VHnZVN6TuyCLl95ShoRXdldyYq6sPYN7GTtIsWEmSBP4pwuKh8OZDmw/eCttl8SUXz7KdGH2/gYMV0mfNRvvk8pt1diNgI173NRRKj0QE6MLMngdMne8AZCEUxlmFnoEOEqp8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1608067692321476.19717739081943; Tue, 15 Dec 2020 13:28:12 -0800 (PST) Received: from localhost ([::1]:51596 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kpB8h-00067r-8V for importer@patchew.org; Tue, 15 Dec 2020 09:17:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34048) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kpB4X-0001Xq-9e for qemu-devel@nongnu.org; Tue, 15 Dec 2020 09:13:01 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:34860) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kpB4K-00078D-RS for qemu-devel@nongnu.org; Tue, 15 Dec 2020 09:13:00 -0500 Received: by mail-wm1-x32e.google.com with SMTP id e25so18631057wme.0 for ; Tue, 15 Dec 2020 06:12:48 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w21sm19667319wmi.45.2020.12.15.06.12.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 06:12:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=0KcOmRFODdzl37ZYt1is0h9nvS6eEXO8j+QkYIiR94Y=; b=w5Ba2W46LqF1Vph4gFtWxj/K9UKzspYTmRhGGzTs5yoRklTwCwtHkdyCt+41hG/Ku8 55G/r/Py0vDP2Rh1PnQvcwkf5LW2ANCIN9cw+EpPq7HsEadZ6biuEEkY9xm3ZwWaF61M ENfqolnAORv+D342nSRwe5NKDkmX4AmjufSTIPGq03pyviXAYsu8gJG/wsCE2z/ryaFD 3O74NICLOs90V1tu70rDF66RnVIjlxGKMhpqpFDMWDdicwaTawguTs8+aUZjrlstNhDd EM3FzP66h/gGjnyp7UK7f8HSvyRA6GhaAmO2o+5TQ5cbFJdYaFveIKJ9T3xr5/iuKhCU Ae1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0KcOmRFODdzl37ZYt1is0h9nvS6eEXO8j+QkYIiR94Y=; b=rvWnD4IwE07wC80y9/TK+xHApsKXr4QPghBEfU5xcZysN78X9mcEZKijibsYObYJAX SDLUtkBKaYxPcnIfNEiIszSuL7cdtn4+PhbK4z5cePIttY+wCgNBNH+s8JyHFxansrlm DWqwLePfjskd1VZrKhIM5IF96JYoPENI4keHTn8Z0zBGWEuyQ9F/5EKvA0XDs0hnPccr io6Pyjai/HJusgUfdtkrtbq1oxZPNGhCQOZfncLOFvUvmP5S5BcUCT9P0Zi+KH5axbaM BMdLl2XZJ4zDv4VDhEwGmBR6FWxCBQUNkDD7frd4FnLhvIxwlj8D7CvznAM+JBzftmfj +DLA== X-Gm-Message-State: AOAM530uwYrFz1bYnTgaFhA3kzCO89Th+BBRNt2aeA6U0IouzPFdtPmc y3lPcHygv+//beEDTTnKZBpdehqOu2KIOw== X-Google-Smtp-Source: ABdhPJzc/wJuxJqu3RvO+aLAKPaoQi5QOWqV4cNn6FrL2c5Gi93CClsEMtSXg1/3FHgrPJidEZb9rQ== X-Received: by 2002:a1c:208f:: with SMTP id g137mr32521530wmg.67.1608041567228; Tue, 15 Dec 2020 06:12:47 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/20] target/nios2: Move nios2_check_interrupts() into target/nios2 Date: Tue, 15 Dec 2020 14:12:23 +0000 Message-Id: <20201215141237.17868-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201215141237.17868-1-peter.maydell@linaro.org> References: <20201215141237.17868-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) The function nios2_check_interrupts)() looks only at CPU-internal state; it belongs in target/nios2, not hw/nios2. Move it into the same file as its only caller, so it can just be local to that file. This removes the only remaining code from cpu_pic.c, so we can delete that file entirely. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20201129174022.26530-3-peter.maydell@linaro.org Reviewed-by: Wentong Wu Tested-by: Wentong Wu --- target/nios2/cpu.h | 2 -- hw/nios2/cpu_pic.c | 36 ------------------------------------ target/nios2/op_helper.c | 9 +++++++++ hw/nios2/meson.build | 2 +- 4 files changed, 10 insertions(+), 39 deletions(-) delete mode 100644 hw/nios2/cpu_pic.c diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index b7efb54ba7e..2ab82fdc713 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -201,8 +201,6 @@ void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr= addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); =20 -void nios2_check_interrupts(CPUNios2State *env); - void do_nios2_semihosting(CPUNios2State *env); =20 #define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU diff --git a/hw/nios2/cpu_pic.c b/hw/nios2/cpu_pic.c deleted file mode 100644 index 3fb621c5c85..00000000000 --- a/hw/nios2/cpu_pic.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Altera Nios2 CPU PIC - * - * Copyright (c) 2016 Marek Vasut - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see - * - */ - -#include "qemu/osdep.h" -#include "cpu.h" -#include "hw/irq.h" - -#include "qemu/config-file.h" - -#include "boot.h" - -void nios2_check_interrupts(CPUNios2State *env) -{ - if (env->irq_pending && - (env->regs[CR_STATUS] & CR_STATUS_PIE)) { - env->irq_pending =3D 0; - cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HARD); - } -} diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index a60730faac3..a59003855ab 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -36,6 +36,15 @@ void helper_mmu_write(CPUNios2State *env, uint32_t rn, u= int32_t v) mmu_write(env, rn, v); } =20 +static void nios2_check_interrupts(CPUNios2State *env) +{ + if (env->irq_pending && + (env->regs[CR_STATUS] & CR_STATUS_PIE)) { + env->irq_pending =3D 0; + cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HARD); + } +} + void helper_check_interrupts(CPUNios2State *env) { qemu_mutex_lock_iothread(); diff --git a/hw/nios2/meson.build b/hw/nios2/meson.build index dd66ebb32f6..6c58e8082b4 100644 --- a/hw/nios2/meson.build +++ b/hw/nios2/meson.build @@ -1,5 +1,5 @@ nios2_ss =3D ss.source_set() -nios2_ss.add(files('boot.c', 'cpu_pic.c')) +nios2_ss.add(files('boot.c')) nios2_ss.add(when: 'CONFIG_NIOS2_10M50', if_true: files('10m50_devboard.c'= )) nios2_ss.add(when: 'CONFIG_NIOS2_GENERIC_NOMMU', if_true: files('generic_n= ommu.c')) =20 --=20 2.20.1 From nobody Thu Dec 18 13:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608071601; cv=none; d=zohomail.com; s=zohoarc; b=P/OcBhiVlBw4kshP/Y2eVWYYPp0zOptjBzOKFOBYa6vOnWgN9RpV01Wa8YGh/pZaIcT6QxyH79nIxR+t1jfUJGdxkV21MPS9rMvgMYI4me7smCD3p1RMyha1wbTTTBUplBIGUJpKEwUFI2lwTKk2pIrChRi/e/BA3pZ05whcE4k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608071601; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cV37AyuORR0cd6TAg8TEpeOVqKh0IrbO2oTQtbw3vqA=; b=Z4rZAP+62EjMkeoqsLUbIdCzOEL57pvunZu5psNslQmeZyRkpvuN/wglPnZ+HpGyC9K68Fo6bDRtgpgNfSaB4DvSuY9G1l+vwexRe4LR4s4+djB1wxSeCUO5AzJmdbf+OEKo4MeTvCwu20qL5zo3TdIYeqEANEuNCQcTePU4yd8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1608071601017294.77139627111353; Tue, 15 Dec 2020 14:33:21 -0800 (PST) Received: from localhost ([::1]:41080 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kpBDf-0004zf-Nz for importer@patchew.org; Tue, 15 Dec 2020 09:22:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33986) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kpB4Q-0001Sb-PX for qemu-devel@nongnu.org; Tue, 15 Dec 2020 09:12:58 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:53570) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kpB4M-00078M-76 for qemu-devel@nongnu.org; Tue, 15 Dec 2020 09:12:54 -0500 Received: by mail-wm1-x32f.google.com with SMTP id k10so17010715wmi.3 for ; Tue, 15 Dec 2020 06:12:49 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w21sm19667319wmi.45.2020.12.15.06.12.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 06:12:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=cV37AyuORR0cd6TAg8TEpeOVqKh0IrbO2oTQtbw3vqA=; b=NlmkWISd/OHV5re3yEMDxBJ9ZKTCPHrV3FuUw1zArhT3wX9E52/+P/Ep9TIH1lb0lv 7x7v1V64Bb1XKZAIpe6MBMfNESlgRJsZ/IT/5Q5wp2asH3Pcs+5bZo+PpKBGHCVYjs8P OJTZSHG3Z201sTUoJgGTLidEOXIjLyOHb4uZaPuQB0QwGSrXVZGSJlc0NVK19j+PWxJl U98PBE83m7Ly6Gsp/XQy4tMq5KtYypTBtcrPTWdam/U887Z5yOLwxAk+AKUYBoE6Ut9A H3uP1IfEfcIImQ666MkrqjOLU2EMQjeCJATfSyJFTxFsKnZm8582XrShqGRmITMc4WqN a+eQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cV37AyuORR0cd6TAg8TEpeOVqKh0IrbO2oTQtbw3vqA=; b=QjsUsn506ykStNCDgqMeIa+BlcPINIIjipOpEjd1qXP8EdU1ybSUuIJs+ZluxUOsBC yJsGSUniz0y9rbLGsmrJQggrsdsyDvlSVL6Hlv1U8ra5ZUXOIWyj7QYDOGdEncaJpNP/ VscGVre9BFz6ptE7wEBHJfHRe0GJ0c9Tz4Pvc8PXHstvxd9kEBrGr0GQ7Zpk0G30AJFE XzihmmgqxzHK4alGKr5EAG/T15Yx3nm2if5qcNUHrcgnUHKPv6fEmpUI3e30D8Jqj90K 40mz5ilWVMvL9z7Lbg+mf8HuzJR15Q++8cJvTDLqKWnufGBJVstusxlrVJS1LuXhEQ8S crig== X-Gm-Message-State: AOAM532KDCPruIowShk1/NC/SASNKyQ8IBJZPvj1OaHI2nHVYn6NLSRl HmshUgiDDpEc3VgdFWcbWsmGFYzLMFod+Q== X-Google-Smtp-Source: ABdhPJzs3Lmh4WriffN4IYM9lgzUHQJbofkElMGJL55TdiTNmey+yUAuwBrO87jvfsGMKeZrVwD3Lw== X-Received: by 2002:a7b:cc0f:: with SMTP id f15mr33362122wmh.29.1608041568203; Tue, 15 Dec 2020 06:12:48 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/20] target/nios2: Use deposit32() to update ipending register Date: Tue, 15 Dec 2020 14:12:24 +0000 Message-Id: <20201215141237.17868-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201215141237.17868-1-peter.maydell@linaro.org> References: <20201215141237.17868-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) In nios2_cpu_set_irq(), use deposit32() rather than raw shift-and-mask operations to set the appropriate bit in the ipending register. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20201129174022.26530-4-peter.maydell@linaro.org --- target/nios2/cpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 52ebda89ca7..58688e1623a 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -71,8 +71,7 @@ static void nios2_cpu_set_irq(void *opaque, int irq, int = level) CPUNios2State *env =3D &cpu->env; CPUState *cs =3D CPU(cpu); =20 - env->regs[CR_IPENDING] &=3D ~(1 << irq); - env->regs[CR_IPENDING] |=3D !!level << irq; + env->regs[CR_IPENDING] =3D deposit32(env->regs[CR_IPENDING], irq, 1, != !level); =20 env->irq_pending =3D env->regs[CR_IPENDING] & env->regs[CR_IENABLE]; =20 --=20 2.20.1 From nobody Thu Dec 18 13:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608046145; cv=none; d=zohomail.com; s=zohoarc; b=VInTU/xUfDdSrkLjHihw2m1RmkLNqe6CbVsQR7OF1mp4P66mF54Bw6f7zktGFcT1u2zogP9AvEE+akMftsEbJLzcd2E1OnWkaLLOioyFn18JZ6eSOkDtOwi2dm8LjTgUTOvPrVhMEfOFqPE5T3Q0gl7mbuauMGObLg2A1Dv8vCA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608046145; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MHT0mJa3dVWHtx0F9Sj68FS/nEuDFGtpOb6OtVQv3Mg=; b=nlSybuUyjhtolUypUV8c5BJxZo+0axm4UR4IAScn5khdyUWOmqp6So6sKZBYfA1HLbyeBpo5ZxYkXnIIPDeyJhYBGwaTJ5RCkpwYHs+Ee5j4PRkW+cwFfvRJJ1aPb1jL8XU1IeHEdTPn+QO3LDizNBkRnoQeiGoX2GKl04b7jgs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1608046145754107.90689175644536; Tue, 15 Dec 2020 07:29:05 -0800 (PST) Received: from localhost ([::1]:44790 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kpBEU-0006U6-Du for importer@patchew.org; Tue, 15 Dec 2020 09:23:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34054) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kpB4X-0001YS-Mu for qemu-devel@nongnu.org; Tue, 15 Dec 2020 09:13:03 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:53573) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kpB4M-00079G-U7 for qemu-devel@nongnu.org; Tue, 15 Dec 2020 09:13:01 -0500 Received: by mail-wm1-x332.google.com with SMTP id k10so17010761wmi.3 for ; Tue, 15 Dec 2020 06:12:50 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w21sm19667319wmi.45.2020.12.15.06.12.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 06:12:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=MHT0mJa3dVWHtx0F9Sj68FS/nEuDFGtpOb6OtVQv3Mg=; b=fs/a2RbcQS1ecuMocKAv4fzSPQkGmjuzhyaWmMNHR2h7Gv+gWLNDjZ4JfPJRMYHaSb PcdH47wijdoF4yB6Y7VCSYZ4a+bG3xw1fFMH9AZopdbwAIUfEuBVqwOffaDOdj+zg03k ht5yQEbijnxXAZtmkHVxEy19YvikDeJ2f2d4c/+MZb4Ch4qco1T6XorZ5B05JR0aIIgP VkCqM1aBetZ4SjAeZnejymlPW/tFvpvznH/yo/T4QA0golUlpctLkn59UXVpee/ISP5g +F/wPkzBd/XXBFvlxBgjsnvAF7kvBLxodUOCN4bvP6+Q7xBBQvYSbAeM/Wc5OTHRWrbu HVkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MHT0mJa3dVWHtx0F9Sj68FS/nEuDFGtpOb6OtVQv3Mg=; b=h8C7EmJ/+O0ml3wl0usTFhEgUAGtKZZR74VLTmrC7rdvysqEIzqhkBNtryq4bku9RY tRSo86btOj0RLO9McUjATCOzaLDk5aqtIRE2eTGdT8UMqNOfRij+smSjr0Oe0qzg1NyG DCKhOsbnZlF85bnw2USu+kIsCRIscee75pqI9iCUWXOUnq/x/EX5f9FWefhkhKnIYj56 CsUO/Wurpx15RhSy/eAX6iMrQOAwaI09m6se2WvNelMfk6UIEiapUmGm5tQnwYX5/bQH R1WfaeAwH5W6vmrCC7FCvdsX8Ghfqzna5gPIbwYy+MqgB7fqumkA3LL42nulsgq6As6X vSjA== X-Gm-Message-State: AOAM532MfuQlcioZkjdLlNrur+qWqvs7g7SnA+rmpSqHVjVN1bwggf8M mvP/OKApZ4mS8uE3nJMRiJOhOQBmAKBWWg== X-Google-Smtp-Source: ABdhPJzROBP5Sb0iIg2OlKYJaHbzflwBrR34ndh2ytOxCpafrrHrAE3cDgeqPb+nyQngZ2aTmZ7jkw== X-Received: by 2002:a1c:3987:: with SMTP id g129mr32408437wma.86.1608041569224; Tue, 15 Dec 2020 06:12:49 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/20] hw/core/loader.c: Track last-seen ROM in rom_check_and_register_reset() Date: Tue, 15 Dec 2020 14:12:25 +0000 Message-Id: <20201215141237.17868-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201215141237.17868-1-peter.maydell@linaro.org> References: <20201215141237.17868-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In rom_check_and_register_reset() we detect overlaps by looking at whether the ROM blob we're currently examining is in the same address space and starts before the previous ROM blob ends. (This works because the ROM list is kept sorted in order by AddressSpace and then by address.) Instead of keeping the AddressSpace and last address of the previous ROM blob in local variables, just keep a pointer to it. This will allow us to print more useful information when we do detect an overlap. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201129203923.10622-2-peter.maydell@linaro.org --- hw/core/loader.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/hw/core/loader.c b/hw/core/loader.c index fea22d265c7..45aaba6158b 100644 --- a/hw/core/loader.c +++ b/hw/core/loader.c @@ -1166,28 +1166,35 @@ static void rom_reset(void *unused) } } =20 +/* Return true if two consecutive ROMs in the ROM list overlap */ +static bool roms_overlap(Rom *last_rom, Rom *this_rom) +{ + if (!last_rom) { + return false; + } + return last_rom->as =3D=3D this_rom->as && + last_rom->addr + last_rom->romsize > this_rom->addr; +} + int rom_check_and_register_reset(void) { - hwaddr addr =3D 0; MemoryRegionSection section; - Rom *rom; - AddressSpace *as =3D NULL; + Rom *rom, *last_rom =3D NULL; =20 QTAILQ_FOREACH(rom, &roms, next) { if (rom->fw_file) { continue; } if (!rom->mr) { - if ((addr > rom->addr) && (as =3D=3D rom->as)) { + if (roms_overlap(last_rom, rom)) { fprintf(stderr, "rom: requested regions overlap " "(rom %s. free=3D0x" TARGET_FMT_plx ", addr=3D0x" TARGET_FMT_plx ")\n", - rom->name, addr, rom->addr); + rom->name, last_rom->addr + last_rom->romsize, + rom->addr); return -1; } - addr =3D rom->addr; - addr +=3D rom->romsize; - as =3D rom->as; + last_rom =3D rom; } section =3D memory_region_find(rom->mr ? rom->mr : get_system_memo= ry(), rom->addr, 1); --=20 2.20.1 From nobody Thu Dec 18 13:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608041698; cv=none; d=zohomail.com; s=zohoarc; b=MsckONcpNIuIiwqYrQZorHsbqiNct/+rPOjfeSxMFkMte0q93ovXt3YoABqcFURKD5VWOda7hXzUjgFTtValDMNyj3M3iJzTBYcUmK7NPggK+BSCxTnoNxHAkprXwyGfNGBesPw+8NV94g9b4jNLI5+0IgqSlpJNVWydqEbEhh4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608041698; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=TM8X4iK9h8+8ZfJgrQHMpFiW1HdJJ6sLTcGF4MsNIDg=; b=azlLTTvD2IzREdoaDrZTJHUA+lgMAvRH5LLsPdgyS5RlTX2agpnp14Ux2dI1MTlVG6KxXC3ScYDlBcp+ka/Bpc8WgVCIvRC7TzNG0rqjaE1jS8uJm/t+jba0dMAyNb0wpE4FvEGh6KXoaKUdSk52sDRHP2vYo7WJ+etvqYhyNZg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1608041698638634.4468464102843; Tue, 15 Dec 2020 06:14:58 -0800 (PST) Received: from localhost ([::1]:44580 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kpB6M-0003D3-36 for importer@patchew.org; Tue, 15 Dec 2020 09:14:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34042) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kpB4X-0001XH-1B for qemu-devel@nongnu.org; Tue, 15 Dec 2020 09:13:01 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:39561) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kpB4O-00079V-2e for qemu-devel@nongnu.org; Tue, 15 Dec 2020 09:13:00 -0500 Received: by mail-wm1-x335.google.com with SMTP id 3so18629084wmg.4 for ; Tue, 15 Dec 2020 06:12:51 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w21sm19667319wmi.45.2020.12.15.06.12.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 06:12:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=TM8X4iK9h8+8ZfJgrQHMpFiW1HdJJ6sLTcGF4MsNIDg=; b=fenOcJyx6Z/3UBwYIKvLsB74CgcRDpY9JtrMQMQpDtYUPlw2nOvv4eXgmFQG8MshGe eQMh+hojEguSaDu/2pwT965B4PIS3ruJn1q86yNy+wWFlmi4F2vaXTaRPA9JtKeF84+Z RsO+YE+6cVebCqD+pshD7K8e4S+mL2P4JhO4VSy8IMdQClO9/sLGFad9Qd4qBbd4gHmP e6iXPstsmP4SnMXFhzsTJBF/z17/RhSdMdoGseA4eYvPDXt3ZYQc69hS4qn/NrXbQk2H i2RfD6Kt5lZ6uwh4TdEJRpKxshxnl/bjdUFe3GrjWzado1jwL5fG7kuY4z6Dk/9xnYDG 5VXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TM8X4iK9h8+8ZfJgrQHMpFiW1HdJJ6sLTcGF4MsNIDg=; b=n6JlbjuJjLzZU9/XyVx3rBBQ3fWq3vlS5oHXro7x6LVH4GWY34PNeL/wgveTjppG6p bPTaZspWc0q+ODIX2f6Atm52SabPlgBrDXpnU2f/lRcqoblj9LvjNLPF8EBXe0mwghv6 q2xSAcwhruuTWSIpte+mlqS8m1HPQzQ9U9NgA5j+V5BzdTzRMvvInET+WBaDsjwYXLPo woveEX2gHv8Ff52bxlCVAsVNnAWJdxw7ScFjOYZaFdN3ivRgRgwRBVGjbWIoztQ5VlXO JOdrZgUz1elICw61Vcej97dLOa4mtyPRN02ZcUSvhOkC346CS1TSZ9UBeskc++lwkLQ5 BH6Q== X-Gm-Message-State: AOAM533IoS0zi4X8ic735aPRevrzpkJ+Fo83N/3SeMs4FEdz7Pr21VFQ bR5PfYsw0EzI07+1ezfxK1xslNaq+/+UBw== X-Google-Smtp-Source: ABdhPJxs8fpIqHVAcDX4DD7qog815XYySThfHx4tre3ytXdktyxVDKpGtiCuCCm5WTU21JZWxoB+Cw== X-Received: by 2002:a1c:6746:: with SMTP id b67mr32936746wmc.8.1608041570396; Tue, 15 Dec 2020 06:12:50 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/20] hw/core/loader.c: Improve reporting of ROM overlap errors Date: Tue, 15 Dec 2020 14:12:26 +0000 Message-Id: <20201215141237.17868-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201215141237.17868-1-peter.maydell@linaro.org> References: <20201215141237.17868-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In rom_check_and_register_reset() we report to the user if there is a "ROM region overlap". This has a couple of problems: * the reported information is not very easy to intepret * the function just prints the overlap to stderr (and relies on its single callsite in vl.c to do an error_report() and exit) * only the first overlap encountered is diagnosed Make this function use error_report() and error_printf() and report a more user-friendly report with all the overlaps diagnosed. Sample old output: rom: requested regions overlap (rom dtb. free=3D0x0000000000008000, addr=3D= 0x0000000000000000) qemu-system-aarch64: rom check and register reset failed Sample new output: qemu-system-aarch64: Some ROM regions are overlapping These ROM regions might have been loaded by direct user request or by defau= lt. They could be BIOS/firmware images, a guest kernel, initrd or some other fi= le loaded into guest memory. Check whether you intended to load all this guest code, and whether it has = been built to load to the correct addresses. The following two regions overlap (in the cpu-memory-0 address space): phdr #0: /home/petmay01/linaro/qemu-misc-tests/ldmia-fault.axf (addresses= 0x0000000000000000 - 0x0000000000008000) dtb (addresses 0x0000000000000000 - 0x0000000000100000) The following two regions overlap (in the cpu-memory-0 address space): phdr #1: /home/petmay01/linaro/qemu-misc-tests/bad-psci-call.axf (address= es 0x0000000040000000 - 0x0000000040000010) phdr #0: /home/petmay01/linaro/qemu-misc-tests/bp-test.elf (addresses 0x0= 000000040000000 - 0x0000000040000020) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201129203923.10622-3-peter.maydell@linaro.org --- hw/core/loader.c | 48 ++++++++++++++++++++++++++++++++++++++++++------ softmmu/vl.c | 1 - 2 files changed, 42 insertions(+), 7 deletions(-) diff --git a/hw/core/loader.c b/hw/core/loader.c index 45aaba6158b..9feca32de98 100644 --- a/hw/core/loader.c +++ b/hw/core/loader.c @@ -1176,10 +1176,42 @@ static bool roms_overlap(Rom *last_rom, Rom *this_r= om) last_rom->addr + last_rom->romsize > this_rom->addr; } =20 +static const char *rom_as_name(Rom *rom) +{ + const char *name =3D rom->as ? rom->as->name : NULL; + return name ?: "anonymous"; +} + +static void rom_print_overlap_error_header(void) +{ + error_report("Some ROM regions are overlapping"); + error_printf( + "These ROM regions might have been loaded by " + "direct user request or by default.\n" + "They could be BIOS/firmware images, a guest kernel, " + "initrd or some other file loaded into guest memory.\n" + "Check whether you intended to load all this guest code, and " + "whether it has been built to load to the correct addresses.\n"); +} + +static void rom_print_one_overlap_error(Rom *last_rom, Rom *rom) +{ + error_printf( + "\nThe following two regions overlap (in the %s address space):\n", + rom_as_name(rom)); + error_printf( + " %s (addresses 0x" TARGET_FMT_plx " - 0x" TARGET_FMT_plx ")\n", + last_rom->name, last_rom->addr, last_rom->addr + last_rom->romsize= ); + error_printf( + " %s (addresses 0x" TARGET_FMT_plx " - 0x" TARGET_FMT_plx ")\n", + rom->name, rom->addr, rom->addr + rom->romsize); +} + int rom_check_and_register_reset(void) { MemoryRegionSection section; Rom *rom, *last_rom =3D NULL; + bool found_overlap =3D false; =20 QTAILQ_FOREACH(rom, &roms, next) { if (rom->fw_file) { @@ -1187,12 +1219,12 @@ int rom_check_and_register_reset(void) } if (!rom->mr) { if (roms_overlap(last_rom, rom)) { - fprintf(stderr, "rom: requested regions overlap " - "(rom %s. free=3D0x" TARGET_FMT_plx - ", addr=3D0x" TARGET_FMT_plx ")\n", - rom->name, last_rom->addr + last_rom->romsize, - rom->addr); - return -1; + if (!found_overlap) { + found_overlap =3D true; + rom_print_overlap_error_header(); + } + rom_print_one_overlap_error(last_rom, rom); + /* Keep going through the list so we report all overlaps */ } last_rom =3D rom; } @@ -1201,6 +1233,10 @@ int rom_check_and_register_reset(void) rom->isrom =3D int128_nz(section.size) && memory_region_is_rom(sec= tion.mr); memory_region_unref(section.mr); } + if (found_overlap) { + return -1; + } + qemu_register_reset(rom_reset, NULL); roms_loaded =3D 1; return 0; diff --git a/softmmu/vl.c b/softmmu/vl.c index 7146fbe2198..cbf3896ce66 100644 --- a/softmmu/vl.c +++ b/softmmu/vl.c @@ -3278,7 +3278,6 @@ static void qemu_machine_creation_done(void) qemu_run_machine_init_done_notifiers(); =20 if (rom_check_and_register_reset() !=3D 0) { - error_report("rom check and register reset failed"); exit(1); } =20 --=20 2.20.1 From nobody Thu Dec 18 13:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608046164; cv=none; d=zohomail.com; s=zohoarc; b=QUeev1dwd1dsAuYn+JM4FakWe6ZXlFsPv21UuDTAjl7LPJGLQerp1VZA0doMibPK1Xnkt3k59qjXkzWquiptfgm8AW9cuHEGjBv8pTAQxSmYUFesFjE8wmUwIjw+DyjVazQchA9qt0E8vhMjbGElgTghYDRtihmlQgC/e29NMAk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608046164; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qgfC7l4EWvSrwnuyqWJuBWbsmGfDi3SFHMaqqRdkMvE=; b=AEANK5XHTn84+90siXXdjTu6mpf08wWGZcvcATmhZIY4crSFV6K+wtLcD4tW3znhfeOHZ6kb8yZMXdsXGhf1kzYCqNgHbnNPjHyr0vPszvEZ6vmDD4l0uCRR1XMGRYVC9TJbwnTsNt5K/9UIIS5x0kSc1/3sYPtKEphFMd8Ldm4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1608046164925851.1570425679217; Tue, 15 Dec 2020 07:29:24 -0800 (PST) Received: from localhost ([::1]:33554 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kpBBj-0001sO-QR for importer@patchew.org; Tue, 15 Dec 2020 09:20:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34038) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kpB4W-0001WA-KK for qemu-devel@nongnu.org; Tue, 15 Dec 2020 09:13:00 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:36184) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kpB4O-00079d-Vz for qemu-devel@nongnu.org; Tue, 15 Dec 2020 09:13:00 -0500 Received: by mail-wm1-x329.google.com with SMTP id y23so18655164wmi.1 for ; Tue, 15 Dec 2020 06:12:52 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w21sm19667319wmi.45.2020.12.15.06.12.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 06:12:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=qgfC7l4EWvSrwnuyqWJuBWbsmGfDi3SFHMaqqRdkMvE=; b=wEp0g04liYWw/H+sTFCDYhYpr5uP+9WAXqoqhO2L2SS7aLg2ALlCfgUZRGMyzyO2fm vsSoekcRtHzLsRsQVEGXiEcdVvY/jOzvrpr75fajzEy3up6rx6fn3TaEFNBdQjLJZg/v 7nTuvTxeffZ9cq37DgYxSB/iYhWrIWMpYyZrL51ddxLstAgbQLJXbHsi6hI2mqOdyRYK oYvBilWq+K9zrNuTe5bcdny4AOrqwF+QFsQtRbjGj0lp0e6V6jYW/Q2W7vk3CPMzIv79 75G+DeEU5n7jto3vcdBpc09lEQmPgaNeyd2A/Wh4aHpFmOibsIMqqRqQ/tf+Kgpu2Rpy g20g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qgfC7l4EWvSrwnuyqWJuBWbsmGfDi3SFHMaqqRdkMvE=; b=ZNLO7pYYOydrJYmXbKHmPGdtjTv9DXNgW+xWIUtZxt1/AJKVFAdusQbZfmwIaqfRpr YqcEUyqwjUhYBEQfPElRGqE2C3B7UkqT+N1++apk479NnTf4Mshd5JRvvRuzw06nxe2g 5O6EremhMTNeyW+1jJpuUhAw3Z+4YYrrlJNf3wCdogG9S46Kms3f4FJAImFrVELgglOC m95DkWSENQy08GT8Ah/dvlhkkgmAMLZh2dlzfIjZ/UuKUvrlFxpYvRHGSThKZq+RgyT4 7zdfgaD99xWnYUUw5NZM7Bl909GREGJi0qiLlVQS1so16/nJj47zJBxQ+wS2No9PBPeo CHDQ== X-Gm-Message-State: AOAM533kT6+Nxml3rYssxWdkWVQZGHRKBRnhfKoYwpeyecAqWjomg1Hn Rb+jqWu0R+ZLVAs0UyClQVAoQimvt1x8sA== X-Google-Smtp-Source: ABdhPJx+0WQJR90XGbLlEvOFvh+gQYn1iqJXnKY6gr8RtVmjc7JtdjnngdwMs46c7AtQCM4yyAJCfQ== X-Received: by 2002:a7b:c7d3:: with SMTP id z19mr22530758wmk.31.1608041571438; Tue, 15 Dec 2020 06:12:51 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/20] elf_ops.h: Don't truncate name of the ROM blobs we create Date: Tue, 15 Dec 2020 14:12:27 +0000 Message-Id: <20201215141237.17868-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201215141237.17868-1-peter.maydell@linaro.org> References: <20201215141237.17868-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Currently the load_elf code assembles the ROM blob name into a local 128 byte fixed-size array. Use g_strdup_printf() instead so that we don't truncate the pathname if it happens to be long. (This matters mostly for monitor 'info roms' output and for the error messages if ROM blobs overlap.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201129203923.10622-4-peter.maydell@linaro.org --- include/hw/elf_ops.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/hw/elf_ops.h b/include/hw/elf_ops.h index 6fdff3dced5..53e0152af53 100644 --- a/include/hw/elf_ops.h +++ b/include/hw/elf_ops.h @@ -330,7 +330,6 @@ static int glue(load_elf, SZ)(const char *name, int fd, uint64_t addr, low =3D (uint64_t)-1, high =3D 0; GMappedFile *mapped_file =3D NULL; uint8_t *data =3D NULL; - char label[128]; int ret =3D ELF_LOAD_FAILED; =20 if (read(fd, &ehdr, sizeof(ehdr)) !=3D sizeof(ehdr)) @@ -544,7 +543,8 @@ static int glue(load_elf, SZ)(const char *name, int fd, */ if (mem_size !=3D 0) { if (load_rom) { - snprintf(label, sizeof(label), "phdr #%d: %s", i, name= ); + g_autofree char *label =3D + g_strdup_printf("phdr #%d: %s", i, name); =20 /* * rom_add_elf_program() takes its own reference to --=20 2.20.1 From nobody Thu Dec 18 13:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608069483; cv=none; d=zohomail.com; s=zohoarc; b=CHAq2YCAUp3iJK7fwdMTSiD0w7tOwfunErh3KqSJSIB4MKxSg4qqi1qTh0RR/2ngnEzgWmrptg+odUnjZtX7mHvJG0AwISZMJrUnbBHsZJQYMEgU1Ap1lYNGw1bJuN7lhnkNSHIHZ/w6aXrLuPD/Ps49JuY0T6K90T6W0Me0ELc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608069483; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vNqEQ8OeKCs61MrvZEg2K4vVh2wkS8dFPkArMrG4Pf4=; b=PJr7+XtJKQELsMzjqqSqrzYlOHtr+z4ZaW0xQL8NSp8v5Wrac43g+OtNp3DgqsvMjFPCxNGKMW9WCAz+oZfe2mSIvxEldBmOcVnuKW/yDv5amFk14qzZ2S5L7uJqBw8WNMAT9JOEYMPjKP0NpO7AzX6BwlYauWVe53OZpOao2Kw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1608069483398926.5195426331056; Tue, 15 Dec 2020 13:58:03 -0800 (PST) Received: from localhost ([::1]:60090 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kpBBR-0001Cn-91 for importer@patchew.org; Tue, 15 Dec 2020 09:20:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34098) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kpB4b-0001Zc-K2 for qemu-devel@nongnu.org; Tue, 15 Dec 2020 09:13:05 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:42018) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kpB4Q-00079r-GT for qemu-devel@nongnu.org; Tue, 15 Dec 2020 09:13:05 -0500 Received: by mail-wr1-x443.google.com with SMTP id m5so19977523wrx.9 for ; Tue, 15 Dec 2020 06:12:53 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w21sm19667319wmi.45.2020.12.15.06.12.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 06:12:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=vNqEQ8OeKCs61MrvZEg2K4vVh2wkS8dFPkArMrG4Pf4=; b=kvoDayvDHRUB5sbbi5HOOK/JcEVZMYFb2cdoL23Nb01hegykHCPrKnzOy2EZNHmxHj teaA94IT+p7zz8yTF2bZyR51tP0ykAMXbzcZIp+q59eCSe8YZfh4oaIkT01NpNN7Pd03 sgPODZyqy19JGzgEiJH7CtBo9kWx54bCXOhHAlCfAzlFOGdNdLnTJwKaMPdEf8WUjeCC /mxorXY109GuiAdce5iuuDlX7M+az/6Ml54VnH83DNhxaGtU7p5FkXED/UdjKf71t1JD Td6k9Im0tabKU1pdmcJ6UkerLDlkH82dBLzAU1l/smKUsXo+jKjgN/0rXRpa6ex1HS6N zdNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vNqEQ8OeKCs61MrvZEg2K4vVh2wkS8dFPkArMrG4Pf4=; b=qJdsaJjLNYTVtsiaHGYzHeXa2V1drJcfZE0oACdpOG5LF8hCfEOKXCVFdc3yShHdAY 6rHxfIIi+Oui84ubOZcaYVhD6NwZu0qenjgPdJSsYaQrlMDTisbzpgpPBblpz9pPV/FM Ph0OTsIvftPth7aLsRTCkGIvToKDznQ+lPPe3msqMT/sgMUyP2DyTVvAu7S27z+VWOnn m7HDytynK+AlxiZv3jTiB4OfFCDHeol0eOcKLggCuCrv+HBdRPx2ngynMKPan0KS6/E3 HvhtQ0Fa7x7tMPUE4z5Ct7xZjnLh8+wCXp0uNWOl8NsJsDRdZJguQEQD8JdZ2TceFy5k GXxQ== X-Gm-Message-State: AOAM530/Y4U1PfaZOGvgQ8ZMXhfZ2YuK/U3nGJINrj8NI3ADYz1W9pIy fdmLWSgStcjSudF6az36Ub/orA7Wre/vig== X-Google-Smtp-Source: ABdhPJxY8+/VVHFfh2FP87Ha9SZB3d6azUvqb+anbTuDOemwIwMXenKQj9E0T4hsy5Jp3xsOldiXAw== X-Received: by 2002:adf:c844:: with SMTP id e4mr35182645wrh.345.1608041572446; Tue, 15 Dec 2020 06:12:52 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/20] elf_ops.h: Be more verbose with ROM blob names Date: Tue, 15 Dec 2020 14:12:28 +0000 Message-Id: <20201215141237.17868-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201215141237.17868-1-peter.maydell@linaro.org> References: <20201215141237.17868-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::443; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x443.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Instead of making the ROM blob name something like: phdr #0: /home/petmay01/linaro/qemu-misc-tests/ldmia-fault.axf make it a little more self-explanatory for people who don't know ELF format details: /home/petmay01/linaro/qemu-misc-tests/ldmia-fault.axf ELF program header = segment 0 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201129203923.10622-5-peter.maydell@linaro.org --- include/hw/elf_ops.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/hw/elf_ops.h b/include/hw/elf_ops.h index 53e0152af53..8e8436831d2 100644 --- a/include/hw/elf_ops.h +++ b/include/hw/elf_ops.h @@ -544,7 +544,8 @@ static int glue(load_elf, SZ)(const char *name, int fd, if (mem_size !=3D 0) { if (load_rom) { g_autofree char *label =3D - g_strdup_printf("phdr #%d: %s", i, name); + g_strdup_printf("%s ELF program header segment %d", + name, i); =20 /* * rom_add_elf_program() takes its own reference to --=20 2.20.1 From nobody Thu Dec 18 13:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608055161; cv=none; d=zohomail.com; s=zohoarc; b=gjlTfhHX/zSsxHOl6Du7fxOhewU5007KjQfObSdTItfxYUuNMaMn5iZ6DORtzseL4/wOFkYCCQ1+8AJ1lFiEEuaAMzMzFMM7kKklkt9i7ikc8+4lJInVj+PRHT2Tnpljb9QHbkS4S6grOeC1QcfWheh61Gi8hNppzfYWDDO7XVc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608055161; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AjSVTnh/mQG/jhr7fSjAA8Ctwp9wsq/rOWNEwCe6vqw=; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w21sm19667319wmi.45.2020.12.15.06.12.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 06:12:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=AjSVTnh/mQG/jhr7fSjAA8Ctwp9wsq/rOWNEwCe6vqw=; b=LC1yrD+oGYs/qEZe6fawt+khC70PwYA+EpNoJd7LZ/rErAMkYN0dXbKBReU3rz4lcU VZySicB8fqc6GrCOGPpPE4i7ONPc7sTT92j/AzDyJ70ZnP+ZEjvg9vpLbjfvycSFZQgo DaCxl6fdXCLv/mLzvoOcb0tZUtK2Umh2FDM9Za8ediyJyRF4KUewUKJ1NWywDflK4IG/ a79PckpxsoBB4G9F31qaGVear3nGZeQc76itYKUlWCQo0/5SD+f8A5hhNq/KF/STARVD dO99cnoIJn9gEORp14NTgYtL4jDksZdvNH2AzNkat0k62ENiwoMsoHSGvSgslwAuYlDk 9o9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AjSVTnh/mQG/jhr7fSjAA8Ctwp9wsq/rOWNEwCe6vqw=; b=Xp7P0W21ydQOM+H7+s2nn5EifONrGvoT2wEHIeuXBPIJiL78dd2y5JPtSCCcClA0bw bK36rh/i1K5EBZwl6XDj0u3R1VesE6OSQmRhheYz8ceesSKZcsQCj0FAmWNjQjSCquC4 wfk/wbgeeVfUnd6/M2oLcooeZ5r7B/1Zd2GtedwrfDjTklX1Gtttggl0bFe2zu7PSNMJ 7m/FWRDYVmEf50NuRf13GHKUGTPoveYCif5ThluacsPYlvKBrRbmxsfCrp+7vixt37kO wHKa+KNvZQMSTauvZ7ubHPrzUqrLu0hLVkwpIkwzhrQfZYwPKlGA9ApZmYAlcyry7kLa mAGw== X-Gm-Message-State: AOAM530ybnJhT2oTP7f8hJyAJ0hyJr4z3oQ0qg3GoD0uizaVOHJn2YB+ Z+CUScTVhTkr91hURk8BO0TJFg9erjMbeg== X-Google-Smtp-Source: ABdhPJx910Ub5X1JwwKiMAbnDkq/OIReP3Lc8hMKuJxOjXTSwJEL634HVbs7Mqmh+vAPIVVnPJwWvA== X-Received: by 2002:a5d:4682:: with SMTP id u2mr33931182wrq.265.1608041573652; Tue, 15 Dec 2020 06:12:53 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/20] usb: Add versal-usb2-ctrl-regs module Date: Tue, 15 Dec 2020 14:12:29 +0000 Message-Id: <20201215141237.17868-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201215141237.17868-1-peter.maydell@linaro.org> References: <20201215141237.17868-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Sai Pavan Boddu This module emulates control registers of versal usb2 controller, this is a= dded just to make guest happy. In general this module would control the phy-reset signal from usb controller, data coherency of the transactions, signals the host system errors received from controller. Signed-off-by: Sai Pavan Boddu Signed-off-by: Vikram Garhwal Reviewed-by: Edgar E. Iglesias Reviewed-by: Peter Maydell Message-id: 1607023357-5096-2-git-send-email-sai.pavan.boddu@xilinx.com Signed-off-by: Peter Maydell --- include/hw/usb/xlnx-versal-usb2-ctrl-regs.h | 45 ++++ hw/usb/xlnx-versal-usb2-ctrl-regs.c | 229 ++++++++++++++++++++ hw/usb/meson.build | 1 + 3 files changed, 275 insertions(+) create mode 100644 include/hw/usb/xlnx-versal-usb2-ctrl-regs.h create mode 100644 hw/usb/xlnx-versal-usb2-ctrl-regs.c diff --git a/include/hw/usb/xlnx-versal-usb2-ctrl-regs.h b/include/hw/usb/x= lnx-versal-usb2-ctrl-regs.h new file mode 100644 index 00000000000..975a717627a --- /dev/null +++ b/include/hw/usb/xlnx-versal-usb2-ctrl-regs.h @@ -0,0 +1,45 @@ +/* + * QEMU model of the VersalUsb2CtrlRegs Register control/Status block for + * USB2.0 controller + * + * Copyright (c) 2020 Xilinx Inc. Vikram Garhwal + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef _XLNX_USB2_REGS_H_ +#define _XLNX_USB2_REGS_H_ + +#define TYPE_XILINX_VERSAL_USB2_CTRL_REGS "xlnx.versal-usb2-ctrl-regs" + +#define XILINX_VERSAL_USB2_CTRL_REGS(obj) \ + OBJECT_CHECK(VersalUsb2CtrlRegs, (obj), TYPE_XILINX_VERSAL_USB2_CTRL_= REGS) + +#define USB2_REGS_R_MAX ((0x78 / 4) + 1) + +typedef struct VersalUsb2CtrlRegs { + SysBusDevice parent_obj; + MemoryRegion iomem; + qemu_irq irq_ir; + + uint32_t regs[USB2_REGS_R_MAX]; + RegisterInfo regs_info[USB2_REGS_R_MAX]; +} VersalUsb2CtrlRegs; + +#endif diff --git a/hw/usb/xlnx-versal-usb2-ctrl-regs.c b/hw/usb/xlnx-versal-usb2-= ctrl-regs.c new file mode 100644 index 00000000000..9eaa59ebb8b --- /dev/null +++ b/hw/usb/xlnx-versal-usb2-ctrl-regs.c @@ -0,0 +1,229 @@ +/* + * QEMU model of the VersalUsb2CtrlRegs Register control/Status block for + * USB2.0 controller + * + * This module should control phy_reset, permanent device plugs, frame len= gth + * time adjust & setting of coherency paths. None of which are emulated in + * present model. + * + * Copyright (c) 2020 Xilinx Inc. Vikram Garhwal + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/irq.h" +#include "hw/register.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qom/object.h" +#include "migration/vmstate.h" +#include "hw/usb/xlnx-versal-usb2-ctrl-regs.h" + +#ifndef XILINX_VERSAL_USB2_CTRL_REGS_ERR_DEBUG +#define XILINX_VERSAL_USB2_CTRL_REGS_ERR_DEBUG 0 +#endif + +REG32(BUS_FILTER, 0x30) + FIELD(BUS_FILTER, BYPASS, 0, 4) +REG32(PORT, 0x34) + FIELD(PORT, HOST_SMI_BAR_WR, 4, 1) + FIELD(PORT, HOST_SMI_PCI_CMD_REG_WR, 3, 1) + FIELD(PORT, HOST_MSI_ENABLE, 2, 1) + FIELD(PORT, PWR_CTRL_PRSNT, 1, 1) + FIELD(PORT, HUB_PERM_ATTACH, 0, 1) +REG32(JITTER_ADJUST, 0x38) + FIELD(JITTER_ADJUST, FLADJ, 0, 6) +REG32(BIGENDIAN, 0x40) + FIELD(BIGENDIAN, ENDIAN_GS, 0, 1) +REG32(COHERENCY, 0x44) + FIELD(COHERENCY, USB_COHERENCY, 0, 1) +REG32(XHC_BME, 0x48) + FIELD(XHC_BME, XHC_BME, 0, 1) +REG32(REG_CTRL, 0x60) + FIELD(REG_CTRL, SLVERR_ENABLE, 0, 1) +REG32(IR_STATUS, 0x64) + FIELD(IR_STATUS, HOST_SYS_ERR, 1, 1) + FIELD(IR_STATUS, ADDR_DEC_ERR, 0, 1) +REG32(IR_MASK, 0x68) + FIELD(IR_MASK, HOST_SYS_ERR, 1, 1) + FIELD(IR_MASK, ADDR_DEC_ERR, 0, 1) +REG32(IR_ENABLE, 0x6c) + FIELD(IR_ENABLE, HOST_SYS_ERR, 1, 1) + FIELD(IR_ENABLE, ADDR_DEC_ERR, 0, 1) +REG32(IR_DISABLE, 0x70) + FIELD(IR_DISABLE, HOST_SYS_ERR, 1, 1) + FIELD(IR_DISABLE, ADDR_DEC_ERR, 0, 1) +REG32(USB3, 0x78) + +static void ir_update_irq(VersalUsb2CtrlRegs *s) +{ + bool pending =3D s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK]; + qemu_set_irq(s->irq_ir, pending); +} + +static void ir_status_postw(RegisterInfo *reg, uint64_t val64) +{ + VersalUsb2CtrlRegs *s =3D XILINX_VERSAL_USB2_CTRL_REGS(reg->opaque); + /* + * TODO: This should also clear USBSTS.HSE field in USB XHCI register. + * May be combine both the modules. + */ + ir_update_irq(s); +} + +static uint64_t ir_enable_prew(RegisterInfo *reg, uint64_t val64) +{ + VersalUsb2CtrlRegs *s =3D XILINX_VERSAL_USB2_CTRL_REGS(reg->opaque); + uint32_t val =3D val64; + + s->regs[R_IR_MASK] &=3D ~val; + ir_update_irq(s); + return 0; +} + +static uint64_t ir_disable_prew(RegisterInfo *reg, uint64_t val64) +{ + VersalUsb2CtrlRegs *s =3D XILINX_VERSAL_USB2_CTRL_REGS(reg->opaque); + uint32_t val =3D val64; + + s->regs[R_IR_MASK] |=3D val; + ir_update_irq(s); + return 0; +} + +static const RegisterAccessInfo usb2_ctrl_regs_regs_info[] =3D { + { .name =3D "BUS_FILTER", .addr =3D A_BUS_FILTER, + .rsvd =3D 0xfffffff0, + },{ .name =3D "PORT", .addr =3D A_PORT, + .rsvd =3D 0xffffffe0, + },{ .name =3D "JITTER_ADJUST", .addr =3D A_JITTER_ADJUST, + .reset =3D 0x20, + .rsvd =3D 0xffffffc0, + },{ .name =3D "BIGENDIAN", .addr =3D A_BIGENDIAN, + .rsvd =3D 0xfffffffe, + },{ .name =3D "COHERENCY", .addr =3D A_COHERENCY, + .rsvd =3D 0xfffffffe, + },{ .name =3D "XHC_BME", .addr =3D A_XHC_BME, + .reset =3D 0x1, + .rsvd =3D 0xfffffffe, + },{ .name =3D "REG_CTRL", .addr =3D A_REG_CTRL, + .rsvd =3D 0xfffffffe, + },{ .name =3D "IR_STATUS", .addr =3D A_IR_STATUS, + .rsvd =3D 0xfffffffc, + .w1c =3D 0x3, + .post_write =3D ir_status_postw, + },{ .name =3D "IR_MASK", .addr =3D A_IR_MASK, + .reset =3D 0x3, + .rsvd =3D 0xfffffffc, + .ro =3D 0x3, + },{ .name =3D "IR_ENABLE", .addr =3D A_IR_ENABLE, + .rsvd =3D 0xfffffffc, + .pre_write =3D ir_enable_prew, + },{ .name =3D "IR_DISABLE", .addr =3D A_IR_DISABLE, + .rsvd =3D 0xfffffffc, + .pre_write =3D ir_disable_prew, + },{ .name =3D "USB3", .addr =3D A_USB3, + } +}; + +static void usb2_ctrl_regs_reset_init(Object *obj, ResetType type) +{ + VersalUsb2CtrlRegs *s =3D XILINX_VERSAL_USB2_CTRL_REGS(obj); + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(s->regs_info); ++i) { + register_reset(&s->regs_info[i]); + } +} + +static void usb2_ctrl_regs_reset_hold(Object *obj) +{ + VersalUsb2CtrlRegs *s =3D XILINX_VERSAL_USB2_CTRL_REGS(obj); + + ir_update_irq(s); +} + +static const MemoryRegionOps usb2_ctrl_regs_ops =3D { + .read =3D register_read_memory, + .write =3D register_write_memory, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +static void usb2_ctrl_regs_init(Object *obj) +{ + VersalUsb2CtrlRegs *s =3D XILINX_VERSAL_USB2_CTRL_REGS(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + RegisterInfoArray *reg_array; + + memory_region_init(&s->iomem, obj, TYPE_XILINX_VERSAL_USB2_CTRL_REGS, + USB2_REGS_R_MAX * 4); + reg_array =3D + register_init_block32(DEVICE(obj), usb2_ctrl_regs_regs_info, + ARRAY_SIZE(usb2_ctrl_regs_regs_info), + s->regs_info, s->regs, + &usb2_ctrl_regs_ops, + XILINX_VERSAL_USB2_CTRL_REGS_ERR_DEBUG, + USB2_REGS_R_MAX * 4); + memory_region_add_subregion(&s->iomem, + 0x0, + ®_array->mem); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq_ir); +} + +static const VMStateDescription vmstate_usb2_ctrl_regs =3D { + .name =3D TYPE_XILINX_VERSAL_USB2_CTRL_REGS, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, VersalUsb2CtrlRegs, USB2_REGS_R_MAX), + VMSTATE_END_OF_LIST(), + } +}; + +static void usb2_ctrl_regs_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + rc->phases.enter =3D usb2_ctrl_regs_reset_init; + rc->phases.hold =3D usb2_ctrl_regs_reset_hold; + dc->vmsd =3D &vmstate_usb2_ctrl_regs; +} + +static const TypeInfo usb2_ctrl_regs_info =3D { + .name =3D TYPE_XILINX_VERSAL_USB2_CTRL_REGS, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(VersalUsb2CtrlRegs), + .class_init =3D usb2_ctrl_regs_class_init, + .instance_init =3D usb2_ctrl_regs_init, +}; + +static void usb2_ctrl_regs_register_types(void) +{ + type_register_static(&usb2_ctrl_regs_info); +} + +type_init(usb2_ctrl_regs_register_types) diff --git a/hw/usb/meson.build b/hw/usb/meson.build index 934e4fa6755..ecfec0a8f46 100644 --- a/hw/usb/meson.build +++ b/hw/usb/meson.build @@ -30,6 +30,7 @@ softmmu_ss.add(when: 'CONFIG_USB_DWC2', if_true: files('h= cd-dwc2.c')) softmmu_ss.add(when: 'CONFIG_TUSB6010', if_true: files('tusb6010.c')) softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('chipidea.c')) softmmu_ss.add(when: 'CONFIG_IMX_USBPHY', if_true: files('imx-usb-phy.c')) +specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-us= b2-ctrl-regs.c')) =20 # emulated usb devices softmmu_ss.add(when: 'CONFIG_USB', if_true: files('dev-hub.c')) --=20 2.20.1 From nobody Thu Dec 18 13:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w21sm19667319wmi.45.2020.12.15.06.12.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 06:12:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ciV4x41mRb1Xf3fRhXxbKt8MrVRXMNb1Nd0vbqINk7Y=; b=YdkBW3NS1qd5SXEkw8mTz5Sm13SNa8YX97vYqDk0gwM7YfylQ7vKbqBVIHNLTJ+lz3 6eVAQ5Q3fucHAxUpIB6paM5p2tFFIO0iPjE9Jz0ItcdZiTKR+Bz3Pol6bU7i2O9MZPey eQNnCUXGKDzj29ohmIgcbIwJZQDAafQYGlmBkPzjJiWo2tYv9ePRRzgMKsGuU4Bb3QGv IBz41EpHLUOiC+XvqA4pS5sILdipkcFguFspnLk8Kc+ju1/NGqHTTw5BITa70xWNksCn WCSB03U3uEJtWAEbcYoeXVVOiwKi+a98lMcL3C4BzshccxMdCpvu8zJok7wgnL3anrUf OI1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ciV4x41mRb1Xf3fRhXxbKt8MrVRXMNb1Nd0vbqINk7Y=; b=lHH3v3crsCIQjs+242PwaLfgOcVTmqg5BqdiwhIE5GB1bCAKBId00oltUtCDetYq/M pe3AsXIdQ+8dV0diE2WcmV2c+Ls95OS7IcNX6Yqf6wyqnLpQkWmBwCHqWAgPD2+dMyiE 4t5vj4JJTbkZ7zBPXZ96aK5em5KcD7bBIef9TOCzGG6sLJmS9ssNoXEKMav3DDMJx4H8 G1UHZifPtiKUrTCIqPkjogWQr/JjMsyc7/UjVqIPzwVB98BTAwca5ishdwwiYfLTTHlK X87M1HQ0Kc0J8ZYZ1cML65rU8Z3fMYL/CUQ4DB8LeTQ39akSdUjdfeTMcu96KAC4cdJr 8S/w== X-Gm-Message-State: AOAM531ZvJsS9G9CFSpHtj0PqS5+hKNvjr7xf0j9QlNQ47tuGmHFt3n9 U4aIyHdWuU5R6B+na1Tjk6xDOAeyZtWXVw== X-Google-Smtp-Source: ABdhPJx/YvzWtnScnXPXUfVxKu3vUAWfxkPqkqcipLP4zmyNowmrMaGrLfQYPwpO5y2GF6kMBDvVbA== X-Received: by 2002:adf:fd05:: with SMTP id e5mr34706029wrr.225.1608041575062; Tue, 15 Dec 2020 06:12:55 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/20] usb: Add DWC3 model Date: Tue, 15 Dec 2020 14:12:30 +0000 Message-Id: <20201215141237.17868-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201215141237.17868-1-peter.maydell@linaro.org> References: <20201215141237.17868-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Vikram Garhwal This patch adds skeleton model of dwc3 usb controller attached to xhci-sysbus device. It defines global register space of DWC3 controller, global registers control the AXI/AHB interfaces properties, external FIFO support and event count support. All of which are unimplemented at present,we are only supporting core reset and read of ID register. Signed-off-by: Vikram Garhwal Signed-off-by: Sai Pavan Boddu Reviewed-by: Edgar E. Iglesias Message-id: 1607023357-5096-3-git-send-email-sai.pavan.boddu@xilinx.com Signed-off-by: Peter Maydell --- include/hw/usb/hcd-dwc3.h | 55 +++ hw/usb/hcd-dwc3.c | 689 ++++++++++++++++++++++++++++++++++++++ hw/usb/Kconfig | 5 + hw/usb/meson.build | 1 + 4 files changed, 750 insertions(+) create mode 100644 include/hw/usb/hcd-dwc3.h create mode 100644 hw/usb/hcd-dwc3.c diff --git a/include/hw/usb/hcd-dwc3.h b/include/hw/usb/hcd-dwc3.h new file mode 100644 index 00000000000..7c804d536d5 --- /dev/null +++ b/include/hw/usb/hcd-dwc3.h @@ -0,0 +1,55 @@ +/* + * QEMU model of the USB DWC3 host controller emulation. + * + * Copyright (c) 2020 Xilinx Inc. + * + * Written by Vikram Garhwal + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ +#ifndef HCD_DWC3_H +#define HCD_DWC3_H + +#include "hw/usb/hcd-xhci.h" +#include "hw/usb/hcd-xhci-sysbus.h" + +#define TYPE_USB_DWC3 "usb_dwc3" + +#define USB_DWC3(obj) \ + OBJECT_CHECK(USBDWC3, (obj), TYPE_USB_DWC3) + +#define USB_DWC3_R_MAX ((0x530 / 4) + 1) +#define DWC3_SIZE 0x10000 + +typedef struct USBDWC3 { + SysBusDevice parent_obj; + MemoryRegion iomem; + XHCISysbusState sysbus_xhci; + + uint32_t regs[USB_DWC3_R_MAX]; + RegisterInfo regs_info[USB_DWC3_R_MAX]; + + struct { + uint8_t mode; + uint32_t dwc_usb3_user; + } cfg; + +} USBDWC3; + +#endif diff --git a/hw/usb/hcd-dwc3.c b/hw/usb/hcd-dwc3.c new file mode 100644 index 00000000000..d547d0538dd --- /dev/null +++ b/hw/usb/hcd-dwc3.c @@ -0,0 +1,689 @@ +/* + * QEMU model of the USB DWC3 host controller emulation. + * + * This model defines global register space of DWC3 controller. Global + * registers control the AXI/AHB interfaces properties, external FIFO supp= ort + * and event count support. All of which are unimplemented at present. We = are + * only supporting core reset and read of ID register. + * + * Copyright (c) 2020 Xilinx Inc. Vikram Garhwal + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/register.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qom/object.h" +#include "migration/vmstate.h" +#include "hw/qdev-properties.h" +#include "hw/usb/hcd-dwc3.h" +#include "qapi/error.h" + +#ifndef USB_DWC3_ERR_DEBUG +#define USB_DWC3_ERR_DEBUG 0 +#endif + +#define HOST_MODE 1 +#define FIFO_LEN 0x1000 + +REG32(GSBUSCFG0, 0x00) + FIELD(GSBUSCFG0, DATRDREQINFO, 28, 4) + FIELD(GSBUSCFG0, DESRDREQINFO, 24, 4) + FIELD(GSBUSCFG0, DATWRREQINFO, 20, 4) + FIELD(GSBUSCFG0, DESWRREQINFO, 16, 4) + FIELD(GSBUSCFG0, RESERVED_15_12, 12, 4) + FIELD(GSBUSCFG0, DATBIGEND, 11, 1) + FIELD(GSBUSCFG0, DESBIGEND, 10, 1) + FIELD(GSBUSCFG0, RESERVED_9_8, 8, 2) + FIELD(GSBUSCFG0, INCR256BRSTENA, 7, 1) + FIELD(GSBUSCFG0, INCR128BRSTENA, 6, 1) + FIELD(GSBUSCFG0, INCR64BRSTENA, 5, 1) + FIELD(GSBUSCFG0, INCR32BRSTENA, 4, 1) + FIELD(GSBUSCFG0, INCR16BRSTENA, 3, 1) + FIELD(GSBUSCFG0, INCR8BRSTENA, 2, 1) + FIELD(GSBUSCFG0, INCR4BRSTENA, 1, 1) + FIELD(GSBUSCFG0, INCRBRSTENA, 0, 1) +REG32(GSBUSCFG1, 0x04) + FIELD(GSBUSCFG1, RESERVED_31_13, 13, 19) + FIELD(GSBUSCFG1, EN1KPAGE, 12, 1) + FIELD(GSBUSCFG1, PIPETRANSLIMIT, 8, 4) + FIELD(GSBUSCFG1, RESERVED_7_0, 0, 8) +REG32(GTXTHRCFG, 0x08) + FIELD(GTXTHRCFG, RESERVED_31, 31, 1) + FIELD(GTXTHRCFG, RESERVED_30, 30, 1) + FIELD(GTXTHRCFG, USBTXPKTCNTSEL, 29, 1) + FIELD(GTXTHRCFG, RESERVED_28, 28, 1) + FIELD(GTXTHRCFG, USBTXPKTCNT, 24, 4) + FIELD(GTXTHRCFG, USBMAXTXBURSTSIZE, 16, 8) + FIELD(GTXTHRCFG, RESERVED_15, 15, 1) + FIELD(GTXTHRCFG, RESERVED_14, 14, 1) + FIELD(GTXTHRCFG, RESERVED_13_11, 11, 3) + FIELD(GTXTHRCFG, RESERVED_10_0, 0, 11) +REG32(GRXTHRCFG, 0x0c) + FIELD(GRXTHRCFG, RESERVED_31_30, 30, 2) + FIELD(GRXTHRCFG, USBRXPKTCNTSEL, 29, 1) + FIELD(GRXTHRCFG, RESERVED_28, 28, 1) + FIELD(GRXTHRCFG, USBRXPKTCNT, 24, 4) + FIELD(GRXTHRCFG, USBMAXRXBURSTSIZE, 19, 5) + FIELD(GRXTHRCFG, RESERVED_18_16, 16, 3) + FIELD(GRXTHRCFG, RESERVED_15, 15, 1) + FIELD(GRXTHRCFG, RESERVED_14_13, 13, 2) + FIELD(GRXTHRCFG, RESVISOCOUTSPC, 0, 13) +REG32(GCTL, 0x10) + FIELD(GCTL, PWRDNSCALE, 19, 13) + FIELD(GCTL, MASTERFILTBYPASS, 18, 1) + FIELD(GCTL, BYPSSETADDR, 17, 1) + FIELD(GCTL, U2RSTECN, 16, 1) + FIELD(GCTL, FRMSCLDWN, 14, 2) + FIELD(GCTL, PRTCAPDIR, 12, 2) + FIELD(GCTL, CORESOFTRESET, 11, 1) + FIELD(GCTL, U1U2TIMERSCALE, 9, 1) + FIELD(GCTL, DEBUGATTACH, 8, 1) + FIELD(GCTL, RAMCLKSEL, 6, 2) + FIELD(GCTL, SCALEDOWN, 4, 2) + FIELD(GCTL, DISSCRAMBLE, 3, 1) + FIELD(GCTL, U2EXIT_LFPS, 2, 1) + FIELD(GCTL, GBLHIBERNATIONEN, 1, 1) + FIELD(GCTL, DSBLCLKGTNG, 0, 1) +REG32(GPMSTS, 0x14) +REG32(GSTS, 0x18) + FIELD(GSTS, CBELT, 20, 12) + FIELD(GSTS, RESERVED_19_12, 12, 8) + FIELD(GSTS, SSIC_IP, 11, 1) + FIELD(GSTS, OTG_IP, 10, 1) + FIELD(GSTS, BC_IP, 9, 1) + FIELD(GSTS, ADP_IP, 8, 1) + FIELD(GSTS, HOST_IP, 7, 1) + FIELD(GSTS, DEVICE_IP, 6, 1) + FIELD(GSTS, CSRTIMEOUT, 5, 1) + FIELD(GSTS, BUSERRADDRVLD, 4, 1) + FIELD(GSTS, RESERVED_3_2, 2, 2) + FIELD(GSTS, CURMOD, 0, 2) +REG32(GUCTL1, 0x1c) + FIELD(GUCTL1, RESUME_OPMODE_HS_HOST, 10, 1) +REG32(GSNPSID, 0x20) +REG32(GGPIO, 0x24) + FIELD(GGPIO, GPO, 16, 16) + FIELD(GGPIO, GPI, 0, 16) +REG32(GUID, 0x28) +REG32(GUCTL, 0x2c) + FIELD(GUCTL, REFCLKPER, 22, 10) + FIELD(GUCTL, NOEXTRDL, 21, 1) + FIELD(GUCTL, RESERVED_20_18, 18, 3) + FIELD(GUCTL, SPRSCTRLTRANSEN, 17, 1) + FIELD(GUCTL, RESBWHSEPS, 16, 1) + FIELD(GUCTL, RESERVED_15, 15, 1) + FIELD(GUCTL, USBHSTINAUTORETRYEN, 14, 1) + FIELD(GUCTL, ENOVERLAPCHK, 13, 1) + FIELD(GUCTL, EXTCAPSUPPTEN, 12, 1) + FIELD(GUCTL, INSRTEXTRFSBODI, 11, 1) + FIELD(GUCTL, DTCT, 9, 2) + FIELD(GUCTL, DTFT, 0, 9) +REG32(GBUSERRADDRLO, 0x30) +REG32(GBUSERRADDRHI, 0x34) +REG32(GHWPARAMS0, 0x40) + FIELD(GHWPARAMS0, GHWPARAMS0_31_24, 24, 8) + FIELD(GHWPARAMS0, GHWPARAMS0_23_16, 16, 8) + FIELD(GHWPARAMS0, GHWPARAMS0_15_8, 8, 8) + FIELD(GHWPARAMS0, GHWPARAMS0_7_6, 6, 2) + FIELD(GHWPARAMS0, GHWPARAMS0_5_3, 3, 3) + FIELD(GHWPARAMS0, GHWPARAMS0_2_0, 0, 3) +REG32(GHWPARAMS1, 0x44) + FIELD(GHWPARAMS1, GHWPARAMS1_31, 31, 1) + FIELD(GHWPARAMS1, GHWPARAMS1_30, 30, 1) + FIELD(GHWPARAMS1, GHWPARAMS1_29, 29, 1) + FIELD(GHWPARAMS1, GHWPARAMS1_28, 28, 1) + FIELD(GHWPARAMS1, GHWPARAMS1_27, 27, 1) + FIELD(GHWPARAMS1, GHWPARAMS1_26, 26, 1) + FIELD(GHWPARAMS1, GHWPARAMS1_25_24, 24, 2) + FIELD(GHWPARAMS1, GHWPARAMS1_23, 23, 1) + FIELD(GHWPARAMS1, GHWPARAMS1_22_21, 21, 2) + FIELD(GHWPARAMS1, GHWPARAMS1_20_15, 15, 6) + FIELD(GHWPARAMS1, GHWPARAMS1_14_12, 12, 3) + FIELD(GHWPARAMS1, GHWPARAMS1_11_9, 9, 3) + FIELD(GHWPARAMS1, GHWPARAMS1_8_6, 6, 3) + FIELD(GHWPARAMS1, GHWPARAMS1_5_3, 3, 3) + FIELD(GHWPARAMS1, GHWPARAMS1_2_0, 0, 3) +REG32(GHWPARAMS2, 0x48) +REG32(GHWPARAMS3, 0x4c) + FIELD(GHWPARAMS3, GHWPARAMS3_31, 31, 1) + FIELD(GHWPARAMS3, GHWPARAMS3_30_23, 23, 8) + FIELD(GHWPARAMS3, GHWPARAMS3_22_18, 18, 5) + FIELD(GHWPARAMS3, GHWPARAMS3_17_12, 12, 6) + FIELD(GHWPARAMS3, GHWPARAMS3_11, 11, 1) + FIELD(GHWPARAMS3, GHWPARAMS3_10, 10, 1) + FIELD(GHWPARAMS3, GHWPARAMS3_9_8, 8, 2) + FIELD(GHWPARAMS3, GHWPARAMS3_7_6, 6, 2) + FIELD(GHWPARAMS3, GHWPARAMS3_5_4, 4, 2) + FIELD(GHWPARAMS3, GHWPARAMS3_3_2, 2, 2) + FIELD(GHWPARAMS3, GHWPARAMS3_1_0, 0, 2) +REG32(GHWPARAMS4, 0x50) + FIELD(GHWPARAMS4, GHWPARAMS4_31_28, 28, 4) + FIELD(GHWPARAMS4, GHWPARAMS4_27_24, 24, 4) + FIELD(GHWPARAMS4, GHWPARAMS4_23, 23, 1) + FIELD(GHWPARAMS4, GHWPARAMS4_22, 22, 1) + FIELD(GHWPARAMS4, GHWPARAMS4_21, 21, 1) + FIELD(GHWPARAMS4, GHWPARAMS4_20_17, 17, 4) + FIELD(GHWPARAMS4, GHWPARAMS4_16_13, 13, 4) + FIELD(GHWPARAMS4, GHWPARAMS4_12, 12, 1) + FIELD(GHWPARAMS4, GHWPARAMS4_11, 11, 1) + FIELD(GHWPARAMS4, GHWPARAMS4_10_9, 9, 2) + FIELD(GHWPARAMS4, GHWPARAMS4_8_7, 7, 2) + FIELD(GHWPARAMS4, GHWPARAMS4_6, 6, 1) + FIELD(GHWPARAMS4, GHWPARAMS4_5_0, 0, 6) +REG32(GHWPARAMS5, 0x54) + FIELD(GHWPARAMS5, GHWPARAMS5_31_28, 28, 4) + FIELD(GHWPARAMS5, GHWPARAMS5_27_22, 22, 6) + FIELD(GHWPARAMS5, GHWPARAMS5_21_16, 16, 6) + FIELD(GHWPARAMS5, GHWPARAMS5_15_10, 10, 6) + FIELD(GHWPARAMS5, GHWPARAMS5_9_4, 4, 6) + FIELD(GHWPARAMS5, GHWPARAMS5_3_0, 0, 4) +REG32(GHWPARAMS6, 0x58) + FIELD(GHWPARAMS6, GHWPARAMS6_31_16, 16, 16) + FIELD(GHWPARAMS6, BUSFLTRSSUPPORT, 15, 1) + FIELD(GHWPARAMS6, BCSUPPORT, 14, 1) + FIELD(GHWPARAMS6, OTG_SS_SUPPORT, 13, 1) + FIELD(GHWPARAMS6, ADPSUPPORT, 12, 1) + FIELD(GHWPARAMS6, HNPSUPPORT, 11, 1) + FIELD(GHWPARAMS6, SRPSUPPORT, 10, 1) + FIELD(GHWPARAMS6, GHWPARAMS6_9_8, 8, 2) + FIELD(GHWPARAMS6, GHWPARAMS6_7, 7, 1) + FIELD(GHWPARAMS6, GHWPARAMS6_6, 6, 1) + FIELD(GHWPARAMS6, GHWPARAMS6_5_0, 0, 6) +REG32(GHWPARAMS7, 0x5c) + FIELD(GHWPARAMS7, GHWPARAMS7_31_16, 16, 16) + FIELD(GHWPARAMS7, GHWPARAMS7_15_0, 0, 16) +REG32(GDBGFIFOSPACE, 0x60) + FIELD(GDBGFIFOSPACE, SPACE_AVAILABLE, 16, 16) + FIELD(GDBGFIFOSPACE, RESERVED_15_9, 9, 7) + FIELD(GDBGFIFOSPACE, FIFO_QUEUE_SELECT, 0, 9) +REG32(GUCTL2, 0x9c) + FIELD(GUCTL2, RESERVED_31_26, 26, 6) + FIELD(GUCTL2, EN_HP_PM_TIMER, 19, 7) + FIELD(GUCTL2, NOLOWPWRDUR, 15, 4) + FIELD(GUCTL2, RST_ACTBITLATER, 14, 1) + FIELD(GUCTL2, RESERVED_13, 13, 1) + FIELD(GUCTL2, DISABLECFC, 11, 1) +REG32(GUSB2PHYCFG, 0x100) + FIELD(GUSB2PHYCFG, U2_FREECLK_EXISTS, 30, 1) + FIELD(GUSB2PHYCFG, ULPI_LPM_WITH_OPMODE_CHK, 29, 1) + FIELD(GUSB2PHYCFG, RESERVED_25, 25, 1) + FIELD(GUSB2PHYCFG, LSTRD, 22, 3) + FIELD(GUSB2PHYCFG, LSIPD, 19, 3) + FIELD(GUSB2PHYCFG, ULPIEXTVBUSINDIACTOR, 18, 1) + FIELD(GUSB2PHYCFG, ULPIEXTVBUSDRV, 17, 1) + FIELD(GUSB2PHYCFG, RESERVED_16, 16, 1) + FIELD(GUSB2PHYCFG, ULPIAUTORES, 15, 1) + FIELD(GUSB2PHYCFG, RESERVED_14, 14, 1) + FIELD(GUSB2PHYCFG, USBTRDTIM, 10, 4) + FIELD(GUSB2PHYCFG, XCVRDLY, 9, 1) + FIELD(GUSB2PHYCFG, ENBLSLPM, 8, 1) + FIELD(GUSB2PHYCFG, PHYSEL, 7, 1) + FIELD(GUSB2PHYCFG, SUSPENDUSB20, 6, 1) + FIELD(GUSB2PHYCFG, FSINTF, 5, 1) + FIELD(GUSB2PHYCFG, ULPI_UTMI_SEL, 4, 1) + FIELD(GUSB2PHYCFG, PHYIF, 3, 1) + FIELD(GUSB2PHYCFG, TOUTCAL, 0, 3) +REG32(GUSB2I2CCTL, 0x140) +REG32(GUSB2PHYACC_ULPI, 0x180) + FIELD(GUSB2PHYACC_ULPI, RESERVED_31_27, 27, 5) + FIELD(GUSB2PHYACC_ULPI, DISUIPIDRVR, 26, 1) + FIELD(GUSB2PHYACC_ULPI, NEWREGREQ, 25, 1) + FIELD(GUSB2PHYACC_ULPI, VSTSDONE, 24, 1) + FIELD(GUSB2PHYACC_ULPI, VSTSBSY, 23, 1) + FIELD(GUSB2PHYACC_ULPI, REGWR, 22, 1) + FIELD(GUSB2PHYACC_ULPI, REGADDR, 16, 6) + FIELD(GUSB2PHYACC_ULPI, EXTREGADDR, 8, 8) + FIELD(GUSB2PHYACC_ULPI, REGDATA, 0, 8) +REG32(GTXFIFOSIZ0, 0x200) + FIELD(GTXFIFOSIZ0, TXFSTADDR_N, 16, 16) + FIELD(GTXFIFOSIZ0, TXFDEP_N, 0, 16) +REG32(GTXFIFOSIZ1, 0x204) + FIELD(GTXFIFOSIZ1, TXFSTADDR_N, 16, 16) + FIELD(GTXFIFOSIZ1, TXFDEP_N, 0, 16) +REG32(GTXFIFOSIZ2, 0x208) + FIELD(GTXFIFOSIZ2, TXFSTADDR_N, 16, 16) + FIELD(GTXFIFOSIZ2, TXFDEP_N, 0, 16) +REG32(GTXFIFOSIZ3, 0x20c) + FIELD(GTXFIFOSIZ3, TXFSTADDR_N, 16, 16) + FIELD(GTXFIFOSIZ3, TXFDEP_N, 0, 16) +REG32(GTXFIFOSIZ4, 0x210) + FIELD(GTXFIFOSIZ4, TXFSTADDR_N, 16, 16) + FIELD(GTXFIFOSIZ4, TXFDEP_N, 0, 16) +REG32(GTXFIFOSIZ5, 0x214) + FIELD(GTXFIFOSIZ5, TXFSTADDR_N, 16, 16) + FIELD(GTXFIFOSIZ5, TXFDEP_N, 0, 16) +REG32(GRXFIFOSIZ0, 0x280) + FIELD(GRXFIFOSIZ0, RXFSTADDR_N, 16, 16) + FIELD(GRXFIFOSIZ0, RXFDEP_N, 0, 16) +REG32(GRXFIFOSIZ1, 0x284) + FIELD(GRXFIFOSIZ1, RXFSTADDR_N, 16, 16) + FIELD(GRXFIFOSIZ1, RXFDEP_N, 0, 16) +REG32(GRXFIFOSIZ2, 0x288) + FIELD(GRXFIFOSIZ2, RXFSTADDR_N, 16, 16) + FIELD(GRXFIFOSIZ2, RXFDEP_N, 0, 16) +REG32(GEVNTADRLO_0, 0x300) +REG32(GEVNTADRHI_0, 0x304) +REG32(GEVNTSIZ_0, 0x308) + FIELD(GEVNTSIZ_0, EVNTINTRPTMASK, 31, 1) + FIELD(GEVNTSIZ_0, RESERVED_30_16, 16, 15) + FIELD(GEVNTSIZ_0, EVENTSIZ, 0, 16) +REG32(GEVNTCOUNT_0, 0x30c) + FIELD(GEVNTCOUNT_0, EVNT_HANDLER_BUSY, 31, 1) + FIELD(GEVNTCOUNT_0, RESERVED_30_16, 16, 15) + FIELD(GEVNTCOUNT_0, EVNTCOUNT, 0, 16) +REG32(GEVNTADRLO_1, 0x310) +REG32(GEVNTADRHI_1, 0x314) +REG32(GEVNTSIZ_1, 0x318) + FIELD(GEVNTSIZ_1, EVNTINTRPTMASK, 31, 1) + FIELD(GEVNTSIZ_1, RESERVED_30_16, 16, 15) + FIELD(GEVNTSIZ_1, EVENTSIZ, 0, 16) +REG32(GEVNTCOUNT_1, 0x31c) + FIELD(GEVNTCOUNT_1, EVNT_HANDLER_BUSY, 31, 1) + FIELD(GEVNTCOUNT_1, RESERVED_30_16, 16, 15) + FIELD(GEVNTCOUNT_1, EVNTCOUNT, 0, 16) +REG32(GEVNTADRLO_2, 0x320) +REG32(GEVNTADRHI_2, 0x324) +REG32(GEVNTSIZ_2, 0x328) + FIELD(GEVNTSIZ_2, EVNTINTRPTMASK, 31, 1) + FIELD(GEVNTSIZ_2, RESERVED_30_16, 16, 15) + FIELD(GEVNTSIZ_2, EVENTSIZ, 0, 16) +REG32(GEVNTCOUNT_2, 0x32c) + FIELD(GEVNTCOUNT_2, EVNT_HANDLER_BUSY, 31, 1) + FIELD(GEVNTCOUNT_2, RESERVED_30_16, 16, 15) + FIELD(GEVNTCOUNT_2, EVNTCOUNT, 0, 16) +REG32(GEVNTADRLO_3, 0x330) +REG32(GEVNTADRHI_3, 0x334) +REG32(GEVNTSIZ_3, 0x338) + FIELD(GEVNTSIZ_3, EVNTINTRPTMASK, 31, 1) + FIELD(GEVNTSIZ_3, RESERVED_30_16, 16, 15) + FIELD(GEVNTSIZ_3, EVENTSIZ, 0, 16) +REG32(GEVNTCOUNT_3, 0x33c) + FIELD(GEVNTCOUNT_3, EVNT_HANDLER_BUSY, 31, 1) + FIELD(GEVNTCOUNT_3, RESERVED_30_16, 16, 15) + FIELD(GEVNTCOUNT_3, EVNTCOUNT, 0, 16) +REG32(GHWPARAMS8, 0x500) +REG32(GTXFIFOPRIDEV, 0x510) + FIELD(GTXFIFOPRIDEV, RESERVED_31_N, 6, 26) + FIELD(GTXFIFOPRIDEV, GTXFIFOPRIDEV, 0, 6) +REG32(GTXFIFOPRIHST, 0x518) + FIELD(GTXFIFOPRIHST, RESERVED_31_16, 3, 29) + FIELD(GTXFIFOPRIHST, GTXFIFOPRIHST, 0, 3) +REG32(GRXFIFOPRIHST, 0x51c) + FIELD(GRXFIFOPRIHST, RESERVED_31_16, 3, 29) + FIELD(GRXFIFOPRIHST, GRXFIFOPRIHST, 0, 3) +REG32(GDMAHLRATIO, 0x524) + FIELD(GDMAHLRATIO, RESERVED_31_13, 13, 19) + FIELD(GDMAHLRATIO, HSTRXFIFO, 8, 5) + FIELD(GDMAHLRATIO, RESERVED_7_5, 5, 3) + FIELD(GDMAHLRATIO, HSTTXFIFO, 0, 5) +REG32(GFLADJ, 0x530) + FIELD(GFLADJ, GFLADJ_REFCLK_240MHZDECR_PLS1, 31, 1) + FIELD(GFLADJ, GFLADJ_REFCLK_240MHZ_DECR, 24, 7) + FIELD(GFLADJ, GFLADJ_REFCLK_LPM_SEL, 23, 1) + FIELD(GFLADJ, RESERVED_22, 22, 1) + FIELD(GFLADJ, GFLADJ_REFCLK_FLADJ, 8, 14) + FIELD(GFLADJ, GFLADJ_30MHZ_SDBND_SEL, 7, 1) + FIELD(GFLADJ, GFLADJ_30MHZ, 0, 6) + +#define DWC3_GLOBAL_OFFSET 0xC100 +static void reset_csr(USBDWC3 * s) +{ + int i =3D 0; + /* + * We reset all CSR regs except GCTL, GUCTL, GSTS, GSNPSID, GGPIO, GUI= D, + * GUSB2PHYCFGn registers and GUSB3PIPECTLn registers. We will skip PHY + * register as we don't implement them. + */ + for (i =3D 0; i < USB_DWC3_R_MAX; i++) { + switch (i) { + case R_GCTL: + break; + case R_GSTS: + break; + case R_GSNPSID: + break; + case R_GGPIO: + break; + case R_GUID: + break; + case R_GUCTL: + break; + case R_GHWPARAMS0...R_GHWPARAMS7: + break; + case R_GHWPARAMS8: + break; + default: + register_reset(&s->regs_info[i]); + break; + } + } + + xhci_sysbus_reset(DEVICE(&s->sysbus_xhci)); +} + +static void usb_dwc3_gctl_postw(RegisterInfo *reg, uint64_t val64) +{ + USBDWC3 *s =3D USB_DWC3(reg->opaque); + + if (ARRAY_FIELD_EX32(s->regs, GCTL, CORESOFTRESET)) { + reset_csr(s); + } +} + +static void usb_dwc3_guid_postw(RegisterInfo *reg, uint64_t val64) +{ + USBDWC3 *s =3D USB_DWC3(reg->opaque); + + s->regs[R_GUID] =3D s->cfg.dwc_usb3_user; +} + +static const RegisterAccessInfo usb_dwc3_regs_info[] =3D { + { .name =3D "GSBUSCFG0", .addr =3D A_GSBUSCFG0, + .ro =3D 0xf300, + .unimp =3D 0xffffffff, + },{ .name =3D "GSBUSCFG1", .addr =3D A_GSBUSCFG1, + .reset =3D 0x300, + .ro =3D 0xffffe0ff, + .unimp =3D 0xffffffff, + },{ .name =3D "GTXTHRCFG", .addr =3D A_GTXTHRCFG, + .ro =3D 0xd000ffff, + .unimp =3D 0xffffffff, + },{ .name =3D "GRXTHRCFG", .addr =3D A_GRXTHRCFG, + .ro =3D 0xd007e000, + .unimp =3D 0xffffffff, + },{ .name =3D "GCTL", .addr =3D A_GCTL, + .reset =3D 0x30c13004, .post_write =3D usb_dwc3_gctl_postw, + },{ .name =3D "GPMSTS", .addr =3D A_GPMSTS, + .ro =3D 0xfffffff, + .unimp =3D 0xffffffff, + },{ .name =3D "GSTS", .addr =3D A_GSTS, + .reset =3D 0x7e800000, + .ro =3D 0xffffffcf, + .w1c =3D 0x30, + .unimp =3D 0xffffffff, + },{ .name =3D "GUCTL1", .addr =3D A_GUCTL1, + .reset =3D 0x198a, + .ro =3D 0x7800, + .unimp =3D 0xffffffff, + },{ .name =3D "GSNPSID", .addr =3D A_GSNPSID, + .reset =3D 0x5533330a, + .ro =3D 0xffffffff, + },{ .name =3D "GGPIO", .addr =3D A_GGPIO, + .ro =3D 0xffff, + .unimp =3D 0xffffffff, + },{ .name =3D "GUID", .addr =3D A_GUID, + .reset =3D 0x12345678, .post_write =3D usb_dwc3_guid_postw, + },{ .name =3D "GUCTL", .addr =3D A_GUCTL, + .reset =3D 0x0c808010, + .ro =3D 0x1c8000, + .unimp =3D 0xffffffff, + },{ .name =3D "GBUSERRADDRLO", .addr =3D A_GBUSERRADDRLO, + .ro =3D 0xffffffff, + },{ .name =3D "GBUSERRADDRHI", .addr =3D A_GBUSERRADDRHI, + .ro =3D 0xffffffff, + },{ .name =3D "GHWPARAMS0", .addr =3D A_GHWPARAMS0, + .ro =3D 0xffffffff, + },{ .name =3D "GHWPARAMS1", .addr =3D A_GHWPARAMS1, + .ro =3D 0xffffffff, + },{ .name =3D "GHWPARAMS2", .addr =3D A_GHWPARAMS2, + .ro =3D 0xffffffff, + },{ .name =3D "GHWPARAMS3", .addr =3D A_GHWPARAMS3, + .ro =3D 0xffffffff, + },{ .name =3D "GHWPARAMS4", .addr =3D A_GHWPARAMS4, + .ro =3D 0xffffffff, + },{ .name =3D "GHWPARAMS5", .addr =3D A_GHWPARAMS5, + .ro =3D 0xffffffff, + },{ .name =3D "GHWPARAMS6", .addr =3D A_GHWPARAMS6, + .ro =3D 0xffffffff, + },{ .name =3D "GHWPARAMS7", .addr =3D A_GHWPARAMS7, + .ro =3D 0xffffffff, + },{ .name =3D "GDBGFIFOSPACE", .addr =3D A_GDBGFIFOSPACE, + .reset =3D 0xa0000, + .ro =3D 0xfffffe00, + .unimp =3D 0xffffffff, + },{ .name =3D "GUCTL2", .addr =3D A_GUCTL2, + .reset =3D 0x40d, + .ro =3D 0x2000, + .unimp =3D 0xffffffff, + },{ .name =3D "GUSB2PHYCFG", .addr =3D A_GUSB2PHYCFG, + .reset =3D 0x40102410, + .ro =3D 0x1e014030, + .unimp =3D 0xffffffff, + },{ .name =3D "GUSB2I2CCTL", .addr =3D A_GUSB2I2CCTL, + .ro =3D 0xffffffff, + .unimp =3D 0xffffffff, + },{ .name =3D "GUSB2PHYACC_ULPI", .addr =3D A_GUSB2PHYACC_ULPI, + .ro =3D 0xfd000000, + .unimp =3D 0xffffffff, + },{ .name =3D "GTXFIFOSIZ0", .addr =3D A_GTXFIFOSIZ0, + .reset =3D 0x2c7000a, + .unimp =3D 0xffffffff, + },{ .name =3D "GTXFIFOSIZ1", .addr =3D A_GTXFIFOSIZ1, + .reset =3D 0x2d10103, + .unimp =3D 0xffffffff, + },{ .name =3D "GTXFIFOSIZ2", .addr =3D A_GTXFIFOSIZ2, + .reset =3D 0x3d40103, + .unimp =3D 0xffffffff, + },{ .name =3D "GTXFIFOSIZ3", .addr =3D A_GTXFIFOSIZ3, + .reset =3D 0x4d70083, + .unimp =3D 0xffffffff, + },{ .name =3D "GTXFIFOSIZ4", .addr =3D A_GTXFIFOSIZ4, + .reset =3D 0x55a0083, + .unimp =3D 0xffffffff, + },{ .name =3D "GTXFIFOSIZ5", .addr =3D A_GTXFIFOSIZ5, + .reset =3D 0x5dd0083, + .unimp =3D 0xffffffff, + },{ .name =3D "GRXFIFOSIZ0", .addr =3D A_GRXFIFOSIZ0, + .reset =3D 0x1c20105, + .unimp =3D 0xffffffff, + },{ .name =3D "GRXFIFOSIZ1", .addr =3D A_GRXFIFOSIZ1, + .reset =3D 0x2c70000, + .unimp =3D 0xffffffff, + },{ .name =3D "GRXFIFOSIZ2", .addr =3D A_GRXFIFOSIZ2, + .reset =3D 0x2c70000, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTADRLO_0", .addr =3D A_GEVNTADRLO_0, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTADRHI_0", .addr =3D A_GEVNTADRHI_0, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTSIZ_0", .addr =3D A_GEVNTSIZ_0, + .ro =3D 0x7fff0000, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTCOUNT_0", .addr =3D A_GEVNTCOUNT_0, + .ro =3D 0x7fff0000, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTADRLO_1", .addr =3D A_GEVNTADRLO_1, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTADRHI_1", .addr =3D A_GEVNTADRHI_1, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTSIZ_1", .addr =3D A_GEVNTSIZ_1, + .ro =3D 0x7fff0000, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTCOUNT_1", .addr =3D A_GEVNTCOUNT_1, + .ro =3D 0x7fff0000, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTADRLO_2", .addr =3D A_GEVNTADRLO_2, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTADRHI_2", .addr =3D A_GEVNTADRHI_2, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTSIZ_2", .addr =3D A_GEVNTSIZ_2, + .ro =3D 0x7fff0000, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTCOUNT_2", .addr =3D A_GEVNTCOUNT_2, + .ro =3D 0x7fff0000, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTADRLO_3", .addr =3D A_GEVNTADRLO_3, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTADRHI_3", .addr =3D A_GEVNTADRHI_3, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTSIZ_3", .addr =3D A_GEVNTSIZ_3, + .ro =3D 0x7fff0000, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTCOUNT_3", .addr =3D A_GEVNTCOUNT_3, + .ro =3D 0x7fff0000, + .unimp =3D 0xffffffff, + },{ .name =3D "GHWPARAMS8", .addr =3D A_GHWPARAMS8, + .ro =3D 0xffffffff, + },{ .name =3D "GTXFIFOPRIDEV", .addr =3D A_GTXFIFOPRIDEV, + .ro =3D 0xffffffc0, + .unimp =3D 0xffffffff, + },{ .name =3D "GTXFIFOPRIHST", .addr =3D A_GTXFIFOPRIHST, + .ro =3D 0xfffffff8, + .unimp =3D 0xffffffff, + },{ .name =3D "GRXFIFOPRIHST", .addr =3D A_GRXFIFOPRIHST, + .ro =3D 0xfffffff8, + .unimp =3D 0xffffffff, + },{ .name =3D "GDMAHLRATIO", .addr =3D A_GDMAHLRATIO, + .ro =3D 0xffffe0e0, + .unimp =3D 0xffffffff, + },{ .name =3D "GFLADJ", .addr =3D A_GFLADJ, + .reset =3D 0xc83f020, + .rsvd =3D 0x40, + .ro =3D 0x400040, + .unimp =3D 0xffffffff, + } +}; + +static void usb_dwc3_reset(DeviceState *dev) +{ + USBDWC3 *s =3D USB_DWC3(dev); + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(s->regs_info); ++i) { + switch (i) { + case R_GHWPARAMS0...R_GHWPARAMS7: + break; + case R_GHWPARAMS8: + break; + default: + register_reset(&s->regs_info[i]); + }; + } + + xhci_sysbus_reset(DEVICE(&s->sysbus_xhci)); +} + +static const MemoryRegionOps usb_dwc3_ops =3D { + .read =3D register_read_memory, + .write =3D register_write_memory, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +static void usb_dwc3_realize(DeviceState *dev, Error **errp) +{ + USBDWC3 *s =3D USB_DWC3(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + Error *err =3D NULL; + + sysbus_realize(SYS_BUS_DEVICE(&s->sysbus_xhci), &err); + if (err) { + error_propagate(errp, err); + return; + } + + memory_region_add_subregion(&s->iomem, 0, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sysbus_xhci), 0)); + sysbus_init_mmio(sbd, &s->iomem); + + /* + * Device Configuration + */ + s->regs[R_GHWPARAMS0] =3D 0x40204048 | s->cfg.mode; + s->regs[R_GHWPARAMS1] =3D 0x222493b; + s->regs[R_GHWPARAMS2] =3D 0x12345678; + s->regs[R_GHWPARAMS3] =3D 0x618c088; + s->regs[R_GHWPARAMS4] =3D 0x47822004; + s->regs[R_GHWPARAMS5] =3D 0x4202088; + s->regs[R_GHWPARAMS6] =3D 0x7850c20; + s->regs[R_GHWPARAMS7] =3D 0x0; + s->regs[R_GHWPARAMS8] =3D 0x478; +} + +static void usb_dwc3_init(Object *obj) +{ + USBDWC3 *s =3D USB_DWC3(obj); + RegisterInfoArray *reg_array; + + memory_region_init(&s->iomem, obj, TYPE_USB_DWC3, DWC3_SIZE); + reg_array =3D + register_init_block32(DEVICE(obj), usb_dwc3_regs_info, + ARRAY_SIZE(usb_dwc3_regs_info), + s->regs_info, s->regs, + &usb_dwc3_ops, + USB_DWC3_ERR_DEBUG, + USB_DWC3_R_MAX * 4); + memory_region_add_subregion(&s->iomem, + DWC3_GLOBAL_OFFSET, + ®_array->mem); + object_initialize_child(obj, "dwc3-xhci", &s->sysbus_xhci, + TYPE_XHCI_SYSBUS); + qdev_alias_all_properties(DEVICE(&s->sysbus_xhci), obj); + + s->cfg.mode =3D HOST_MODE; +} + +static const VMStateDescription vmstate_usb_dwc3 =3D { + .name =3D "usb-dwc3", + .version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, USBDWC3, USB_DWC3_R_MAX), + VMSTATE_UINT8(cfg.mode, USBDWC3), + VMSTATE_UINT32(cfg.dwc_usb3_user, USBDWC3), + VMSTATE_END_OF_LIST() + } +}; + +static Property usb_dwc3_properties[] =3D { + DEFINE_PROP_UINT32("DWC_USB3_USERID", USBDWC3, cfg.dwc_usb3_user, + 0x12345678), + DEFINE_PROP_END_OF_LIST(), +}; + +static void usb_dwc3_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->reset =3D usb_dwc3_reset; + dc->realize =3D usb_dwc3_realize; + dc->vmsd =3D &vmstate_usb_dwc3; + device_class_set_props(dc, usb_dwc3_properties); +} + +static const TypeInfo usb_dwc3_info =3D { + .name =3D TYPE_USB_DWC3, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(USBDWC3), + .class_init =3D usb_dwc3_class_init, + .instance_init =3D usb_dwc3_init, +}; + +static void usb_dwc3_register_types(void) +{ + type_register_static(&usb_dwc3_info); +} + +type_init(usb_dwc3_register_types) diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig index 7fbae18bc80..56da78a4faf 100644 --- a/hw/usb/Kconfig +++ b/hw/usb/Kconfig @@ -112,3 +112,8 @@ config IMX_USBPHY bool default y depends on USB + +config USB_DWC3 + bool + select USB_XHCI_SYSBUS + select REGISTER diff --git a/hw/usb/meson.build b/hw/usb/meson.build index ecfec0a8f46..433c27e833e 100644 --- a/hw/usb/meson.build +++ b/hw/usb/meson.build @@ -26,6 +26,7 @@ softmmu_ss.add(when: 'CONFIG_USB_XHCI_SYSBUS', if_true: f= iles('hcd-xhci-sysbus.c softmmu_ss.add(when: 'CONFIG_USB_XHCI_NEC', if_true: files('hcd-xhci-nec.c= ')) softmmu_ss.add(when: 'CONFIG_USB_MUSB', if_true: files('hcd-musb.c')) softmmu_ss.add(when: 'CONFIG_USB_DWC2', if_true: files('hcd-dwc2.c')) +softmmu_ss.add(when: 'CONFIG_USB_DWC3', if_true: files('hcd-dwc3.c')) =20 softmmu_ss.add(when: 'CONFIG_TUSB6010', if_true: files('tusb6010.c')) softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('chipidea.c')) --=20 2.20.1 From nobody Thu Dec 18 13:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w21sm19667319wmi.45.2020.12.15.06.12.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 06:12:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Wfa/U1kU0UDN9y21zzgk5Zm+h6nZ9h0WDfMI1dRr7eI=; b=fjIJJs5ThcijIJ0XAV+wmq7dYLQGKL46ine3rXN5XwfYVyGadWCVYR98+X/lSWRDK1 HbbdadPF/0/l/B+kVEYEJsuUxgd0ap5oKjAIq+EsOT1UgV74G0nP5pphd0qZheUeILKV 9D6stSYx8Na/FvNM9E6CG3Gh5KXUE/EZ631zQwkO/9sovf2A3/Fd5y9udx5Kwhc8qo1u ocInKjz8N0OTq6RxAhdxQjI1Pepj2O1lZpC1O5woZWICmmEiqIK+OVVGDT0SsL57Fx/q qUakJ4D4XH5HgByqeCy+vVRnrP88myMIIFQbbIyn3Hd5ENfY98ILX61Y0u3sxB2dK11n OE6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Wfa/U1kU0UDN9y21zzgk5Zm+h6nZ9h0WDfMI1dRr7eI=; b=fzkdOaTXxcYfjKX6hQweFFj8KpJhzYln6EM5i4ElZMhP6fM9toc8m8/4bmxfrVqATu 45W/DDUYVqAUAZjpSGRamR9mmYb7CN4UCrybQzPIwlGJ6boJSo9g7ONxDIuA8GyqppGb 0rKl1+R0kDX4SzPjL5we75T0HDdQqavSXtPDq+d9cTl4+aFWic5zkm7SwxDuhiBCP/sv EEcGFbVvC1noiEeFD2W/OHskCL64j7BkZ94KMJDJfcri1Yn/8AY//h5+Z7/FcuGWqDiZ +Uj3IIhAEyrxea2uH0lUAmOPUmm1fWnmYlY5UCm88GAv80buE6WYwTbImFVHJ3J/XzMs lb3g== X-Gm-Message-State: AOAM531qsgNKKKomQmKDip9uWb2zLHZ95ycldggI31iH8i0LvxH+vjF2 MjIRuuUzRw19WV274WOYO7i3qnSOfvDNbg== X-Google-Smtp-Source: ABdhPJwZlZlmJ+JCHZJyPQpuqgiP6IATFsAZQ0ztkNOZSiVlcO9ZqNmWB1rl3TrNX5q6Gi4eaSQogw== X-Received: by 2002:a1c:3d55:: with SMTP id k82mr32466200wma.57.1608041576038; Tue, 15 Dec 2020 06:12:56 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/20] usb: xlnx-usb-subsystem: Add xilinx usb subsystem Date: Tue, 15 Dec 2020 14:12:31 +0000 Message-Id: <20201215141237.17868-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201215141237.17868-1-peter.maydell@linaro.org> References: <20201215141237.17868-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Sai Pavan Boddu This model is a top level integration wrapper for hcd-dwc3 and versal-usb2-ctrl-regs modules, this is used by xilinx versal soc's and future xilinx usb subsystems would also be part of it. Signed-off-by: Sai Pavan Boddu Reviewed-by: Edgar E. Iglesias Reviewed-by: Peter Maydell Message-id: 1607023357-5096-4-git-send-email-sai.pavan.boddu@xilinx.com Signed-off-by: Peter Maydell --- include/hw/usb/xlnx-usb-subsystem.h | 45 ++++++++++++++ hw/usb/xlnx-usb-subsystem.c | 94 +++++++++++++++++++++++++++++ hw/usb/Kconfig | 5 ++ hw/usb/meson.build | 1 + 4 files changed, 145 insertions(+) create mode 100644 include/hw/usb/xlnx-usb-subsystem.h create mode 100644 hw/usb/xlnx-usb-subsystem.c diff --git a/include/hw/usb/xlnx-usb-subsystem.h b/include/hw/usb/xlnx-usb-= subsystem.h new file mode 100644 index 00000000000..739bef7f451 --- /dev/null +++ b/include/hw/usb/xlnx-usb-subsystem.h @@ -0,0 +1,45 @@ +/* + * QEMU model of the Xilinx usb subsystem + * + * Copyright (c) 2020 Xilinx Inc. Sai Pavan Boddu + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef _XLNX_VERSAL_USB_SUBSYSTEM_H_ +#define _XLNX_VERSAL_USB_SUBSYSTEM_H_ + +#include "hw/usb/xlnx-versal-usb2-ctrl-regs.h" +#include "hw/usb/hcd-dwc3.h" + +#define TYPE_XILINX_VERSAL_USB2 "xlnx.versal-usb2" + +#define VERSAL_USB2(obj) \ + OBJECT_CHECK(VersalUsb2, (obj), TYPE_XILINX_VERSAL_USB2) + +typedef struct VersalUsb2 { + SysBusDevice parent_obj; + MemoryRegion dwc3_mr; + MemoryRegion usb2Ctrl_mr; + + VersalUsb2CtrlRegs usb2Ctrl; + USBDWC3 dwc3; +} VersalUsb2; + +#endif diff --git a/hw/usb/xlnx-usb-subsystem.c b/hw/usb/xlnx-usb-subsystem.c new file mode 100644 index 00000000000..568257370cb --- /dev/null +++ b/hw/usb/xlnx-usb-subsystem.c @@ -0,0 +1,94 @@ +/* + * QEMU model of the Xilinx usb subsystem + * + * Copyright (c) 2020 Xilinx Inc. Sai Pavan Boddu + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/irq.h" +#include "hw/register.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qom/object.h" +#include "qapi/error.h" +#include "hw/qdev-properties.h" +#include "hw/usb/xlnx-usb-subsystem.h" + +static void versal_usb2_realize(DeviceState *dev, Error **errp) +{ + VersalUsb2 *s =3D VERSAL_USB2(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + Error *err =3D NULL; + + sysbus_realize(SYS_BUS_DEVICE(&s->dwc3), &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_realize(SYS_BUS_DEVICE(&s->usb2Ctrl), &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_init_mmio(sbd, &s->dwc3_mr); + sysbus_init_mmio(sbd, &s->usb2Ctrl_mr); + qdev_pass_gpios(DEVICE(&s->dwc3.sysbus_xhci), dev, SYSBUS_DEVICE_GPIO_= IRQ); +} + +static void versal_usb2_init(Object *obj) +{ + VersalUsb2 *s =3D VERSAL_USB2(obj); + + object_initialize_child(obj, "versal.dwc3", &s->dwc3, + TYPE_USB_DWC3); + object_initialize_child(obj, "versal.usb2-ctrl", &s->usb2Ctrl, + TYPE_XILINX_VERSAL_USB2_CTRL_REGS); + memory_region_init_alias(&s->dwc3_mr, obj, "versal.dwc3_alias", + &s->dwc3.iomem, 0, DWC3_SIZE); + memory_region_init_alias(&s->usb2Ctrl_mr, obj, "versal.usb2Ctrl_alias", + &s->usb2Ctrl.iomem, 0, USB2_REGS_R_MAX * 4); + qdev_alias_all_properties(DEVICE(&s->dwc3), obj); + qdev_alias_all_properties(DEVICE(&s->dwc3.sysbus_xhci), obj); + object_property_add_alias(obj, "dma", OBJECT(&s->dwc3.sysbus_xhci), "d= ma"); +} + +static void versal_usb2_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D versal_usb2_realize; +} + +static const TypeInfo versal_usb2_info =3D { + .name =3D TYPE_XILINX_VERSAL_USB2, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(VersalUsb2), + .class_init =3D versal_usb2_class_init, + .instance_init =3D versal_usb2_init, +}; + +static void versal_usb_types(void) +{ + type_register_static(&versal_usb2_info); +} + +type_init(versal_usb_types) diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig index 56da78a4faf..40093d7ea6b 100644 --- a/hw/usb/Kconfig +++ b/hw/usb/Kconfig @@ -117,3 +117,8 @@ config USB_DWC3 bool select USB_XHCI_SYSBUS select REGISTER + +config XLNX_USB_SUBSYS + bool + default y if XLNX_VERSAL + select USB_DWC3 diff --git a/hw/usb/meson.build b/hw/usb/meson.build index 433c27e833e..f46c6b66553 100644 --- a/hw/usb/meson.build +++ b/hw/usb/meson.build @@ -32,6 +32,7 @@ softmmu_ss.add(when: 'CONFIG_TUSB6010', if_true: files('t= usb6010.c')) softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('chipidea.c')) softmmu_ss.add(when: 'CONFIG_IMX_USBPHY', if_true: files('imx-usb-phy.c')) specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-us= b2-ctrl-regs.c')) +specific_ss.add(when: 'CONFIG_XLNX_USB_SUBSYS', if_true: files('xlnx-usb-s= ubsystem.c')) =20 # emulated usb devices softmmu_ss.add(when: 'CONFIG_USB', if_true: files('dev-hub.c')) --=20 2.20.1 From nobody Thu Dec 18 13:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w21sm19667319wmi.45.2020.12.15.06.12.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 06:12:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=BVdQYpeeDaGlQTLZrRZJpRjKa+WjOxoqQv5yiE7c3/w=; b=ksPWwL9pnQXC9+bvueitMHjEQEg7N6KjEyyrWImFIyXhHLqGIzyZE/Zqa+N2PQFbjc mfpYglf28+fe7khE2XD84E+wmi+fLjR2DgCXMia+gv5EIBMnr3sEfVY5G4pXYSEYAefg IXJG6TK4nUG86fRJBRVKWFWCnsA/PfwGmUZFS3A9k4f2UjV5JlJbqhkGXJ/0ERB05q/d dDA6rUhaunhycakjalUpE8+kNMYmstjyZp3Hk79zloPfb55VZHrqN5pHPDvaUORv2d3+ RO98sS3ntT6cZcov0/SyImFzZkcAuEiRKpLmgyDXWIDb4INLealWXE2K+akOMSWVCNhV KOvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BVdQYpeeDaGlQTLZrRZJpRjKa+WjOxoqQv5yiE7c3/w=; b=pq2IBkFV1WRKaMO4WV0PI7RDuGcGqDaltEB98yc1Bu0wQFL4RF+03xOORxnQrSkKW+ VZUqVAMflE9S9WVQTleG9vQxeqDVcszQEk0WQQw6/qqZO7jOaEbme8eZTQtctKv/davy TizpHAJMjzTRIXCUW0la2cRN9EyYNVShW7Kz1PYUzGV4akCCUmHw6HVoPo2IuJ0oXaZ3 mMEZTzJeBx7JdaitYZMJV9oQF5jZI5Gl8B7QFJnWRpcbfskvezpTePWvc9HqxM1mhw7l NEdTRFJZd5XG2hBms1kpuZhAVnF64JUMwT7iHWdKEiamWjM5PZ9hkozbh/UedY/JLZ/k wmmw== X-Gm-Message-State: AOAM530UAWSZMyLbsmRuDQK/3gDPscT7MAgu/ENZsel5elvtUfvQVAWC gv6ULsfH9r7uSqukJIyk7CKBJ/mViUCvIw== X-Google-Smtp-Source: ABdhPJwTVRAI2jyrJwnHKCM1/f1Ej5RXN2jYvKaQsFqeVP1OE+2BniczjPpWQs1WJ3j+OrMAqpAdyg== X-Received: by 2002:adf:fbc5:: with SMTP id d5mr2925197wrs.82.1608041577257; Tue, 15 Dec 2020 06:12:57 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/20] arm: xlnx-versal: Connect usb to virt-versal Date: Tue, 15 Dec 2020 14:12:32 +0000 Message-Id: <20201215141237.17868-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201215141237.17868-1-peter.maydell@linaro.org> References: <20201215141237.17868-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Vikram Garhwal Connect VersalUsb2 subsystem to xlnx-versal SOC, its placed in iou of lpd domain and configure it as dual port host controller. Add the respective guest dts nodes for "xlnx-versal-virt" machine. Signed-off-by: Vikram Garhwal Signed-off-by: Sai Pavan Boddu Reviewed-by: Edgar E. Iglesias Message-id: 1607023357-5096-5-git-send-email-sai.pavan.boddu@xilinx.com Signed-off-by: Peter Maydell --- include/hw/arm/xlnx-versal.h | 9 ++++++ hw/arm/xlnx-versal-virt.c | 55 ++++++++++++++++++++++++++++++++++++ hw/arm/xlnx-versal.c | 26 +++++++++++++++++ 3 files changed, 90 insertions(+) diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 8ce8e63b56c..2b76885afd6 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -21,6 +21,7 @@ #include "hw/net/cadence_gem.h" #include "hw/rtc/xlnx-zynqmp-rtc.h" #include "qom/object.h" +#include "hw/usb/xlnx-usb-subsystem.h" =20 #define TYPE_XLNX_VERSAL "xlnx-versal" OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) @@ -59,6 +60,7 @@ struct Versal { PL011State uart[XLNX_VERSAL_NR_UARTS]; CadenceGEMState gem[XLNX_VERSAL_NR_GEMS]; XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS]; + VersalUsb2 usb; } iou; } lpd; =20 @@ -88,6 +90,7 @@ struct Versal { =20 #define VERSAL_UART0_IRQ_0 18 #define VERSAL_UART1_IRQ_0 19 +#define VERSAL_USB0_IRQ_0 22 #define VERSAL_GEM0_IRQ_0 56 #define VERSAL_GEM0_WAKE_IRQ_0 57 #define VERSAL_GEM1_IRQ_0 58 @@ -125,6 +128,12 @@ struct Versal { #define MM_OCM 0xfffc0000U #define MM_OCM_SIZE 0x40000 =20 +#define MM_USB2_CTRL_REGS 0xFF9D0000 +#define MM_USB2_CTRL_REGS_SIZE 0x10000 + +#define MM_USB_0 0xFE200000 +#define MM_USB_0_SIZE 0x10000 + #define MM_TOP_DDR 0x0 #define MM_TOP_DDR_SIZE 0x80000000U #define MM_TOP_DDR_2 0x800000000ULL diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index ee1282241e3..8482cd61960 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -39,6 +39,8 @@ struct VersalVirt { uint32_t ethernet_phy[2]; uint32_t clk_125Mhz; uint32_t clk_25Mhz; + uint32_t usb; + uint32_t dwc; } phandle; struct arm_boot_info binfo; =20 @@ -66,6 +68,8 @@ static void fdt_create(VersalVirt *s) s->phandle.clk_25Mhz =3D qemu_fdt_alloc_phandle(s->fdt); s->phandle.clk_125Mhz =3D qemu_fdt_alloc_phandle(s->fdt); =20 + s->phandle.usb =3D qemu_fdt_alloc_phandle(s->fdt); + s->phandle.dwc =3D qemu_fdt_alloc_phandle(s->fdt); /* Create /chosen node for load_dtb. */ qemu_fdt_add_subnode(s->fdt, "/chosen"); =20 @@ -148,6 +152,56 @@ static void fdt_add_timer_nodes(VersalVirt *s) compat, sizeof(compat)); } =20 +static void fdt_add_usb_xhci_nodes(VersalVirt *s) +{ + const char clocknames[] =3D "bus_clk\0ref_clk"; + const char irq_name[] =3D "dwc_usb3"; + const char compatVersalDWC3[] =3D "xlnx,versal-dwc3"; + const char compatDWC3[] =3D "snps,dwc3"; + char *name =3D g_strdup_printf("/usb@%" PRIx32, MM_USB2_CTRL_REGS); + + qemu_fdt_add_subnode(s->fdt, name); + qemu_fdt_setprop(s->fdt, name, "compatible", + compatVersalDWC3, sizeof(compatVersalDWC3)); + qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", + 2, MM_USB2_CTRL_REGS, + 2, MM_USB2_CTRL_REGS_SIZE); + qemu_fdt_setprop(s->fdt, name, "clock-names", + clocknames, sizeof(clocknames)); + qemu_fdt_setprop_cells(s->fdt, name, "clocks", + s->phandle.clk_25Mhz, s->phandle.clk_125Mhz= ); + qemu_fdt_setprop(s->fdt, name, "ranges", NULL, 0); + qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 2); + qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 2); + qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.usb); + g_free(name); + + name =3D g_strdup_printf("/usb@%" PRIx32 "/dwc3@%" PRIx32, + MM_USB2_CTRL_REGS, MM_USB_0); + qemu_fdt_add_subnode(s->fdt, name); + qemu_fdt_setprop(s->fdt, name, "compatible", + compatDWC3, sizeof(compatDWC3)); + qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", + 2, MM_USB_0, 2, MM_USB_0_SIZE); + qemu_fdt_setprop(s->fdt, name, "interrupt-names", + irq_name, sizeof(irq_name)); + qemu_fdt_setprop_cells(s->fdt, name, "interrupts", + GIC_FDT_IRQ_TYPE_SPI, VERSAL_USB0_IRQ_0, + GIC_FDT_IRQ_FLAGS_LEVEL_HI); + qemu_fdt_setprop_cell(s->fdt, name, + "snps,quirk-frame-length-adjustment", 0x20); + qemu_fdt_setprop_cells(s->fdt, name, "#stream-id-cells", 1); + qemu_fdt_setprop_string(s->fdt, name, "dr_mode", "host"); + qemu_fdt_setprop_string(s->fdt, name, "phy-names", "usb3-phy"); + qemu_fdt_setprop(s->fdt, name, "snps,dis_u2_susphy_quirk", NULL, 0); + qemu_fdt_setprop(s->fdt, name, "snps,dis_u3_susphy_quirk", NULL, 0); + qemu_fdt_setprop(s->fdt, name, "snps,refclk_fladj", NULL, 0); + qemu_fdt_setprop(s->fdt, name, "snps,mask_phy_reset", NULL, 0); + qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.dwc); + qemu_fdt_setprop_string(s->fdt, name, "maximum-speed", "high-speed"); + g_free(name); +} + static void fdt_add_uart_nodes(VersalVirt *s) { uint64_t addrs[] =3D { MM_UART1, MM_UART0 }; @@ -515,6 +569,7 @@ static void versal_virt_init(MachineState *machine) fdt_add_gic_nodes(s); fdt_add_timer_nodes(s); fdt_add_zdma_nodes(s); + fdt_add_usb_xhci_nodes(s); fdt_add_sd_nodes(s); fdt_add_rtc_node(s); fdt_add_cpu_nodes(s, psci_conduit); diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 12ba6c4ebae..b0777166e89 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -145,6 +145,31 @@ static void versal_create_uarts(Versal *s, qemu_irq *p= ic) } } =20 +static void versal_create_usbs(Versal *s, qemu_irq *pic) +{ + DeviceState *dev; + MemoryRegion *mr; + + object_initialize_child(OBJECT(s), "usb2", &s->lpd.iou.usb, + TYPE_XILINX_VERSAL_USB2); + dev =3D DEVICE(&s->lpd.iou.usb); + + object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps), + &error_abort); + qdev_prop_set_uint32(dev, "intrs", 1); + qdev_prop_set_uint32(dev, "slots", 2); + + sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); + + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + memory_region_add_subregion(&s->mr_ps, MM_USB_0, mr); + + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_USB0_IRQ_0]); + + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); + memory_region_add_subregion(&s->mr_ps, MM_USB2_CTRL_REGS, mr); +} + static void versal_create_gems(Versal *s, qemu_irq *pic) { int i; @@ -333,6 +358,7 @@ static void versal_realize(DeviceState *dev, Error **er= rp) versal_create_apu_cpus(s); versal_create_apu_gic(s, pic); versal_create_uarts(s, pic); + versal_create_usbs(s, pic); versal_create_gems(s, pic); versal_create_admas(s, pic); versal_create_sds(s, pic); --=20 2.20.1 From nobody Thu Dec 18 13:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608046151; cv=none; d=zohomail.com; s=zohoarc; b=oLPzCsOzKibfLs8SMdMU+h83sAfvZY1YpTSi2uD1WDToFPnogCrqFeQ0D3dqpyDdWUw0I3DxAXmVRIGZHCWcPbJuoAjB2Mhr7r7o/yxR8vJUardHklYf95a9aIUGrqdciqxPYHhmm64D3E0IzxSSd0Im0PP0d+kHqI8hirOUqRk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w21sm19667319wmi.45.2020.12.15.06.12.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 06:12:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=omEaEv7tsoVESKVfIPchee3NEbEA4EUcrD+MDCo3biM=; b=zurU6hqObufGMVUtwXwABxtEPbFnl0pO+rdSFdtPEmIw/h3JV49zfVAcl0+3FR+FAl 3ac7hHloXWrrVA9axp0GWIQtifQrw5OB7D8yxgiQ2jkU9cprRr3UScCYttvnjbqT/SUk MfIYk6/PEsuu4pK21SqB70sF+XJuqyYWNQXGeKubwZ0hFLpqRdGVrhwJx5wkt77JXv6H OW6xrkwTG9dsfUuoJ3JQ06AStrvY2OP77jTTCZuwfKDx5rw+IEWcPrv3PGNMwyvls8hr c9QeAcVCv5FsQqopIpfMceBwZNobvoLZ0frM3q/6WowbvgcinfYsfG8cAA9k54W5lDOn Oqmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=omEaEv7tsoVESKVfIPchee3NEbEA4EUcrD+MDCo3biM=; b=CTqvCI3feYmcDgFzyH9uOt4+Lt6s54i4NIr1zcvoznzMWTNzcT+3Sl4t6H+lQ+9Wld qT76nVQiC9+ySNvmjTBDrPK+w77bIfH/bMhkwQyzaZLRj/g0YmGwatV9OrFGQfwCvgqJ e7VwSVLbvXNZGT88SNOcMHqULEoG1VLpUaT2fBt97i1/+z7C91iDY2uW/EfjpvcRXwGr yrMzZY9CTaRuhS4Y/3GXH//F3/9aQWC0cmMEVexUYLNfVAxNxJSPFR6myFRnrrZZhPr2 /RGKR52vxT4lztsCIjpM7EbmeZbhHBIwHqrfeM5QMM4rJwZZePnJMJ9tDcbQynE7zVeG Wa8A== X-Gm-Message-State: AOAM530s7oIbhHUM9SzIM7J70ctkmvy1+qoq2ZSzlH9PzUP9HJjYwH9K Uihm1f//ResyMBcW01qRUgcO1RxbTX/1aw== X-Google-Smtp-Source: ABdhPJwagXwcr3ZqN7WvDP23txD7iQQlgRG0RIsm/QX8gNmPQH1aINTwtJgZumYc7xJ2S1f47OZP8g== X-Received: by 2002:a7b:cc0f:: with SMTP id f15mr33363123wmh.29.1608041578343; Tue, 15 Dec 2020 06:12:58 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/20] hw/misc/zynq_slcr: Avoid #DIV/0! error Date: Tue, 15 Dec 2020 14:12:33 +0000 Message-Id: <20201215141237.17868-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201215141237.17868-1-peter.maydell@linaro.org> References: <20201215141237.17868-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Philippe Mathieu-Daud=C3=A9 Malicious user can set the feedback divisor for the PLLs to zero, triggering a floating-point exception (SIGFPE). As the datasheet [*] is not clear how hardware behaves when these bits are zeroes, use the maximum divisor possible (128) to avoid the software FPE. [*] Zynq-7000 TRM, UG585 (v1.12.2) B.28 System Level Control Registers (slcr) -> "Register (slcr) ARM_PLL_CTRL" 25.10.4 PLLs -> "Software-Controlled PLL Update" Fixes: 38867cb7ec9 ("hw/misc/zynq_slcr: add clock generation for uarts") Reported-by: Gaoning Pan Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Reviewed-by: Damien Hedde Message-id: 20201210141610.884600-1-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/misc/zynq_slcr.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index a2b28019e3c..66504a9d3ab 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -217,6 +217,11 @@ static uint64_t zynq_slcr_compute_pll(uint64_t input, = uint32_t ctrl_reg) return 0; } =20 + /* Consider zero feedback as maximum divide ratio possible */ + if (!mult) { + mult =3D 1 << R_xxx_PLL_CTRL_PLL_FPDIV_LENGTH; + } + /* frequency multiplier -> period division */ return input / mult; } --=20 2.20.1 From nobody Thu Dec 18 13:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608067912; cv=none; d=zohomail.com; s=zohoarc; b=RLXNCZ7TeTcvn8XoNpPWzTadD4/3by/Bc1f9LoyYJigBNxJoPz81V+S2NZB9+O3TwViXx98XfToAL9ed4zj6myLg0fEswW2WB3LOr+1Y86qH9grgwj8fpdn+F6juRu+B1dOBhaBIibp+u75Eg6dLMDPGjUC8RlRbPSEExLvvvSE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608067912; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=V7Ov92RUYFvG6DWeSAUrDBWYIPL7mYHIZYb3185Jc8w=; b=PZ3VgIz6rjgYMm6U+pinEw9mulQIsrbEoyG0CWFB4zPUFk+C2S2A1pDAgrSPKVPTFSNPww0N35jQd2CEFBhLfvVWWhzfc745WSNc2rs0XiodA7m24hk/QeMnmykXfj6YFyDgEaj5NPxFywSO9PX8Y891PfcYsH4ETPq0wQxD0zQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 160806791224317.292194815813446; Tue, 15 Dec 2020 13:31:52 -0800 (PST) Received: from localhost ([::1]:41850 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kpBLv-0008K4-FG for importer@patchew.org; Tue, 15 Dec 2020 09:30:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34164) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kpB4j-0001dF-69 for qemu-devel@nongnu.org; Tue, 15 Dec 2020 09:13:14 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:35685) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kpB4W-0007BM-V5 for qemu-devel@nongnu.org; Tue, 15 Dec 2020 09:13:12 -0500 Received: by mail-wm1-x342.google.com with SMTP id e25so18631822wme.0 for ; Tue, 15 Dec 2020 06:13:00 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w21sm19667319wmi.45.2020.12.15.06.12.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 06:12:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=V7Ov92RUYFvG6DWeSAUrDBWYIPL7mYHIZYb3185Jc8w=; b=u622psWw+Bfq1xhawMyyWg0KgGSktGjkhI6Hpqk5ebOoFXkJVtevuXgmBdWtOaRq49 ULao6Ey5IrLb6dMKcVKqpcp5CZK4S5bCNhf5xnHDyKvS+VrZJkuxhmVaHLFThsVOGGQG 9whxAE6h9pmMXuCoGpawKhyh+d+qMQabUOVUgkBvxBoVQDO+uDSwYsiOxiE35/JeYpTP w7FeLIUKxbbIRwmI+SfPseVedV/olR00I4aWtP0bpoRjQwvsBX/UJ6k0ZinySh6360gO Bsa01Xu1/gb15+CLOZnlOoFVLD1hnJYeLBeZEJWvPLreZVNyV3oSMRyzxBysg9yi3CcN knlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=V7Ov92RUYFvG6DWeSAUrDBWYIPL7mYHIZYb3185Jc8w=; b=EL12aH2OFWi4IBS/u7MrEvOKgBET4yeF1PyMXjdmQlmzLdLki2qQBeDV024MY6dPoH vEkeHhdsF2Bb8aS7DyynaLM646yK/zwdGU1r3wY+5ZvB5ZSboZGMWUGLcWE3H5sRh8BO 6IpsVcTt5f80PZGGH9AKqPhvdbnNzYMv7BRNAS0mT8r/N4J7iot9xNyp4JNrgOWX/d5x j72eg1upCAesopP0d15IUgK9RjyXct2J8GZqXsK1bWda/Eji4jNlwArFDW9gV4zMQPs4 HTLW+K+LuH8Gym3ENWxKvnejjV6ei9KWh573epDdHlK9oHlVx8ciGuxvA3SctDXS3pI+ ek6A== X-Gm-Message-State: AOAM53320e5x+Z/Rta6zwdFPdKQ/2ccjXBwOwVumMHUmyCiCf8KidWqm 3V1RTa8W+P7r/7iRJRAjcMRlVCLNB4qTxQ== X-Google-Smtp-Source: ABdhPJynBDRRmw8Yuv6+BnmyiGFnrJJqpK64ExRGSrk/Asi6lZ3+u0N2F9DEBC4pPdfZmazoEIIioQ== X-Received: by 2002:a1c:6746:: with SMTP id b67mr32937632wmc.8.1608041579410; Tue, 15 Dec 2020 06:12:59 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/20] hw/block/m25p80: Make Numonyx config field names more accurate Date: Tue, 15 Dec 2020 14:12:34 +0000 Message-Id: <20201215141237.17868-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201215141237.17868-1-peter.maydell@linaro.org> References: <20201215141237.17868-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x342.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Joe Komlodi The previous naming of the configuration registers made it sound like that = if the bits were set the settings would be enabled, while the opposite is true. Signed-off-by: Joe Komlodi Reviewed-by: Francisco Iglesias Message-id: 1605568264-26376-2-git-send-email-komlodi@xilinx.com Signed-off-by: Peter Maydell --- hw/block/m25p80.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index d09a811767a..bad72538386 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -136,7 +136,7 @@ typedef struct FlashPartInfo { #define VCFG_WRAP_SEQUENTIAL 0x2 #define NVCFG_XIP_MODE_DISABLED (7 << 9) #define NVCFG_XIP_MODE_MASK (7 << 9) -#define VCFG_XIP_MODE_ENABLED (1 << 3) +#define VCFG_XIP_MODE_DISABLED (1 << 3) #define CFG_DUMMY_CLK_LEN 4 #define NVCFG_DUMMY_CLK_POS 12 #define VCFG_DUMMY_CLK_POS 4 @@ -144,9 +144,9 @@ typedef struct FlashPartInfo { #define EVCFG_VPP_ACCELERATOR (1 << 3) #define EVCFG_RESET_HOLD_ENABLED (1 << 4) #define NVCFG_DUAL_IO_MASK (1 << 2) -#define EVCFG_DUAL_IO_ENABLED (1 << 6) +#define EVCFG_DUAL_IO_DISABLED (1 << 6) #define NVCFG_QUAD_IO_MASK (1 << 3) -#define EVCFG_QUAD_IO_ENABLED (1 << 7) +#define EVCFG_QUAD_IO_DISABLED (1 << 7) #define NVCFG_4BYTE_ADDR_MASK (1 << 0) #define NVCFG_LOWER_SEGMENT_MASK (1 << 1) =20 @@ -769,7 +769,7 @@ static void reset_memory(Flash *s) s->volatile_cfg |=3D VCFG_WRAP_SEQUENTIAL; if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK) !=3D NVCFG_XIP_MODE_DISABLED) { - s->volatile_cfg |=3D VCFG_XIP_MODE_ENABLED; + s->volatile_cfg |=3D VCFG_XIP_MODE_DISABLED; } s->volatile_cfg |=3D deposit32(s->volatile_cfg, VCFG_DUMMY_CLK_POS, @@ -784,10 +784,10 @@ static void reset_memory(Flash *s) s->enh_volatile_cfg |=3D EVCFG_VPP_ACCELERATOR; s->enh_volatile_cfg |=3D EVCFG_RESET_HOLD_ENABLED; if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) { - s->enh_volatile_cfg |=3D EVCFG_DUAL_IO_ENABLED; + s->enh_volatile_cfg |=3D EVCFG_DUAL_IO_DISABLED; } if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) { - s->enh_volatile_cfg |=3D EVCFG_QUAD_IO_ENABLED; + s->enh_volatile_cfg |=3D EVCFG_QUAD_IO_DISABLED; } if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) { s->four_bytes_address_mode =3D true; --=20 2.20.1 From nobody Thu Dec 18 13:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608069517; cv=none; d=zohomail.com; s=zohoarc; b=WpDs4WjdPsnzdnBGrnb2eT4icsOAWHT9M5J8nuJk6NEcBU5P7su+GjKafafV3slEYwy7Ia7xBa8Mexpg5ogRN5Vg7Mh0jn2kXs2xjN8fIeVoZoJwkzOSEasiWeFthWS0yhD9+XF9FpskC9J3Xjxb3Ru69Itl4DhxVIg9n45V0xo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608069517; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6oHI4nI9UNd7uvlc5Xb1A8Ko50Iz35kwbptxV7aPIF8=; b=hCTsJbPvrEtG1qo2cxtZtOZIXKJTgcZzHADdgxpluCT2Uwqx7F/nHW7nnbPVlYMUcFd2MH5niwIGm2MZOH30f/CXN0yYY3sBoxgIq8tmLZHCdY9Y4meviWrHx7ti0EJWnSAyxJD9t2hfxDHM8hyitUnCOu1tl+HaSzn1DybMg4k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1608069517052805.7578834242939; Tue, 15 Dec 2020 13:58:37 -0800 (PST) Received: from localhost ([::1]:36922 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kpBJz-0006LH-Gp for importer@patchew.org; Tue, 15 Dec 2020 09:28:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34176) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kpB4l-0001eC-6i for qemu-devel@nongnu.org; Tue, 15 Dec 2020 09:13:15 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:34751) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kpB4Z-0007Ba-Cm for qemu-devel@nongnu.org; Tue, 15 Dec 2020 09:13:14 -0500 Received: by mail-wm1-x32b.google.com with SMTP id g25so11100192wmh.1 for ; Tue, 15 Dec 2020 06:13:01 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w21sm19667319wmi.45.2020.12.15.06.12.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 06:12:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=6oHI4nI9UNd7uvlc5Xb1A8Ko50Iz35kwbptxV7aPIF8=; b=yO5sx1v6gDzE4VdJpkQUYiqXp7oFgdBBbGbGaAG4RVBBCynIGZ9bBGLHJQcVHlT9zl 9LF0GLyg5xZRSbS8qlEF0tXeF+qBDD6uPSF4uu0dUgbnDMXmbbVxvDBBPBww0DjDJoYP v6syNfLAxBNjH61tXV6WsDzMGmu9rmTt+DdvTZjTQZoeTMYZwvmKIs0dBoZuQ3rBN01L XWcfNQa0WUD3tlKAkSD9hZdbeVEgmXCg3IEPQdnVHEUCdXhtGDn62tgq3EyehfOPtjZ0 B3EMLLmYBPq+m8n+064Ei8ZFwVWIobBnd3E5EwE1JiXJluP7AbyLbUby6p4m9WSIgQB2 a54A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6oHI4nI9UNd7uvlc5Xb1A8Ko50Iz35kwbptxV7aPIF8=; b=c3qqlP63NchDOIDifIL0dvbYvBNg6CDKaMt3yuVyAFD4fodkSlTghZvoNs2uajZdDV RY42VBaVrnh8Qv2tBISj0BfW/5FrxYj+jiUaD2jeq8ZnhGx0jF8wZGAshIVJrpVI/lk2 aRhSsHeCW6+DwXl8kUrahdFpSE96j+KnYERbhOwo142f01LUUeuhegfFNCKMwBQ437ug UjGHYYId/jOEzeiTnm2dHNZmkD059Wg3MVVltfRk0mvWfbMUr3j1Qg4/kDhkCWUe/bgZ cl6RBP7ecQ0JkifmIZArBIvaUY3VVltjtxHHiSmJvY0rS4Dy7xsOB8Q7KzmGx5e+QUjy 9Ocw== X-Gm-Message-State: AOAM531tzmdKtpLCgxumTfMB3UaQlBQu7XBPnxzG+uAXP1FlNJIYK+4F dMw+vFUtsIObUAy1w5n9BrpSJohgTJLIxQ== X-Google-Smtp-Source: ABdhPJyasY+tFVH2VrYkW9DAwKNrybbUfzwlgoA1pUuU6681MWdXXnhs/kO7lr3YqzNylhBtAUvv+g== X-Received: by 2002:a1c:151:: with SMTP id 78mr33597452wmb.24.1608041580440; Tue, 15 Dec 2020 06:13:00 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/20] hw/block/m25p80: Fix when VCFG XIP bit is set for Numonyx Date: Tue, 15 Dec 2020 14:12:35 +0000 Message-Id: <20201215141237.17868-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201215141237.17868-1-peter.maydell@linaro.org> References: <20201215141237.17868-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Joe Komlodi VCFG XIP is set (disabled) when the NVCFG XIP bits are all set (disabled). Signed-off-by: Joe Komlodi Reviewed-by: Francisco Iglesias Message-id: 1605568264-26376-3-git-send-email-komlodi@xilinx.com Signed-off-by: Peter Maydell --- hw/block/m25p80.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index bad72538386..7e1d56442f3 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -768,7 +768,7 @@ static void reset_memory(Flash *s) s->volatile_cfg |=3D VCFG_DUMMY; s->volatile_cfg |=3D VCFG_WRAP_SEQUENTIAL; if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK) - !=3D NVCFG_XIP_MODE_DISABLED) { + =3D=3D NVCFG_XIP_MODE_DISABLED) { s->volatile_cfg |=3D VCFG_XIP_MODE_DISABLED; } s->volatile_cfg |=3D deposit32(s->volatile_cfg, --=20 2.20.1 From nobody Thu Dec 18 13:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608064105; cv=none; d=zohomail.com; s=zohoarc; b=YMiAmC46JAa4AYGj8N2T6R4lEdWUHRHVaHp/qFM45Xyrtt2ilVnAUC67OLbWY3eWCsQ/yW+xU7rRoWH0+ZXTT+KG4vonG+HCA0E9eM9GqcMQZquNlxlhCqLBRj/LGFocByQ97UCbij6EXgQyAWx3OSG0FS4Ft65Uqdoy+Rn5LuA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1608064105; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=iwN8xvm/zL8pYcvIAxnIOen7Kx3k9vmW7ZQu1bw5NlI=; b=KU9McwxWGn5dkheTaZdVO3x2OdxjhMZ+P2hVewWj5+CfHPCg1dAXoKPHVgNU6fGIQWj94U1Ut7xDCCgDW7z4P6cnWGDJTP+OtAHoeGLZlqW0ZIwgSdgT4z8FvRWO8zqoZMHM68i+kQrKrw9B4CVd6WZUG8mi2X5wxBH7i1Brn7g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1608064105808113.73526342679804; Tue, 15 Dec 2020 12:28:25 -0800 (PST) Received: from localhost ([::1]:56920 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kpBHi-0002zc-6T for importer@patchew.org; Tue, 15 Dec 2020 09:26:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34174) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kpB4k-0001ds-Pv for qemu-devel@nongnu.org; Tue, 15 Dec 2020 09:13:14 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:56236) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kpB4Z-0007Bo-DC for qemu-devel@nongnu.org; Tue, 15 Dec 2020 09:13:14 -0500 Received: by mail-wm1-x32b.google.com with SMTP id x22so17002724wmc.5 for ; Tue, 15 Dec 2020 06:13:02 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id w21sm19667319wmi.45.2020.12.15.06.13.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 06:13:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=iwN8xvm/zL8pYcvIAxnIOen7Kx3k9vmW7ZQu1bw5NlI=; b=yywqEv8xhprbUlYnT0+imlSo14RDDjO/vsg/e5jvv3f8nPT00ynir02DAaphNXW3N7 uYND73nbL5ydi57A3atqU7OkAN9DO6FYQ45XVAh12uGjWWMi6DBIuU4yArDOlsC9Ts1p gyBeAe6xG+3UoN0+5h/RnDDfch7fdpBXDg1VUOt0wQg6zqERSVff6EQtcm4jkSJ5HkwO oK8DVl+aOFudlNUQeG7gRFYcuPVX389izbsFS0uFX01oULoqt0YSRCgtcWV5jqqdDuIy L43CmyuuS6uxn4mQdh3daXdAdWuzEk60Aor9aZsgFaspYHO6Xv3e8qd+6PWoFD3XDILM yTPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iwN8xvm/zL8pYcvIAxnIOen7Kx3k9vmW7ZQu1bw5NlI=; b=j9HCJUSlJFGGHiGfOkYsAzTrHlv0wXikQRTBJziaDBI9IoJxvah4CQ4kHEDH9HAiZb BfGs52HGGI3HyBimCiNNydQLEwDhbII6kMJ3VXJ2KsCiHmbBk13n7W6mMMTEKNzSPtnb hdG2b2eO+UVjJfcz9hZ+2tJkVISe3Xz8h1Qn44xiCMOpRrSDpm1TVbdD7S0DnQCuYu0C ZNC7z2+xV4xY+SZSw5UGURhfXDt/Si9SwBHq0XW5zvlEd2PWwPQ0kSiJES2rikZnzeKp 8n5GkAusssLOOsBoh9wpjSaI3rMcgbFc0eg4Y/0rDapcJQu1SnMJ8kGU4ji4m7ywGGm2 qObw== X-Gm-Message-State: AOAM530XqvsCRETWVPs8siSUiENQ9YvkOcsO5oBfLLXDXzM3oUZOUO2A LXFrdFXvetknxsMTiBIjepGx0xfq3u88mg== X-Google-Smtp-Source: ABdhPJzuEF8O5xfrG/lHonMYjEK4RQCzk9OPN80G7g6x/CFbQ/fFbTdY5gNFqbLexyk07jOGE5bRaA== X-Received: by 2002:a7b:c19a:: with SMTP id y26mr32066096wmi.20.1608041581415; Tue, 15 Dec 2020 06:13:01 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/20] hw/block/m25p80: Check SPI mode before running some Numonyx commands Date: Tue, 15 Dec 2020 14:12:36 +0000 Message-Id: <20201215141237.17868-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201215141237.17868-1-peter.maydell@linaro.org> References: <20201215141237.17868-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Joe Komlodi Some Numonyx flash commands cannot be executed in DIO and QIO mode, such as trying to do DPP or DOR when in QIO mode. Signed-off-by: Joe Komlodi Reviewed-by: Francisco Iglesias Message-id: 1605568264-26376-4-git-send-email-komlodi@xilinx.com Signed-off-by: Peter Maydell --- hw/block/m25p80.c | 114 ++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 95 insertions(+), 19 deletions(-) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 7e1d56442f3..f1d7da65c85 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -413,6 +413,12 @@ typedef enum { MAN_GENERIC, } Manufacturer; =20 +typedef enum { + MODE_STD =3D 0, + MODE_DIO =3D 1, + MODE_QIO =3D 2 +} SPIMode; + #define M25P80_INTERNAL_DATA_BUFFER_SZ 16 =20 struct Flash { @@ -820,6 +826,17 @@ static void reset_memory(Flash *s) trace_m25p80_reset_done(s); } =20 +static uint8_t numonyx_mode(Flash *s) +{ + if (!(s->enh_volatile_cfg & EVCFG_QUAD_IO_DISABLED)) { + return MODE_QIO; + } else if (!(s->enh_volatile_cfg & EVCFG_DUAL_IO_DISABLED)) { + return MODE_DIO; + } else { + return MODE_STD; + } +} + static void decode_fast_read_cmd(Flash *s) { s->needed_bytes =3D get_addr_length(s); @@ -950,14 +967,8 @@ static void decode_new_cmd(Flash *s, uint32_t value) case ERASE4_32K: case ERASE_SECTOR: case ERASE4_SECTOR: - case READ: - case READ4: - case DPP: - case QPP: - case QPP_4: case PP: case PP4: - case PP4_4: case DIE_ERASE: case RDID_90: case RDID_AB: @@ -966,24 +977,84 @@ static void decode_new_cmd(Flash *s, uint32_t value) s->len =3D 0; s->state =3D STATE_COLLECTING_DATA; break; + case READ: + case READ4: + if (get_man(s) !=3D MAN_NUMONYX || numonyx_mode(s) =3D=3D MODE_STD= ) { + s->needed_bytes =3D get_addr_length(s); + s->pos =3D 0; + s->len =3D 0; + s->state =3D STATE_COLLECTING_DATA; + } else { + qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x = in " + "DIO or QIO mode\n", s->cmd_in_progress); + } + break; + case DPP: + if (get_man(s) !=3D MAN_NUMONYX || numonyx_mode(s) !=3D MODE_QIO) { + s->needed_bytes =3D get_addr_length(s); + s->pos =3D 0; + s->len =3D 0; + s->state =3D STATE_COLLECTING_DATA; + } else { + qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x = in " + "QIO mode\n", s->cmd_in_progress); + } + break; + case QPP: + case QPP_4: + case PP4_4: + if (get_man(s) !=3D MAN_NUMONYX || numonyx_mode(s) !=3D MODE_DIO) { + s->needed_bytes =3D get_addr_length(s); + s->pos =3D 0; + s->len =3D 0; + s->state =3D STATE_COLLECTING_DATA; + } else { + qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x = in " + "DIO mode\n", s->cmd_in_progress); + } + break; =20 case FAST_READ: case FAST_READ4: + decode_fast_read_cmd(s); + break; case DOR: case DOR4: + if (get_man(s) !=3D MAN_NUMONYX || numonyx_mode(s) !=3D MODE_QIO) { + decode_fast_read_cmd(s); + } else { + qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x = in " + "QIO mode\n", s->cmd_in_progress); + } + break; case QOR: case QOR4: - decode_fast_read_cmd(s); + if (get_man(s) !=3D MAN_NUMONYX || numonyx_mode(s) !=3D MODE_DIO) { + decode_fast_read_cmd(s); + } else { + qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x = in " + "DIO mode\n", s->cmd_in_progress); + } break; =20 case DIOR: case DIOR4: - decode_dio_read_cmd(s); + if (get_man(s) !=3D MAN_NUMONYX || numonyx_mode(s) !=3D MODE_QIO) { + decode_dio_read_cmd(s); + } else { + qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x = in " + "QIO mode\n", s->cmd_in_progress); + } break; =20 case QIOR: case QIOR4: - decode_qio_read_cmd(s); + if (get_man(s) !=3D MAN_NUMONYX || numonyx_mode(s) !=3D MODE_DIO) { + decode_qio_read_cmd(s); + } else { + qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x = in " + "DIO mode\n", s->cmd_in_progress); + } break; =20 case WRSR: @@ -1035,17 +1106,22 @@ static void decode_new_cmd(Flash *s, uint32_t value) break; =20 case JEDEC_READ: - trace_m25p80_populated_jedec(s); - for (i =3D 0; i < s->pi->id_len; i++) { - s->data[i] =3D s->pi->id[i]; - } - for (; i < SPI_NOR_MAX_ID_LEN; i++) { - s->data[i] =3D 0; - } + if (get_man(s) !=3D MAN_NUMONYX || numonyx_mode(s) =3D=3D MODE_STD= ) { + trace_m25p80_populated_jedec(s); + for (i =3D 0; i < s->pi->id_len; i++) { + s->data[i] =3D s->pi->id[i]; + } + for (; i < SPI_NOR_MAX_ID_LEN; i++) { + s->data[i] =3D 0; + } =20 - s->len =3D SPI_NOR_MAX_ID_LEN; - s->pos =3D 0; - s->state =3D STATE_READING_DATA; + s->len =3D SPI_NOR_MAX_ID_LEN; + s->pos =3D 0; + s->state =3D STATE_READING_DATA; + } else { + qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute JEDEC r= ead " + "in DIO or QIO mode\n"); + } break; =20 case RDCR: --=20 2.20.1 From nobody Thu Dec 18 13:35:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1608043020; cv=none; d=zohomail.com; s=zohoarc; b=balz2p+/R154loRu2WdGtvyN5xrrQwAtaIJRuCiVNcki9E5K3/9KMm5japbHcGt8bZRqqQeLujHRSjqMWG4SqEiCQwtJ1+8Q4OyypGc8iXLNuGAtVa4rknXWfDIoho9DekX3othTwiKA2ywgS2StD5Tcb4tDdRzJhIjA707BZzE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w21sm19667319wmi.45.2020.12.15.06.13.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 06:13:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=vfsjB+5EKQ5ZFSeZREuqmO7AlPzocEX4KU0OKohIt3c=; b=frfWHKaAe+fHHAfmdqqEsoftWpDK53HDkWRjg43IipnW2un6OE5RbDwnPy1wKS++05 TrCwAnkpCin7VOHUtHN2aHJ2AusPq+1y8enWfrBoJkYIpWcoWUw1Sa+w+baplR4B7opf I7MioIk6snMhQZqAhPmxcyqeSMuVkIDMQvSYgFksAibBXsizPBkIsJmz62wagHpKjB/0 HcI0GCqkVzSvOH0Is24meI/fo+bzbcHTDEBD7OepoaQ+hUqKPekEzpece+hWe8K1oDNi IH60xGl2CzI0IQEPMVG/gbFbkL4QHd3odkwBy8DhV4g3zw0Hm1Q0NiktfPgwM2USjJkc wnKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vfsjB+5EKQ5ZFSeZREuqmO7AlPzocEX4KU0OKohIt3c=; b=mE/fqvP/PnCzudwDFxvAVZVW3tsDsChlCLeeISQVSXX70I9nFtI/M9tQoGNjYc8iZz ebLf48HjL2pylgfr3O6Bl8EV98cU/zvNS42DQvNYNIF22/x5q0p7/qNHqVhO+VLJogd9 LoNoutUcDb9AXEjsav8QfTUB9HT9VrF+GPYHgYXfjPmiWHe9M+gQr+elKBKY/2p4GNYJ bEth9FXK9qAdIKEdcvRIeN87mKfMJ5bO+enzZAxAdORkhxl+iRSkHTV42iS2nRLB+Nz+ 81g/q6/L6WTgAYf7NBYspMgFmJvCKAa52KN5YWJJyZIcDJCP29lTUYG0rTU72e7tVCMr doEQ== X-Gm-Message-State: AOAM532srqOu5shCB+jjg94D0vgHU54Zve8stlyGenvtJ0CGmNsi38Ll KDcDr0oc/emYM7iZFR0X5ZQU/YEYbXo2DQ== X-Google-Smtp-Source: ABdhPJzb7+Cl1yUy4DQpghhp7trcG5do1e8NRDTzidwu81o8/O7XISFaoh3RY9ej8l/cL1ik91uQ/g== X-Received: by 2002:a5d:69c2:: with SMTP id s2mr2918340wrw.36.1608041582546; Tue, 15 Dec 2020 06:13:02 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/20] hw/block/m25p80: Fix Numonyx fast read dummy cycle count Date: Tue, 15 Dec 2020 14:12:37 +0000 Message-Id: <20201215141237.17868-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201215141237.17868-1-peter.maydell@linaro.org> References: <20201215141237.17868-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Joe Komlodi Numonyx chips determine the number of cycles to wait based on bits 7:4 in the volatile configuration register. However, if these bits are 0x0 or 0xF, the number of dummy cycles to wait is 10 for QIOR and QIOR4 commands or when in QIO mode, and otherwise 8= for the currently supported fast read commands. [1] [1] https://www.micron.com/-/media/client/global/documents/products/data-sheet/= nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_u_02g_cbb_0.pdf?rev=3D9b167= fbf2b3645efba6385949a72e453 Signed-off-by: Joe Komlodi Reviewed-by: Francisco Iglesias Message-id: 1605568264-26376-5-git-send-email-komlodi@xilinx.com Signed-off-by: Peter Maydell --- hw/block/m25p80.c | 30 +++++++++++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index f1d7da65c85..c45afdd2cb3 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -837,6 +837,30 @@ static uint8_t numonyx_mode(Flash *s) } } =20 +static uint8_t numonyx_extract_cfg_num_dummies(Flash *s) +{ + uint8_t num_dummies; + uint8_t mode; + assert(get_man(s) =3D=3D MAN_NUMONYX); + + mode =3D numonyx_mode(s); + num_dummies =3D extract32(s->volatile_cfg, 4, 4); + + if (num_dummies =3D=3D 0x0 || num_dummies =3D=3D 0xf) { + switch (s->cmd_in_progress) { + case QIOR: + case QIOR4: + num_dummies =3D 10; + break; + default: + num_dummies =3D (mode =3D=3D MODE_QIO) ? 10 : 8; + break; + } + } + + return num_dummies; +} + static void decode_fast_read_cmd(Flash *s) { s->needed_bytes =3D get_addr_length(s); @@ -846,7 +870,7 @@ static void decode_fast_read_cmd(Flash *s) s->needed_bytes +=3D 8; break; case MAN_NUMONYX: - s->needed_bytes +=3D extract32(s->volatile_cfg, 4, 4); + s->needed_bytes +=3D numonyx_extract_cfg_num_dummies(s); break; case MAN_MACRONIX: if (extract32(s->volatile_cfg, 6, 2) =3D=3D 1) { @@ -885,7 +909,7 @@ static void decode_dio_read_cmd(Flash *s) ); break; case MAN_NUMONYX: - s->needed_bytes +=3D extract32(s->volatile_cfg, 4, 4); + s->needed_bytes +=3D numonyx_extract_cfg_num_dummies(s); break; case MAN_MACRONIX: switch (extract32(s->volatile_cfg, 6, 2)) { @@ -925,7 +949,7 @@ static void decode_qio_read_cmd(Flash *s) ); break; case MAN_NUMONYX: - s->needed_bytes +=3D extract32(s->volatile_cfg, 4, 4); + s->needed_bytes +=3D numonyx_extract_cfg_num_dummies(s); break; case MAN_MACRONIX: switch (extract32(s->volatile_cfg, 6, 2)) { --=20 2.20.1