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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id b71sm2193033oii.5.2020.12.14.14.13.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 14:13:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NFSXYsZ6wJ6D+hIm4zULuabqSYFj3mqX+hLo+adztBw=; b=E5K/fAwmR+8PY6ggWzapzwrqig3PuTIa3RlSnN5fkyn5rVfBrXwLREgd2J88v9/CJk LKU9tM4UbOG/7p1Y9T6GhYWuXbV0vc6G4+huhimgNoTKmoEYJP8ZgkEzpx1vW+XbrNZD OqUSKCSBjflLITEP61LZv6UiDxgLZ0KKWI7uljpl/J+qwbg9AWcFphgDJkIrX4pmMTkQ nfA7bwomg5bW0LHr8opBehdBJPsviEgA7KkOygSuKV0w/eGZVuEprvrAzz/7oxE6ZL8F XffZ1TNnlIjFvDA6vfeDYFWFS6LwXhOcZn+0LYNuloFbswYgnj3JfP/ijA3UZxV0uykO wNZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NFSXYsZ6wJ6D+hIm4zULuabqSYFj3mqX+hLo+adztBw=; b=sokVbs+21eGfffysTYs5PabDDPa8XImzLorgf1nPybmrHvWO3bq6MjZpzmIHkUH2/l WBRb9spPV8jSKyGT1DagT24gahAifqJOoMkftwQbSBKuJdg18xyl9f43n2qc8BjJDUQf Kk4mIHYnE89aDNRSHwE03Pn52T7Eem8/+24esId0Ji6SCXRCjfippie6W/Y/a8G9hcQy mlZLW+42w6iC3v8WDc//IdkCEfLHE5FktrETVkhRLUDVQcD2HndhfT1Dybm3XnAIam7T nbE2X/Xex8TeU0zH8ZZEeVLpTaHskTSJqxBFOXdpkd5a9AofjwioY13CGCngcRj5BpgL LM4g== X-Gm-Message-State: AOAM533LmB/Eymh2hAbjXNPVHOv9qHPcl3McBpvHIhWjM6XkGoPGA01f AHMNQDu4OGuTDFq5UyyE0JDqlX9vWXfCTXbL X-Google-Smtp-Source: ABdhPJzldYvRHYl5UBWVTZDIzMdb0ANNu7RYDtzEFh9ZMGNdMZwbDSEL+Fqy2vaiIalyT42oMQdN/g== X-Received: by 2002:a9d:5613:: with SMTP id e19mr21107841oti.153.1607984039511; Mon, 14 Dec 2020 14:13:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 1/4] target/s390x: Improve cc computation for ADD LOGICAL Date: Mon, 14 Dec 2020 16:13:53 -0600 Message-Id: <20201214221356.68039-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214221356.68039-1-richard.henderson@linaro.org> References: <20201214221356.68039-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::332; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The resulting cc is only dependent on the result and the carry-out. So save those things rather than the inputs. Carry-out for 64-bit inputs is had via tcg_gen_add2_i64 directly into cc_src. Carry-out for 32-bit inputs is had via extraction from a normal 64-bit add (with zero-extended inputs). Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/internal.h | 4 +- target/s390x/cc_helper.c | 25 ++++----- target/s390x/helper.c | 3 +- target/s390x/translate.c | 103 ++++++++++++++++++++++++------------- target/s390x/insn-data.def | 36 ++++++------- 5 files changed, 97 insertions(+), 74 deletions(-) diff --git a/target/s390x/internal.h b/target/s390x/internal.h index 64602660ae..55c5442102 100644 --- a/target/s390x/internal.h +++ b/target/s390x/internal.h @@ -160,6 +160,8 @@ enum cc_op { CC_OP_STATIC, /* CC value is env->cc_op */ =20 CC_OP_NZ, /* env->cc_dst !=3D 0 */ + CC_OP_ADDU, /* dst !=3D 0, src =3D carry out (0,1) */ + CC_OP_LTGT_32, /* signed less/greater than (32bit) */ CC_OP_LTGT_64, /* signed less/greater than (64bit) */ CC_OP_LTUGTU_32, /* unsigned less/greater than (32bit) */ @@ -168,7 +170,6 @@ enum cc_op { CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */ =20 CC_OP_ADD_64, /* overflow on add (64bit) */ - CC_OP_ADDU_64, /* overflow on unsigned add (64bit) */ CC_OP_ADDC_64, /* overflow on unsigned add-carry (64bit) = */ CC_OP_SUB_64, /* overflow on subtraction (64bit) */ CC_OP_SUBU_64, /* overflow on unsigned subtraction (64bit= ) */ @@ -178,7 +179,6 @@ enum cc_op { CC_OP_MULS_64, /* overflow on signed multiply (64bit) */ =20 CC_OP_ADD_32, /* overflow on add (32bit) */ - CC_OP_ADDU_32, /* overflow on unsigned add (32bit) */ CC_OP_ADDC_32, /* overflow on unsigned add-carry (32bit) = */ CC_OP_SUB_32, /* overflow on subtraction (32bit) */ CC_OP_SUBU_32, /* overflow on unsigned subtraction (32bit= ) */ diff --git a/target/s390x/cc_helper.c b/target/s390x/cc_helper.c index 5432aeeed4..59da4d1cc2 100644 --- a/target/s390x/cc_helper.c +++ b/target/s390x/cc_helper.c @@ -123,6 +123,12 @@ static uint32_t cc_calc_nz(uint64_t dst) return !!dst; } =20 +static uint32_t cc_calc_addu(uint64_t carry_out, uint64_t result) +{ + g_assert(carry_out <=3D 1); + return (result !=3D 0) + 2 * carry_out; +} + static uint32_t cc_calc_add_64(int64_t a1, int64_t a2, int64_t ar) { if ((a1 > 0 && a2 > 0 && ar < 0) || (a1 < 0 && a2 < 0 && ar > 0)) { @@ -138,11 +144,6 @@ static uint32_t cc_calc_add_64(int64_t a1, int64_t a2,= int64_t ar) } } =20 -static uint32_t cc_calc_addu_64(uint64_t a1, uint64_t a2, uint64_t ar) -{ - return (ar !=3D 0) + 2 * (ar < a1); -} - static uint32_t cc_calc_addc_64(uint64_t a1, uint64_t a2, uint64_t ar) { /* Recover a2 + carry_in. */ @@ -239,11 +240,6 @@ static uint32_t cc_calc_add_32(int32_t a1, int32_t a2,= int32_t ar) } } =20 -static uint32_t cc_calc_addu_32(uint32_t a1, uint32_t a2, uint32_t ar) -{ - return (ar !=3D 0) + 2 * (ar < a1); -} - static uint32_t cc_calc_addc_32(uint32_t a1, uint32_t a2, uint32_t ar) { /* Recover a2 + carry_in. */ @@ -483,12 +479,12 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32= _t cc_op, case CC_OP_NZ: r =3D cc_calc_nz(dst); break; + case CC_OP_ADDU: + r =3D cc_calc_addu(src, dst); + break; case CC_OP_ADD_64: r =3D cc_calc_add_64(src, dst, vr); break; - case CC_OP_ADDU_64: - r =3D cc_calc_addu_64(src, dst, vr); - break; case CC_OP_ADDC_64: r =3D cc_calc_addc_64(src, dst, vr); break; @@ -517,9 +513,6 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t= cc_op, case CC_OP_ADD_32: r =3D cc_calc_add_32(src, dst, vr); break; - case CC_OP_ADDU_32: - r =3D cc_calc_addu_32(src, dst, vr); - break; case CC_OP_ADDC_32: r =3D cc_calc_addc_32(src, dst, vr); break; diff --git a/target/s390x/helper.c b/target/s390x/helper.c index b877690845..db87a62a57 100644 --- a/target/s390x/helper.c +++ b/target/s390x/helper.c @@ -395,6 +395,7 @@ const char *cc_name(enum cc_op cc_op) [CC_OP_DYNAMIC] =3D "CC_OP_DYNAMIC", [CC_OP_STATIC] =3D "CC_OP_STATIC", [CC_OP_NZ] =3D "CC_OP_NZ", + [CC_OP_ADDU] =3D "CC_OP_ADDU", [CC_OP_LTGT_32] =3D "CC_OP_LTGT_32", [CC_OP_LTGT_64] =3D "CC_OP_LTGT_64", [CC_OP_LTUGTU_32] =3D "CC_OP_LTUGTU_32", @@ -402,7 +403,6 @@ const char *cc_name(enum cc_op cc_op) [CC_OP_LTGT0_32] =3D "CC_OP_LTGT0_32", [CC_OP_LTGT0_64] =3D "CC_OP_LTGT0_64", [CC_OP_ADD_64] =3D "CC_OP_ADD_64", - [CC_OP_ADDU_64] =3D "CC_OP_ADDU_64", [CC_OP_ADDC_64] =3D "CC_OP_ADDC_64", [CC_OP_SUB_64] =3D "CC_OP_SUB_64", [CC_OP_SUBU_64] =3D "CC_OP_SUBU_64", @@ -410,7 +410,6 @@ const char *cc_name(enum cc_op cc_op) [CC_OP_ABS_64] =3D "CC_OP_ABS_64", [CC_OP_NABS_64] =3D "CC_OP_NABS_64", [CC_OP_ADD_32] =3D "CC_OP_ADD_32", - [CC_OP_ADDU_32] =3D "CC_OP_ADDU_32", [CC_OP_ADDC_32] =3D "CC_OP_ADDC_32", [CC_OP_SUB_32] =3D "CC_OP_SUB_32", [CC_OP_SUBU_32] =3D "CC_OP_SUBU_32", diff --git a/target/s390x/translate.c b/target/s390x/translate.c index be32938f6d..b473233edf 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -600,13 +600,11 @@ static void gen_op_calc_cc(DisasContext *s) dummy =3D tcg_const_i64(0); /* FALLTHRU */ case CC_OP_ADD_64: - case CC_OP_ADDU_64: case CC_OP_ADDC_64: case CC_OP_SUB_64: case CC_OP_SUBU_64: case CC_OP_SUBB_64: case CC_OP_ADD_32: - case CC_OP_ADDU_32: case CC_OP_ADDC_32: case CC_OP_SUB_32: case CC_OP_SUBU_32: @@ -650,6 +648,7 @@ static void gen_op_calc_cc(DisasContext *s) /* 1 argument */ gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, dummy, cc_dst, dum= my); break; + case CC_OP_ADDU: case CC_OP_ICM: case CC_OP_LTGT_32: case CC_OP_LTGT_64: @@ -666,13 +665,11 @@ static void gen_op_calc_cc(DisasContext *s) gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, du= mmy); break; case CC_OP_ADD_64: - case CC_OP_ADDU_64: case CC_OP_ADDC_64: case CC_OP_SUB_64: case CC_OP_SUBU_64: case CC_OP_SUBB_64: case CC_OP_ADD_32: - case CC_OP_ADDU_32: case CC_OP_ADDC_32: case CC_OP_SUB_32: case CC_OP_SUBU_32: @@ -849,20 +846,19 @@ static void disas_jcc(DisasContext *s, DisasCompare *= c, uint32_t mask) account_inline_branch(s, old_cc_op); break; =20 - case CC_OP_ADDU_32: - case CC_OP_ADDU_64: + case CC_OP_ADDU: switch (mask) { - case 8 | 2: /* vr =3D=3D 0 */ + case 8 | 2: /* result =3D=3D 0 */ cond =3D TCG_COND_EQ; break; - case 4 | 1: /* vr !=3D 0 */ + case 4 | 1: /* result !=3D 0 */ cond =3D TCG_COND_NE; break; - case 8 | 4: /* no carry -> vr >=3D src */ - cond =3D TCG_COND_GEU; + case 8 | 4: /* no carry */ + cond =3D TCG_COND_EQ; break; - case 2 | 1: /* carry -> vr < src */ - cond =3D TCG_COND_LTU; + case 2 | 1: /* carry */ + cond =3D TCG_COND_NE; break; default: goto do_dynamic; @@ -950,26 +946,21 @@ static void disas_jcc(DisasContext *s, DisasCompare *= c, uint32_t mask) tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst); break; =20 - case CC_OP_ADDU_32: - c->is_64 =3D false; - c->u.s32.a =3D tcg_temp_new_i32(); - c->u.s32.b =3D tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(c->u.s32.a, cc_vr); - if (cond =3D=3D TCG_COND_EQ || cond =3D=3D TCG_COND_NE) { - tcg_gen_movi_i32(c->u.s32.b, 0); - } else { - tcg_gen_extrl_i64_i32(c->u.s32.b, cc_src); - } - break; - - case CC_OP_ADDU_64: - c->u.s64.a =3D cc_vr; + case CC_OP_ADDU: + c->is_64 =3D true; + c->u.s64.b =3D tcg_const_i64(0); c->g1 =3D true; - if (cond =3D=3D TCG_COND_EQ || cond =3D=3D TCG_COND_NE) { - c->u.s64.b =3D tcg_const_i64(0); - } else { - c->u.s64.b =3D cc_src; - c->g2 =3D true; + switch (mask) { + case 8 | 2: + case 4 | 1: /* result */ + c->u.s64.a =3D cc_dst; + break; + case 8 | 4: + case 2 | 1: /* carry */ + c->u.s64.a =3D cc_src; + break; + default: + g_assert_not_reached(); } break; =20 @@ -1445,6 +1436,13 @@ static DisasJumpType op_add(DisasContext *s, DisasOp= s *o) return DISAS_NEXT; } =20 +static DisasJumpType op_addu64(DisasContext *s, DisasOps *o) +{ + tcg_gen_movi_i64(cc_src, 0); + tcg_gen_add2_i64(o->out, cc_src, o->in1, cc_src, o->in2, cc_src); + return DISAS_NEXT; +} + static DisasJumpType op_addc(DisasContext *s, DisasOps *o) { DisasCompare cmp; @@ -1474,9 +1472,10 @@ static DisasJumpType op_addc(DisasContext *s, DisasO= ps *o) =20 static DisasJumpType op_asi(DisasContext *s, DisasOps *o) { - o->in1 =3D tcg_temp_new_i64(); + bool non_atomic =3D !s390_has_feat(S390_FEAT_STFLE_45); =20 - if (!s390_has_feat(S390_FEAT_STFLE_45)) { + o->in1 =3D tcg_temp_new_i64(); + if (non_atomic) { tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->da= ta); } else { /* Perform the atomic addition in memory. */ @@ -1487,7 +1486,30 @@ static DisasJumpType op_asi(DisasContext *s, DisasOp= s *o) /* Recompute also for atomic case: needed for setting CC. */ tcg_gen_add_i64(o->out, o->in1, o->in2); =20 - if (!s390_has_feat(S390_FEAT_STFLE_45)) { + if (non_atomic) { + tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->da= ta); + } + return DISAS_NEXT; +} + +static DisasJumpType op_asiu64(DisasContext *s, DisasOps *o) +{ + bool non_atomic =3D !s390_has_feat(S390_FEAT_STFLE_45); + + o->in1 =3D tcg_temp_new_i64(); + if (non_atomic) { + tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->da= ta); + } else { + /* Perform the atomic addition in memory. */ + tcg_gen_atomic_fetch_add_i64(o->in1, o->addr1, o->in2, get_mem_ind= ex(s), + s->insn->data); + } + + /* Recompute also for atomic case: needed for setting CC. */ + tcg_gen_movi_i64(cc_src, 0); + tcg_gen_add2_i64(o->out, cc_src, o->in1, cc_src, o->in2, cc_src); + + if (non_atomic) { tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->da= ta); } return DISAS_NEXT; @@ -5185,12 +5207,14 @@ static void cout_adds64(DisasContext *s, DisasOps *= o) =20 static void cout_addu32(DisasContext *s, DisasOps *o) { - gen_op_update3_cc_i64(s, CC_OP_ADDU_32, o->in1, o->in2, o->out); + tcg_gen_shri_i64(cc_src, o->out, 32); + tcg_gen_ext32u_i64(cc_dst, o->out); + gen_op_update2_cc_i64(s, CC_OP_ADDU, cc_src, cc_dst); } =20 static void cout_addu64(DisasContext *s, DisasOps *o) { - gen_op_update3_cc_i64(s, CC_OP_ADDU_64, o->in1, o->in2, o->out); + gen_op_update2_cc_i64(s, CC_OP_ADDU, cc_src, o->out); } =20 static void cout_addc32(DisasContext *s, DisasOps *o) @@ -5637,6 +5661,13 @@ static void in1_r2_sr32(DisasContext *s, DisasOps *o) } #define SPEC_in1_r2_sr32 0 =20 +static void in1_r2_32u(DisasContext *s, DisasOps *o) +{ + o->in1 =3D tcg_temp_new_i64(); + tcg_gen_ext32u_i64(o->in1, regs[get_field(s, r2)]); +} +#define SPEC_in1_r2_32u 0 + static void in1_r3(DisasContext *s, DisasOps *o) { o->in1 =3D load_reg(get_field(s, r3)); diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index b95bc98d35..5461e6aa3b 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -58,29 +58,29 @@ C(0xa70b, AGHI, RI_a, Z, r1, i2, r1, 0, add, adds64) =20 /* ADD LOGICAL */ - C(0x1e00, ALR, RR_a, Z, r1, r2, new, r1_32, add, addu32) - C(0xb9fa, ALRK, RRF_a, DO, r2, r3, new, r1_32, add, addu32) - C(0x5e00, AL, RX_a, Z, r1, m2_32u, new, r1_32, add, addu32) - C(0xe35e, ALY, RXY_a, LD, r1, m2_32u, new, r1_32, add, addu32) - C(0xb90a, ALGR, RRE, Z, r1, r2, r1, 0, add, addu64) - C(0xb91a, ALGFR, RRE, Z, r1, r2_32u, r1, 0, add, addu64) - C(0xb9ea, ALGRK, RRF_a, DO, r2, r3, r1, 0, add, addu64) - C(0xe30a, ALG, RXY_a, Z, r1, m2_64, r1, 0, add, addu64) - C(0xe31a, ALGF, RXY_a, Z, r1, m2_32u, r1, 0, add, addu64) + C(0x1e00, ALR, RR_a, Z, r1_32u, r2_32u, new, r1_32, add, addu32) + C(0xb9fa, ALRK, RRF_a, DO, r2_32u, r3_32u, new, r1_32, add, addu32) + C(0x5e00, AL, RX_a, Z, r1_32u, m2_32u, new, r1_32, add, addu32) + C(0xe35e, ALY, RXY_a, LD, r1_32u, m2_32u, new, r1_32, add, addu32) + C(0xb90a, ALGR, RRE, Z, r1, r2, r1, 0, addu64, addu64) + C(0xb91a, ALGFR, RRE, Z, r1, r2_32u, r1, 0, addu64, addu64) + C(0xb9ea, ALGRK, RRF_a, DO, r2, r3, r1, 0, addu64, addu64) + C(0xe30a, ALG, RXY_a, Z, r1, m2_64, r1, 0, addu64, addu64) + C(0xe31a, ALGF, RXY_a, Z, r1, m2_32u, r1, 0, addu64, addu64) /* ADD LOGICAL HIGH */ C(0xb9ca, ALHHHR, RRF_a, HW, r2_sr32, r3_sr32, new, r1_32h, add, add= u32) - C(0xb9da, ALHHLR, RRF_a, HW, r2_sr32, r3, new, r1_32h, add, addu32) + C(0xb9da, ALHHLR, RRF_a, HW, r2_sr32, r3_32u, new, r1_32h, add, addu= 32) /* ADD LOGICAL IMMEDIATE */ - C(0xc20b, ALFI, RIL_a, EI, r1, i2_32u, new, r1_32, add, addu32) - C(0xc20a, ALGFI, RIL_a, EI, r1, i2_32u, r1, 0, add, addu64) + C(0xc20b, ALFI, RIL_a, EI, r1_32u, i2_32u, new, r1_32, add, addu32) + C(0xc20a, ALGFI, RIL_a, EI, r1, i2_32u, r1, 0, addu64, addu64) /* ADD LOGICAL WITH SIGNED IMMEDIATE */ - D(0xeb6e, ALSI, SIY, GIE, la1, i2, new, 0, asi, addu32, MO_TEUL) - C(0xecda, ALHSIK, RIE_d, DO, r3, i2, new, r1_32, add, addu32) - D(0xeb7e, ALGSI, SIY, GIE, la1, i2, new, 0, asi, addu64, MO_TEQ) - C(0xecdb, ALGHSIK, RIE_d, DO, r3, i2, r1, 0, add, addu64) + D(0xeb6e, ALSI, SIY, GIE, la1, i2_32u, new, 0, asi, addu32, MO_TE= UL) + C(0xecda, ALHSIK, RIE_d, DO, r3_32u, i2_32u, new, r1_32, add, addu32) + C(0xeb7e, ALGSI, SIY, GIE, la1, i2, r1, 0, asiu64, addu64) + C(0xecdb, ALGHSIK, RIE_d, DO, r3, i2, r1, 0, addu64, addu64) /* ADD LOGICAL WITH SIGNED IMMEDIATE HIGH */ - C(0xcc0a, ALSIH, RIL_a, HW, r1_sr32, i2, new, r1_32h, add, addu32) - C(0xcc0b, ALSIHN, RIL_a, HW, r1_sr32, i2, new, r1_32h, add, 0) + C(0xcc0a, ALSIH, RIL_a, HW, r1_sr32, i2_32u, new, r1_32h, add, addu= 32) + C(0xcc0b, ALSIHN, RIL_a, HW, r1_sr32, i2_32u, new, r1_32h, add, 0) /* ADD LOGICAL WITH CARRY */ C(0xb998, ALCR, RRE, Z, r1, r2, new, r1_32, addc, addc32) C(0xb988, ALCGR, RRE, Z, r1, r2, r1, 0, addc, addc64) --=20 2.25.1 From nobody Tue May 21 07:10:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id b71sm2193033oii.5.2020.12.14.14.13.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 14:14:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=W2vyPK2fc+F5KGu2bjD5WehS57Sv6Ydyg5eJ0ydNqAE=; b=PGWQpq6+d7b2r+N97R9PnF2h8pUqPZaz9RXJRArVAM2ju6UsrnoRCUm6CeTmsr59/g Te4v+SUoP247nTISVrFeCmaB/PMv8Z8PCFoUyUeoR6LdwA5jM1uhjRIUbqgGitFt6rbX 3w0nPzL0y4lItXAz3jy5Op2ThLCuW9zwOEUzil3fxJddHCbBOUm8hkFYZDOuCscrS1iB AGPhN57Wqeg0AA+Z5BAO4UexyA0e8AIm8tmKSYGDf34Cy3y9rVLYoSfpgvdOnXSIMUn1 3Vg1eMrmvu6UExcoujEM70/1iDP844EGb9knmDc2gio/TmmNVczm2LmG9Juts0TUX7O/ tj3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=W2vyPK2fc+F5KGu2bjD5WehS57Sv6Ydyg5eJ0ydNqAE=; b=nnU7WghnGF5y4U1IY/DzDrQu6LsbQO1bUrmx8OsZYmM+2SDt/6qC5mt86Ce2tnfMfg J3OYoD7BDJP50aQHcvc3QYmtWP8m+sEswRkX8ARizGBSgCIHoi3VoDals2BZK2fkWntv xmp6hvYVNiW4P4omKGriT/xVaI4JnAH1wm0jSdESiuWGXnVy47hkzeMqncNW3k/SjsdP mU8crbFLbkdj8SwT0Ti9wlZ2esbqkl4exwD6oJlGrKgaTUjkrF+/JO4xNplggYgPKegV DlLg2pRNP4Admgy9Oi2TcnRc+yJQvnK1hW+ELr4USVMVKDlNF8nvOCTnPHieS4u7nliq BsJA== X-Gm-Message-State: AOAM5309qPSIdZuHWXUxULY11cM10RmxE5qtDYeAfFW7XoY6ODt+j5SW 5m8HXRXzS8IXX12dNh5u7o7qXrkuy+ROLBLN X-Google-Smtp-Source: ABdhPJyFDk1h9b+sQrfWrtieh3r0KqGBXF2gyUNhk6//KZ7nAEgnnWXJ3Ta+BbQw68ubJnLPVm5b8A== X-Received: by 2002:a05:6830:cf:: with SMTP id x15mr21140982oto.55.1607984040678; Mon, 14 Dec 2020 14:14:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 2/4] target/s390x: Improve ADD LOGICAL WITH CARRY Date: Mon, 14 Dec 2020 16:13:54 -0600 Message-Id: <20201214221356.68039-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214221356.68039-1-richard.henderson@linaro.org> References: <20201214221356.68039-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::341; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x341.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Now that ADD LOGICAL outputs carry, we can use that as input directly. It also means we can re-use CC_OP_ADDU and produce an output carry directly from ADD LOGICAL WITH CARRY. Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/internal.h | 2 -- target/s390x/cc_helper.c | 26 --------------- target/s390x/helper.c | 2 -- target/s390x/translate.c | 67 ++++++++++++++++++-------------------- target/s390x/insn-data.def | 8 ++--- 5 files changed, 36 insertions(+), 69 deletions(-) diff --git a/target/s390x/internal.h b/target/s390x/internal.h index 55c5442102..f5f3ae063e 100644 --- a/target/s390x/internal.h +++ b/target/s390x/internal.h @@ -170,7 +170,6 @@ enum cc_op { CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */ =20 CC_OP_ADD_64, /* overflow on add (64bit) */ - CC_OP_ADDC_64, /* overflow on unsigned add-carry (64bit) = */ CC_OP_SUB_64, /* overflow on subtraction (64bit) */ CC_OP_SUBU_64, /* overflow on unsigned subtraction (64bit= ) */ CC_OP_SUBB_64, /* overflow on unsigned sub-borrow (64bit)= */ @@ -179,7 +178,6 @@ enum cc_op { CC_OP_MULS_64, /* overflow on signed multiply (64bit) */ =20 CC_OP_ADD_32, /* overflow on add (32bit) */ - CC_OP_ADDC_32, /* overflow on unsigned add-carry (32bit) = */ CC_OP_SUB_32, /* overflow on subtraction (32bit) */ CC_OP_SUBU_32, /* overflow on unsigned subtraction (32bit= ) */ CC_OP_SUBB_32, /* overflow on unsigned sub-borrow (32bit)= */ diff --git a/target/s390x/cc_helper.c b/target/s390x/cc_helper.c index 59da4d1cc2..cd2c5c4b39 100644 --- a/target/s390x/cc_helper.c +++ b/target/s390x/cc_helper.c @@ -144,16 +144,6 @@ static uint32_t cc_calc_add_64(int64_t a1, int64_t a2,= int64_t ar) } } =20 -static uint32_t cc_calc_addc_64(uint64_t a1, uint64_t a2, uint64_t ar) -{ - /* Recover a2 + carry_in. */ - uint64_t a2c =3D ar - a1; - /* Check for a2+carry_in overflow, then a1+a2c overflow. */ - int carry_out =3D (a2c < a2) || (ar < a1); - - return (ar !=3D 0) + 2 * carry_out; -} - static uint32_t cc_calc_sub_64(int64_t a1, int64_t a2, int64_t ar) { if ((a1 > 0 && a2 < 0 && ar < 0) || (a1 < 0 && a2 > 0 && ar > 0)) { @@ -240,16 +230,6 @@ static uint32_t cc_calc_add_32(int32_t a1, int32_t a2,= int32_t ar) } } =20 -static uint32_t cc_calc_addc_32(uint32_t a1, uint32_t a2, uint32_t ar) -{ - /* Recover a2 + carry_in. */ - uint32_t a2c =3D ar - a1; - /* Check for a2+carry_in overflow, then a1+a2c overflow. */ - int carry_out =3D (a2c < a2) || (ar < a1); - - return (ar !=3D 0) + 2 * carry_out; -} - static uint32_t cc_calc_sub_32(int32_t a1, int32_t a2, int32_t ar) { if ((a1 > 0 && a2 < 0 && ar < 0) || (a1 < 0 && a2 > 0 && ar > 0)) { @@ -485,9 +465,6 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t= cc_op, case CC_OP_ADD_64: r =3D cc_calc_add_64(src, dst, vr); break; - case CC_OP_ADDC_64: - r =3D cc_calc_addc_64(src, dst, vr); - break; case CC_OP_SUB_64: r =3D cc_calc_sub_64(src, dst, vr); break; @@ -513,9 +490,6 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t= cc_op, case CC_OP_ADD_32: r =3D cc_calc_add_32(src, dst, vr); break; - case CC_OP_ADDC_32: - r =3D cc_calc_addc_32(src, dst, vr); - break; case CC_OP_SUB_32: r =3D cc_calc_sub_32(src, dst, vr); break; diff --git a/target/s390x/helper.c b/target/s390x/helper.c index db87a62a57..4f4561bc64 100644 --- a/target/s390x/helper.c +++ b/target/s390x/helper.c @@ -403,14 +403,12 @@ const char *cc_name(enum cc_op cc_op) [CC_OP_LTGT0_32] =3D "CC_OP_LTGT0_32", [CC_OP_LTGT0_64] =3D "CC_OP_LTGT0_64", [CC_OP_ADD_64] =3D "CC_OP_ADD_64", - [CC_OP_ADDC_64] =3D "CC_OP_ADDC_64", [CC_OP_SUB_64] =3D "CC_OP_SUB_64", [CC_OP_SUBU_64] =3D "CC_OP_SUBU_64", [CC_OP_SUBB_64] =3D "CC_OP_SUBB_64", [CC_OP_ABS_64] =3D "CC_OP_ABS_64", [CC_OP_NABS_64] =3D "CC_OP_NABS_64", [CC_OP_ADD_32] =3D "CC_OP_ADD_32", - [CC_OP_ADDC_32] =3D "CC_OP_ADDC_32", [CC_OP_SUB_32] =3D "CC_OP_SUB_32", [CC_OP_SUBU_32] =3D "CC_OP_SUBU_32", [CC_OP_SUBB_32] =3D "CC_OP_SUBB_32", diff --git a/target/s390x/translate.c b/target/s390x/translate.c index b473233edf..d1d97e4696 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -600,12 +600,10 @@ static void gen_op_calc_cc(DisasContext *s) dummy =3D tcg_const_i64(0); /* FALLTHRU */ case CC_OP_ADD_64: - case CC_OP_ADDC_64: case CC_OP_SUB_64: case CC_OP_SUBU_64: case CC_OP_SUBB_64: case CC_OP_ADD_32: - case CC_OP_ADDC_32: case CC_OP_SUB_32: case CC_OP_SUBU_32: case CC_OP_SUBB_32: @@ -665,12 +663,10 @@ static void gen_op_calc_cc(DisasContext *s) gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, du= mmy); break; case CC_OP_ADD_64: - case CC_OP_ADDC_64: case CC_OP_SUB_64: case CC_OP_SUBU_64: case CC_OP_SUBB_64: case CC_OP_ADD_32: - case CC_OP_ADDC_32: case CC_OP_SUB_32: case CC_OP_SUBU_32: case CC_OP_SUBB_32: @@ -1443,30 +1439,41 @@ static DisasJumpType op_addu64(DisasContext *s, Dis= asOps *o) return DISAS_NEXT; } =20 -static DisasJumpType op_addc(DisasContext *s, DisasOps *o) +/* Compute carry into cc_src. */ +static void compute_carry(DisasContext *s) { - DisasCompare cmp; - TCGv_i64 carry; - - tcg_gen_add_i64(o->out, o->in1, o->in2); - - /* The carry flag is the msb of CC, therefore the branch mask that wou= ld - create that comparison is 3. Feeding the generated comparison to - setcond produces the carry flag that we desire. */ - disas_jcc(s, &cmp, 3); - carry =3D tcg_temp_new_i64(); - if (cmp.is_64) { - tcg_gen_setcond_i64(cmp.cond, carry, cmp.u.s64.a, cmp.u.s64.b); - } else { - TCGv_i32 t =3D tcg_temp_new_i32(); - tcg_gen_setcond_i32(cmp.cond, t, cmp.u.s32.a, cmp.u.s32.b); - tcg_gen_extu_i32_i64(carry, t); - tcg_temp_free_i32(t); + switch (s->cc_op) { + case CC_OP_ADDU: + /* The carry value is already in cc_src (1,0). */ + break; + default: + gen_op_calc_cc(s); + /* fall through */ + case CC_OP_STATIC: + /* The carry flag is the msb of CC; compute into cc_src. */ + tcg_gen_extu_i32_i64(cc_src, cc_op); + tcg_gen_shri_i64(cc_src, cc_src, 1); + break; } - free_compare(&cmp); +} + +static DisasJumpType op_addc32(DisasContext *s, DisasOps *o) +{ + compute_carry(s); + tcg_gen_add_i64(o->out, o->in1, o->in2); + tcg_gen_add_i64(o->out, o->out, cc_src); + return DISAS_NEXT; +} + +static DisasJumpType op_addc64(DisasContext *s, DisasOps *o) +{ + compute_carry(s); + + TCGv_i64 zero =3D tcg_const_i64(0); + tcg_gen_add2_i64(o->out, cc_src, o->in1, zero, cc_src, zero); + tcg_gen_add2_i64(o->out, cc_src, o->out, cc_src, o->in2, zero); + tcg_temp_free_i64(zero); =20 - tcg_gen_add_i64(o->out, o->out, carry); - tcg_temp_free_i64(carry); return DISAS_NEXT; } =20 @@ -5217,16 +5224,6 @@ static void cout_addu64(DisasContext *s, DisasOps *o) gen_op_update2_cc_i64(s, CC_OP_ADDU, cc_src, o->out); } =20 -static void cout_addc32(DisasContext *s, DisasOps *o) -{ - gen_op_update3_cc_i64(s, CC_OP_ADDC_32, o->in1, o->in2, o->out); -} - -static void cout_addc64(DisasContext *s, DisasOps *o) -{ - gen_op_update3_cc_i64(s, CC_OP_ADDC_64, o->in1, o->in2, o->out); -} - static void cout_cmps32(DisasContext *s, DisasOps *o) { gen_op_update2_cc_i64(s, CC_OP_LTGT_32, o->in1, o->in2); diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index 5461e6aa3b..e380723dcd 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -82,10 +82,10 @@ C(0xcc0a, ALSIH, RIL_a, HW, r1_sr32, i2_32u, new, r1_32h, add, addu= 32) C(0xcc0b, ALSIHN, RIL_a, HW, r1_sr32, i2_32u, new, r1_32h, add, 0) /* ADD LOGICAL WITH CARRY */ - C(0xb998, ALCR, RRE, Z, r1, r2, new, r1_32, addc, addc32) - C(0xb988, ALCGR, RRE, Z, r1, r2, r1, 0, addc, addc64) - C(0xe398, ALC, RXY_a, Z, r1, m2_32u, new, r1_32, addc, addc32) - C(0xe388, ALCG, RXY_a, Z, r1, m2_64, r1, 0, addc, addc64) + C(0xb998, ALCR, RRE, Z, r1_32u, r2_32u, new, r1_32, addc32, add= u32) + C(0xb988, ALCGR, RRE, Z, r1, r2, r1, 0, addc64, addu64) + C(0xe398, ALC, RXY_a, Z, r1_32u, m2_32u, new, r1_32, addc32, add= u32) + C(0xe388, ALCG, RXY_a, Z, r1, m2_64, r1, 0, addc64, addu64) =20 /* AND */ C(0x1400, NR, RR_a, Z, r1, r2, new, r1_32, and, nz32) --=20 2.25.1 From nobody Tue May 21 07:10:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id b71sm2193033oii.5.2020.12.14.14.14.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 14:14:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=e9erwDb1mAbXzLgtuY1WLt5HoIjjgM9iUfCmf/uzBv8=; b=DpOMD4vrJDQ9sriw5C4lYATN+ipNWeN4Zfulf5Gft9pnT2Bjx+L1lb+h6VPNMzVb9w RnqX/V1L+diPI8710bWrcKMijVIrel/MI8NXl948bnBpQpggLOyKzi7EfMh+kBZBWv+M jVJivlwTvB7gxK40+6Lh1nwBChqEQvLJXp14Ak3ibolDIBy3c0jz9shUX3VHzMS9k7E9 dwO3v2I6C2lgltR/CcEnBz9QqxzHF0cTA/FuYEl82f6bGiJldIVnJ0lNCCir5I1MLdhK xtxbILSSe90xJ+UjUcZftrM2jqoaC14UhuwtcmxfWYiZEPIunuSkUHshbVC4S81GKMHU wWjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=e9erwDb1mAbXzLgtuY1WLt5HoIjjgM9iUfCmf/uzBv8=; b=e3IzDec2L5m/BkfAhVLlpkRbrhpX6qUlX0/BDX52Ju0jx6nl5siSpcMw2z8sLJOolm dwPCZvkYy/Qss0593MgHhTBZAgAXdw9fHUt9Mc98nyOydpAYUT1bKILO+bK2Oe8nW5C3 bMWSC9hybzYxIl4wBJ7UNQyIwL92s0aN3idaEPDwJMF+B3v/a9inggId8mAoxyA769Oz gsXasXPJMOt2ECWyHUbOCSJZXYENNE0iICOHDpwxRBm2JwbAcSSnvGX/iagbDQzpszLi rsWVQnLfaSe0ZvlUDxR0l6QoQMMkpOdDZCTSlnnB238r3dfZhd+vyRxFdV1KER5aVkgx 5tNA== X-Gm-Message-State: AOAM533p6GpOfKqn15gaS1ZJMZY9zwEv9SBANJtikLQpdTIrb7OkXRO8 G3UPgLt/IUGC2UIjnXGS3q3NHUIdTqN+woCZ X-Google-Smtp-Source: ABdhPJyAvCwy+oSx8odtn2lxwQw3RJMYpAdTQwN/muF4iZhMBApZjgPvLLE73yrVnHgx2m0vNUjwVg== X-Received: by 2002:a05:6830:1d71:: with SMTP id l17mr21581744oti.269.1607984041909; Mon, 14 Dec 2020 14:14:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 3/4] target/s390x: Improve cc computation for SUBTRACT LOGICAL Date: Mon, 14 Dec 2020 16:13:55 -0600 Message-Id: <20201214221356.68039-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214221356.68039-1-richard.henderson@linaro.org> References: <20201214221356.68039-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The resulting cc is only dependent on the result and the carry-out. Carry-out and borrow-out are inverses, so are trivially converted. With tcg ops, it is easier to compute borrow-out than carry-out, so save result and borrow-out rather than the inputs. Borrow-out for 64-bit inputs is had via tcg_gen_sub2_i64 directly into cc_src. Borrow-out for 32-bit inputs is had via extraction from a normal 64-bit sub (with zero-extended inputs). Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/internal.h | 3 +-- target/s390x/cc_helper.c | 40 ++++++--------------------- target/s390x/helper.c | 3 +-- target/s390x/translate.c | 55 +++++++++++++++----------------------- target/s390x/insn-data.def | 24 ++++++++--------- 5 files changed, 43 insertions(+), 82 deletions(-) diff --git a/target/s390x/internal.h b/target/s390x/internal.h index f5f3ae063e..4077047494 100644 --- a/target/s390x/internal.h +++ b/target/s390x/internal.h @@ -161,6 +161,7 @@ enum cc_op { =20 CC_OP_NZ, /* env->cc_dst !=3D 0 */ CC_OP_ADDU, /* dst !=3D 0, src =3D carry out (0,1) */ + CC_OP_SUBU, /* dst !=3D 0, src =3D borrow out (0,-1) */ =20 CC_OP_LTGT_32, /* signed less/greater than (32bit) */ CC_OP_LTGT_64, /* signed less/greater than (64bit) */ @@ -171,7 +172,6 @@ enum cc_op { =20 CC_OP_ADD_64, /* overflow on add (64bit) */ CC_OP_SUB_64, /* overflow on subtraction (64bit) */ - CC_OP_SUBU_64, /* overflow on unsigned subtraction (64bit= ) */ CC_OP_SUBB_64, /* overflow on unsigned sub-borrow (64bit)= */ CC_OP_ABS_64, /* sign eval on abs (64bit) */ CC_OP_NABS_64, /* sign eval on nabs (64bit) */ @@ -179,7 +179,6 @@ enum cc_op { =20 CC_OP_ADD_32, /* overflow on add (32bit) */ CC_OP_SUB_32, /* overflow on subtraction (32bit) */ - CC_OP_SUBU_32, /* overflow on unsigned subtraction (32bit= ) */ CC_OP_SUBB_32, /* overflow on unsigned sub-borrow (32bit)= */ CC_OP_ABS_32, /* sign eval on abs (64bit) */ CC_OP_NABS_32, /* sign eval on nabs (64bit) */ diff --git a/target/s390x/cc_helper.c b/target/s390x/cc_helper.c index cd2c5c4b39..c7728d1225 100644 --- a/target/s390x/cc_helper.c +++ b/target/s390x/cc_helper.c @@ -129,6 +129,11 @@ static uint32_t cc_calc_addu(uint64_t carry_out, uint6= 4_t result) return (result !=3D 0) + 2 * carry_out; } =20 +static uint32_t cc_calc_subu(uint64_t borrow_out, uint64_t result) +{ + return cc_calc_addu(borrow_out + 1, result); +} + static uint32_t cc_calc_add_64(int64_t a1, int64_t a2, int64_t ar) { if ((a1 > 0 && a2 > 0 && ar < 0) || (a1 < 0 && a2 < 0 && ar > 0)) { @@ -159,19 +164,6 @@ static uint32_t cc_calc_sub_64(int64_t a1, int64_t a2,= int64_t ar) } } =20 -static uint32_t cc_calc_subu_64(uint64_t a1, uint64_t a2, uint64_t ar) -{ - if (ar =3D=3D 0) { - return 2; - } else { - if (a2 > a1) { - return 1; - } else { - return 3; - } - } -} - static uint32_t cc_calc_subb_64(uint64_t a1, uint64_t a2, uint64_t ar) { int borrow_out; @@ -245,19 +237,6 @@ static uint32_t cc_calc_sub_32(int32_t a1, int32_t a2,= int32_t ar) } } =20 -static uint32_t cc_calc_subu_32(uint32_t a1, uint32_t a2, uint32_t ar) -{ - if (ar =3D=3D 0) { - return 2; - } else { - if (a2 > a1) { - return 1; - } else { - return 3; - } - } -} - static uint32_t cc_calc_subb_32(uint32_t a1, uint32_t a2, uint32_t ar) { int borrow_out; @@ -462,15 +441,15 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32= _t cc_op, case CC_OP_ADDU: r =3D cc_calc_addu(src, dst); break; + case CC_OP_SUBU: + r =3D cc_calc_subu(src, dst); + break; case CC_OP_ADD_64: r =3D cc_calc_add_64(src, dst, vr); break; case CC_OP_SUB_64: r =3D cc_calc_sub_64(src, dst, vr); break; - case CC_OP_SUBU_64: - r =3D cc_calc_subu_64(src, dst, vr); - break; case CC_OP_SUBB_64: r =3D cc_calc_subb_64(src, dst, vr); break; @@ -493,9 +472,6 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t= cc_op, case CC_OP_SUB_32: r =3D cc_calc_sub_32(src, dst, vr); break; - case CC_OP_SUBU_32: - r =3D cc_calc_subu_32(src, dst, vr); - break; case CC_OP_SUBB_32: r =3D cc_calc_subb_32(src, dst, vr); break; diff --git a/target/s390x/helper.c b/target/s390x/helper.c index 4f4561bc64..fa3aa500e5 100644 --- a/target/s390x/helper.c +++ b/target/s390x/helper.c @@ -396,6 +396,7 @@ const char *cc_name(enum cc_op cc_op) [CC_OP_STATIC] =3D "CC_OP_STATIC", [CC_OP_NZ] =3D "CC_OP_NZ", [CC_OP_ADDU] =3D "CC_OP_ADDU", + [CC_OP_SUBU] =3D "CC_OP_SUBU", [CC_OP_LTGT_32] =3D "CC_OP_LTGT_32", [CC_OP_LTGT_64] =3D "CC_OP_LTGT_64", [CC_OP_LTUGTU_32] =3D "CC_OP_LTUGTU_32", @@ -404,13 +405,11 @@ const char *cc_name(enum cc_op cc_op) [CC_OP_LTGT0_64] =3D "CC_OP_LTGT0_64", [CC_OP_ADD_64] =3D "CC_OP_ADD_64", [CC_OP_SUB_64] =3D "CC_OP_SUB_64", - [CC_OP_SUBU_64] =3D "CC_OP_SUBU_64", [CC_OP_SUBB_64] =3D "CC_OP_SUBB_64", [CC_OP_ABS_64] =3D "CC_OP_ABS_64", [CC_OP_NABS_64] =3D "CC_OP_NABS_64", [CC_OP_ADD_32] =3D "CC_OP_ADD_32", [CC_OP_SUB_32] =3D "CC_OP_SUB_32", - [CC_OP_SUBU_32] =3D "CC_OP_SUBU_32", [CC_OP_SUBB_32] =3D "CC_OP_SUBB_32", [CC_OP_ABS_32] =3D "CC_OP_ABS_32", [CC_OP_NABS_32] =3D "CC_OP_NABS_32", diff --git a/target/s390x/translate.c b/target/s390x/translate.c index d1d97e4696..40add1df1f 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -601,11 +601,9 @@ static void gen_op_calc_cc(DisasContext *s) /* FALLTHRU */ case CC_OP_ADD_64: case CC_OP_SUB_64: - case CC_OP_SUBU_64: case CC_OP_SUBB_64: case CC_OP_ADD_32: case CC_OP_SUB_32: - case CC_OP_SUBU_32: case CC_OP_SUBB_32: local_cc_op =3D tcg_const_i32(s->cc_op); break; @@ -656,6 +654,7 @@ static void gen_op_calc_cc(DisasContext *s) case CC_OP_TM_64: case CC_OP_SLA_32: case CC_OP_SLA_64: + case CC_OP_SUBU: case CC_OP_NZ_F128: case CC_OP_VC: case CC_OP_MULS_64: @@ -664,11 +663,9 @@ static void gen_op_calc_cc(DisasContext *s) break; case CC_OP_ADD_64: case CC_OP_SUB_64: - case CC_OP_SUBU_64: case CC_OP_SUBB_64: case CC_OP_ADD_32: case CC_OP_SUB_32: - case CC_OP_SUBU_32: case CC_OP_SUBB_32: /* 3 arguments */ gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, cc= _vr); @@ -843,6 +840,7 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,= uint32_t mask) break; =20 case CC_OP_ADDU: + case CC_OP_SUBU: switch (mask) { case 8 | 2: /* result =3D=3D 0 */ cond =3D TCG_COND_EQ; @@ -850,33 +848,11 @@ static void disas_jcc(DisasContext *s, DisasCompare *= c, uint32_t mask) case 4 | 1: /* result !=3D 0 */ cond =3D TCG_COND_NE; break; - case 8 | 4: /* no carry */ - cond =3D TCG_COND_EQ; + case 8 | 4: /* !carry (borrow) */ + cond =3D old_cc_op =3D=3D CC_OP_ADDU ? TCG_COND_EQ : TCG_COND_= NE; break; - case 2 | 1: /* carry */ - cond =3D TCG_COND_NE; - break; - default: - goto do_dynamic; - } - account_inline_branch(s, old_cc_op); - break; - - case CC_OP_SUBU_32: - case CC_OP_SUBU_64: - /* Note that CC=3D0 is impossible; treat it as dont-care. */ - switch (mask & 7) { - case 2: /* zero -> op1 =3D=3D op2 */ - cond =3D TCG_COND_EQ; - break; - case 4 | 1: /* !zero -> op1 !=3D op2 */ - cond =3D TCG_COND_NE; - break; - case 4: /* borrow (!carry) -> op1 < op2 */ - cond =3D TCG_COND_LTU; - break; - case 2 | 1: /* !borrow (carry) -> op1 >=3D op2 */ - cond =3D TCG_COND_GEU; + case 2 | 1: /* carry (!borrow) */ + cond =3D old_cc_op =3D=3D CC_OP_ADDU ? TCG_COND_NE : TCG_COND_= EQ; break; default: goto do_dynamic; @@ -911,7 +887,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,= uint32_t mask) break; case CC_OP_LTGT_32: case CC_OP_LTUGTU_32: - case CC_OP_SUBU_32: c->is_64 =3D false; c->u.s32.a =3D tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(c->u.s32.a, cc_src); @@ -928,7 +903,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,= uint32_t mask) break; case CC_OP_LTGT_64: case CC_OP_LTUGTU_64: - case CC_OP_SUBU_64: c->u.s64.a =3D cc_src; c->u.s64.b =3D cc_dst; c->g1 =3D c->g2 =3D true; @@ -943,6 +917,7 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,= uint32_t mask) break; =20 case CC_OP_ADDU: + case CC_OP_SUBU: c->is_64 =3D true; c->u.s64.b =3D tcg_const_i64(0); c->g1 =3D true; @@ -1446,6 +1421,9 @@ static void compute_carry(DisasContext *s) case CC_OP_ADDU: /* The carry value is already in cc_src (1,0). */ break; + case CC_OP_SUBU: + tcg_gen_addi_i64(cc_src, cc_src, 1); + break; default: gen_op_calc_cc(s); /* fall through */ @@ -4761,6 +4739,13 @@ static DisasJumpType op_sub(DisasContext *s, DisasOp= s *o) return DISAS_NEXT; } =20 +static DisasJumpType op_subu64(DisasContext *s, DisasOps *o) +{ + tcg_gen_movi_i64(cc_src, 0); + tcg_gen_sub2_i64(o->out, cc_src, o->in1, cc_src, o->in2, cc_src); + return DISAS_NEXT; +} + static DisasJumpType op_subb(DisasContext *s, DisasOps *o) { DisasCompare cmp; @@ -5312,12 +5297,14 @@ static void cout_subs64(DisasContext *s, DisasOps *= o) =20 static void cout_subu32(DisasContext *s, DisasOps *o) { - gen_op_update3_cc_i64(s, CC_OP_SUBU_32, o->in1, o->in2, o->out); + tcg_gen_sari_i64(cc_src, o->out, 32); + tcg_gen_ext32u_i64(cc_dst, o->out); + gen_op_update2_cc_i64(s, CC_OP_SUBU, cc_src, cc_dst); } =20 static void cout_subu64(DisasContext *s, DisasOps *o) { - gen_op_update3_cc_i64(s, CC_OP_SUBU_64, o->in1, o->in2, o->out); + gen_op_update2_cc_i64(s, CC_OP_SUBU, cc_src, o->out); } =20 static void cout_subb32(DisasContext *s, DisasOps *o) diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index e380723dcd..7ff3e7e517 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -900,21 +900,21 @@ C(0xb9c9, SHHHR, RRF_a, HW, r2_sr32, r3_sr32, new, r1_32h, sub, sub= s32) C(0xb9d9, SHHLR, RRF_a, HW, r2_sr32, r3, new, r1_32h, sub, subs32) /* SUBTRACT LOGICAL */ - C(0x1f00, SLR, RR_a, Z, r1, r2, new, r1_32, sub, subu32) - C(0xb9fb, SLRK, RRF_a, DO, r2, r3, new, r1_32, sub, subu32) - C(0x5f00, SL, RX_a, Z, r1, m2_32u, new, r1_32, sub, subu32) - C(0xe35f, SLY, RXY_a, LD, r1, m2_32u, new, r1_32, sub, subu32) - C(0xb90b, SLGR, RRE, Z, r1, r2, r1, 0, sub, subu64) - C(0xb91b, SLGFR, RRE, Z, r1, r2_32u, r1, 0, sub, subu64) - C(0xb9eb, SLGRK, RRF_a, DO, r2, r3, r1, 0, sub, subu64) - C(0xe30b, SLG, RXY_a, Z, r1, m2_64, r1, 0, sub, subu64) - C(0xe31b, SLGF, RXY_a, Z, r1, m2_32u, r1, 0, sub, subu64) + C(0x1f00, SLR, RR_a, Z, r1_32u, r2_32u, new, r1_32, sub, subu32) + C(0xb9fb, SLRK, RRF_a, DO, r2_32u, r3_32u, new, r1_32, sub, subu32) + C(0x5f00, SL, RX_a, Z, r1_32u, m2_32u, new, r1_32, sub, subu32) + C(0xe35f, SLY, RXY_a, LD, r1_32u, m2_32u, new, r1_32, sub, subu32) + C(0xb90b, SLGR, RRE, Z, r1, r2, r1, 0, subu64, subu64) + C(0xb91b, SLGFR, RRE, Z, r1, r2_32u, r1, 0, subu64, subu64) + C(0xb9eb, SLGRK, RRF_a, DO, r2, r3, r1, 0, subu64, subu64) + C(0xe30b, SLG, RXY_a, Z, r1, m2_64, r1, 0, subu64, subu64) + C(0xe31b, SLGF, RXY_a, Z, r1, m2_32u, r1, 0, subu64, subu64) /* SUBTRACT LOCICAL HIGH */ C(0xb9cb, SLHHHR, RRF_a, HW, r2_sr32, r3_sr32, new, r1_32h, sub, sub= u32) - C(0xb9db, SLHHLR, RRF_a, HW, r2_sr32, r3, new, r1_32h, sub, subu32) + C(0xb9db, SLHHLR, RRF_a, HW, r2_sr32, r3_32u, new, r1_32h, sub, subu= 32) /* SUBTRACT LOGICAL IMMEDIATE */ - C(0xc205, SLFI, RIL_a, EI, r1, i2_32u, new, r1_32, sub, subu32) - C(0xc204, SLGFI, RIL_a, EI, r1, i2_32u, r1, 0, sub, subu64) + C(0xc205, SLFI, RIL_a, EI, r1_32u, i2_32u, new, r1_32, sub, subu32) + C(0xc204, SLGFI, RIL_a, EI, r1, i2_32u, r1, 0, subu64, subu64) /* SUBTRACT LOGICAL WITH BORROW */ C(0xb999, SLBR, RRE, Z, r1, r2, new, r1_32, subb, subb32) C(0xb989, SLBGR, RRE, Z, r1, r2, r1, 0, subb, subb64) --=20 2.25.1 From nobody Tue May 21 07:10:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id b71sm2193033oii.5.2020.12.14.14.14.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 14:14:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pXWJfPIZobw28rXcpmksqEkRI3kkMq+o5FnlNZTZN2Y=; b=Fp78xmxGmwMdWrSvANHW9Zj1MtcqyDdTH2kfsbR0T5TxnjUm7YonOdO9w0Ek6xaIMx p0hJtRC5WwekKe5sfFM6Bf7wAbN7WkJAci2SPxoDhw7gD/++/mj9cI2gP5GU0X4yADGI etiw3imWlflO/Nh9pxhvS6AHuQAyrALSk9ZAmS8m25RSCGQzXTsWzqGXPpDJyM44BXpF kYZTsZImnpIX5uA4xOoDY+uj/q7u9CtNHG4ihBfvR00bKXKURvv0mjyTDHuoQJNuiXEw cxgCNeC12msazMPuRciPNr+YazY/XPm6raldtEDQGQf30yINjv46qIuZHV3WNZBCnv7X nKHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pXWJfPIZobw28rXcpmksqEkRI3kkMq+o5FnlNZTZN2Y=; b=rgw5QL8jPc5aFoqHkxw9OwxOKqkdxJj9X92kFMkCA1T6Ta0K1+kzC44+J1UjJ4Mczo iwegw/eMSZE1BVlWg4guDdXrPK3R9SoxXoqUqynESzMDsJlH1Cv7SfK0dMTDTwSmyPdd MgidmHBmJG9ddizQ6IXKdS2rXGOqxilrlw6qG0LhjGl7+B1H+2gor1ffddSKEkqAP9rL zZ5or/7EHEC+uKGsPGNvmjmC/2u7f9DDxZW2v1bYjjim2pjW/Hzq9fxz/pZtN+RzEbLl kDISH93SoiOd3UnAT7t8VgkSp/CNV60WbDqu8lwdbrPTCcfiswQGgCqVwIpLvOe4SrIi DgCQ== X-Gm-Message-State: AOAM532FbpGkc/fbTJ2Vx+hE6elDO197GJsDDBf+IEb2cbFEYDoM1QMm 9pdN3RzRPijrqUQ7LMIoBwG/28+yMCxwCTEW X-Google-Smtp-Source: ABdhPJxnQ96lVpymglRwp/Y9vghTEfTvfxUTDUToTm35Frf5mcA/ZP6vqhlWoS1w5ptNkkHRMi5e8Q== X-Received: by 2002:a9d:7746:: with SMTP id t6mr21683131otl.349.1607984043094; Mon, 14 Dec 2020 14:14:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 4/4] target/s390x: Improve SUB LOGICAL WITH BORROW Date: Mon, 14 Dec 2020 16:13:56 -0600 Message-Id: <20201214221356.68039-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201214221356.68039-1-richard.henderson@linaro.org> References: <20201214221356.68039-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::343; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x343.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Now that SUB LOGICAL outputs borrow, we can use that as input directly. It also means we can re-use CC_OP_SUBU and produce an output borrow directly from SUB LOGICAL WITH BORROW. Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/internal.h | 2 - target/s390x/cc_helper.c | 32 ---------------- target/s390x/helper.c | 2 - target/s390x/translate.c | 76 +++++++++++++++++++++----------------- target/s390x/insn-data.def | 8 ++-- 5 files changed, 46 insertions(+), 74 deletions(-) diff --git a/target/s390x/internal.h b/target/s390x/internal.h index 4077047494..11515bb617 100644 --- a/target/s390x/internal.h +++ b/target/s390x/internal.h @@ -172,14 +172,12 @@ enum cc_op { =20 CC_OP_ADD_64, /* overflow on add (64bit) */ CC_OP_SUB_64, /* overflow on subtraction (64bit) */ - CC_OP_SUBB_64, /* overflow on unsigned sub-borrow (64bit)= */ CC_OP_ABS_64, /* sign eval on abs (64bit) */ CC_OP_NABS_64, /* sign eval on nabs (64bit) */ CC_OP_MULS_64, /* overflow on signed multiply (64bit) */ =20 CC_OP_ADD_32, /* overflow on add (32bit) */ CC_OP_SUB_32, /* overflow on subtraction (32bit) */ - CC_OP_SUBB_32, /* overflow on unsigned sub-borrow (32bit)= */ CC_OP_ABS_32, /* sign eval on abs (64bit) */ CC_OP_NABS_32, /* sign eval on nabs (64bit) */ CC_OP_MULS_32, /* overflow on signed multiply (32bit) */ diff --git a/target/s390x/cc_helper.c b/target/s390x/cc_helper.c index c7728d1225..e7039d0d18 100644 --- a/target/s390x/cc_helper.c +++ b/target/s390x/cc_helper.c @@ -164,19 +164,6 @@ static uint32_t cc_calc_sub_64(int64_t a1, int64_t a2,= int64_t ar) } } =20 -static uint32_t cc_calc_subb_64(uint64_t a1, uint64_t a2, uint64_t ar) -{ - int borrow_out; - - if (ar !=3D a1 - a2) { /* difference means borrow-in */ - borrow_out =3D (a2 >=3D a1); - } else { - borrow_out =3D (a2 > a1); - } - - return (ar !=3D 0) + 2 * !borrow_out; -} - static uint32_t cc_calc_abs_64(int64_t dst) { if ((uint64_t)dst =3D=3D 0x8000000000000000ULL) { @@ -237,19 +224,6 @@ static uint32_t cc_calc_sub_32(int32_t a1, int32_t a2,= int32_t ar) } } =20 -static uint32_t cc_calc_subb_32(uint32_t a1, uint32_t a2, uint32_t ar) -{ - int borrow_out; - - if (ar !=3D a1 - a2) { /* difference means borrow-in */ - borrow_out =3D (a2 >=3D a1); - } else { - borrow_out =3D (a2 > a1); - } - - return (ar !=3D 0) + 2 * !borrow_out; -} - static uint32_t cc_calc_abs_32(int32_t dst) { if ((uint32_t)dst =3D=3D 0x80000000UL) { @@ -450,9 +424,6 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t= cc_op, case CC_OP_SUB_64: r =3D cc_calc_sub_64(src, dst, vr); break; - case CC_OP_SUBB_64: - r =3D cc_calc_subb_64(src, dst, vr); - break; case CC_OP_ABS_64: r =3D cc_calc_abs_64(dst); break; @@ -472,9 +443,6 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t= cc_op, case CC_OP_SUB_32: r =3D cc_calc_sub_32(src, dst, vr); break; - case CC_OP_SUBB_32: - r =3D cc_calc_subb_32(src, dst, vr); - break; case CC_OP_ABS_32: r =3D cc_calc_abs_32(dst); break; diff --git a/target/s390x/helper.c b/target/s390x/helper.c index fa3aa500e5..7678994feb 100644 --- a/target/s390x/helper.c +++ b/target/s390x/helper.c @@ -405,12 +405,10 @@ const char *cc_name(enum cc_op cc_op) [CC_OP_LTGT0_64] =3D "CC_OP_LTGT0_64", [CC_OP_ADD_64] =3D "CC_OP_ADD_64", [CC_OP_SUB_64] =3D "CC_OP_SUB_64", - [CC_OP_SUBB_64] =3D "CC_OP_SUBB_64", [CC_OP_ABS_64] =3D "CC_OP_ABS_64", [CC_OP_NABS_64] =3D "CC_OP_NABS_64", [CC_OP_ADD_32] =3D "CC_OP_ADD_32", [CC_OP_SUB_32] =3D "CC_OP_SUB_32", - [CC_OP_SUBB_32] =3D "CC_OP_SUBB_32", [CC_OP_ABS_32] =3D "CC_OP_ABS_32", [CC_OP_NABS_32] =3D "CC_OP_NABS_32", [CC_OP_COMP_32] =3D "CC_OP_COMP_32", diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 40add1df1f..3d5c0d6106 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -601,10 +601,8 @@ static void gen_op_calc_cc(DisasContext *s) /* FALLTHRU */ case CC_OP_ADD_64: case CC_OP_SUB_64: - case CC_OP_SUBB_64: case CC_OP_ADD_32: case CC_OP_SUB_32: - case CC_OP_SUBB_32: local_cc_op =3D tcg_const_i32(s->cc_op); break; case CC_OP_CONST0: @@ -663,10 +661,8 @@ static void gen_op_calc_cc(DisasContext *s) break; case CC_OP_ADD_64: case CC_OP_SUB_64: - case CC_OP_SUBB_64: case CC_OP_ADD_32: case CC_OP_SUB_32: - case CC_OP_SUBB_32: /* 3 arguments */ gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, cc= _vr); break; @@ -4746,29 +4742,51 @@ static DisasJumpType op_subu64(DisasContext *s, Dis= asOps *o) return DISAS_NEXT; } =20 -static DisasJumpType op_subb(DisasContext *s, DisasOps *o) +/* Compute borrow (0, -1) into cc_src. */ +static void compute_borrow(DisasContext *s) { - DisasCompare cmp; - TCGv_i64 borrow; - - tcg_gen_sub_i64(o->out, o->in1, o->in2); - - /* The !borrow flag is the msb of CC. Since we want the inverse of - that, we ask for a comparison of CC=3D0 | CC=3D1 -> mask of 8 | 4. = */ - disas_jcc(s, &cmp, 8 | 4); - borrow =3D tcg_temp_new_i64(); - if (cmp.is_64) { - tcg_gen_setcond_i64(cmp.cond, borrow, cmp.u.s64.a, cmp.u.s64.b); - } else { - TCGv_i32 t =3D tcg_temp_new_i32(); - tcg_gen_setcond_i32(cmp.cond, t, cmp.u.s32.a, cmp.u.s32.b); - tcg_gen_extu_i32_i64(borrow, t); - tcg_temp_free_i32(t); + switch (s->cc_op) { + case CC_OP_SUBU: + /* The borrow value is already in cc_src (0,-1). */ + break; + default: + gen_op_calc_cc(s); + /* fall through */ + case CC_OP_STATIC: + /* The carry flag is the msb of CC; compute into cc_src. */ + tcg_gen_extu_i32_i64(cc_src, cc_op); + tcg_gen_shri_i64(cc_src, cc_src, 1); + /* fall through */ + case CC_OP_ADDU: + /* Convert carry (1,0) to borrow (0,-1). */ + tcg_gen_subi_i64(cc_src, cc_src, 1); + break; } - free_compare(&cmp); +} + +static DisasJumpType op_subb32(DisasContext *s, DisasOps *o) +{ + compute_borrow(s); + + /* Borrow is {0, -1}, so add to subtract. */ + tcg_gen_add_i64(o->out, o->in1, cc_src); + tcg_gen_sub_i64(o->out, o->out, o->in2); + return DISAS_NEXT; +} + +static DisasJumpType op_subb64(DisasContext *s, DisasOps *o) +{ + compute_borrow(s); + + /* + * Borrow is {0, -1}, so add to subtract; replicate the + * borrow input to produce 128-bit -1 for the addition. + */ + TCGv_i64 zero =3D tcg_const_i64(0); + tcg_gen_add2_i64(o->out, cc_src, o->in1, zero, cc_src, cc_src); + tcg_gen_sub2_i64(o->out, cc_src, o->out, cc_src, o->in2, zero); + tcg_temp_free_i64(zero); =20 - tcg_gen_sub_i64(o->out, o->out, borrow); - tcg_temp_free_i64(borrow); return DISAS_NEXT; } =20 @@ -5307,16 +5325,6 @@ static void cout_subu64(DisasContext *s, DisasOps *o) gen_op_update2_cc_i64(s, CC_OP_SUBU, cc_src, o->out); } =20 -static void cout_subb32(DisasContext *s, DisasOps *o) -{ - gen_op_update3_cc_i64(s, CC_OP_SUBB_32, o->in1, o->in2, o->out); -} - -static void cout_subb64(DisasContext *s, DisasOps *o) -{ - gen_op_update3_cc_i64(s, CC_OP_SUBB_64, o->in1, o->in2, o->out); -} - static void cout_tm32(DisasContext *s, DisasOps *o) { gen_op_update2_cc_i64(s, CC_OP_TM_32, o->in1, o->in2); diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index 7ff3e7e517..26badb663a 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -916,10 +916,10 @@ C(0xc205, SLFI, RIL_a, EI, r1_32u, i2_32u, new, r1_32, sub, subu32) C(0xc204, SLGFI, RIL_a, EI, r1, i2_32u, r1, 0, subu64, subu64) /* SUBTRACT LOGICAL WITH BORROW */ - C(0xb999, SLBR, RRE, Z, r1, r2, new, r1_32, subb, subb32) - C(0xb989, SLBGR, RRE, Z, r1, r2, r1, 0, subb, subb64) - C(0xe399, SLB, RXY_a, Z, r1, m2_32u, new, r1_32, subb, subb32) - C(0xe389, SLBG, RXY_a, Z, r1, m2_64, r1, 0, subb, subb64) + C(0xb999, SLBR, RRE, Z, r1_32u, r2_32u, new, r1_32, subb32, sub= u32) + C(0xb989, SLBGR, RRE, Z, r1, r2, r1, 0, subb64, subu64) + C(0xe399, SLB, RXY_a, Z, r1_32u, m2_32u, new, r1_32, subb32, sub= u32) + C(0xe389, SLBG, RXY_a, Z, r1, m2_64, r1, 0, subb64, subu64) =20 /* SUPERVISOR CALL */ C(0x0a00, SVC, I, Z, 0, 0, 0, 0, svc, 0) --=20 2.25.1