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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id a141sm20927524pfa.189.2020.12.14.12.23.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 12:23:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0/870XNH4HDaR8yVuCboXl+zTH18vO9+XdLVrm/RwSM=; b=QhKPbDr+fkSO/22Kui/6+i75nXTv3YHH9iZb2iUQRv3vm7/MmBMiUZav+DytQUFzaq Hs2LrVHbM4d+pK571QzdWGX6k0dGmaUNWcqjj39CPm3Z2ykdforvkxFGTpfDGgHdvfHE wA9drswXrYdU+j6gbI9xZnfuSAdIdCgEbBhBhIkEXTPFa51bngxF2iv+tIZ3lsJ++T3X Zp6BH6H8xRwp3RTbaXXLSRMdifKPoGIrfeqKqDejni9ioV8XVtmeuUCWpFJQmH9X3oJv 5ZE8v+vVheA2+qWoSQNho0J6FSNyCXGEXyfwbPHxhDOZVBhatNSCDlbeV183bohXe/JO 7Y3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0/870XNH4HDaR8yVuCboXl+zTH18vO9+XdLVrm/RwSM=; b=Lf6cJ2NkRk+kLzpHbxx5cEkhUzH3FCFuIgkc6/UmdkJl+67pttYlGuibaSaJx+o7P0 MDsdtCZa6eOZKva+U5zzjP3l1GObOkio1a1qnxanXql+3cAUXcMuE01F6h0AoDb3iXOn dAIwTRcS0RWoUMHgZXHyApBhSIcuVQPV0eKyj2nUrmD8T9Isrpb7px/NRguyJN8Utdum N6+TAKxcRFmQOz81EIQKV9bV4ciozD7lwb6IXMMLyfs5c5jtmRNDzS0xFwTAOm3ephC/ 9IjWsAdoC1JphXCB1N5g67SQeRLRtj5r6z5MjxjtEpZKKcWVPN0jPvJ+9GwJuLKvZ+Wr uFJg== X-Gm-Message-State: AOAM5338kIw0763RmSYvtseg3V/v2ZJr/0HrafGcYuLc3jh7zi/H7M/n ZA9jTCrQY5B+Q7lRn7iXOJpuxYb8+5ZqA0ntXLtlHELHdM0s9bWaW/CRR01oBsjZAvpjnV6O4Pl Erqg8RuTXu0jePWcLTEoqNom1B88k43Lx4o5+9AOvBJW2enSNsB9Ha1aDsiO1ygsaBS/+kMIOAw == X-Google-Smtp-Source: ABdhPJyZzYoiNJWw6v67KQH3H8TR7p93esoJ/JWh7ct2Y2JMyPi4RuGBYiaDntQktMBVCNcvLE2cnA== X-Received: by 2002:a17:90a:74cd:: with SMTP id p13mr10058166pjl.25.1607977424521; Mon, 14 Dec 2020 12:23:44 -0800 (PST) From: Rebecca Cran To: qemu-devel@nongnu.org Subject: [PATCH 2/3] target/arm: add FEAT_TLBIRANGE support Date: Mon, 14 Dec 2020 13:23:28 -0700 Message-Id: <20201214202329.26765-3-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214202329.26765-1-rebecca@nuviainc.com> References: <20201214202329.26765-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=rebecca@nuviainc.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Rebecca Cran , Richard Henderson , qemu-arm@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" ARMv8.4 adds the mandatory FEAT_TLBIRANGE, which provides instructions for invalidating ranges of entries. Signed-off-by: Rebecca Cran --- accel/tcg/cputlb.c | 24 ++ include/exec/exec-all.h | 39 +++ target/arm/helper.c | 273 ++++++++++++++++++++ 3 files changed, 336 insertions(+) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 42ab79c1a582..103f363b42f3 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -603,6 +603,30 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr) tlb_flush_page_by_mmuidx(cpu, addr, ALL_MMUIDX_BITS); } =20 +void tlb_flush_page_range_by_mmuidx(CPUState *cpu, target_ulong addr, + int num_pages, uint16_t idxmap) +{ + int i; + + for (i =3D 0; i < num_pages; i++) { + tlb_flush_page_by_mmuidx(cpu, addr + (i * TARGET_PAGE_SIZE), idxma= p); + } +} + +void tlb_flush_page_range_by_mmuidx_all_cpus_synced(CPUState *src_cpu, + target_ulong addr, + int num_pages, + uint16_t idxmap) +{ + int i; + + for (i =3D 0; i < num_pages; i++) { + tlb_flush_page_by_mmuidx_all_cpus_synced(src_cpu, + addr + (i * TARGET_PAGE_S= IZE), + idxmap); + } +} + void tlb_flush_page_by_mmuidx_all_cpus(CPUState *src_cpu, target_ulong add= r, uint16_t idxmap) { diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 94fe05daaa18..c379e2404443 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -220,6 +220,35 @@ void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, = target_ulong addr, */ void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong = addr, uint16_t idxmap); +/** + * tlb_flush_page_range_by_mmuidx: + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of start of page range to be flushed + * @num_pages: the number of pages to be flushed + * @idxmap: bitmap of MMU indexes to flush + * + * Flush a range of pages from the TLB of the specified CPU, for the speci= fied + * MMU indexes. + */ +void tlb_flush_page_range_by_mmuidx(CPUState *cpu, target_ulong addr, + int num_pages, uint16_t idxmap); +/** + * tlb_flush_page_range_by_mmuidx_all_cpus_synced: + * @cpu: Originating CPU of the flush + * @addr: virtual address of start of page range to be flushed + * @num_pages: the number of pages to be flushed + * @idxmap: bitmap of MMU indexes to flush + * + * Flush a range of pages from the TLB of all CPUs, for the specified MMU + * indexes like tlb_flush_page_by_mmuidx_all_cpus except the source + * vCPUs work is scheduled as safe work meaning all flushes will be + * complete once the source vCPUs safe work is complete. This will + * depend on when the guests translation ends the TB. + */ +void tlb_flush_page_range_by_mmuidx_all_cpus_synced(CPUState *cpu, + target_ulong addr, + int num_pages, + uint16_t idxmap); /** * tlb_flush_by_mmuidx: * @cpu: CPU whose TLB should be flushed @@ -321,6 +350,16 @@ static inline void tlb_flush_page_all_cpus_synced(CPUS= tate *src, target_ulong addr) { } +static void tlb_flush_page_range_by_mmuidx(CPUState *cpu, target_ulong add= r, + int num_pages, int idxmap) +{ +} +static void tlb_flush_page_range_by_mmuidx_all_cpus_synced(CPUState *src_c= pu, + target_ulong addr, + int num_pages, + uint16_t idxmap) +{ +} static inline void tlb_flush(CPUState *cpu) { } diff --git a/target/arm/helper.c b/target/arm/helper.c index 28556eb48b44..fffac1e1efa9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4667,6 +4667,165 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env= , const ARMCPRegInfo *ri, ARMMMUIdxBit_SE3, bits); } =20 +static int tlbi_aa64_range_get_num_pages(CPUARMState *env, uint64_t value, + uint64_t addr) +{ + uint64_t exponent; + uint64_t high_addr; + int page_size; + int page_shift; + uint64_t scale =3D (value >> 44) & 0x3; + uint64_t num =3D (value >> 39) & 0xF; + int page_size_granule =3D (value >> 46) & 0x3; + + switch (page_size_granule) { + case 1: + page_size =3D 4096; + page_shift =3D 12; + break; + case 2: + page_size =3D 16384; + page_shift =3D 14; + break; + case 3: + page_size =3D 65536; + page_shift =3D 16; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n", + page_size_granule); + + raise_exception(env, EXCP_UDEF, syn_uncategorized(), + exception_target_el(env)); + + break; + } + + exponent =3D (5 * scale) + 1; + high_addr =3D addr + (((num + 1) << exponent) * page_size); + + return (high_addr - addr) >> page_shift; +} + + +static void tlbi_aa64_rvae1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA range, EL1&0. + * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1, + * since we don't support flush-for-specific-ASID-only or + * flush-last-level-only. + */ + CPUState *cs =3D env_cpu(env); + int mask =3D vae1_tlbmask(env); + uint64_t addr =3D (value & 0xFFFFFFFFFUL) << TARGET_PAGE_BITS; + int num_pages =3D tlbi_aa64_range_get_num_pages(env, value, addr); + + if (tlb_force_broadcast(env)) { + tlb_flush_page_range_by_mmuidx_all_cpus_synced(cs, addr, num_pages, + mask); + } else { + tlb_flush_page_range_by_mmuidx(cs, addr, num_pages, mask); + } +} + +static void tlbi_aa64_rvae1is_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + /* + * Invalidate by VA range, Inner/Outer Shareable EL1&0. + * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS, + * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support + * flush-for-specific-ASID-only, flush-last-level-only or inner/outer + * shareable specific flushes. + */ + CPUState *cs =3D env_cpu(env); + int mask =3D vae1_tlbmask(env); + uint64_t addr =3D (value & 0xFFFFFFFFFUL) << TARGET_PAGE_BITS; + int num_pages =3D tlbi_aa64_range_get_num_pages(env, value, addr); + + tlb_flush_page_range_by_mmuidx_all_cpus_synced(cs, addr, num_pages, ma= sk); +} + +static void tlbi_aa64_rvae2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA range, EL2. + * Currently handles all of RVAE2, RVAAE2, RVAALE2 and RVALE2, + * since we don't support flush-for-specific-ASID-only or + * flush-last-level-only. + */ + CPUState *cs =3D env_cpu(env); + uint64_t addr =3D (value & 0xFFFFFFFFFUL) << TARGET_PAGE_BITS; + int num_pages =3D tlbi_aa64_range_get_num_pages(env, value, addr); + + if (tlb_force_broadcast(env)) { + tlb_flush_page_range_by_mmuidx_all_cpus_synced(cs, addr, num_pages, + ARMMMUIdxBit_E2); + } else { + tlb_flush_page_range_by_mmuidx(cs, addr, num_pages, ARMMMUIdxBit_E= 2); + } +} + +static void tlbi_aa64_rvae2is_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + /* + * Invalidate by VA range, Inner/Outer Shareable, EL2. + * Currently handles all of RVAE2IS, RVAE2OS, RVAAE2IS, RVAAE2OS, + * RVAALE2IS, RVAALE2OS, RVALE2IS and RVALE2OS, since we don't support + * flush-for-specific-ASID-only, flush-last-level-only or inner/outer + * shareable specific flushes. + */ + CPUState *cs =3D env_cpu(env); + uint64_t addr =3D (value & 0xFFFFFFFFFUL) << TARGET_PAGE_BITS; + int num_pages =3D tlbi_aa64_range_get_num_pages(env, value, addr); + + tlb_flush_page_range_by_mmuidx_all_cpus_synced(cs, addr, num_pages, + ARMMMUIdxBit_E2); +} + +static void tlbi_aa64_rvae3_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA range, EL3. + * Currently handles all of RVAE3, RVAAE3, RVAALE3 and RVALE3, + * since we don't support flush-for-specific-ASID-only or + * flush-last-level-only. + */ + CPUState *cs =3D env_cpu(env); + uint64_t addr =3D (value & 0xFFFFFFFFFUL) << TARGET_PAGE_BITS; + int num_pages =3D tlbi_aa64_range_get_num_pages(env, value, addr); + + if (tlb_force_broadcast(env)) { + tlb_flush_page_range_by_mmuidx_all_cpus_synced(cs, addr, num_pages, + ARMMMUIdxBit_SE3); + } else { + tlb_flush_page_range_by_mmuidx(cs, addr, num_pages, ARMMMUIdxBit_S= E3); + } +} + +static void tlbi_aa64_rvae3is_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + /* + * Invalidate by VA range, EL3, Inner/Outer Shareable. + * Currently handles all of RVAE3IS, RVAE3OS, RVAAE3IS, RVAAE3OS, + * RVAALE3IS, RVAALE3OS, RVALE3IS, and RVALE3OS, since we don't support + * flush-for-specific-ASID-only, flush-last-level-only or inner/outer + * specific flushes. + */ + CPUState *cs =3D env_cpu(env); + uint64_t addr =3D (value & 0xFFFFFFFFFUL) << TARGET_PAGE_BITS; + int num_pages =3D tlbi_aa64_range_get_num_pages(env, value, addr); + + tlb_flush_page_range_by_mmuidx_all_cpus_synced(cs, addr, num_pages, + ARMMMUIdxBit_SE3); +} + static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo= *ri, bool isread) { @@ -4938,6 +5097,63 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "TLBI_IPAS2LE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 4, .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RIPAS2E1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 2, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RIPAS2E1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 2, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RIPAS2E1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 3, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RVAAE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 3, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .writefn =3D tlbi_aa64_rvae1_write }, + { .name =3D "TLBI_RVAAE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 3, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAAE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 3, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .writefn =3D tlbi_aa64_rvae1_write }, + { .name =3D "TLBI_RVAE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAE2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, + .access =3D PL2_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .writefn =3D tlbi_aa64_rvae2_write }, + { .name =3D "TLBI_RVAE2IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, + .access =3D PL2_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .writefn =3D tlbi_aa64_rvae2is_write }, + { .name =3D "TLBI_RVAE2OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, + .access =3D PL2_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .writefn =3D tlbi_aa64_rvae2is_write }, + { .name =3D "TLBI_RVAE3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, + .access =3D PL3_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .writefn =3D tlbi_aa64_rvae3_write }, + { .name =3D "TLBI_RVAE3IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, + .access =3D PL3_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .writefn =3D tlbi_aa64_rvae3is_write }, + { .name =3D "TLBI_RVAE3OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, + .access =3D PL3_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .writefn =3D tlbi_aa64_rvae3is_write }, { .name =3D "TLBI_ALLE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 4, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, @@ -5046,6 +5262,63 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "TLBIIPAS2LIS", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 5, .type =3D ARM_CP_NOP, .access =3D PL2_W }, + { .name =3D "TLBI_RIPAS2LE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 6, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RIPAS2LE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 6, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RIPAS2LE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 7, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_RVAALE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 7, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1_write }, + { .name =3D "TLBI_RVAALE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 7, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVAALE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 7, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVALE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1_write }, + { .name =3D "TLBI_RVALE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVALE1OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae1is_write }, + { .name =3D "TLBI_RVALE2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2_write }, + { .name =3D "TLBI_RVALE2IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2is_write }, + { .name =3D "TLBI_RVALE2OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae2is_write }, + { .name =3D "TLBI_RVALE3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3_write }, + { .name =3D "TLBI_RVALE3IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3is_write }, + { .name =3D "TLBI_RVALE3OS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_rvae3is_write }, /* 32 bit cache operations */ { .name =3D "ICIALLUIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D= 1, .opc2 =3D 0, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= pou_access }, --=20 2.26.2