From nobody Tue Feb 10 11:14:37 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.65 as permitted sender) client-ip=209.85.128.65; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f65.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.65 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1607971130; cv=none; d=zohomail.com; s=zohoarc; b=YxhBS0LiaVbDybMCVZ4D5pH1Ive32EiLAkCnnC1phvWKqrT+Xla6QXf3Yd9W9ELCIist/rfD/mKxSw85RIH5eDRTjr6ydnJZPtoOIZ/npcfxLodKLQYhK6ecv1mP60575SR0LDdAnwhJOPVA+qBLlkRFIytm+x9W6N8+5wfA/Uw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607971130; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sGSxHagedQ+yelQida/tJJ2/RA7bkSvNOfSJ4MvCHXk=; b=frMJ+AGkAEGnld+HSvAujSZKAj8VDFB8StfjQErMLz1MCupxz+Wtxjenpxic7qiQW8Ff9lJ/Ehmwm0sYWVJO1Q1e4uiJ37DUQEwX6Stb+YxGsaEGtEvMy5OL0ARcs/RQgLt4ApdAjc8rwnZJx/51Z5+Il9JWCDYx+85AlO3qccg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.65 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f65.google.com (mail-wm1-f65.google.com [209.85.128.65]) by mx.zohomail.com with SMTPS id 16079711304352.567691847179276; Mon, 14 Dec 2020 10:38:50 -0800 (PST) Received: by mail-wm1-f65.google.com with SMTP id g185so16202462wmf.3 for ; Mon, 14 Dec 2020 10:38:49 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id q1sm31550246wrj.8.2020.12.14.10.38.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:38:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sGSxHagedQ+yelQida/tJJ2/RA7bkSvNOfSJ4MvCHXk=; b=PdSHiahu3St5VPIxw5aGKQa7K7soukaPOYYVdf/QPSoLLOBPUeVCn0gowQsQAr7YYE NLJhufzfKz0zIQTMtTCQ+ocR6odMrWjCl5njCq8vxlTqVrRn7MLPY/bj13uxoVZks4kZ lI+YMmJ87KZKix9XH12FDURZPfZooNyoIpqMNq9ZxMbdsm+QEKq+CJDzIkxxELwFrKdc 2E0yD6cHl61TCXsXrz+BOta+Rv8tB4cV1GGBwt2tggbizC7hTjEKeXgtgwreqtgmi4hx a7fLRTp+OcP0pDMU7cfusvzEfSGdMGQ34/dd+RypzUSU5dvpgFmrqMNDzVV8svgQVGkM wKxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=sGSxHagedQ+yelQida/tJJ2/RA7bkSvNOfSJ4MvCHXk=; b=XIoGieLmLEtuOBQ8HkBj05WHR3/bpuROPXu1Ww30/yczOC2/xPRBuRVUEaIqykTdKf 2I0P4ecQcT5wbdYj8rFR9N9rTbloDSuPI8mw55u9+tJI23583BgNU663HsWZI+KdNNF7 g83wuQs+s8/UcQ28z/Hpn2DwBb/+kIyJLpGk7UPFEH+08DZxf7L3/msNAhJFxi4iXjBh 1FfXkET98cKUZ3uHN7mIoNaS4+PFTi7w+B/TGrOc/5oaquE7/j2xtq3pyJ88i8vNkWS6 bGNfKKiopPe6JAm2JlHs5L6jdZb2j+zh0VRFYfyb/Z4Aa5MAE7ltiXJkIisV/H1vKIz3 psHQ== X-Gm-Message-State: AOAM5333EPsEcRmo1R9Pf5gCeejJMs7CPpSisrG3H9Axvg934NJLetJH y7fuIOWQIPnM2jrN9OG1MQU= X-Google-Smtp-Source: ABdhPJwlWmaCfmRQI8uZTvnZeWtXOWcn1UpyDEcuDiHJq+ZLXK9T69n/wJpn/e+Xd/au+GiANqM0BA== X-Received: by 2002:a05:600c:2255:: with SMTP id a21mr29697641wmm.122.1607971128564; Mon, 14 Dec 2020 10:38:48 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v2 13/16] target/mips/translate: Add declarations for generic code Date: Mon, 14 Dec 2020 19:37:36 +0100 Message-Id: <20201214183739.500368-14-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Some CPU translation functions / registers / macros and definitions can be used by ISA / ASE / extensions out of the big translate.c file. Declare them in "translate.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201207235539.4070364-3-f4bug@amsat.org> --- target/mips/translate.h | 38 ++++++++++++++++++++++++++++++++ target/mips/translate.c | 48 +++++++++++++---------------------------- 2 files changed, 53 insertions(+), 33 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index fcda1a99001..989d6c43207 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -10,6 +10,8 @@ =20 #include "exec/translator.h" =20 +#define MIPS_DEBUG_DISAS 0 + typedef struct DisasContext { DisasContextBase base; target_ulong saved_pc; @@ -47,4 +49,40 @@ typedef struct DisasContext { int gi; } DisasContext; =20 +/* MIPS major opcodes */ +#define MASK_OP_MAJOR(op) (op & (0x3F << 26)) + +void generate_exception_err(DisasContext *ctx, int excp, int err); +void generate_exception_end(DisasContext *ctx, int excp); +void gen_reserved_instruction(DisasContext *ctx); +void check_insn(DisasContext *ctx, uint64_t flags); +#ifdef TARGET_MIPS64 +void check_mips_64(DisasContext *ctx); +#endif + +void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offs= et); +void gen_load_gpr(TCGv t, int reg); +void gen_store_gpr(TCGv t, int reg); + +extern TCGv cpu_gpr[32], cpu_PC; +extern TCGv bcond; + +#define LOG_DISAS(...) = \ + do { = \ + if (MIPS_DEBUG_DISAS) { = \ + qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); = \ + } = \ + } while (0) + +#define MIPS_INVAL(op) = \ + do { = \ + if (MIPS_DEBUG_DISAS) { = \ + qemu_log_mask(CPU_LOG_TB_IN_ASM, = \ + TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\= n", \ + ctx->base.pc_next, ctx->opcode, op, = \ + ctx->opcode >> 26, ctx->opcode & 0x3F, = \ + ((ctx->opcode >> 16) & 0x1F)); = \ + } = \ + } while (0) + #endif diff --git a/target/mips/translate.c b/target/mips/translate.c index 0db0fce3789..318642cbcfe 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -38,11 +38,6 @@ #include "fpu_helper.h" #include "translate.h" =20 -#define MIPS_DEBUG_DISAS 0 - -/* MIPS major opcodes */ -#define MASK_OP_MAJOR(op) (op & (0x3F << 26)) - enum { /* indirect opcode tables */ OPC_SPECIAL =3D (0x00 << 26), @@ -2491,9 +2486,10 @@ enum { }; =20 /* global register indices */ -static TCGv cpu_gpr[32], cpu_PC; +TCGv cpu_gpr[32], cpu_PC; static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; -static TCGv cpu_dspctrl, btarget, bcond; +static TCGv cpu_dspctrl, btarget; +TCGv bcond; static TCGv cpu_lladdr, cpu_llval; static TCGv_i32 hflags; static TCGv_i32 fpu_fcr0, fpu_fcr31; @@ -2606,26 +2602,8 @@ static const char * const mxuregnames[] =3D { }; #endif =20 -#define LOG_DISAS(...) = \ - do { = \ - if (MIPS_DEBUG_DISAS) { = \ - qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); = \ - } = \ - } while (0) - -#define MIPS_INVAL(op) = \ - do { = \ - if (MIPS_DEBUG_DISAS) { = \ - qemu_log_mask(CPU_LOG_TB_IN_ASM, = \ - TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\= n", \ - ctx->base.pc_next, ctx->opcode, op, = \ - ctx->opcode >> 26, ctx->opcode & 0x3F, = \ - ((ctx->opcode >> 16) & 0x1F)); = \ - } = \ - } while (0) - /* General purpose registers moves. */ -static inline void gen_load_gpr(TCGv t, int reg) +void gen_load_gpr(TCGv t, int reg) { if (reg =3D=3D 0) { tcg_gen_movi_tl(t, 0); @@ -2634,7 +2612,7 @@ static inline void gen_load_gpr(TCGv t, int reg) } } =20 -static inline void gen_store_gpr(TCGv t, int reg) +void gen_store_gpr(TCGv t, int reg) { if (reg !=3D 0) { tcg_gen_mov_tl(cpu_gpr[reg], t); @@ -2763,7 +2741,7 @@ static inline void restore_cpu_state(CPUMIPSState *en= v, DisasContext *ctx) } } =20 -static inline void generate_exception_err(DisasContext *ctx, int excp, int= err) +void generate_exception_err(DisasContext *ctx, int excp, int err) { TCGv_i32 texcp =3D tcg_const_i32(excp); TCGv_i32 terr =3D tcg_const_i32(err); @@ -2779,11 +2757,16 @@ static inline void generate_exception(DisasContext = *ctx, int excp) gen_helper_0e0i(raise_exception, excp); } =20 -static inline void generate_exception_end(DisasContext *ctx, int excp) +void generate_exception_end(DisasContext *ctx, int excp) { generate_exception_err(ctx, excp, 0); } =20 +void gen_reserved_instruction(DisasContext *ctx) +{ + generate_exception_end(ctx, EXCP_RI); +} + /* Floating point register moves. */ static void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg) { @@ -3013,7 +2996,7 @@ static inline void check_dsp_r3(DisasContext *ctx) * This code generates a "reserved instruction" exception if the * CPU does not support the instruction set corresponding to flags. */ -static inline void check_insn(DisasContext *ctx, uint64_t flags) +void check_insn(DisasContext *ctx, uint64_t flags) { if (unlikely(!(ctx->insn_flags & flags))) { gen_reserved_instruction(ctx); @@ -3064,7 +3047,7 @@ static inline void check_ps(DisasContext *ctx) * This code generates a "reserved instruction" exception if 64-bit * instructions are not enabled. */ -static inline void check_mips_64(DisasContext *ctx) +void check_mips_64(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) { gen_reserved_instruction(ctx); @@ -3390,8 +3373,7 @@ OP_LD_ATOMIC(lld, ld64); #endif #undef OP_LD_ATOMIC =20 -static void gen_base_offset_addr(DisasContext *ctx, TCGv addr, - int base, int offset) +void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offs= et) { if (base =3D=3D 0) { tcg_gen_movi_tl(addr, offset); --=20 2.26.2