From nobody Sun May 5 06:21:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.67 as permitted sender) client-ip=209.85.128.67; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f67.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.67 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1607971070; cv=none; d=zohomail.com; s=zohoarc; b=jazmeqrBmXlZV6rvPUunVaRW9S4sRMPoTlsFUN6lkiRDB2Rj9FYNKi9xnXXdTvagY2/yYiwEnsTnVEN9510A93MTMW06LLJK7PTBXobpnU8vQXYy5nXTNUQlTIsqiQFsdRSgu33yMxp5xyZeRxfH95Vlblh8ScB9gFAKweufVC4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607971070; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PkbswluQKWjRx3dBtHaGXoEp5nk30ZYfIfOdkw/Z4mE=; b=aIGZNPtbFOiKZlfuYyEei3xuY+Cx+i1GWcTeQ/NLBoduKMedwNUDCDZleZ3uCCziR9+Y9eCqZ0UWBkLBKQdq6kRLflf2cLn5giyh9DvzFFEnXwTAeSvdSld4bTDp/tXUaqMD3ho+4HCaCgyFIp90mIyJVVfvpMdTaD9t3+0tu8w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.67 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f67.google.com (mail-wm1-f67.google.com [209.85.128.67]) by mx.zohomail.com with SMTPS id 1607971070246643.948847832296; Mon, 14 Dec 2020 10:37:50 -0800 (PST) Received: by mail-wm1-f67.google.com with SMTP id g185so16200120wmf.3 for ; Mon, 14 Dec 2020 10:37:48 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id y7sm33139083wmb.37.2020.12.14.10.37.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:37:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PkbswluQKWjRx3dBtHaGXoEp5nk30ZYfIfOdkw/Z4mE=; b=so87HLcUDeHLMSRrrBIoaQWUwBf8G3+RiGUHx0pXI0M8i8oVclm5u38oWxGVU+nRE9 H1/I+bkvfeohZvPRDLGNrptdMb+bS/XgK3I3hemaCE4VuYbp+oP8+OEm6BaxdYpVWC5q 7kdq8C+VkX1BkPWurVnCHTbxnFpB1RkgtRNapuqHjZDaFp5gokompzmmnRBHp7irMovG HplSBu+h5qd5YPQpXjbyjrz2Qx+8dbFmeEToshnQT5AEFmjWT8/8pf5RXYihAN8NPqqV XW+aOXYWZUP/uJ/OYB3uskd5w4ddXWksjA52rV84hF4Rzc6VUX3VxpFwzSY8JvoiQx3F TryQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=PkbswluQKWjRx3dBtHaGXoEp5nk30ZYfIfOdkw/Z4mE=; b=m2YPUTLkQEQUMqaD/M1asp6uQjoM9QJ0anfx3WnZNl432rQTf9RrI33oVxxncXoSgi X15U9zrhVTLYaMx271lk81vGBgwcE+GNG0Kh6T2Gj/7ly13UvpwM1DTCwSpQo2zsDhOp UF3B0RMuUJR8Y3afDST//vK0keaycXWJy89v5CQJ1fMF8gAkJLDwQfgiedt4tCHNICTo 2f6Rj+MjirUh+UMdDoOZBOgkuAWkJkc/KJpLl/Wbjk/INbhM8hhFVOLrPQIsu+zDthbm HUZYem6uXcAUZWPZyH9ukGT7ZEZr8HXe5TO53+1QBAXD3BghMJuTtxMmeS+0I/cHDPrq ClMg== X-Gm-Message-State: AOAM533726Uo1tq6nM0QxG4tCOGiZYz2Yj7Drh868z1LHUUN+XSaqL0z U1t06mdyPYJxZw4DJEDfj8M= X-Google-Smtp-Source: ABdhPJwGXLAxo6yN+sLIdbUznMxVePFYOVX87wckAVWiT7wsnNmHFrE3HhgsbKkK5tMFh6Kt4WouSg== X-Received: by 2002:a1c:2c83:: with SMTP id s125mr29306057wms.161.1607971067021; Mon, 14 Dec 2020 10:37:47 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 01/16] target/mips: Inline cpu_state_reset() in mips_cpu_reset() Date: Mon, 14 Dec 2020 19:37:24 +0100 Message-Id: <20201214183739.500368-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/cpu.c | 26 +++++++++----------------- 1 file changed, 9 insertions(+), 17 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index aadc6f8e74d..7a0dcb11ecd 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -104,10 +104,16 @@ static bool mips_cpu_has_work(CPUState *cs) =20 #include "translate_init.c.inc" =20 -/* TODO QOM'ify CPU reset and remove */ -static void cpu_state_reset(CPUMIPSState *env) +static void mips_cpu_reset(DeviceState *dev) { - CPUState *cs =3D env_cpu(env); + CPUState *cs =3D CPU(dev); + MIPSCPU *cpu =3D MIPS_CPU(cs); + MIPSCPUClass *mcc =3D MIPS_CPU_GET_CLASS(cpu); + CPUMIPSState *env =3D &cpu->env; + + mcc->parent_reset(dev); + + memset(env, 0, offsetof(CPUMIPSState, end_reset_fields)); =20 /* Reset registers to their default values */ env->CP0_PRid =3D env->cpu_model->CP0_PRid; @@ -330,20 +336,6 @@ static void cpu_state_reset(CPUMIPSState *env) /* UHI interface can be used to obtain argc and argv */ env->active_tc.gpr[4] =3D -1; } -} - -static void mips_cpu_reset(DeviceState *dev) -{ - CPUState *s =3D CPU(dev); - MIPSCPU *cpu =3D MIPS_CPU(s); - MIPSCPUClass *mcc =3D MIPS_CPU_GET_CLASS(cpu); - CPUMIPSState *env =3D &cpu->env; - - mcc->parent_reset(dev); - - memset(env, 0, offsetof(CPUMIPSState, end_reset_fields)); - - cpu_state_reset(env); =20 #ifndef CONFIG_USER_ONLY if (kvm_enabled()) { --=20 2.26.2 From nobody Sun May 5 06:21:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) client-ip=209.85.221.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1607971074; cv=none; d=zohomail.com; s=zohoarc; b=aEsQr1LGtH5+fI1MpR/yKXki0ZXStorq/1caB2wMI05o9ZPdFf6FjGhyGU5NKRSHwbwITAgkqusQVz2vBpW89Hgg8fZ1EW9qbkOsk6wnGzLo6W77rOiNspd65LcIjRh0HkcjgQxCx14osx866s7ZDXpM5IJPK/fUqUR0PxB8jk4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607971074; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sHs7veobjgUtipOw413RUmMgxkozqNiInWyl2lKSMtU=; b=F1gh3I70m9euCbkrEKGXJxfH8SVD4cActX8Ct3XxxKRpszm0KA84eoG38kmEO8g/MlDc/e+9MlErDxUbtu0azD4f3dChWn7Fn+wIzs/pxC/SZGOgerEdm0M2sT3R7ibv1LOMdOw3PfY4/KqGQvUUS4fqma+TMGT2DcO1lgsjrO4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) by mx.zohomail.com with SMTPS id 1607971074433768.2001597363685; Mon, 14 Dec 2020 10:37:54 -0800 (PST) Received: by mail-wr1-f48.google.com with SMTP id q18so9928331wrn.1 for ; Mon, 14 Dec 2020 10:37:53 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id a62sm35673893wmh.40.2020.12.14.10.37.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:37:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sHs7veobjgUtipOw413RUmMgxkozqNiInWyl2lKSMtU=; b=R6N8xTI/TZtt1/ttVRJTmldNvalaoWhTKj05I/CefXL1w6qwVuoX5FlfsUPcBdXMFD 56U7USzIa7r4f9rCItTPiLdGHoD5wnwAcn/8gALZyd/AazBiwMgCdzM8IdQl8V80Rg8X JNHa0vDoEcrc5CuALtXrP2iSKIQ6yIumZm+kOzKMuNKzXlNwXvXmaohGukV+a5Y+QRRm ev6sbJeHWeYHg52DQ/KnKGRRcjPz/hoXWb6nTDucsf7Lzm68XBAZaHh4j54rhl58h5ST QrRKyGmqvMifpyWAC52NebHSz6bfrXtJe9BR9RXUOw4MBCf0N58rmEq5ywLAsDPQkZ9/ RGfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=sHs7veobjgUtipOw413RUmMgxkozqNiInWyl2lKSMtU=; b=Acc7Pra0HADmolCYwszkri73fyCYT5I+IurXfCshtdJO4VU1NFAup0N348T2KhQ8MJ ZJMIb6Chyg40vUAHhYZuT6I1uTNfW4lE+Qt2t3jlP6OgEy8IBgie7eEKjz7UgZFdCeeu yYdLuL2LJxjCHIbv4Q5T+xSsZGnYgdGwfNOdO4bvEArPGR37Og2FI6lY9x0fl0A6LXhr mLh+yADXZeLjd8HbCdHeLJkjOTvKKod2IQOnw8TZUDWvjphoTGC0CV/pZyqeOOBoR4rw oIK+k3XRnh3j3D3bbxL8Ffd3Ah21n7SAW2fzuuPZNSaA+LokatmMsp+AlTSAi9Xv1j4l d0mQ== X-Gm-Message-State: AOAM530rtQf0Gwr8piTKF1/RrEarJGjL1Tle/Q/1Y20P6Vguw77SDtoA w4KaaPWO7P9abFfsxNaOt23EhUEyO44= X-Google-Smtp-Source: ABdhPJxr14U7LFHQpzDw1aBFzgQBJzKBC+fQhPUojU/M0bLtxPrBLZNJG3iXGeF6lA9w6JG8I1YYew== X-Received: by 2002:a5d:6888:: with SMTP id h8mr30614055wru.268.1607971072553; Mon, 14 Dec 2020 10:37:52 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v2 02/16] target/mips: Extract FPU helpers to 'fpu_helper.h' Date: Mon, 14 Dec 2020 19:37:25 +0100 Message-Id: <20201214183739.500368-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Extract FPU specific helpers from "internal.h" to "fpu_helper.h". Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20201120210844.2625602-2-f4bug@amsat.org> --- target/mips/fpu_helper.h | 59 ++++++++++++++++++++++++++++++++ target/mips/internal.h | 49 -------------------------- linux-user/mips/cpu_loop.c | 1 + target/mips/fpu_helper.c | 1 + target/mips/gdbstub.c | 1 + target/mips/kvm.c | 1 + target/mips/machine.c | 1 + target/mips/msa_helper.c | 1 + target/mips/op_helper.c | 2 +- target/mips/translate.c | 1 + target/mips/translate_init.c.inc | 2 ++ 11 files changed, 69 insertions(+), 50 deletions(-) create mode 100644 target/mips/fpu_helper.h diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h new file mode 100644 index 00000000000..1c2d6d35a71 --- /dev/null +++ b/target/mips/fpu_helper.h @@ -0,0 +1,59 @@ +/* + * Helpers for emulation of FPU-related MIPS instructions. + * + * Copyright (C) 2004-2005 Jocelyn Mayer + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#include "fpu/softfloat-helpers.h" +#include "cpu.h" + +extern const FloatRoundMode ieee_rm[4]; + +uint32_t float_class_s(uint32_t arg, float_status *fst); +uint64_t float_class_d(uint64_t arg, float_status *fst); + +static inline void restore_rounding_mode(CPUMIPSState *env) +{ + set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], + &env->active_fpu.fp_status); +} + +static inline void restore_flush_mode(CPUMIPSState *env) +{ + set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) !=3D 0, + &env->active_fpu.fp_status); +} + +static inline void restore_snan_bit_mode(CPUMIPSState *env) +{ + set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) =3D= =3D 0, + &env->active_fpu.fp_status); +} + +static inline void restore_fp_status(CPUMIPSState *env) +{ + restore_rounding_mode(env); + restore_flush_mode(env); + restore_snan_bit_mode(env); +} + +/* MSA */ + +enum CPUMIPSMSADataFormat { + DF_BYTE =3D 0, + DF_HALF, + DF_WORD, + DF_DOUBLE +}; + +static inline void restore_msa_fp_status(CPUMIPSState *env) +{ + float_status *status =3D &env->active_tc.msa_fp_status; + int rounding_mode =3D (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSAC= SR_RM; + bool flush_to_zero =3D (env->active_tc.msacsr & MSACSR_FS_MASK) !=3D 0; + + set_float_rounding_mode(ieee_rm[rounding_mode], status); + set_flush_to_zero(flush_to_zero, status); + set_flush_inputs_to_zero(flush_to_zero, status); +} diff --git a/target/mips/internal.h b/target/mips/internal.h index e4d2d9f44f9..24d9f0d6a5c 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -9,7 +9,6 @@ #define MIPS_INTERNAL_H =20 #include "exec/memattrs.h" -#include "fpu/softfloat-helpers.h" =20 /* * MMU types, the first four entries have the same layout as the @@ -75,13 +74,6 @@ struct mips_def_t { extern const struct mips_def_t mips_defs[]; extern const int mips_defs_number; =20 -enum CPUMIPSMSADataFormat { - DF_BYTE =3D 0, - DF_HALF, - DF_WORD, - DF_DOUBLE -}; - void mips_cpu_do_interrupt(CPUState *cpu); bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags); @@ -220,49 +212,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, bool probe, uintptr_t retaddr); =20 /* op_helper.c */ -uint32_t float_class_s(uint32_t arg, float_status *fst); -uint64_t float_class_d(uint64_t arg, float_status *fst); - -extern const FloatRoundMode ieee_rm[4]; - void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk); =20 -static inline void restore_rounding_mode(CPUMIPSState *env) -{ - set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], - &env->active_fpu.fp_status); -} - -static inline void restore_flush_mode(CPUMIPSState *env) -{ - set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) !=3D 0, - &env->active_fpu.fp_status); -} - -static inline void restore_snan_bit_mode(CPUMIPSState *env) -{ - set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) =3D= =3D 0, - &env->active_fpu.fp_status); -} - -static inline void restore_fp_status(CPUMIPSState *env) -{ - restore_rounding_mode(env); - restore_flush_mode(env); - restore_snan_bit_mode(env); -} - -static inline void restore_msa_fp_status(CPUMIPSState *env) -{ - float_status *status =3D &env->active_tc.msa_fp_status; - int rounding_mode =3D (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSAC= SR_RM; - bool flush_to_zero =3D (env->active_tc.msacsr & MSACSR_FS_MASK) !=3D 0; - - set_float_rounding_mode(ieee_rm[rounding_mode], status); - set_flush_to_zero(flush_to_zero, status); - set_flush_inputs_to_zero(flush_to_zero, status); -} - static inline void restore_pamask(CPUMIPSState *env) { if (env->hflags & MIPS_HFLAG_ELPA) { diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index cfe7ba5c47d..b58dbeb83d1 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -23,6 +23,7 @@ #include "cpu_loop-common.h" #include "elf.h" #include "internal.h" +#include "fpu_helper.h" =20 # ifdef TARGET_ABI_MIPSO32 # define MIPS_SYSCALL_NUMBER_UNUSED -1 diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index bdb65065ee7..a3c05160b35 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -27,6 +27,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "fpu/softfloat.h" +#include "fpu_helper.h" =20 =20 /* Complex FPU operations which may need stack space. */ diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c index e39f8d75cf0..f1c2a2cf6d6 100644 --- a/target/mips/gdbstub.c +++ b/target/mips/gdbstub.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "internal.h" #include "exec/gdbstub.h" +#include "fpu_helper.h" =20 int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { diff --git a/target/mips/kvm.c b/target/mips/kvm.c index 477692566a4..a5b6fe35dbc 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -24,6 +24,7 @@ #include "sysemu/runstate.h" #include "kvm_mips.h" #include "hw/boards.h" +#include "fpu_helper.h" =20 #define DEBUG_KVM 0 =20 diff --git a/target/mips/machine.c b/target/mips/machine.c index 5b23e3e912a..a4ea67c2980 100644 --- a/target/mips/machine.c +++ b/target/mips/machine.c @@ -2,6 +2,7 @@ #include "cpu.h" #include "internal.h" #include "migration/cpu.h" +#include "fpu_helper.h" =20 static int cpu_post_load(void *opaque, int version_id) { diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 249f0fdad80..b89b4c44902 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -23,6 +23,7 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" +#include "fpu_helper.h" =20 /* Data format min and max values */ #define DF_BITS(df) (1 << ((df) + 3)) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 5aa97902e98..3386b8228e9 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -24,7 +24,7 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "exec/memop.h" - +#include "fpu_helper.h" =20 /*************************************************************************= ****/ /* Exceptions processing helpers */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 19933b7868c..d2614796214 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -35,6 +35,7 @@ #include "exec/translator.h" #include "exec/log.h" #include "qemu/qemu-print.h" +#include "fpu_helper.h" =20 #define MIPS_DEBUG_DISAS 0 =20 diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.= c.inc index f72fee3b40a..915277dd1f6 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -18,6 +18,8 @@ * License along with this library; if not, see . */ =20 +#include "fpu_helper.h" + /* CPU / CPU family specific config register values. */ =20 /* Have config1, uncached coherency */ --=20 2.26.2 From nobody Sun May 5 06:21:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) client-ip=209.85.128.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1607971081; cv=none; d=zohomail.com; s=zohoarc; b=R19QddnhkCUEJ5fXxVP1cJWW4rhMgj8qB6yF1C95MjG27U9Kphb1IjAymfSFXufYp8DpgMzHiAUr53I6yonlZ4y7F83OdLuUVq2WV+jVItkDwIG118G421W9oDCh6QGz1ajP4F8bqqiseLFZ/wOJHGSRkeqLlAi/+MPQlBn5mFw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607971081; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=tkYIisFgK6Je25iDH+AcvdFQgbr8b03Vk9AV0zMlHWI=; b=il5GKdvPtMSfOlLSCx/nLxXHHXbp1r3FF0/9zeK557PtdaDhrOpEbb8B/lLW4NqVxqnchRVVLieF8fUqVlooUZL4Zxkvfn+FhptCZ/kU4l3aSTFcGpkK+y8zG9LNffnoPnYmnFrnMnDUKrm6yGr/Hlf6E0Qf7KukMf09l1v2whs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) by mx.zohomail.com with SMTPS id 1607971081212102.03534550329152; Mon, 14 Dec 2020 10:38:01 -0800 (PST) Received: by mail-wm1-f54.google.com with SMTP id k10so14688624wmi.3 for ; Mon, 14 Dec 2020 10:38:00 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id p15sm24306743wrt.15.2020.12.14.10.37.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:37:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tkYIisFgK6Je25iDH+AcvdFQgbr8b03Vk9AV0zMlHWI=; b=hgL3Ac52u3mHBafiHWMQFZ22Iz9iA+Su5rN5IOY9SxxsUtNm3tSIXIZgoUPSbW35cm c2SVS3s/gtJEm0xzO+5g7DRoQmlZ4fwJEgCwd1trER19AAl5aD1P30esrymA8yESj3ND l8tbsA6hnXMPal+/PgwbdFUAVa6uUKbTCIxkzxYUzyNPD5jBKTOuCBvizf382DksF7JP YbNBCSN5D3xjr5rq8dIL/lR8YDyXg/iYvUYglHdyRPTNoQq9DjEU01Gqd8tIt2V91JKz STe93f1h68AdAskIYZb/HAua3Tc4iNJAxv8u2rKyNuJnQEq4VHADmGiJNBmBGVhNZcK1 X6Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=tkYIisFgK6Je25iDH+AcvdFQgbr8b03Vk9AV0zMlHWI=; b=R6USWAMMLGyoYvoiVGA+i4HyrharCqcKXWrrKNJ0INz9RWcFK8Wgha8t4p0lC5MF6D iZGGO+mtUqIa8GCjr4yG6Txty8yuDwzcFczEx8q0RuoCocgKwxIP5FvYeK7CnTNalLzg xaUj2DyAbsRcJaI1xNuXCSWXiolVwqTHxEUII7KEhRajNr/eTZ6FHPgfaX7v5jxpfH1e UzgSxTV2ixbfxiAQ0y7Roq7rCvK/HYZa9U3+Dbnmpc7i3TgNmc/ZgbPump0vVyNZu0y4 99RKDLf0eG9cmvps4LsHbQIV/0GQ0DfUojImva+dAXHLYOpRLme3l5ia5pNQmFakt3V/ cYRA== X-Gm-Message-State: AOAM532HT4EmaF2qgMUSH7Xuj63q4+N8bINqJTzusSGUUL70265pVR8w MsJ80GyCwvjvqDkOeDJncRk= X-Google-Smtp-Source: ABdhPJwzkNHg3Tv/g0fScefe8FqRMtvselhx3j0oy/GqpnxEqHkfTN6UAORwsjlkl1T0lM6wjnSslA== X-Received: by 2002:a1c:6a10:: with SMTP id f16mr29145023wmc.106.1607971077643; Mon, 14 Dec 2020 10:37:57 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 03/16] target/mips: Add !CONFIG_USER_ONLY comment after #endif Date: Mon, 14 Dec 2020 19:37:26 +0100 Message-Id: <20201214183739.500368-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) To help understand ifdef'ry, add comment after #endif. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/helper.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/target/mips/helper.c b/target/mips/helper.c index 87296fbad69..cdd7704789d 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -455,7 +455,8 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulo= ng val) } } } -#endif + +#endif /* !CONFIG_USER_ONLY */ =20 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, int rw, int tlb_error) @@ -537,6 +538,7 @@ static void raise_mmu_exception(CPUMIPSState *env, targ= et_ulong address, } =20 #if !defined(CONFIG_USER_ONLY) + hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { MIPSCPU *cpu =3D MIPS_CPU(cs); @@ -550,7 +552,7 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr= addr) } return phys_addr; } -#endif +#endif /* !CONFIG_USER_ONLY */ =20 #if !defined(CONFIG_USER_ONLY) #if !defined(TARGET_MIPS64) @@ -886,7 +888,7 @@ refill: return true; } #endif -#endif +#endif /* !CONFIG_USER_ONLY */ =20 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, @@ -1088,7 +1090,8 @@ static inline void set_badinstr_registers(CPUMIPSStat= e *env) env->CP0_BadInstrP =3D cpu_ldl_code(env, env->active_tc.PC - 4); } } -#endif + +#endif /* !CONFIG_USER_ONLY */ =20 void mips_cpu_do_interrupt(CPUState *cs) { @@ -1482,7 +1485,7 @@ void r4k_invalidate_tlb(CPUMIPSState *env, int idx, i= nt use_extra) } } } -#endif +#endif /* !CONFIG_USER_ONLY */ =20 void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception, --=20 2.26.2 From nobody Sun May 5 06:21:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.68 as permitted sender) client-ip=209.85.128.68; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f68.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.68 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1607971087; cv=none; d=zohomail.com; s=zohoarc; b=EM3qgwbJfkmSjg989Zk4eiDFBXvRDDnwAjmExI+zc+8KK+VzjairBgz0JevIrb+iBpX/GjAKsg1OfHIjRdejduKJKgWYbP4EbvG7R8K7Y3AuT6xxQagAoNgkjHGVAXZ6aFCHvhNv9jZ+TttZTMpbe17dZt1vgzCuhiw8AR5zFh0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607971087; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DvL7rsuXwOy7A4uG7jIuuMdjlMIgZJtQ8Sw9rQv0vgk=; b=UlyUPul7oDW3rgrH4+iN3jhwE3v9dBmMetUY1HHA/F/sIJFsOiKPymNjYhK8eU4ssziafN5v09c83hyZJu17VLEVBTGmKza7g1M2uoIpo/aMATIbjxaZXiIT88RKPgzMayJHCGgFlgI6VK45Y4WEJpSnUQpmUegjDfUXxVDgSsY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.68 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f68.google.com (mail-wm1-f68.google.com [209.85.128.68]) by mx.zohomail.com with SMTPS id 1607971087278554.6788808408198; Mon, 14 Dec 2020 10:38:07 -0800 (PST) Received: by mail-wm1-f68.google.com with SMTP id a6so14683698wmc.2 for ; Mon, 14 Dec 2020 10:38:06 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id n14sm32217432wmi.1.2020.12.14.10.38.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:38:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DvL7rsuXwOy7A4uG7jIuuMdjlMIgZJtQ8Sw9rQv0vgk=; b=kXAzLtsWvoRZNkxK3QfzhePj2xCpEwPeaCxWn+hS8EOAxYHORP2YvWwjfrJVnVvPsE 8Tlkx8zC5Q9G1DJ2ykbNA2MO3XK+2vihDVbBhyiamt12b0N+9sdBXuXFxr1EzW6HvxZM zL9L2cbM+QEvORrXsqF0pL5zzKDY5ACFV+L9dgpApMdTneuUglmnQA5tp0DE9xmhFUwg thbUNg+kismdH916KVP0g1X+s80HA/3zqzsINrVStNv/eNpf5KP4iimlNyn0ztxLfinf SNuSU7BrO+q17UUQv1Inb6nDwbXmE7dcF81tJeJgDX+unA0FPWD8yW1JtK2NnISt/MKg bJeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=DvL7rsuXwOy7A4uG7jIuuMdjlMIgZJtQ8Sw9rQv0vgk=; b=EXhDUGXOFbpNs0Fzk6Lozrl0qjZRjh+CvytIbmZdMMVjYp7IxJCLtBsZGu7T3knrHt udJ3O00Cnennzdvo6UVqb3mXG2j0ly1aIW+wSV0SGNB0LB3l3u1oCLKD2MVW14u4RRoR jSy5jUy1Hy3hCdaat7J4+ZKCbBf5stQCHjy4nzL7dCl5pNFui+z88ZD6XcFm0KBzRU7S 7y2qGW13gh/KswpPPjFCzhB+8F4JxO0qDsUb8lrOetQFqFIdIFTfhfQ2vssd29q3DMD4 1vswRsi1EVBqukeGaCYyT/U9HspSeTIKFoEKF1Xs+POQeBgA6IAoqgFvsjkrYs3i7Z/B KK0Q== X-Gm-Message-State: AOAM531ff+rlsLglcAY21s4OK2ZFN0dOe/Wq5Wf5lYacxsqE1dyM3YY3 vdt7ek5FxFTBMW6RlrjNui0= X-Google-Smtp-Source: ABdhPJx3txinzJGaex7i/x3SQ8SYsfnEhn9muwCasq9NZdu9YYmx4x6odxQdU+R6stgDbXJrnCktAg== X-Received: by 2002:a1c:4d0a:: with SMTP id o10mr30042071wmh.185.1607971082664; Mon, 14 Dec 2020 10:38:02 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 04/16] target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs Date: Mon, 14 Dec 2020 19:37:27 +0100 Message-Id: <20201214183739.500368-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/helper.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/mips/helper.c b/target/mips/helper.c index cdd7704789d..0692e232f0a 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -552,9 +552,7 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr= addr) } return phys_addr; } -#endif /* !CONFIG_USER_ONLY */ =20 -#if !defined(CONFIG_USER_ONLY) #if !defined(TARGET_MIPS64) =20 /* --=20 2.26.2 From nobody Sun May 5 06:21:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) client-ip=209.85.221.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1607971821; cv=none; d=zohomail.com; s=zohoarc; b=Etdd2oa0kuA3pxS3sTNE6fc+CK0NozUdCjYOSZCGmTFjMCWNQUFytysOPGXSl1bGQJQpzFZrJoR3G8Y5mMYQzbF6CZkWpEzZByZMK50nl28JRDHjB0o+nx7zCxaT/SorDtQhlSg060u30IiwLgZteFe00yfJeN9yNAIBBSkaQXU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607971821; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=35iXDZeU1/ndOktt2O4X9ATnWZ6nXG6x/rceHWRoTA0=; b=avLKl/wTZlKjIMLby3SWPlgIP/ZGVrcWr1eB10p47mor9KPTzRnuoNmI3chgGeeAjKLNfGGN8Z9naJTwLgbFuPtm7dQMuoAwVVLOcTQ/f1YDulDunt0WjaK0R4ZeyI1XiJLnNuwtdOVht1uwlFAMIpFUWqspsSqk+8IFj1urfqU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) by mx.zohomail.com with SMTPS id 1607971821256392.9757983588386; Mon, 14 Dec 2020 10:50:21 -0800 (PST) Received: by mail-wr1-f48.google.com with SMTP id r14so17492743wrn.0 for ; Mon, 14 Dec 2020 10:50:20 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id m17sm36097710wrn.0.2020.12.14.10.38.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:38:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=35iXDZeU1/ndOktt2O4X9ATnWZ6nXG6x/rceHWRoTA0=; b=tBRSMIu6NzbVXjf3kPj/Qm9VfXdPqPMDdFPreznoNjiHORdK9vRa9pkfieDv+sGlbe MQoKiNx+ycUodFcc5q5Xc1DiVDW6v+m3HlI+6Ixj5cJaxdUxS9RgGBcvhpWCsgJoUkyG BilUjY9090lHE8FRyLBcMm6VjJBtWLeBdJSMaY1CIcYG4YT9qrW1wQ8LcSlC9guoK2n3 7KC0e9S8zw3Qen3YUVQR3gWDUEWRpMLj5KhW/TGks+xQ7GRQ16Ip9p2hSEg5jyF90j1+ CP6XnTKRRWYC65fywUq4BhlPftAVXBjgPWZL4zmFiaiYjtqw3Ist99Am6Jjh4mkItEN2 YIpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=35iXDZeU1/ndOktt2O4X9ATnWZ6nXG6x/rceHWRoTA0=; b=ONU8647pMQxFrGo/I7faxUPQalHG3q0dNxcBMAZjKJj45uD1Ignqg4MrIRm4JhKu/D Dlq9iXCX3m31166V5BTUjYxy8O1wQ/dQRz6lk+bA5+9s7s9/I7J2XaLgUCzp22z93uXc ulrkrUpomK22Q5cMBrWT4T2FOEepaw+6p/5YP5GU3c28iGpHLqBIMfbVxe11EfLEX6+A FO/Am6P7AqeIiJyhUfLjCL/OT4OYbXkWabog7Kgw35e6rTN8qK3nHxdZlMEyjC3zWMMa +gDDz263sro9Lwg/m+0MI5BS9sZPCJDuEH+NeujdyjPPlUFTg6A6lWsSA6vV5tWUnO7P RaUw== X-Gm-Message-State: AOAM532lVkmwsr0GFl0aAvbvCkqTm7g2S/22RNqctbPPBMSAae2eO7v6 6zGUfPiOe1IbS44/pZI0zXyF/cjLwyA= X-Google-Smtp-Source: ABdhPJzOy3HrSvo4JfYrDgPumHlTtg+Y0kA0lzttaDAXBEXF7YA8bLQlFtHcqal6W3UXiziMszSZKg== X-Received: by 2002:adf:a388:: with SMTP id l8mr30321919wrb.354.1607971087743; Mon, 14 Dec 2020 10:38:07 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 05/16] target/mips: Extract common helpers from helper.c to common_helper.c Date: Mon, 14 Dec 2020 19:37:28 +0100 Message-Id: <20201214183739.500368-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The rest of helper.c is TLB related. Extract the non TLB specific functions to a new file, so we can rename helper.c as tlb_helper.c in the next commit. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/internal.h | 2 + target/mips/cpu.c | 215 +++++++++++++++++++++++++++++++++++++++-- target/mips/helper.c | 201 -------------------------------------- 3 files changed, 211 insertions(+), 207 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 24d9f0d6a5c..c1401492c46 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -399,6 +399,8 @@ void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cp= u, int tc); void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); =20 +const char *mips_exception_name(int32_t exception); + void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exce= ption, int error_code, uintptr_t pc); =20 diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 7a0dcb11ecd..a54be034a2b 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -34,6 +34,215 @@ #include "hw/semihosting/semihost.h" #include "qapi/qapi-commands-machine-target.h" =20 +#if !defined(CONFIG_USER_ONLY) + +/* Called for updates to CP0_Status. */ +void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) +{ + int32_t tcstatus, *tcst; + uint32_t v =3D cpu->CP0_Status; + uint32_t cu, mx, asid, ksu; + uint32_t mask =3D ((1 << CP0TCSt_TCU3) + | (1 << CP0TCSt_TCU2) + | (1 << CP0TCSt_TCU1) + | (1 << CP0TCSt_TCU0) + | (1 << CP0TCSt_TMX) + | (3 << CP0TCSt_TKSU) + | (0xff << CP0TCSt_TASID)); + + cu =3D (v >> CP0St_CU0) & 0xf; + mx =3D (v >> CP0St_MX) & 0x1; + ksu =3D (v >> CP0St_KSU) & 0x3; + asid =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + + tcstatus =3D cu << CP0TCSt_TCU0; + tcstatus |=3D mx << CP0TCSt_TMX; + tcstatus |=3D ksu << CP0TCSt_TKSU; + tcstatus |=3D asid; + + if (tc =3D=3D cpu->current_tc) { + tcst =3D &cpu->active_tc.CP0_TCStatus; + } else { + tcst =3D &cpu->tcs[tc].CP0_TCStatus; + } + + *tcst &=3D ~mask; + *tcst |=3D tcstatus; + compute_hflags(cpu); +} + +void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) +{ + uint32_t mask =3D env->CP0_Status_rw_bitmask; + target_ulong old =3D env->CP0_Status; + + if (env->insn_flags & ISA_MIPS32R6) { + bool has_supervisor =3D extract32(mask, CP0St_KSU, 2) =3D=3D 0x3; +#if defined(TARGET_MIPS64) + uint32_t ksux =3D (1 << CP0St_KX) & val; + ksux |=3D (ksux >> 1) & val; /* KX =3D 0 forces SX to be 0 */ + ksux |=3D (ksux >> 1) & val; /* SX =3D 0 forces UX to be 0 */ + val =3D (val & ~(7 << CP0St_UX)) | ksux; +#endif + if (has_supervisor && extract32(val, CP0St_KSU, 2) =3D=3D 0x3) { + mask &=3D ~(3 << CP0St_KSU); + } + mask &=3D ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); + } + + env->CP0_Status =3D (old & ~mask) | (val & mask); +#if defined(TARGET_MIPS64) + if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { + /* Access to at least one of the 64-bit segments has been disabled= */ + tlb_flush(env_cpu(env)); + } +#endif + if (ase_mt_available(env)) { + sync_c0_status(env, env, env->current_tc); + } else { + compute_hflags(env); + } +} + +void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) +{ + uint32_t mask =3D 0x00C00300; + uint32_t old =3D env->CP0_Cause; + int i; + + if (env->insn_flags & ISA_MIPS32R2) { + mask |=3D 1 << CP0Ca_DC; + } + if (env->insn_flags & ISA_MIPS32R6) { + mask &=3D ~((1 << CP0Ca_WP) & val); + } + + env->CP0_Cause =3D (env->CP0_Cause & ~mask) | (val & mask); + + if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { + if (env->CP0_Cause & (1 << CP0Ca_DC)) { + cpu_mips_stop_count(env); + } else { + cpu_mips_start_count(env); + } + } + + /* Set/reset software interrupts */ + for (i =3D 0 ; i < 2 ; i++) { + if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { + cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i= ))); + } + } +} + +#endif /* !CONFIG_USER_ONLY */ + +static const char * const excp_names[EXCP_LAST + 1] =3D { + [EXCP_RESET] =3D "reset", + [EXCP_SRESET] =3D "soft reset", + [EXCP_DSS] =3D "debug single step", + [EXCP_DINT] =3D "debug interrupt", + [EXCP_NMI] =3D "non-maskable interrupt", + [EXCP_MCHECK] =3D "machine check", + [EXCP_EXT_INTERRUPT] =3D "interrupt", + [EXCP_DFWATCH] =3D "deferred watchpoint", + [EXCP_DIB] =3D "debug instruction breakpoint", + [EXCP_IWATCH] =3D "instruction fetch watchpoint", + [EXCP_AdEL] =3D "address error load", + [EXCP_AdES] =3D "address error store", + [EXCP_TLBF] =3D "TLB refill", + [EXCP_IBE] =3D "instruction bus error", + [EXCP_DBp] =3D "debug breakpoint", + [EXCP_SYSCALL] =3D "syscall", + [EXCP_BREAK] =3D "break", + [EXCP_CpU] =3D "coprocessor unusable", + [EXCP_RI] =3D "reserved instruction", + [EXCP_OVERFLOW] =3D "arithmetic overflow", + [EXCP_TRAP] =3D "trap", + [EXCP_FPE] =3D "floating point", + [EXCP_DDBS] =3D "debug data break store", + [EXCP_DWATCH] =3D "data watchpoint", + [EXCP_LTLBL] =3D "TLB modify", + [EXCP_TLBL] =3D "TLB load", + [EXCP_TLBS] =3D "TLB store", + [EXCP_DBE] =3D "data bus error", + [EXCP_DDBL] =3D "debug data break load", + [EXCP_THREAD] =3D "thread", + [EXCP_MDMX] =3D "MDMX", + [EXCP_C2E] =3D "precise coprocessor 2", + [EXCP_CACHE] =3D "cache error", + [EXCP_TLBXI] =3D "TLB execute-inhibit", + [EXCP_TLBRI] =3D "TLB read-inhibit", + [EXCP_MSADIS] =3D "MSA disabled", + [EXCP_MSAFPE] =3D "MSA floating point", +}; + +const char *mips_exception_name(int32_t exception) +{ + if (exception < 0 || exception > EXCP_LAST) { + return "unknown"; + } + return excp_names[exception]; +} + +void cpu_set_exception_base(int vp_index, target_ulong address) +{ + MIPSCPU *vp =3D MIPS_CPU(qemu_get_cpu(vp_index)); + vp->env.exception_base =3D address; +} + +target_ulong exception_resume_pc(CPUMIPSState *env) +{ + target_ulong bad_pc; + target_ulong isa_mode; + + isa_mode =3D !!(env->hflags & MIPS_HFLAG_M16); + bad_pc =3D env->active_tc.PC | isa_mode; + if (env->hflags & MIPS_HFLAG_BMASK) { + /* + * If the exception was raised from a delay slot, come back to + * the jump. + */ + bad_pc -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); + } + + return bad_pc; +} + +bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + if (interrupt_request & CPU_INTERRUPT_HARD) { + MIPSCPU *cpu =3D MIPS_CPU(cs); + CPUMIPSState *env =3D &cpu->env; + + if (cpu_mips_hw_interrupts_enabled(env) && + cpu_mips_hw_interrupts_pending(env)) { + /* Raise it */ + cs->exception_index =3D EXCP_EXT_INTERRUPT; + env->error_code =3D 0; + mips_cpu_do_interrupt(cs); + return true; + } + } + return false; +} + +void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, + uint32_t exception, + int error_code, + uintptr_t pc) +{ + CPUState *cs =3D env_cpu(env); + + qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n", + __func__, exception, mips_exception_name(exception), + error_code); + cs->exception_index =3D exception; + env->error_code =3D error_code; + + cpu_loop_exit_restore(cs, pc); +} + static void mips_cpu_set_pc(CPUState *cs, vaddr value) { MIPSCPU *cpu =3D MIPS_CPU(cs); @@ -591,9 +800,3 @@ bool cpu_type_supports_cps_smp(const char *cpu_type) const MIPSCPUClass *mcc =3D MIPS_CPU_CLASS(object_class_by_name(cpu_ty= pe)); return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) !=3D 0; } - -void cpu_set_exception_base(int vp_index, target_ulong address) -{ - MIPSCPU *vp =3D MIPS_CPU(qemu_get_cpu(vp_index)); - vp->env.exception_base =3D address; -} diff --git a/target/mips/helper.c b/target/mips/helper.c index 0692e232f0a..59787b870b8 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -357,105 +357,6 @@ void cpu_mips_tlb_flush(CPUMIPSState *env) env->tlb->tlb_in_use =3D env->tlb->nb_tlb; } =20 -/* Called for updates to CP0_Status. */ -void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) -{ - int32_t tcstatus, *tcst; - uint32_t v =3D cpu->CP0_Status; - uint32_t cu, mx, asid, ksu; - uint32_t mask =3D ((1 << CP0TCSt_TCU3) - | (1 << CP0TCSt_TCU2) - | (1 << CP0TCSt_TCU1) - | (1 << CP0TCSt_TCU0) - | (1 << CP0TCSt_TMX) - | (3 << CP0TCSt_TKSU) - | (0xff << CP0TCSt_TASID)); - - cu =3D (v >> CP0St_CU0) & 0xf; - mx =3D (v >> CP0St_MX) & 0x1; - ksu =3D (v >> CP0St_KSU) & 0x3; - asid =3D env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - - tcstatus =3D cu << CP0TCSt_TCU0; - tcstatus |=3D mx << CP0TCSt_TMX; - tcstatus |=3D ksu << CP0TCSt_TKSU; - tcstatus |=3D asid; - - if (tc =3D=3D cpu->current_tc) { - tcst =3D &cpu->active_tc.CP0_TCStatus; - } else { - tcst =3D &cpu->tcs[tc].CP0_TCStatus; - } - - *tcst &=3D ~mask; - *tcst |=3D tcstatus; - compute_hflags(cpu); -} - -void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) -{ - uint32_t mask =3D env->CP0_Status_rw_bitmask; - target_ulong old =3D env->CP0_Status; - - if (env->insn_flags & ISA_MIPS32R6) { - bool has_supervisor =3D extract32(mask, CP0St_KSU, 2) =3D=3D 0x3; -#if defined(TARGET_MIPS64) - uint32_t ksux =3D (1 << CP0St_KX) & val; - ksux |=3D (ksux >> 1) & val; /* KX =3D 0 forces SX to be 0 */ - ksux |=3D (ksux >> 1) & val; /* SX =3D 0 forces UX to be 0 */ - val =3D (val & ~(7 << CP0St_UX)) | ksux; -#endif - if (has_supervisor && extract32(val, CP0St_KSU, 2) =3D=3D 0x3) { - mask &=3D ~(3 << CP0St_KSU); - } - mask &=3D ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); - } - - env->CP0_Status =3D (old & ~mask) | (val & mask); -#if defined(TARGET_MIPS64) - if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { - /* Access to at least one of the 64-bit segments has been disabled= */ - tlb_flush(env_cpu(env)); - } -#endif - if (ase_mt_available(env)) { - sync_c0_status(env, env, env->current_tc); - } else { - compute_hflags(env); - } -} - -void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) -{ - uint32_t mask =3D 0x00C00300; - uint32_t old =3D env->CP0_Cause; - int i; - - if (env->insn_flags & ISA_MIPS32R2) { - mask |=3D 1 << CP0Ca_DC; - } - if (env->insn_flags & ISA_MIPS32R6) { - mask &=3D ~((1 << CP0Ca_WP) & val); - } - - env->CP0_Cause =3D (env->CP0_Cause & ~mask) | (val & mask); - - if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { - if (env->CP0_Cause & (1 << CP0Ca_DC)) { - cpu_mips_stop_count(env); - } else { - cpu_mips_start_count(env); - } - } - - /* Set/reset software interrupts */ - for (i =3D 0 ; i < 2 ; i++) { - if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { - cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i= ))); - } - } -} - #endif /* !CONFIG_USER_ONLY */ =20 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, @@ -977,75 +878,7 @@ hwaddr cpu_mips_translate_address(CPUMIPSState *env, t= arget_ulong address, return physical; } } -#endif /* !CONFIG_USER_ONLY */ =20 -static const char * const excp_names[EXCP_LAST + 1] =3D { - [EXCP_RESET] =3D "reset", - [EXCP_SRESET] =3D "soft reset", - [EXCP_DSS] =3D "debug single step", - [EXCP_DINT] =3D "debug interrupt", - [EXCP_NMI] =3D "non-maskable interrupt", - [EXCP_MCHECK] =3D "machine check", - [EXCP_EXT_INTERRUPT] =3D "interrupt", - [EXCP_DFWATCH] =3D "deferred watchpoint", - [EXCP_DIB] =3D "debug instruction breakpoint", - [EXCP_IWATCH] =3D "instruction fetch watchpoint", - [EXCP_AdEL] =3D "address error load", - [EXCP_AdES] =3D "address error store", - [EXCP_TLBF] =3D "TLB refill", - [EXCP_IBE] =3D "instruction bus error", - [EXCP_DBp] =3D "debug breakpoint", - [EXCP_SYSCALL] =3D "syscall", - [EXCP_BREAK] =3D "break", - [EXCP_CpU] =3D "coprocessor unusable", - [EXCP_RI] =3D "reserved instruction", - [EXCP_OVERFLOW] =3D "arithmetic overflow", - [EXCP_TRAP] =3D "trap", - [EXCP_FPE] =3D "floating point", - [EXCP_DDBS] =3D "debug data break store", - [EXCP_DWATCH] =3D "data watchpoint", - [EXCP_LTLBL] =3D "TLB modify", - [EXCP_TLBL] =3D "TLB load", - [EXCP_TLBS] =3D "TLB store", - [EXCP_DBE] =3D "data bus error", - [EXCP_DDBL] =3D "debug data break load", - [EXCP_THREAD] =3D "thread", - [EXCP_MDMX] =3D "MDMX", - [EXCP_C2E] =3D "precise coprocessor 2", - [EXCP_CACHE] =3D "cache error", - [EXCP_TLBXI] =3D "TLB execute-inhibit", - [EXCP_TLBRI] =3D "TLB read-inhibit", - [EXCP_MSADIS] =3D "MSA disabled", - [EXCP_MSAFPE] =3D "MSA floating point", -}; - -static const char *mips_exception_name(int32_t exception) -{ - if (exception < 0 || exception > EXCP_LAST) { - return "unknown"; - } - return excp_names[exception]; -} - -target_ulong exception_resume_pc(CPUMIPSState *env) -{ - target_ulong bad_pc; - target_ulong isa_mode; - - isa_mode =3D !!(env->hflags & MIPS_HFLAG_M16); - bad_pc =3D env->active_tc.PC | isa_mode; - if (env->hflags & MIPS_HFLAG_BMASK) { - /* - * If the exception was raised from a delay slot, come back to - * the jump. - */ - bad_pc -=3D (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); - } - - return bad_pc; -} - -#if !defined(CONFIG_USER_ONLY) static void set_hflags_for_handler(CPUMIPSState *env) { /* Exception handlers are entered in 32-bit mode. */ @@ -1400,24 +1233,6 @@ void mips_cpu_do_interrupt(CPUState *cs) cs->exception_index =3D EXCP_NONE; } =20 -bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - if (interrupt_request & CPU_INTERRUPT_HARD) { - MIPSCPU *cpu =3D MIPS_CPU(cs); - CPUMIPSState *env =3D &cpu->env; - - if (cpu_mips_hw_interrupts_enabled(env) && - cpu_mips_hw_interrupts_pending(env)) { - /* Raise it */ - cs->exception_index =3D EXCP_EXT_INTERRUPT; - env->error_code =3D 0; - mips_cpu_do_interrupt(cs); - return true; - } - } - return false; -} - #if !defined(CONFIG_USER_ONLY) void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra) { @@ -1484,19 +1299,3 @@ void r4k_invalidate_tlb(CPUMIPSState *env, int idx, = int use_extra) } } #endif /* !CONFIG_USER_ONLY */ - -void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, - uint32_t exception, - int error_code, - uintptr_t pc) -{ - CPUState *cs =3D env_cpu(env); - - qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n", - __func__, exception, mips_exception_name(exception), - error_code); - cs->exception_index =3D exception; - env->error_code =3D error_code; - - cpu_loop_exit_restore(cs, pc); -} --=20 2.26.2 From nobody Sun May 5 06:21:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.65 as permitted sender) client-ip=209.85.128.65; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f65.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.65 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1607971097; cv=none; d=zohomail.com; s=zohoarc; b=LZP3F3rQD8rjLTIhx3fqYeTrLxOCa9FXoGUK5JEI2/9z76s/kUKuQjNNPYLL7XOqd8zfVwPO7FxvEglAL6M+J0ebxGTWa0mg3/WlTLYHMFbdCwxVX3hhsrcCfQG9s4U4WCPQc/tYdwM5S5A9gL61+EGgr30yxFKaP22EUWoQFm4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607971097; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8LC7/cpbLmFmCpCdsWMBAZLA2elqMbfY/U5LRkkEQ4w=; b=Om9WMCLssBk5RFa1QX+CEQq62TsP4knVFTH13eBZK9d2ceG3dBjM3wnhVIBghUGahj2L59DxMdVGB9CukGbEA2Q2sIGAj7MNgAgkSjMbpaIxH0LsERz8Tl3owPFhlx0sFrOzDYn0m8bJhc6CMtYjjE2OZH+lH6eZwub6WJs0R5E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.65 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f65.google.com (mail-wm1-f65.google.com [209.85.128.65]) by mx.zohomail.com with SMTPS id 1607971097115176.15041234485886; Mon, 14 Dec 2020 10:38:17 -0800 (PST) Received: by mail-wm1-f65.google.com with SMTP id a3so16189478wmb.5 for ; Mon, 14 Dec 2020 10:38:15 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id v20sm31460263wml.34.2020.12.14.10.38.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:38:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8LC7/cpbLmFmCpCdsWMBAZLA2elqMbfY/U5LRkkEQ4w=; b=URmAnvrSw3+rmfGrZ+no4b5Lcrec0Kqp0lNe2JuQLRP1bILan3ppJpC/IQgdIxKs7Q +bmK30fxdvE58S0Y+OwPM2NwWrZ4n0TOwtfDJXZxIQOngo9u2a4EoKzUM775qmkjXWwE h63BP5nBBLU3zGcT/LFFQmV4Jk8O9Zvz2MJmEmycHnP/xdX3xAQyXXJPO+FemWhalK50 XcchaHG1hnu4sMNw8XAdQDRxgRhbiO+qjRzicNrFi2Uzl9R+qYHGKVXwduOcD+JYHLtL aBLjhH8t3ODfbEBG47jOTvxH1aURoBSwVWpDrtpB0tX58NLt+V7o4NJKj9YeEwRbgm7W coHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=8LC7/cpbLmFmCpCdsWMBAZLA2elqMbfY/U5LRkkEQ4w=; b=sIyuUnILmFHOYh1F54FvSw+iVoAwMvb5F0TDDwP+cqmJ3hkEq9gV7s4bDXDprvWfQq S6PANq6KxBlO+XCH/bsAa7kQOAhxdpKCt76HHaNC5M5xTSlDwV9C99V+vfDcJgIB6G5I j2uPoHmMbY0NPeKBUjrqWpW5FcECbDiTLUTkNL5RiGj3wwWB1jJSEKSCGEnUB/vfepdh k/XrdMhR7/MvrcTF6+cBlwKnFWE45VAEAMc7tkIO54D+7NIcoCgOAqm1JerWuzK160C7 zxxlQNRCuw9cOTz2z0KIb8y4h9y0GcdqGSMxHeJsm3UfAVwWFvMEA14G0ZR68jGWW7Jp NKnQ== X-Gm-Message-State: AOAM530Y7YBHL2B2tYq4tXAFNxA+nBbGFnu5ETyVGKMxX/wNr4ThNSSz BdfsZ3qOa9TdUhED4vWxMKg= X-Google-Smtp-Source: ABdhPJypoAc+0LLSY2eLKsIDkQhh04/COoZyQzQJoudCNtNC1CMePgXrJmRksR8sstCKXszd7R/AUA== X-Received: by 2002:a1c:7d88:: with SMTP id y130mr28665528wmc.158.1607971092851; Mon, 14 Dec 2020 10:38:12 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v2 06/16] target/mips: Rename helper.c as tlb_helper.c Date: Mon, 14 Dec 2020 19:37:29 +0100 Message-Id: <20201214183739.500368-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) This file contains functions related to TLB management, rename it as 'tlb_helper.c'. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-13-f4bug@amsat.org> --- target/mips/{helper.c =3D> tlb_helper.c} | 2 +- target/mips/meson.build | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) rename target/mips/{helper.c =3D> tlb_helper.c} (99%) diff --git a/target/mips/helper.c b/target/mips/tlb_helper.c similarity index 99% rename from target/mips/helper.c rename to target/mips/tlb_helper.c index 59787b870b8..2e52539a511 100644 --- a/target/mips/helper.c +++ b/target/mips/tlb_helper.c @@ -1,5 +1,5 @@ /* - * MIPS emulation helpers for qemu. + * MIPS TLB (Translation lookaside buffer) helpers. * * Copyright (c) 2004-2005 Jocelyn Mayer * diff --git a/target/mips/meson.build b/target/mips/meson.build index 4179395a8ea..5a49951c6d7 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -4,10 +4,10 @@ 'dsp_helper.c', 'fpu_helper.c', 'gdbstub.c', - 'helper.c', 'lmmi_helper.c', 'msa_helper.c', 'op_helper.c', + 'tlb_helper.c', 'translate.c', )) mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) --=20 2.26.2 From nobody Sun May 5 06:21:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.41 as permitted sender) client-ip=209.85.128.41; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f41.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1607971102; cv=none; d=zohomail.com; s=zohoarc; b=SFPDs7GHcZaKuJpL08oSh7cnzy0+650mH1AwFObMACWe1WSCT/ls5vksS5EfdFYN9OGBr5FjiUXeTG2G35fnlYl57PAOkGtC8LG+VTpfA9DkYNP0GJI10AXdLhIcROS8HFzNXIhwS6kxNRhvvxHNRhmWujea86Z7JGQo2nSQqzc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607971102; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1YHqfW9C9zJMYC4AZlw/rgEaF/1fbEs/5bZEvXJxOms=; b=OQBnoEISILLrYJMWaqH4RJO24lrcKLVqPxX6+Du4L5DCoEnoJ13jZEIzgZ6uDPo/gjnj05cFvCdzoOaj3btGyq8iNFZKOsSIyaTQ7kBMQxW809BrMTrlLL+9bLUodaI1NNG/oSLh4rIYw7+YCEO+n/eUg5mYXfebAleQTXl4O2g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) by mx.zohomail.com with SMTPS id 1607971102362201.15484849346853; Mon, 14 Dec 2020 10:38:22 -0800 (PST) Received: by mail-wm1-f41.google.com with SMTP id 3so16187326wmg.4 for ; Mon, 14 Dec 2020 10:38:19 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id j10sm15660953wmj.7.2020.12.14.10.38.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:38:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1YHqfW9C9zJMYC4AZlw/rgEaF/1fbEs/5bZEvXJxOms=; b=NFZKb47HS15qKB3UYMr+dzqvtDKW4LVGYn53nUuezRuuuZx0/i+K9MpNxIaDZQkfD7 o9XG0NfiKVZAZCviwFql8IBz5V4qlv3xKF/AnfImdPOU6cg0sw22R45IkKZIvOk9e2+x PsTMXsFYEasWyTX7FJOX2/8Ef0nf99oADa8+d9c8v4C+jhIYCVUIRnZLAlcCuFTrMpSr LKGQWD57apC7qhn+WBRbcQmORjXvXY24jm/Ism+alV6z5uRJ5mPICo+nle0BD2vlJy+c bW+0hx1pyfIY/rHS3Iib1Q4H47kvRSp5Pe+4fW/qHfF04v++9DU4Mw4eH64by8e+PUXF X1Bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=1YHqfW9C9zJMYC4AZlw/rgEaF/1fbEs/5bZEvXJxOms=; b=WIw18YVrYiKMuy9W/0S5LW/mtk8J0C2x3H28xG4WfKDIlVnhXNGidG9h3w9qMJ3ZeZ JGCuqMEn8Nc7cX3whNkNvLcXowBlBqKpoX7fVkVWXMtTCzjnTxPSbrVWVsbub9frJHsf M/ylGs7PsffXayf3xuYzpfwO3/Heg4HzXbWZpu/DB7ddhYC5nIKJepWbiPC/8WB4KYK9 acp7Y4xgyJrGdGOak6tanb9MCXdlFmPpJlD4qzcxFh2yPrPVBQkT/4dh05BeZmnqt7Wf eYWc9PZUfay1c+Gbp6pNZgeND+7krmiEcP/0ZE90NzGD6uCdJaWf5sNcWJ0xuOF2aLy1 1Cvw== X-Gm-Message-State: AOAM531tDBpORrqtQv7bp4mnEAfZnBy+TswoYDe6sZUkOpAwtm8IrPn1 SvVdWDC4zNQ9DEUv//yXWso= X-Google-Smtp-Source: ABdhPJxwtUczlKopDRSmG1EyYSoU0DtPkmTvGdqnbZDV9LhACCcRBx2qy8ZipUeryy41Sg/B180lGQ== X-Received: by 2002:a1c:790f:: with SMTP id l15mr29516909wme.188.1607971097824; Mon, 14 Dec 2020 10:38:17 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v2 07/16] target/mips: Fix code style for checkpatch.pl Date: Mon, 14 Dec 2020 19:37:30 +0100 Message-Id: <20201214183739.500368-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We are going to move this code, fix its style first. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-14-f4bug@amsat.org> --- target/mips/translate_init.c.inc | 36 ++++++++++++++++---------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.= c.inc index 915277dd1f6..ff14502529b 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -934,19 +934,19 @@ void mips_cpu_list(void) } =20 #ifndef CONFIG_USER_ONLY -static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def) +static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def) { env->tlb->nb_tlb =3D 1; env->tlb->map_address =3D &no_mmu_map_address; } =20 -static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def) +static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def) { env->tlb->nb_tlb =3D 1; env->tlb->map_address =3D &fixed_mmu_map_address; } =20 -static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) +static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def) { env->tlb->nb_tlb =3D 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); env->tlb->map_address =3D &r4k_map_address; @@ -958,25 +958,25 @@ static void r4k_mmu_init (CPUMIPSState *env, const mi= ps_def_t *def) env->tlb->helper_tlbinvf =3D r4k_helper_tlbinvf; } =20 -static void mmu_init (CPUMIPSState *env, const mips_def_t *def) +static void mmu_init(CPUMIPSState *env, const mips_def_t *def) { env->tlb =3D g_malloc0(sizeof(CPUMIPSTLBContext)); =20 switch (def->mmu_type) { - case MMU_TYPE_NONE: - no_mmu_init(env, def); - break; - case MMU_TYPE_R4000: - r4k_mmu_init(env, def); - break; - case MMU_TYPE_FMT: - fixed_mmu_init(env, def); - break; - case MMU_TYPE_R3000: - case MMU_TYPE_R6000: - case MMU_TYPE_R8000: - default: - cpu_abort(env_cpu(env), "MMU type not supported\n"); + case MMU_TYPE_NONE: + no_mmu_init(env, def); + break; + case MMU_TYPE_R4000: + r4k_mmu_init(env, def); + break; + case MMU_TYPE_FMT: + fixed_mmu_init(env, def); + break; + case MMU_TYPE_R3000: + case MMU_TYPE_R6000: + case MMU_TYPE_R8000: + default: + cpu_abort(env_cpu(env), "MMU type not supported\n"); } } #endif /* CONFIG_USER_ONLY */ --=20 2.26.2 From nobody Sun May 5 06:21:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) client-ip=209.85.221.41; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f41.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1607971104; cv=none; d=zohomail.com; s=zohoarc; b=fNcFW6EP97/nIiXVtypD4I2F0OQQdR5c5vV+HVc2l1YiKC3UmyDi5zAklP5Agh48CSQssxTqzxL2uJxbRVa+/ii6IXdKXn4o9vm9NEpOgBX+1g9ptGwp7I4rJjNKyDBw8E2yo3/4c6M6yUy0SBVgTxW6UzPNvad3JP6IGkR2L1U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607971104; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Pxw5yz+fseWQ/dQcwxqgNwkSctI6l6EW+pu9mjED4a0=; b=k0nTgzQmCmRh50Obz9On6LI7PdBLq1aKdWr9OiRj4TVrOnlBkxCZfMwFuQUI/bpkR+emR967Gic4aZufiKTwvzS4LZxgvtZSyPlF668LucuH8wRF+rto1ftd9iHK/Rzo9N+2wTNBBCA8y4kLX+doj1tl7ZDadzqXysRAO8Newdk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) by mx.zohomail.com with SMTPS id 160797110493171.89804756253261; Mon, 14 Dec 2020 10:38:24 -0800 (PST) Received: by mail-wr1-f41.google.com with SMTP id a11so9707089wrr.13 for ; Mon, 14 Dec 2020 10:38:24 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id e16sm36965915wra.94.2020.12.14.10.38.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:38:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Pxw5yz+fseWQ/dQcwxqgNwkSctI6l6EW+pu9mjED4a0=; b=eG+rZt31DsZsT8XFwZ5zWXKppwa4lzEcEGnNBXebed7vDj4MxqtXSGUsR4eixHW6pm F3ExTzKgY2hVmLcA3Y/+M+pFCCt38W0keXX9wK3Cv3DL94W5Dl+wZkmAM6Q5BYHeC/uq Fw6kUyCzIjcIHR/cjpLO/lBUgMhkO1nTIP/lLf6fINpRKhD1j8odvqEWMT7oO2HPQhWz Y58qS5FvhifFEjWdVGKBIKj8m+/ZChqwnfdRFnXrmdxB+oOvoIuc3J56FVZjwifkdqXQ F2ysxu2Xu+2pRtQQC+DEtw5Mvrl4Tr7Km/4Aal9bAH4Hky2pwOiCzdCS84N6KiU5q0BD NKzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Pxw5yz+fseWQ/dQcwxqgNwkSctI6l6EW+pu9mjED4a0=; b=MCbwmfh3M7AVg0XcoYklshYS/DLAiy37h0b2vlthCyAkSCEkm2Su2lcfCYCc16gjsf nNKNL/hasqDj1zVSCbuM+cB6HumPaioo2yeyoodr6VV0zXO0XVH38sUWtO19GzaJ6b/c Jmow9owlNn9LF2VVf8ssFT2JhxoQmJX/YDDejJC25uUNLDysbEq7gJSZwUUhRg3vUPm6 xdj4v7yVYzd/P/BcMIOTeZsukLuYiAqi09WL0ABj62Ik5jnJXSbDl9CVkUwv5ApvjlC3 THCvKq/r8SgZkLhc8S5GMpJrQr7B6LczrfuGp3AilWzn4tMYGNGbEY9+u9WC2e20OWsJ erWQ== X-Gm-Message-State: AOAM530z95bguYVBdiXouB6DWTp9mq2wjzHz/sGSyLvSv08TicZk5jZ4 j+rP6HeH2e1kcuZQV6s8Ij8= X-Google-Smtp-Source: ABdhPJziMYXAnUWCqbPBIaNucXK2KRgqogVbVQ+OduRyvXOkAxSuRmEn6ZfGwHWYFMs9FiPSOATzPg== X-Received: by 2002:a5d:43c3:: with SMTP id v3mr6016210wrr.184.1607971102985; Mon, 14 Dec 2020 10:38:22 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v2 08/16] target/mips: Move mmu_init() functions to tlb_helper.c Date: Mon, 14 Dec 2020 19:37:31 +0100 Message-Id: <20201214183739.500368-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-15-f4bug@amsat.org> --- target/mips/internal.h | 1 + target/mips/tlb_helper.c | 46 ++++++++++++++++++++++++++++++ target/mips/translate_init.c.inc | 48 -------------------------------- 3 files changed, 47 insertions(+), 48 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index c1401492c46..968a3a8db8f 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -207,6 +207,7 @@ void cpu_mips_start_count(CPUMIPSState *env); void cpu_mips_stop_count(CPUMIPSState *env); =20 /* helper.c */ +void mmu_init(CPUMIPSState *env, const mips_def_t *def); bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c index 2e52539a511..94a482e3dbe 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tlb_helper.c @@ -120,6 +120,52 @@ int r4k_map_address(CPUMIPSState *env, hwaddr *physica= l, int *prot, return TLBRET_NOMATCH; } =20 +static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def) +{ + env->tlb->nb_tlb =3D 1; + env->tlb->map_address =3D &no_mmu_map_address; +} + +static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def) +{ + env->tlb->nb_tlb =3D 1; + env->tlb->map_address =3D &fixed_mmu_map_address; +} + +static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def) +{ + env->tlb->nb_tlb =3D 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); + env->tlb->map_address =3D &r4k_map_address; + env->tlb->helper_tlbwi =3D r4k_helper_tlbwi; + env->tlb->helper_tlbwr =3D r4k_helper_tlbwr; + env->tlb->helper_tlbp =3D r4k_helper_tlbp; + env->tlb->helper_tlbr =3D r4k_helper_tlbr; + env->tlb->helper_tlbinv =3D r4k_helper_tlbinv; + env->tlb->helper_tlbinvf =3D r4k_helper_tlbinvf; +} + +void mmu_init(CPUMIPSState *env, const mips_def_t *def) +{ + env->tlb =3D g_malloc0(sizeof(CPUMIPSTLBContext)); + + switch (def->mmu_type) { + case MMU_TYPE_NONE: + no_mmu_init(env, def); + break; + case MMU_TYPE_R4000: + r4k_mmu_init(env, def); + break; + case MMU_TYPE_FMT: + fixed_mmu_init(env, def); + break; + case MMU_TYPE_R3000: + case MMU_TYPE_R6000: + case MMU_TYPE_R8000: + default: + cpu_abort(env_cpu(env), "MMU type not supported\n"); + } +} + static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx) { /* diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.= c.inc index ff14502529b..a788f5a6b6d 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -933,54 +933,6 @@ void mips_cpu_list(void) } } =20 -#ifndef CONFIG_USER_ONLY -static void no_mmu_init(CPUMIPSState *env, const mips_def_t *def) -{ - env->tlb->nb_tlb =3D 1; - env->tlb->map_address =3D &no_mmu_map_address; -} - -static void fixed_mmu_init(CPUMIPSState *env, const mips_def_t *def) -{ - env->tlb->nb_tlb =3D 1; - env->tlb->map_address =3D &fixed_mmu_map_address; -} - -static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def) -{ - env->tlb->nb_tlb =3D 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); - env->tlb->map_address =3D &r4k_map_address; - env->tlb->helper_tlbwi =3D r4k_helper_tlbwi; - env->tlb->helper_tlbwr =3D r4k_helper_tlbwr; - env->tlb->helper_tlbp =3D r4k_helper_tlbp; - env->tlb->helper_tlbr =3D r4k_helper_tlbr; - env->tlb->helper_tlbinv =3D r4k_helper_tlbinv; - env->tlb->helper_tlbinvf =3D r4k_helper_tlbinvf; -} - -static void mmu_init(CPUMIPSState *env, const mips_def_t *def) -{ - env->tlb =3D g_malloc0(sizeof(CPUMIPSTLBContext)); - - switch (def->mmu_type) { - case MMU_TYPE_NONE: - no_mmu_init(env, def); - break; - case MMU_TYPE_R4000: - r4k_mmu_init(env, def); - break; - case MMU_TYPE_FMT: - fixed_mmu_init(env, def); - break; - case MMU_TYPE_R3000: - case MMU_TYPE_R6000: - case MMU_TYPE_R8000: - default: - cpu_abort(env_cpu(env), "MMU type not supported\n"); - } -} -#endif /* CONFIG_USER_ONLY */ - static void fpu_init (CPUMIPSState *env, const mips_def_t *def) { int i; --=20 2.26.2 From nobody Sun May 5 06:21:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) client-ip=209.85.128.43; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f43.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1607971110; cv=none; d=zohomail.com; s=zohoarc; b=cAEdCKKmkAFPDEoYSrtF/wO98v03h6hz2Z8oarFNEFgIRObzVR/5l6VrjODto7cp3R8zQJa7QqXW5/SChnFYe5Vfh2hDHctJyrxr/7A6iR3kWitNHFCzDP4p9OjnnuSZX7Q+vj0YunQxGuC+JaMOBFxr3VCdKshWfpmuZoFcVrw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607971110; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=klGFn3hgbo3GHDfsgMyJiiPYSrCAsjHYiV/EbjhfoW8=; b=XXeIyTJhlAtF1eLCjG3twqOi2SjlZOTLe7dAJ/t2jRo2CGCNAklAki1julchUSk+GAml9Fn81CcbsakMjC/Z2O+oOQbShfQXT14JbI9svXcsRT+A9gbJQQTF1sxt1IpSA1wCGh4dnKc9wZx7c37zHRmsiqVdUBu2ysg0x12RnYY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) by mx.zohomail.com with SMTPS id 1607971110064862.2637550021628; Mon, 14 Dec 2020 10:38:30 -0800 (PST) Received: by mail-wm1-f43.google.com with SMTP id k10so14690005wmi.3 for ; Mon, 14 Dec 2020 10:38:29 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id i7sm20396778wrv.12.2020.12.14.10.38.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:38:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=klGFn3hgbo3GHDfsgMyJiiPYSrCAsjHYiV/EbjhfoW8=; b=CfuHL44otRpfSJlVrA7fEOVv4k4CUkmVu9LTTPz4deOlBK0C1oHElDzWpSNIEhhUyK wzOP+WTWzwTB673iXjSOqxnHXT5Za5YADguwGPDlnRZuNDxhPz6YzoDGFFSFj0Owt37P 2qvgbzypxffE7Gj6OKAb3NPTTfJf/zU+ndpApB+teYdeN/erVCGlN2FwyPB7mIxodBTq 2qsUk9KbW3SHhfyB87dKQwU8YTsYnhC7DL6xMTpQ4Dv1i34VYT/5MUBa2j1ntNmxJSCW diR5/uSlHzp7lrKTC4xMbZj7tlhrFaBv22Vt8Ju1RiPxLVHWFElxIddUZI7flxOWocEt HSTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=klGFn3hgbo3GHDfsgMyJiiPYSrCAsjHYiV/EbjhfoW8=; b=ggv9sy0okphdkU1JwzquGJ4SFPJ8dUX1T9DXInWyaNqOZGhu9oRn7p/xw248tJ6vmu qsuJ5w11+GBeYCncxS1qfCCnbmBIVtm94vgkBAMO8s5cfz5es0pnaKHnurW2p+af+ffa DpyTxdxTAotu3kJQx1cIC+kw/EBSaJkRN0hxatZrzo9+PyDuMaH2UKoK3ZJIYS0IouXR yI4QUfATuR4c0grhOrC8dIOIusjWA/FRMc+9QxyWSHAKuzD7d3+o7yI1A3TWNh9R0Lq8 mKfJbopY1ljQ0nPtVV4NW+Dee9Qfqh0ng+owwZc/QKFsYNpakfsNY2p/21kxilLhChLL vKLQ== X-Gm-Message-State: AOAM533OcwTtyQRl29U47gUy/Q46gtbSCdul9+XcBpYfc5G1RQenNQaG VVebD1iR0d60nIi4l8Dapfs= X-Google-Smtp-Source: ABdhPJwTylQrlnQiAcKtSTABN0Cyubl7ydCIKMOBhBiDuRoYFl1iO9R9G02tB86I99Zq8ufgPtmWqg== X-Received: by 2002:a7b:c208:: with SMTP id x8mr29319888wmi.179.1607971107920; Mon, 14 Dec 2020 10:38:27 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 09/16] target/mips: Rename translate_init.c as cpu-defs.c Date: Mon, 14 Dec 2020 19:37:32 +0100 Message-Id: <20201214183739.500368-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) This file is not TCG specific, contains CPU definitions and is consumed by cpu.c. Rename it as such. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/cpu.c | 2 +- target/mips/{translate_init.c.inc =3D> cpu-defs.c.inc} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename target/mips/{translate_init.c.inc =3D> cpu-defs.c.inc} (100%) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index a54be034a2b..4191c0741f4 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -311,7 +311,7 @@ static bool mips_cpu_has_work(CPUState *cs) return has_work; } =20 -#include "translate_init.c.inc" +#include "cpu-defs.c.inc" =20 static void mips_cpu_reset(DeviceState *dev) { diff --git a/target/mips/translate_init.c.inc b/target/mips/cpu-defs.c.inc similarity index 100% rename from target/mips/translate_init.c.inc rename to target/mips/cpu-defs.c.inc --=20 2.26.2 From nobody Sun May 5 06:21:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.65 as permitted sender) client-ip=209.85.221.65; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f65.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.65 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1607971116; cv=none; d=zohomail.com; s=zohoarc; b=huK3jqYPViUZEmbSM3MsTE1O12Ug8sfY9RXavGkbWKEyQ+eeRKw1uUfIYE8rvUlgrW+wN3bwbQme9+JYJKs0WhhztRlVPEn7beDn38rvyKB5opdi9fcAt/IKhHikKV50LKwd2VT/9HJYOxmmWKzBSC15b4TfDoIKLJUraNnkqvM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607971116; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LfYo5MaDY/iw8/2Abe7qf6wWPlyXVqcAmraXknKsAuI=; b=HQjExuuZEReoGRK3WeA5sDL/AHCLyGJogvFdTnQ8Nffz0t7vDg3pGz9O7ds6krLbJomvDW0aTmwtTVM+xKpaQzAUCUhAe7uRsPou3rrRn1DDaRxadmiI+6DfDN8/zby2H0DKhw7ve6afj/pFjFTFKOroAq6jJnOS5fB25+AeWNk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.65 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f65.google.com (mail-wr1-f65.google.com [209.85.221.65]) by mx.zohomail.com with SMTPS id 1607971116075281.20347015471657; Mon, 14 Dec 2020 10:38:36 -0800 (PST) Received: by mail-wr1-f65.google.com with SMTP id i9so17460525wrc.4 for ; Mon, 14 Dec 2020 10:38:34 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id o7sm16373552wrw.62.2020.12.14.10.38.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:38:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LfYo5MaDY/iw8/2Abe7qf6wWPlyXVqcAmraXknKsAuI=; b=cDfL6rFJmoXL5vtpNF/4gnVblMRdchArkhxPQyCm3J2TZeP57Jcvrf5TIbIrVGIUeT 35nGhFPTcFlGqxFusVNpIQlEjtGgbkvzQIr+L9MnVklUn/V5secx8J6xPA5GHYOY5qna nFlJwbfJ51llCxurlCT8mDUQkPXNIBZuW7Qpa4O1304oeGInFXN5/C6MmL5myfYLE4WJ mGjVrgqzk0p6Jin1wWS95Wbq7VGZVjmsNQKunn2SmQdefd5mIluNkKGBoEaQOVNJlXY1 UvxRg5mRSj2T1apqPMkD46FISkHhgdZY2lI54fRnk9jU6IpjeUZ7jCpcgGOq5nO79xbg nyag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=LfYo5MaDY/iw8/2Abe7qf6wWPlyXVqcAmraXknKsAuI=; b=ocb4CbUNA0puvg5l7qumh9c4gqn6v1Y80lUOCR2LF9HhGZMnggr0/BkP5vwYqc7Bk9 D/yZx9xQMgaCwqP3QtAHreDTs7MvYDUhQZ1BbjBX8zNX7N1jgD7z2DlXAA1uCQBN/0Qr YjU8JcBjWYNvTsqklQIZxcv0R+NOYgcSHKXUt9c0QDMFoP42eHTu+6MjokkjhB9HsLcW pR3Wh28ekdWCIH1GC3B98tfK8R4x7WiKVQ/c6TM4U04wgrsEk4PohN0IwO+xbwaHzAwi 8qxy3xKd7nSL4ftHZIvnT6qbFwHaCT5Azkd1jfx2zCqBPdsPrESRuOKj3Wd6Wq3owVNi E8qQ== X-Gm-Message-State: AOAM532DiIaKbqyaP3WISpSVDe2vcXxv6CdJoaSoRgH9CiRlKWEsDtDE bx6VTmEEmKdriXGgCALwEkY= X-Google-Smtp-Source: ABdhPJxPEIZTvdb4fQSO7SAH8bxWAMxU5T9x6Cy3p1ighhXZQ87LEqC4RFNJudb1413UkAGHmoxApA== X-Received: by 2002:a5d:61c4:: with SMTP id q4mr30479856wrv.304.1607971113318; Mon, 14 Dec 2020 10:38:33 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 10/16] target/mips: Replace gen_exception_err(err=0) by gen_exception_end() Date: Mon, 14 Dec 2020 19:37:33 +0100 Message-Id: <20201214183739.500368-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) generate_exception_err(err=3D0) is simply generate_exception_end(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/translate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index d2614796214..2662cf26fe7 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2956,7 +2956,7 @@ static inline void gen_move_high32(TCGv ret, TCGv_i64= arg) static inline void check_cp0_enabled(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) { - generate_exception_err(ctx, EXCP_CpU, 0); + generate_exception_end(ctx, EXCP_CpU); } } =20 @@ -3162,10 +3162,10 @@ static inline void check_mt(DisasContext *ctx) static inline void check_cp0_mt(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) { - generate_exception_err(ctx, EXCP_CpU, 0); + generate_exception_end(ctx, EXCP_CpU); } else { if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) { - generate_exception_err(ctx, EXCP_RI, 0); + generate_exception_end(ctx, EXCP_RI); } } } --=20 2.26.2 From nobody Sun May 5 06:21:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.48 as permitted sender) client-ip=209.85.128.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1607971121; cv=none; d=zohomail.com; s=zohoarc; b=djrRo+JS7GvkhGZXrGEUw4l9VPQYhqgcZpUaDkMOsmuLLF8SQtiftqkVTwPzU39m0jlG/kQ4Rh6InCkE1vY7pU0FTA4aQ0lreI4+MQK5bbjW0gMO9LCuEPYYYCjF9bHMhgbWs/5oh2ykkO0Hay5QO0GZYOtxw5s3haq315Ehztk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607971121; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zOZe2uFU6BqfO8jeL11G69ZcASFHm/sscpUhCkf7gHM=; b=DGX3C98KmKyIzTaYXYB24JC+mBJVKEkpSLCMq4eqRlsjRLVtX1TFG6Lbu343MBQ7v+erCfD78vaWPPMYN3kh6YChNujzNX25dIop9EOumv28P3qb6mfrz95HicftLcVbumyf3Ftz0Yk87Nw0gYoo0U0HDghnsW7H8xrdSKhl358= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) by mx.zohomail.com with SMTPS id 1607971121617727.8216769046156; Mon, 14 Dec 2020 10:38:41 -0800 (PST) Received: by mail-wm1-f48.google.com with SMTP id y23so16217850wmi.1 for ; Mon, 14 Dec 2020 10:38:40 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id s63sm35837608wms.18.2020.12.14.10.38.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:38:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zOZe2uFU6BqfO8jeL11G69ZcASFHm/sscpUhCkf7gHM=; b=iXHrVljB7AwPb77aDQJHecHkrRjLpBZGTDdQJW68Ex4ApdRKZ6PAkHTpCgdK44DCGP XW7QLQLROlblzc2RY77M57YHzuv/ZC9cgLbVERK+uoSuZe1XmtLNpY2wvUGpDVu0WiL9 /9hqjyH7BjWnqEs+d1r8bgh3Hejqj+9E5pw8gcVzalhZitnNCInYrT1pxPdhEu1tTNhq zMdejDBlWhwvfypuyVz8Q5vNR0v7901Dj/XSNbUe3NNf7hwe0iqpJK2fvkvscaBSyEiy VmGiK4Z4JGnHTngcq9MGv4aUQr/pGl3VcfN9j50qGqk98CDfQIUD9ztxN8JQcjRNuovC /Nsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=zOZe2uFU6BqfO8jeL11G69ZcASFHm/sscpUhCkf7gHM=; b=i0Jv0pnlPWWJUJnr12lIxqSgrToFtg13uB1IjVqXdpatmC75kTH7c92GVxnxLoBFkz 8eO9sEgphei8UqLJz8rJUadyYoXgTH6LkiQ6I388oQoa/JHQ6HsQZa2K8tl8nra8IuVa S/E2WIWRQXHTJb7ogVimoakOs2sE+Cye9OOuEqUfx7J3SFFnQ3ZIUfqApLh7iNnNNr/8 hUL8LFDl2rRPXhq58jlssBAuxEMumVkXmnhlgpZ1rBWv5nex1+K2DiE0Pt0N04v6Bw6U aemF6fuHdPRQJ+3sVUjQxiZyilN5O19RwD1WhK/ZwLMsTR82m4FlmXK2tBAZyvtLCS2P MmSQ== X-Gm-Message-State: AOAM530uhjwqECC/46gmy20EgG1Q/D5i6a3LVyxaiC263wf2BT7/1eki owp9KkNkILdVf8L+I4oHwnk= X-Google-Smtp-Source: ABdhPJyXfJHofcrL/CKLHe0k/7UrymMY7gtmRigbbtHLfPsb06EDNz6XIhrkPE97Oop5Fxz/J4Hqrg== X-Received: by 2002:a1c:741a:: with SMTP id p26mr30189208wmc.47.1607971118535; Mon, 14 Dec 2020 10:38:38 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 11/16] target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction Date: Mon, 14 Dec 2020 19:37:34 +0100 Message-Id: <20201214183739.500368-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) gen_reserved_instruction() is easier to read than generate_exception_end(ctx, EXCP_RI), replace it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/translate.c | 724 ++++++++++++++++++++-------------------- 1 file changed, 362 insertions(+), 362 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 2662cf26fe7..49570a95615 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2975,7 +2975,7 @@ static inline void check_cp1_enabled(DisasContext *ct= x) static inline void check_cop1x(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } =20 @@ -2986,7 +2986,7 @@ static inline void check_cop1x(DisasContext *ctx) static inline void check_cp1_64bitmode(DisasContext *ctx) { if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } =20 @@ -3004,7 +3004,7 @@ static inline void check_cp1_64bitmode(DisasContext *= ctx) static inline void check_cp1_registers(DisasContext *ctx, int regs) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } =20 @@ -3018,7 +3018,7 @@ static inline void check_dsp(DisasContext *ctx) if (ctx->insn_flags & ASE_DSP) { generate_exception_end(ctx, EXCP_DSPDIS); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } } @@ -3029,7 +3029,7 @@ static inline void check_dsp_r2(DisasContext *ctx) if (ctx->insn_flags & ASE_DSP) { generate_exception_end(ctx, EXCP_DSPDIS); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } } @@ -3040,7 +3040,7 @@ static inline void check_dsp_r3(DisasContext *ctx) if (ctx->insn_flags & ASE_DSP) { generate_exception_end(ctx, EXCP_DSPDIS); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } } @@ -3052,7 +3052,7 @@ static inline void check_dsp_r3(DisasContext *ctx) static inline void check_insn(DisasContext *ctx, uint64_t flags) { if (unlikely(!(ctx->insn_flags & flags))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } =20 @@ -3064,7 +3064,7 @@ static inline void check_insn(DisasContext *ctx, uint= 64_t flags) static inline void check_insn_opc_removed(DisasContext *ctx, uint64_t flag= s) { if (unlikely(ctx->insn_flags & flags)) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } =20 @@ -3103,7 +3103,7 @@ static inline void check_ps(DisasContext *ctx) static inline void check_mips_64(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } #endif @@ -3124,7 +3124,7 @@ static inline void check_mvh(DisasContext *ctx) static inline void check_xnp(DisasContext *ctx) { if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_XNP))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } =20 @@ -3136,7 +3136,7 @@ static inline void check_xnp(DisasContext *ctx) static inline void check_pw(DisasContext *ctx) { if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_PW)))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } #endif @@ -3148,7 +3148,7 @@ static inline void check_pw(DisasContext *ctx) static inline void check_mt(DisasContext *ctx) { if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } =20 @@ -3165,7 +3165,7 @@ static inline void check_cp0_mt(DisasContext *ctx) generate_exception_end(ctx, EXCP_CpU); } else { if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } } @@ -3178,7 +3178,7 @@ static inline void check_cp0_mt(DisasContext *ctx) static inline void check_nms(DisasContext *ctx) { if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } =20 @@ -3195,7 +3195,7 @@ static inline void check_nms_dl_il_sl_tl_l2c(DisasCon= text *ctx) !(ctx->CP0_Config2 & (1 << CP0C2_SL)) && !(ctx->CP0_Config2 & (1 << CP0C2_TL)) && !(ctx->CP0_Config5 & (1 << CP0C5_L2C)))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } =20 @@ -3206,7 +3206,7 @@ static inline void check_nms_dl_il_sl_tl_l2c(DisasCon= text *ctx) static inline void check_eva(DisasContext *ctx) { if (unlikely(!(ctx->CP0_Config5 & (1 << CP0C5_EVA)))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } =20 @@ -3872,7 +3872,7 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t = opc, int ft, break; default: MIPS_INVAL("flt_ldst"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -4521,7 +4521,7 @@ static void gen_HILO1_tx79(DisasContext *ctx, uint32_= t opc, int reg) break; default: MIPS_INVAL("mfthilo1 TX79"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -4656,7 +4656,7 @@ static inline void gen_pcrel(DisasContext *ctx, int o= pc, target_ulong pc, #endif default: MIPS_INVAL("OPC_PCREL"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -4867,7 +4867,7 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,= int rd, int rs, int rt) #endif default: MIPS_INVAL("r6 mul/div"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } out: @@ -4925,7 +4925,7 @@ static void gen_div1_tx79(DisasContext *ctx, uint32_t= opc, int rs, int rt) break; default: MIPS_INVAL("div1 TX79"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } out: @@ -5118,7 +5118,7 @@ static void gen_muldiv(DisasContext *ctx, uint32_t op= c, break; default: MIPS_INVAL("mul/div"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } out: @@ -5249,7 +5249,7 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t = opc, break; default: MIPS_INVAL("mul/madd TXx9"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } =20 @@ -5312,7 +5312,7 @@ static void gen_mul_vr54xx(DisasContext *ctx, uint32_= t opc, break; default: MIPS_INVAL("mul vr54xx"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } gen_store_gpr(t0, rd); @@ -5938,7 +5938,7 @@ static void gen_loongson_multimedia(DisasContext *ctx= , int rd, int rs, int rt) break; default: MIPS_INVAL("loongson_cp2"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } =20 @@ -6127,7 +6127,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, #endif default: MIPS_INVAL("loongson_gsshfl"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -6175,13 +6175,13 @@ static void gen_loongson_lswc2(DisasContext *ctx, i= nt rt, #endif default: MIPS_INVAL("loongson_gsshfs"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; default: MIPS_INVAL("loongson_gslsq"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } tcg_temp_free(t0); @@ -6230,7 +6230,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int= rt, break; default: MIPS_INVAL("loongson_lsdc2"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; break; } @@ -6486,7 +6486,7 @@ static void gen_compute_branch(DisasContext *ctx, uin= t32_t opc, LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx "\n", ctx->base.pc_next); #endif - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } =20 @@ -6549,14 +6549,14 @@ static void gen_compute_branch(DisasContext *ctx, u= int32_t opc, * others are reserved. */ MIPS_INVAL("jump hint"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } gen_load_gpr(btarget, rs); break; default: MIPS_INVAL("branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } if (bcond_compute =3D=3D 0) { @@ -6621,7 +6621,7 @@ static void gen_compute_branch(DisasContext *ctx, uin= t32_t opc, break; default: MIPS_INVAL("branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } } else { @@ -6692,7 +6692,7 @@ static void gen_compute_branch(DisasContext *ctx, uin= t32_t opc, break; default: MIPS_INVAL("conditional branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } } @@ -6769,14 +6769,14 @@ static void gen_compute_branch_nm(DisasContext *ctx= , uint32_t opc, * others are reserved. */ MIPS_INVAL("jump hint"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } gen_load_gpr(btarget, rs); break; default: MIPS_INVAL("branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } if (bcond_compute =3D=3D 0) { @@ -6809,7 +6809,7 @@ static void gen_compute_branch_nm(DisasContext *ctx, = uint32_t opc, break; default: MIPS_INVAL("branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } } else { @@ -6832,7 +6832,7 @@ static void gen_compute_branch_nm(DisasContext *ctx, = uint32_t opc, break; default: MIPS_INVAL("conditional branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } } @@ -6912,7 +6912,7 @@ static void gen_bitops(DisasContext *ctx, uint32_t op= c, int rt, default: fail: MIPS_INVAL("bitops"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); tcg_temp_free(t0); tcg_temp_free(t1); return; @@ -6990,7 +6990,7 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2= , int rt, int rd) #endif default: MIPS_INVAL("bsfhl"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); tcg_temp_free(t0); return; } @@ -10644,7 +10644,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContex= t *ctx, int rt, int rd, die: tcg_temp_free(t0); LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } =20 static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, @@ -10854,7 +10854,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContex= t *ctx, int rd, int rt, die: tcg_temp_free(t0); LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } =20 static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, @@ -11014,7 +11014,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext= *ctx, uint32_t opc, } if (!(ctx->hflags & MIPS_HFLAG_DM)) { MIPS_INVAL(opn); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } else { gen_helper_deret(cpu_env); ctx->base.is_jmp =3D DISAS_EXIT; @@ -11037,7 +11037,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext= *ctx, uint32_t opc, default: die: MIPS_INVAL(opn); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } (void)opn; /* avoid a compiler warning */ @@ -11052,7 +11052,7 @@ static void gen_compute_branch1(DisasContext *ctx, = uint32_t op, TCGv_i32 t0 =3D tcg_temp_new_i32(); =20 if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->hflags & MIPS_HFLAG_BMAS= K)) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } =20 @@ -11143,7 +11143,7 @@ static void gen_compute_branch1(DisasContext *ctx, = uint32_t op, break; default: MIPS_INVAL("cp1 cond branch"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } ctx->btarget =3D btarget; @@ -11165,7 +11165,7 @@ static void gen_compute_branch1_r6(DisasContext *ct= x, uint32_t op, LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx "\n", ctx->base.pc_next); #endif - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } =20 @@ -11185,7 +11185,7 @@ static void gen_compute_branch1_r6(DisasContext *ct= x, uint32_t op, break; default: MIPS_INVAL("cp1 cond branch"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } =20 @@ -11493,7 +11493,7 @@ static void gen_cp1(DisasContext *ctx, uint32_t opc= , int rt, int fs) break; default: MIPS_INVAL("cp1 move"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } =20 @@ -11630,7 +11630,7 @@ static void gen_sel_s(DisasContext *ctx, enum fopco= de op1, int fd, int ft, break; default: MIPS_INVAL("gen_sel_s"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -11667,7 +11667,7 @@ static void gen_sel_d(DisasContext *ctx, enum fopco= de op1, int fd, int ft, break; default: MIPS_INVAL("gen_sel_d"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -13101,7 +13101,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, break; default: MIPS_INVAL("farith"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } } @@ -13440,7 +13440,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint3= 2_t opc, break; default: MIPS_INVAL("flt3_arith"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } } @@ -13515,13 +13515,13 @@ static void gen_rdhwr(DisasContext *ctx, int rt, = int rd, int sel) offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); gen_store_gpr(t0, rt); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } break; #endif default: /* Invalid */ MIPS_INVAL("rdhwr"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } tcg_temp_free(t0); @@ -13620,7 +13620,7 @@ static void gen_compute_compact_branch(DisasContext= *ctx, uint32_t opc, LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx "\n", ctx->base.pc_next); #endif - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } =20 @@ -13682,7 +13682,7 @@ static void gen_compute_compact_branch(DisasContext= *ctx, uint32_t opc, break; default: MIPS_INVAL("Compact branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } =20 @@ -13703,7 +13703,7 @@ static void gen_compute_compact_branch(DisasContext= *ctx, uint32_t opc, break; default: MIPS_INVAL("Compact branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } =20 @@ -13826,7 +13826,7 @@ static void gen_compute_compact_branch(DisasContext= *ctx, uint32_t opc, break; default: MIPS_INVAL("Compact conditional branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } =20 @@ -14000,7 +14000,7 @@ static void gen_mips16_save(DisasContext *ctx, args =3D 4; break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } =20 @@ -14096,7 +14096,7 @@ static void gen_mips16_save(DisasContext *ctx, astatic =3D 4; break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } =20 @@ -14202,7 +14202,7 @@ static void gen_mips16_restore(DisasContext *ctx, astatic =3D 4; break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } =20 @@ -14233,7 +14233,7 @@ static void gen_addiupc(DisasContext *ctx, int rx, = int imm, TCGv t0; =20 if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } =20 @@ -14291,7 +14291,7 @@ static void decode_i64_mips16(DisasContext *ctx, check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } else { offset =3D extended ? offset : offset << 3; gen_ld(ctx, OPC_LDPC, ry, 0, offset); @@ -14368,7 +14368,7 @@ static int decode_extended_mips16_opc(CPUMIPSState = *env, DisasContext *ctx) check_mips_64(ctx); gen_shift_imm(ctx, OPC_DSLL, rx, ry, sa); #else - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); #endif break; case 0x2: @@ -14396,7 +14396,7 @@ static int decode_extended_mips16_opc(CPUMIPSState = *env, DisasContext *ctx) check_mips_64(ctx); gen_arith_imm(ctx, OPC_DADDIU, ry, rx, imm); #else - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); #endif } else { gen_arith_imm(ctx, OPC_ADDIU, ry, rx, imm); @@ -14448,7 +14448,7 @@ static int decode_extended_mips16_opc(CPUMIPSState = *env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -14511,7 +14511,7 @@ static int decode_extended_mips16_opc(CPUMIPSState = *env, DisasContext *ctx) break; #endif default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -14600,7 +14600,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) check_mips_64(ctx); gen_shift_imm(ctx, OPC_DSLL, rx, ry, sa); #else - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); #endif break; case 0x2: @@ -14628,7 +14628,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) check_mips_64(ctx); gen_arith_imm(ctx, OPC_DADDIU, ry, rx, imm); #else - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); #endif } else { gen_arith_imm(ctx, OPC_ADDIU, ry, rx, imm); @@ -14712,7 +14712,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) gen_arith(ctx, OPC_ADDU, ry, reg32, 0); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -14802,7 +14802,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) break; #endif default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto done; } =20 @@ -14919,7 +14919,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) break; #endif default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -14983,7 +14983,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) break; #endif default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -14998,7 +14998,7 @@ static int decode_mips16_opc(CPUMIPSState *env, Dis= asContext *ctx) break; #endif default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -15696,7 +15696,7 @@ static void gen_ldst_multiple(DisasContext *ctx, ui= nt32_t opc, int reglist, TCGv_i32 t2; =20 if (ctx->hflags & MIPS_HFLAG_BMASK) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } =20 @@ -15849,7 +15849,7 @@ static void gen_pool16c_insn(DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -15994,7 +15994,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32= _t opc, int rd, TCGv t0, t1; =20 if (ctx->hflags & MIPS_HFLAG_BMASK || rd =3D=3D 31) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } =20 @@ -16006,7 +16006,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32= _t opc, int rd, switch (opc) { case LWP: if (rd =3D=3D base) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); @@ -16027,7 +16027,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32= _t opc, int rd, #ifdef TARGET_MIPS64 case LDP: if (rd =3D=3D base) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEQ); @@ -16372,7 +16372,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) } else { check_insn(ctx, ISA_MIPS32); if (ctx->hflags & MIPS_HFLAG_SBRI) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } else { generate_exception_end(ctx, EXCP_DBp); } @@ -16422,7 +16422,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasC= ontext *ctx, int rt, int rs) default: pool32axf_invalid: MIPS_INVAL("pool32axf"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -16691,7 +16691,7 @@ static void gen_pool32fxf(DisasContext *ctx, int rt= , int rs) break; default: MIPS_INVAL("pool32fxf"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -16895,12 +16895,12 @@ static void decode_micromips32_opc(CPUMIPSState *= env, DisasContext *ctx) break; case SIGRIE: check_insn(ctx, ISA_MIPS32R6); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: pool32a_invalid: MIPS_INVAL("pool32a"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -16942,7 +16942,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) break; default: MIPS_INVAL("pool32b"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -17422,7 +17422,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) default: pool32f_invalid: MIPS_INVAL("pool32f"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } else { @@ -17584,7 +17584,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) /* Fall through */ default: MIPS_INVAL("pool32i"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -17667,7 +17667,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) case LD_EVA: if (!ctx->eva) { MIPS_INVAL("pool32c ld-eva"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } check_cp0_enabled(ctx); @@ -17706,7 +17706,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) case ST_EVA: if (!ctx->eva) { MIPS_INVAL("pool32c st-eva"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } check_cp0_enabled(ctx); @@ -17758,7 +17758,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) break; default: MIPS_INVAL("pool32c"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -18050,7 +18050,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) gen_st(ctx, mips32_op, rt, rs, imm); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -18081,7 +18081,7 @@ static int decode_micromips_opc(CPUMIPSState *env, = DisasContext *ctx) case 7: /* LB32, LH32, LWC132, LDC132, LW32 */ if (ctx->hflags & MIPS_HFLAG_BDS16) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return 2; } break; @@ -18092,7 +18092,7 @@ static int decode_micromips_opc(CPUMIPSState *env, = DisasContext *ctx) case 3: /* MOVE16, ANDI16, POOL16D, POOL16E, BEQZ16, BNEZ16, B16, LI16 */ if (ctx->hflags & MIPS_HFLAG_BDS32) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return 2; } break; @@ -18165,7 +18165,7 @@ static int decode_micromips_opc(CPUMIPSState *env, = DisasContext *ctx) case POOL16F: check_insn_opc_removed(ctx, ISA_MIPS32R6); if (ctx->opcode & 1) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } else { /* MOVEP */ int enc_dest =3D uMIPS_RD(ctx->opcode); @@ -18303,7 +18303,7 @@ static int decode_micromips_opc(CPUMIPSState *env, = DisasContext *ctx) case RES_29: case RES_31: case RES_39: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: decode_micromips32_opc(env, ctx); @@ -19561,7 +19561,7 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState= *env, DisasContext *ctx) gen_helper_dvpe(t0, cpu_env); gen_store_gpr(t0, rt); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } break; case 1: @@ -19576,7 +19576,7 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState= *env, DisasContext *ctx) gen_helper_evpe(t0, cpu_env); gen_store_gpr(t0, rt); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } break; } @@ -19626,7 +19626,7 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState= *env, DisasContext *ctx) break; #endif default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -19667,7 +19667,7 @@ static void gen_pool32axf_1_5_nanomips_insn(DisasCo= ntext *ctx, uint32_t opc, gen_helper_maq_sa_w_phl(t0, v1_t, v0_t, cpu_env); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -19718,7 +19718,7 @@ static void gen_pool32axf_1_nanomips_insn(DisasCont= ext *ctx, uint32_t opc, gen_helper_shilo(t0, v0_t, cpu_env); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -19792,7 +19792,7 @@ static void gen_pool32axf_1_nanomips_insn(DisasCont= ext *ctx, uint32_t opc, } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -19830,7 +19830,7 @@ static void gen_pool32axf_2_multiply(DisasContext *= ctx, uint32_t opc, gen_helper_dpsq_s_w_ph(t0, v1, v0, cpu_env); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -19853,7 +19853,7 @@ static void gen_pool32axf_2_multiply(DisasContext *= ctx, uint32_t opc, gen_helper_dpsq_sa_l_w(t0, v0, v1, cpu_env); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -19880,7 +19880,7 @@ static void gen_pool32axf_2_multiply(DisasContext *= ctx, uint32_t opc, gen_helper_mulsa_w_ph(t0, v0, v1, cpu_env); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -19907,12 +19907,12 @@ static void gen_pool32axf_2_multiply(DisasContext= *ctx, uint32_t opc, gen_helper_mulsaq_s_w_ph(t0, v1, v0, cpu_env); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -20056,7 +20056,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasCont= ext *ctx, uint32_t opc, gen_store_gpr(t0, ret); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -20149,7 +20149,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasCont= ext *ctx, uint32_t opc, } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -20292,7 +20292,7 @@ static void gen_pool32axf_4_nanomips_insn(DisasCont= ext *ctx, uint32_t opc, gen_bshfl(ctx, OPC_WSBH, ret, rs); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -20347,7 +20347,7 @@ static void gen_pool32axf_7_nanomips_insn(DisasCont= ext *ctx, uint32_t opc, } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } tcg_temp_free(t0); @@ -20444,7 +20444,7 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSStat= e *env, DisasContext *ctx) break; #endif default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -20455,7 +20455,7 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSStat= e *env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -20488,7 +20488,7 @@ static void gen_compute_imm_branch(DisasContext *ct= x, uint32_t opc, case NM_BBNEZC: check_nms(ctx); if (imm >=3D 32 && !(ctx->hflags & MIPS_HFLAG_64)) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } else if (rt =3D=3D 0 && opc =3D=3D NM_BBEQZC) { /* Unconditional branch */ @@ -20538,7 +20538,7 @@ static void gen_compute_imm_branch(DisasContext *ct= x, uint32_t opc, break; default: MIPS_INVAL("Immediate Value Compact branch"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } =20 @@ -20651,7 +20651,7 @@ static void gen_compute_compact_branch_nm(DisasCont= ext *ctx, uint32_t opc, break; default: MIPS_INVAL("Compact branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } =20 @@ -20663,7 +20663,7 @@ static void gen_compute_compact_branch_nm(DisasCont= ext *ctx, uint32_t opc, break; default: MIPS_INVAL("Compact branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } } else { @@ -20724,7 +20724,7 @@ static void gen_compute_compact_branch_nm(DisasCont= ext *ctx, uint32_t opc, break; default: MIPS_INVAL("Compact conditional branch/jump"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } =20 @@ -20768,7 +20768,7 @@ static void gen_compute_branch_cp1_nm(DisasContext = *ctx, uint32_t op, break; default: MIPS_INVAL("cp1 cond branch"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); goto out; } =20 @@ -20898,7 +20898,7 @@ static void gen_p_lsx(DisasContext *ctx, int rd, in= t rs, int rt) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -20915,7 +20915,7 @@ static void gen_pool32f_nanomips_insn(DisasContext = *ctx) rd =3D extract32(ctx->opcode, 11, 5); =20 if (!(ctx->CP0_Config1 & (1 << CP0C1_FP))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } check_cp1_enabled(ctx); @@ -20989,7 +20989,7 @@ static void gen_pool32f_nanomips_insn(DisasContext = *ctx) gen_farith(ctx, OPC_MSUBF_D, rt, rs, rd, 0); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -21178,7 +21178,7 @@ static void gen_pool32f_nanomips_insn(DisasContext = *ctx) gen_farith(ctx, OPC_CVT_S_L, -1, rs, rt, 0); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -21195,12 +21195,12 @@ static void gen_pool32f_nanomips_insn(DisasContex= t *ctx) gen_r6_cmp_d(ctx, extract32(ctx->opcode, 6, 5), rt, rs, rd); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -21726,7 +21726,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, gen_store_gpr(v1_t, rt); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -21748,7 +21748,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -21776,13 +21776,13 @@ static int decode_nanomips_32_48_opc(CPUMIPSState= *env, DisasContext *ctx) switch (extract32(ctx->opcode, 19, 2)) { case NM_SIGRIE: default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case NM_P_SYSCALL: if ((extract32(ctx->opcode, 18, 1)) =3D=3D NM_SYSCALL) { generate_exception_end(ctx, EXCP_SYSCALL); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } break; case NM_BREAK: @@ -21793,7 +21793,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) gen_helper_do_semihosting(cpu_env); } else { if (ctx->hflags & MIPS_HFLAG_SBRI) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } else { generate_exception_end(ctx, EXCP_DBp); } @@ -21851,12 +21851,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState= *env, DisasContext *ctx) gen_pool32axf_nanomips_insn(env, ctx); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -21875,7 +21875,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) gen_st(ctx, OPC_SW, rt, 28, extract32(ctx->opcode, 2, 19) << 2= ); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -21946,7 +21946,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } return 6; @@ -21981,12 +21981,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState= *env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; case NM_P_SR_F: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22074,7 +22074,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) extract32(ctx->opcode, 6, 5)); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22087,12 +22087,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState= *env, DisasContext *ctx) extract32(ctx->opcode, 6, 5)); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22160,7 +22160,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) gen_st(ctx, OPC_SH, rt, 28, u); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22182,7 +22182,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -22242,7 +22242,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) gen_cop1_ldst(ctx, OPC_SDC1, rt, rs, u); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -22305,7 +22305,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22445,7 +22445,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) gen_llwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3,= 5)); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22465,7 +22465,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) true); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22516,7 +22516,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -22560,7 +22560,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) gen_compute_nanomips_pbalrsc_branch(ctx, rs, rt); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22595,7 +22595,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22644,7 +22644,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -22660,7 +22660,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } return 4; @@ -22699,7 +22699,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, D= isasContext *ctx) if (extract32(ctx->opcode, 2, 1) =3D=3D 0) { generate_exception_end(ctx, EXCP_SYSCALL); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } break; case NM_BREAK16: @@ -22710,14 +22710,14 @@ static int decode_nanomips_opc(CPUMIPSState *env,= DisasContext *ctx) gen_helper_do_semihosting(cpu_env); } else { if (ctx->hflags & MIPS_HFLAG_SBRI) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } else { generate_exception_end(ctx, EXCP_DBp); } } break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -22756,7 +22756,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, D= isasContext *ctx) gen_arith_imm(ctx, OPC_ADDIU, rt, 29, imm); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22805,7 +22805,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, D= isasContext *ctx) gen_r6_muldiv(ctx, R6_OPC_MUL, rt, rs, rt); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22841,7 +22841,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, D= isasContext *ctx) gen_ld(ctx, OPC_LBU, rt, rs, offset); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -22860,7 +22860,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, D= isasContext *ctx) gen_ld(ctx, OPC_LHU, rt, rs, offset); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -23639,7 +23639,7 @@ static void gen_mipsdsp_shift(DisasContext *ctx, ui= nt32_t opc, break; default: /* Invalid */ MIPS_INVAL("MASK SHLL.QB"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -23754,7 +23754,7 @@ static void gen_mipsdsp_shift(DisasContext *ctx, ui= nt32_t opc, break; default: /* Invalid */ MIPS_INVAL("MASK SHLL.OB"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -24445,7 +24445,7 @@ static void gen_mipsdsp_append(CPUMIPSState *env, D= isasContext *ctx, break; default: /* Invalid */ MIPS_INVAL("MASK APPEND"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -24479,7 +24479,7 @@ static void gen_mipsdsp_append(CPUMIPSState *env, D= isasContext *ctx, break; default: /* Invalid */ MIPS_INVAL("MASK DAPPEND"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -24748,7 +24748,7 @@ static void decode_opc_special_r6(CPUMIPSState *env= , DisasContext *ctx) break; default: MIPS_INVAL("special_r6 muldiv"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -24765,7 +24765,7 @@ static void decode_opc_special_r6(CPUMIPSState *env= , DisasContext *ctx) */ gen_cl(ctx, op1, rd, rs); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } break; case R6_OPC_SDBBP: @@ -24773,7 +24773,7 @@ static void decode_opc_special_r6(CPUMIPSState *env= , DisasContext *ctx) gen_helper_do_semihosting(cpu_env); } else { if (ctx->hflags & MIPS_HFLAG_SBRI) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } else { generate_exception_end(ctx, EXCP_DBp); } @@ -24794,7 +24794,7 @@ static void decode_opc_special_r6(CPUMIPSState *env= , DisasContext *ctx) check_mips_64(ctx); gen_cl(ctx, op1, rd, rs); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } break; case OPC_DMULT: @@ -24817,14 +24817,14 @@ static void decode_opc_special_r6(CPUMIPSState *e= nv, DisasContext *ctx) break; default: MIPS_INVAL("special_r6 muldiv"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; #endif default: /* Invalid */ MIPS_INVAL("special_r6"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -24871,7 +24871,7 @@ static void decode_opc_special_tx79(CPUMIPSState *e= nv, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("special_tx79"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -24942,16 +24942,16 @@ static void decode_opc_special_legacy(CPUMIPSStat= e *env, DisasContext *ctx) case OPC_SPIM: #ifdef MIPS_STRICT_STANDARD MIPS_INVAL("SPIM"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); #else /* Implemented as RI exception for now. */ MIPS_INVAL("spim (unofficial)"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); #endif break; default: /* Invalid */ MIPS_INVAL("special_legacy"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -24973,7 +24973,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) rs =3D=3D 0 && rt =3D=3D 0) { /* PAUSE */ if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -24993,7 +24993,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) gen_shift_imm(ctx, op1, rd, rt, sa); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -25019,7 +25019,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) gen_shift(ctx, op1, rd, rs, rt); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -25053,7 +25053,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) /* Pmon entry point, also R4010 selsl */ #ifdef MIPS_STRICT_STANDARD MIPS_INVAL("PMON / selsl"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); #else gen_helper_0e0i(pmon, sa); #endif @@ -25094,7 +25094,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) gen_shift_imm(ctx, op1, rd, rt, sa); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -25112,7 +25112,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) gen_shift_imm(ctx, op1, rd, rt, sa); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -25144,7 +25144,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) gen_shift(ctx, op1, rd, rs, rt); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -25209,7 +25209,7 @@ static void gen_mmi_pcpyh(DisasContext *ctx) rd =3D extract32(opcode, 11, 5); =20 if (unlikely(pd !=3D 0)) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } else if (rd =3D=3D 0) { /* nop */ } else if (rt =3D=3D 0) { @@ -26416,16 +26416,16 @@ static void decode_opc_mxu__pool00(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_Q8SLT: /* TODO: Implement emulation of Q8SLT instruction. */ MIPS_INVAL("OPC_MXU_Q8SLT"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q8SLTU: /* TODO: Implement emulation of Q8SLTU instruction. */ MIPS_INVAL("OPC_MXU_Q8SLTU"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26455,41 +26455,41 @@ static void decode_opc_mxu__pool01(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_S32SLT: /* TODO: Implement emulation of S32SLT instruction. */ MIPS_INVAL("OPC_MXU_S32SLT"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D16SLT: /* TODO: Implement emulation of D16SLT instruction. */ MIPS_INVAL("OPC_MXU_D16SLT"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D16AVG: /* TODO: Implement emulation of D16AVG instruction. */ MIPS_INVAL("OPC_MXU_D16AVG"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D16AVGR: /* TODO: Implement emulation of D16AVGR instruction. */ MIPS_INVAL("OPC_MXU_D16AVGR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q8AVG: /* TODO: Implement emulation of Q8AVG instruction. */ MIPS_INVAL("OPC_MXU_Q8AVG"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q8AVGR: /* TODO: Implement emulation of Q8AVGR instruction. */ MIPS_INVAL("OPC_MXU_Q8AVGR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q8ADD: /* TODO: Implement emulation of Q8ADD instruction. */ MIPS_INVAL("OPC_MXU_Q8ADD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26512,26 +26512,26 @@ static void decode_opc_mxu__pool02(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_S32CPS: /* TODO: Implement emulation of S32CPS instruction. */ MIPS_INVAL("OPC_MXU_S32CPS"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D16CPS: /* TODO: Implement emulation of D16CPS instruction. */ MIPS_INVAL("OPC_MXU_D16CPS"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q8ABD: /* TODO: Implement emulation of Q8ABD instruction. */ MIPS_INVAL("OPC_MXU_Q8ABD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q16SAT: /* TODO: Implement emulation of Q16SAT instruction. */ MIPS_INVAL("OPC_MXU_Q16SAT"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26561,16 +26561,16 @@ static void decode_opc_mxu__pool03(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_D16MULF: /* TODO: Implement emulation of D16MULF instruction. */ MIPS_INVAL("OPC_MXU_D16MULF"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D16MULE: /* TODO: Implement emulation of D16MULE instruction. */ MIPS_INVAL("OPC_MXU_D16MULE"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26596,7 +26596,7 @@ static void decode_opc_mxu__pool04(CPUMIPSState *en= v, DisasContext *ctx) break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26619,16 +26619,16 @@ static void decode_opc_mxu__pool05(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_S32STD: /* TODO: Implement emulation of S32STD instruction. */ MIPS_INVAL("OPC_MXU_S32STD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32STDR: /* TODO: Implement emulation of S32STDR instruction. */ MIPS_INVAL("OPC_MXU_S32STDR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26651,16 +26651,16 @@ static void decode_opc_mxu__pool06(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_S32LDDV: /* TODO: Implement emulation of S32LDDV instruction. */ MIPS_INVAL("OPC_MXU_S32LDDV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32LDDVR: /* TODO: Implement emulation of S32LDDVR instruction. */ MIPS_INVAL("OPC_MXU_S32LDDVR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26683,16 +26683,16 @@ static void decode_opc_mxu__pool07(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_S32STDV: /* TODO: Implement emulation of S32TDV instruction. */ MIPS_INVAL("OPC_MXU_S32TDV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32STDVR: /* TODO: Implement emulation of S32TDVR instruction. */ MIPS_INVAL("OPC_MXU_S32TDVR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26715,16 +26715,16 @@ static void decode_opc_mxu__pool08(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_S32LDI: /* TODO: Implement emulation of S32LDI instruction. */ MIPS_INVAL("OPC_MXU_S32LDI"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32LDIR: /* TODO: Implement emulation of S32LDIR instruction. */ MIPS_INVAL("OPC_MXU_S32LDIR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26747,16 +26747,16 @@ static void decode_opc_mxu__pool09(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_S32SDI: /* TODO: Implement emulation of S32SDI instruction. */ MIPS_INVAL("OPC_MXU_S32SDI"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32SDIR: /* TODO: Implement emulation of S32SDIR instruction. */ MIPS_INVAL("OPC_MXU_S32SDIR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26779,16 +26779,16 @@ static void decode_opc_mxu__pool10(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_S32LDIV: /* TODO: Implement emulation of S32LDIV instruction. */ MIPS_INVAL("OPC_MXU_S32LDIV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32LDIVR: /* TODO: Implement emulation of S32LDIVR instruction. */ MIPS_INVAL("OPC_MXU_S32LDIVR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26811,16 +26811,16 @@ static void decode_opc_mxu__pool11(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_S32SDIV: /* TODO: Implement emulation of S32SDIV instruction. */ MIPS_INVAL("OPC_MXU_S32SDIV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32SDIVR: /* TODO: Implement emulation of S32SDIVR instruction. */ MIPS_INVAL("OPC_MXU_S32SDIVR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26843,21 +26843,21 @@ static void decode_opc_mxu__pool12(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_D32ACC: /* TODO: Implement emulation of D32ACC instruction. */ MIPS_INVAL("OPC_MXU_D32ACC"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D32ACCM: /* TODO: Implement emulation of D32ACCM instruction. */ MIPS_INVAL("OPC_MXU_D32ACCM"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D32ASUM: /* TODO: Implement emulation of D32ASUM instruction. */ MIPS_INVAL("OPC_MXU_D32ASUM"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26880,21 +26880,21 @@ static void decode_opc_mxu__pool13(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_Q16ACC: /* TODO: Implement emulation of Q16ACC instruction. */ MIPS_INVAL("OPC_MXU_Q16ACC"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q16ACCM: /* TODO: Implement emulation of Q16ACCM instruction. */ MIPS_INVAL("OPC_MXU_Q16ACCM"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q16ASUM: /* TODO: Implement emulation of Q16ASUM instruction. */ MIPS_INVAL("OPC_MXU_Q16ASUM"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26924,21 +26924,21 @@ static void decode_opc_mxu__pool14(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_Q8ADDE: /* TODO: Implement emulation of Q8ADDE instruction. */ MIPS_INVAL("OPC_MXU_Q8ADDE"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D8SUM: /* TODO: Implement emulation of D8SUM instruction. */ MIPS_INVAL("OPC_MXU_D8SUM"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D8SUMC: /* TODO: Implement emulation of D8SUMC instruction. */ MIPS_INVAL("OPC_MXU_D8SUMC"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -26968,26 +26968,26 @@ static void decode_opc_mxu__pool15(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_S32MUL: /* TODO: Implement emulation of S32MUL instruction. */ MIPS_INVAL("OPC_MXU_S32MUL"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32MULU: /* TODO: Implement emulation of S32MULU instruction. */ MIPS_INVAL("OPC_MXU_S32MULU"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32EXTR: /* TODO: Implement emulation of S32EXTR instruction. */ MIPS_INVAL("OPC_MXU_S32EXTR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32EXTRV: /* TODO: Implement emulation of S32EXTRV instruction. */ MIPS_INVAL("OPC_MXU_S32EXTRV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -27035,12 +27035,12 @@ static void decode_opc_mxu__pool16(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_D32SARW: /* TODO: Implement emulation of D32SARW instruction. */ MIPS_INVAL("OPC_MXU_D32SARW"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32ALN: /* TODO: Implement emulation of S32ALN instruction. */ MIPS_INVAL("OPC_MXU_S32ALN"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32ALNI: gen_mxu_S32ALNI(ctx); @@ -27048,7 +27048,7 @@ static void decode_opc_mxu__pool16(CPUMIPSState *en= v, DisasContext *ctx) case OPC_MXU_S32LUI: /* TODO: Implement emulation of S32LUI instruction. */ MIPS_INVAL("OPC_MXU_S32LUI"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32NOR: gen_mxu_S32NOR(ctx); @@ -27064,7 +27064,7 @@ static void decode_opc_mxu__pool16(CPUMIPSState *en= v, DisasContext *ctx) break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -27087,31 +27087,31 @@ static void decode_opc_mxu__pool17(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_LXW: /* TODO: Implement emulation of LXW instruction. */ MIPS_INVAL("OPC_MXU_LXW"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_LXH: /* TODO: Implement emulation of LXH instruction. */ MIPS_INVAL("OPC_MXU_LXH"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_LXHU: /* TODO: Implement emulation of LXHU instruction. */ MIPS_INVAL("OPC_MXU_LXHU"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_LXB: /* TODO: Implement emulation of LXB instruction. */ MIPS_INVAL("OPC_MXU_LXB"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_LXBU: /* TODO: Implement emulation of LXBU instruction. */ MIPS_INVAL("OPC_MXU_LXBU"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -27133,36 +27133,36 @@ static void decode_opc_mxu__pool18(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_D32SLLV: /* TODO: Implement emulation of D32SLLV instruction. */ MIPS_INVAL("OPC_MXU_D32SLLV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D32SLRV: /* TODO: Implement emulation of D32SLRV instruction. */ MIPS_INVAL("OPC_MXU_D32SLRV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D32SARV: /* TODO: Implement emulation of D32SARV instruction. */ MIPS_INVAL("OPC_MXU_D32SARV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q16SLLV: /* TODO: Implement emulation of Q16SLLV instruction. */ MIPS_INVAL("OPC_MXU_Q16SLLV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q16SLRV: /* TODO: Implement emulation of Q16SLRV instruction. */ MIPS_INVAL("OPC_MXU_Q16SLRV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q16SARV: /* TODO: Implement emulation of Q16SARV instruction. */ MIPS_INVAL("OPC_MXU_Q16SARV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -27188,7 +27188,7 @@ static void decode_opc_mxu__pool19(CPUMIPSState *en= v, DisasContext *ctx) break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -27211,36 +27211,36 @@ static void decode_opc_mxu__pool20(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_Q8MOVZ: /* TODO: Implement emulation of Q8MOVZ instruction. */ MIPS_INVAL("OPC_MXU_Q8MOVZ"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q8MOVN: /* TODO: Implement emulation of Q8MOVN instruction. */ MIPS_INVAL("OPC_MXU_Q8MOVN"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D16MOVZ: /* TODO: Implement emulation of D16MOVZ instruction. */ MIPS_INVAL("OPC_MXU_D16MOVZ"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D16MOVN: /* TODO: Implement emulation of D16MOVN instruction. */ MIPS_INVAL("OPC_MXU_D16MOVN"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32MOVZ: /* TODO: Implement emulation of S32MOVZ instruction. */ MIPS_INVAL("OPC_MXU_S32MOVZ"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32MOVN: /* TODO: Implement emulation of S32MOVN instruction. */ MIPS_INVAL("OPC_MXU_S32MOVN"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -27263,16 +27263,16 @@ static void decode_opc_mxu__pool21(CPUMIPSState *= env, DisasContext *ctx) case OPC_MXU_Q8MAC: /* TODO: Implement emulation of Q8MAC instruction. */ MIPS_INVAL("OPC_MXU_Q8MAC"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q8MACSU: /* TODO: Implement emulation of Q8MACSU instruction. */ MIPS_INVAL("OPC_MXU_Q8MACSU"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -27331,12 +27331,12 @@ static void decode_opc_mxu(CPUMIPSState *env, Dis= asContext *ctx) case OPC_MXU_S32MADD: /* TODO: Implement emulation of S32MADD instruction. */ MIPS_INVAL("OPC_MXU_S32MADD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32MADDU: /* TODO: Implement emulation of S32MADDU instruction. */ MIPS_INVAL("OPC_MXU_S32MADDU"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU__POOL00: decode_opc_mxu__pool00(env, ctx); @@ -27344,12 +27344,12 @@ static void decode_opc_mxu(CPUMIPSState *env, Dis= asContext *ctx) case OPC_MXU_S32MSUB: /* TODO: Implement emulation of S32MSUB instruction. */ MIPS_INVAL("OPC_MXU_S32MSUB"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32MSUBU: /* TODO: Implement emulation of S32MSUBU instruction. */ MIPS_INVAL("OPC_MXU_S32MSUBU"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU__POOL01: decode_opc_mxu__pool01(env, ctx); @@ -27369,27 +27369,27 @@ static void decode_opc_mxu(CPUMIPSState *env, Dis= asContext *ctx) case OPC_MXU_D16MACF: /* TODO: Implement emulation of D16MACF instruction. */ MIPS_INVAL("OPC_MXU_D16MACF"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D16MADL: /* TODO: Implement emulation of D16MADL instruction. */ MIPS_INVAL("OPC_MXU_D16MADL"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S16MAD: /* TODO: Implement emulation of S16MAD instruction. */ MIPS_INVAL("OPC_MXU_S16MAD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q16ADD: /* TODO: Implement emulation of Q16ADD instruction. */ MIPS_INVAL("OPC_MXU_Q16ADD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D16MACE: /* TODO: Implement emulation of D16MACE instruction. */ MIPS_INVAL("OPC_MXU_D16MACE"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU__POOL04: decode_opc_mxu__pool04(env, ctx); @@ -27418,7 +27418,7 @@ static void decode_opc_mxu(CPUMIPSState *env, Disas= Context *ctx) case OPC_MXU_D32ADD: /* TODO: Implement emulation of D32ADD instruction. */ MIPS_INVAL("OPC_MXU_D32ADD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU__POOL12: decode_opc_mxu__pool12(env, ctx); @@ -27432,7 +27432,7 @@ static void decode_opc_mxu(CPUMIPSState *env, Disas= Context *ctx) case OPC_MXU_Q8ACCE: /* TODO: Implement emulation of Q8ACCE instruction. */ MIPS_INVAL("OPC_MXU_Q8ACCE"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S8LDD: gen_mxu_s8ldd(ctx); @@ -27440,17 +27440,17 @@ static void decode_opc_mxu(CPUMIPSState *env, Dis= asContext *ctx) case OPC_MXU_S8STD: /* TODO: Implement emulation of S8STD instruction. */ MIPS_INVAL("OPC_MXU_S8STD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S8LDI: /* TODO: Implement emulation of S8LDI instruction. */ MIPS_INVAL("OPC_MXU_S8LDI"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S8SDI: /* TODO: Implement emulation of S8SDI instruction. */ MIPS_INVAL("OPC_MXU_S8SDI"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU__POOL15: decode_opc_mxu__pool15(env, ctx); @@ -27464,52 +27464,52 @@ static void decode_opc_mxu(CPUMIPSState *env, Dis= asContext *ctx) case OPC_MXU_S16LDD: /* TODO: Implement emulation of S16LDD instruction. */ MIPS_INVAL("OPC_MXU_S16LDD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S16STD: /* TODO: Implement emulation of S16STD instruction. */ MIPS_INVAL("OPC_MXU_S16STD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S16LDI: /* TODO: Implement emulation of S16LDI instruction. */ MIPS_INVAL("OPC_MXU_S16LDI"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S16SDI: /* TODO: Implement emulation of S16SDI instruction. */ MIPS_INVAL("OPC_MXU_S16SDI"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D32SLL: /* TODO: Implement emulation of D32SLL instruction. */ MIPS_INVAL("OPC_MXU_D32SLL"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D32SLR: /* TODO: Implement emulation of D32SLR instruction. */ MIPS_INVAL("OPC_MXU_D32SLR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D32SARL: /* TODO: Implement emulation of D32SARL instruction. */ MIPS_INVAL("OPC_MXU_D32SARL"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_D32SAR: /* TODO: Implement emulation of D32SAR instruction. */ MIPS_INVAL("OPC_MXU_D32SAR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q16SLL: /* TODO: Implement emulation of Q16SLL instruction. */ MIPS_INVAL("OPC_MXU_Q16SLL"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q16SLR: /* TODO: Implement emulation of Q16SLR instruction. */ MIPS_INVAL("OPC_MXU_Q16SLR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU__POOL18: decode_opc_mxu__pool18(env, ctx); @@ -27517,7 +27517,7 @@ static void decode_opc_mxu(CPUMIPSState *env, Disas= Context *ctx) case OPC_MXU_Q16SAR: /* TODO: Implement emulation of Q16SAR instruction. */ MIPS_INVAL("OPC_MXU_Q16SAR"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU__POOL19: decode_opc_mxu__pool19(env, ctx); @@ -27531,26 +27531,26 @@ static void decode_opc_mxu(CPUMIPSState *env, Dis= asContext *ctx) case OPC_MXU_Q16SCOP: /* TODO: Implement emulation of Q16SCOP instruction. */ MIPS_INVAL("OPC_MXU_Q16SCOP"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q8MADL: /* TODO: Implement emulation of Q8MADL instruction. */ MIPS_INVAL("OPC_MXU_Q8MADL"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_S32SFL: /* TODO: Implement emulation of S32SFL instruction. */ MIPS_INVAL("OPC_MXU_S32SFL"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_MXU_Q8SAD: /* TODO: Implement emulation of Q8SAD instruction. */ MIPS_INVAL("OPC_MXU_Q8SAD"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; default: MIPS_INVAL("decode_opc_mxu"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } =20 gen_set_label(l_exit); @@ -27629,7 +27629,7 @@ static void decode_opc_special2_legacy(CPUMIPSState= *env, DisasContext *ctx) #endif default: /* Invalid */ MIPS_INVAL("special2_legacy"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -27651,7 +27651,7 @@ static void decode_opc_special3_r6(CPUMIPSState *en= v, DisasContext *ctx) case R6_OPC_PREF: if (rt >=3D 24) { /* hint codes 24-31 are reserved and signal RI */ - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } /* Treat as NOP. */ break; @@ -27690,7 +27690,7 @@ static void decode_opc_special3_r6(CPUMIPSState *en= v, DisasContext *ctx) #ifndef CONFIG_USER_ONLY case OPC_GINV: if (unlikely(ctx->gi <=3D 1)) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } check_cp0_enabled(ctx); switch ((ctx->opcode >> 6) & 3) { @@ -27701,7 +27701,7 @@ static void decode_opc_special3_r6(CPUMIPSState *en= v, DisasContext *ctx) gen_helper_0e1i(ginvt, cpu_gpr[rs], extract32(ctx->opcode, 8, = 2)); break; default: - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -27742,7 +27742,7 @@ static void decode_opc_special3_r6(CPUMIPSState *en= v, DisasContext *ctx) #endif default: /* Invalid */ MIPS_INVAL("special3_r6"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -27793,13 +27793,13 @@ static void decode_opc_special3_legacy(CPUMIPSSta= te *env, DisasContext *ctx) break; default: MIPS_INVAL("MASK ADDUH.QB"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } else if (ctx->insn_flags & INSN_LOONGSON2E) { gen_loongson_integer(ctx, op1, rd, rs, rt); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } break; case OPC_LX_DSP: @@ -27815,7 +27815,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK LX"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -27846,7 +27846,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) break; default: MIPS_INVAL("MASK ABSQ_S.PH"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -27883,7 +27883,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK ADDU.QB"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; =20 } @@ -27923,7 +27923,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK CMPU.EQ.QB"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -27959,7 +27959,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK DPAW.PH"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -27989,7 +27989,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) } default: /* Invalid */ MIPS_INVAL("MASK INSV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -28024,7 +28024,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK EXTR.W"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -28070,7 +28070,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK ABSQ_S.QH"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -28109,7 +28109,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK ADDU.OB"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -28154,7 +28154,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK CMPU_EQ.OB"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -28191,7 +28191,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK EXTR.W"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -28230,7 +28230,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK DPAQ.W.QH"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -28260,7 +28260,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) } default: /* Invalid */ MIPS_INVAL("MASK DINSV"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -28270,7 +28270,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) #endif default: /* Invalid */ MIPS_INVAL("special3_legacy"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -28308,11 +28308,11 @@ static void decode_mmi0(CPUMIPSState *env, DisasC= ontext *ctx) case MMI_OPC_0_PPACB: /* TODO: MMI_OPC_0_PPACB */ case MMI_OPC_0_PEXT5: /* TODO: MMI_OPC_0_PEXT5 */ case MMI_OPC_0_PPAC5: /* TODO: MMI_OPC_0_PPAC5 */ - generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI0 = */ + gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI0 */ break; default: MIPS_INVAL("TX79 MMI class MMI0"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -28340,11 +28340,11 @@ static void decode_mmi1(CPUMIPSState *env, DisasC= ontext *ctx) case MMI_OPC_1_PSUBUB: /* TODO: MMI_OPC_1_PSUBUB */ case MMI_OPC_1_PEXTUB: /* TODO: MMI_OPC_1_PEXTUB */ case MMI_OPC_1_QFSRV: /* TODO: MMI_OPC_1_QFSRV */ - generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI1 = */ + gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI1 */ break; default: MIPS_INVAL("TX79 MMI class MMI1"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -28375,14 +28375,14 @@ static void decode_mmi2(CPUMIPSState *env, DisasC= ontext *ctx) case MMI_OPC_2_PDIVBW: /* TODO: MMI_OPC_2_PDIVBW */ case MMI_OPC_2_PEXEW: /* TODO: MMI_OPC_2_PEXEW */ case MMI_OPC_2_PROT3W: /* TODO: MMI_OPC_2_PROT3W */ - generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI2 = */ + gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI2 */ break; case MMI_OPC_2_PCPYLD: gen_mmi_pcpyld(ctx); break; default: MIPS_INVAL("TX79 MMI class MMI2"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -28403,7 +28403,7 @@ static void decode_mmi3(CPUMIPSState *env, DisasCon= text *ctx) case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */ case MMI_OPC_3_PEXCH: /* TODO: MMI_OPC_3_PEXCH */ case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */ - generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 = */ + gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI3 */ break; case MMI_OPC_3_PCPYH: gen_mmi_pcpyh(ctx); @@ -28413,7 +28413,7 @@ static void decode_mmi3(CPUMIPSState *env, DisasCon= text *ctx) break; default: MIPS_INVAL("TX79 MMI class MMI3"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -28467,23 +28467,23 @@ static void decode_mmi(CPUMIPSState *env, DisasCo= ntext *ctx) case MMI_OPC_PSLLW: /* TODO: MMI_OPC_PSLLW */ case MMI_OPC_PSRLW: /* TODO: MMI_OPC_PSRLW */ case MMI_OPC_PSRAW: /* TODO: MMI_OPC_PSRAW */ - generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MM= I */ + gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI */ break; default: MIPS_INVAL("TX79 MMI class"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } =20 static void gen_mmi_lq(CPUMIPSState *env, DisasContext *ctx) { - generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_LQ */ + gen_reserved_instruction(ctx); /* TODO: MMI_OPC_LQ */ } =20 static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset) { - generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_SQ */ + gen_reserved_instruction(ctx); /* TODO: MMI_OPC_SQ */ } =20 /* @@ -28691,7 +28691,7 @@ static inline int check_msa_access(DisasContext *ct= x) { if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) && !(ctx->hflags & MIPS_HFLAG_F64))) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return 0; } =20 @@ -28700,7 +28700,7 @@ static inline int check_msa_access(DisasContext *ct= x) generate_exception_end(ctx, EXCP_MSADIS); return 0; } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return 0; } } @@ -28757,7 +28757,7 @@ static void gen_msa_branch(CPUMIPSState *env, Disas= Context *ctx, uint32_t op1) check_msa_access(ctx); =20 if (ctx->hflags & MIPS_HFLAG_BMASK) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } switch (op1) { @@ -28832,7 +28832,7 @@ static void gen_msa_i8(CPUMIPSState *env, DisasCont= ext *ctx) { uint8_t df =3D (ctx->opcode >> 24) & 0x3; if (df =3D=3D DF_DOUBLE) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } else { TCGv_i32 tdf =3D tcg_const_i32(df); gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, ti8); @@ -28842,7 +28842,7 @@ static void gen_msa_i8(CPUMIPSState *env, DisasCont= ext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -28914,7 +28914,7 @@ static void gen_msa_i5(CPUMIPSState *env, DisasCont= ext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -28950,7 +28950,7 @@ static void gen_msa_bit(CPUMIPSState *env, DisasCon= text *ctx) m =3D dfm & 0x7; df =3D DF_BYTE; } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } =20 @@ -28998,7 +28998,7 @@ static void gen_msa_bit(CPUMIPSState *env, DisasCon= text *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -29843,7 +29843,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_HSUB_S_df: case OPC_HSUB_U_df: if (df =3D=3D DF_BYTE) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } switch (MASK_MSA_3R(ctx->opcode)) { @@ -29981,7 +29981,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } tcg_temp_free_i32(twd); @@ -30013,7 +30013,7 @@ static void gen_msa_elm_3e(CPUMIPSState *env, Disas= Context *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -30050,12 +30050,12 @@ static void gen_msa_elm_df(CPUMIPSState *env, Dis= asContext *ctx, uint32_t df, #if !defined(TARGET_MIPS64) /* Double format valid only for MIPS64 */ if (df =3D=3D DF_DOUBLE) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } if ((MASK_MSA_ELM(ctx->opcode) =3D=3D OPC_COPY_U_df) && (df =3D=3D DF_WORD)) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } #endif @@ -30125,7 +30125,7 @@ static void gen_msa_elm_df(CPUMIPSState *env, Disas= Context *ctx, uint32_t df, break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } tcg_temp_free_i32(twd); tcg_temp_free_i32(tws); @@ -30155,7 +30155,7 @@ static void gen_msa_elm(CPUMIPSState *env, DisasCon= text *ctx) gen_msa_elm_3e(env, ctx); return; } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); return; } =20 @@ -30310,7 +30310,7 @@ static void gen_msa_3rf(CPUMIPSState *env, DisasCon= text *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -30338,7 +30338,7 @@ static void gen_msa_2r(CPUMIPSState *env, DisasCont= ext *ctx) #if !defined(TARGET_MIPS64) /* Double format valid only for MIPS64 */ if (df =3D=3D DF_DOUBLE) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } #endif @@ -30394,7 +30394,7 @@ static void gen_msa_2r(CPUMIPSState *env, DisasCont= ext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -30509,7 +30509,7 @@ static void gen_msa_vec_v(CPUMIPSState *env, DisasC= ontext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -30538,7 +30538,7 @@ static void gen_msa_vec(CPUMIPSState *env, DisasCon= text *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -30636,7 +30636,7 @@ static void gen_msa(CPUMIPSState *env, DisasContext= *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } =20 @@ -30720,7 +30720,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) /* OPC_NAL, OPC_BAL */ gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2, 4); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } } else { gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4); @@ -30739,7 +30739,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; case OPC_SIGRIE: check_insn(ctx, ISA_MIPS32R6); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; case OPC_SYNCI: check_insn(ctx, ISA_MIPS32R2); @@ -30774,7 +30774,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) #endif default: /* Invalid */ MIPS_INVAL("regimm"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -30883,7 +30883,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; default: /* Invalid */ MIPS_INVAL("mfmc0"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } tcg_temp_free(t0); @@ -30900,7 +30900,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; default: MIPS_INVAL("cp0"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -30936,7 +30936,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC, OPC_BLEZL */ if (ctx->insn_flags & ISA_MIPS32R6) { if (rt =3D=3D 0) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } /* OPC_BLEZC, OPC_BGEZC, OPC_BGEC */ @@ -30949,7 +30949,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC, OPC_BGTZL */ if (ctx->insn_flags & ISA_MIPS32R6) { if (rt =3D=3D 0) { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } /* OPC_BGTZC, OPC_BLTZC, OPC_BLTC */ @@ -31198,7 +31198,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; default: MIPS_INVAL("cp1"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } break; @@ -31284,7 +31284,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; default: MIPS_INVAL("cp3"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } else { @@ -31349,7 +31349,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); } else { MIPS_INVAL("major opcode"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); } break; #endif @@ -31367,7 +31367,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) tcg_temp_free(t0); } #else - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); MIPS_INVAL("major opcode"); #endif } else { @@ -31393,7 +31393,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) break; default: /* Invalid */ MIPS_INVAL("major opcode"); - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); break; } } @@ -31498,7 +31498,7 @@ static void mips_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cs) ctx->opcode =3D cpu_lduw_code(env, ctx->base.pc_next); insn_bytes =3D decode_mips16_opc(env, ctx); } else { - generate_exception_end(ctx, EXCP_RI); + gen_reserved_instruction(ctx); g_assert(ctx->base.is_jmp =3D=3D DISAS_NORETURN); return; } --=20 2.26.2 From nobody Sun May 5 06:21:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607972243; cv=none; d=zohomail.com; s=zohoarc; b=g7J9Erx1pOWot5kcSwQ7UmEiDaUHHZT+EcMDktOD5zEiBaqJVJ3+892H3d3+I+gKYk4l1ifWCDiJkmzXQrDXbZXx03jIcStyhrg2wEz3FjFn3LxQ0zyhVTw5cEgs0KBmIC72X/7cvDN1T1bUMzTFum+ICv5sZeIEJ2AVlovswlc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607972243; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=z4msl+4E6QtN6RCQD089Ehf2sv+vjVAWY6z4uBcfgdk=; b=jzsu0h6AmOWGWngF2JLspHjb3oePUM5v7Afl4cBKXB2cfW055guBw8nMS3zz54HOWGCsmvGZ1RIntrFHlQwIebRz2PA9H1N3m1/4sdP6KCjHdHG7BG6fwg+532RwkjAzRj7A4BSP414okQi095mNeHbLpLdLLbnr4kThpIAlnT4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607972243865138.72445961366066; Mon, 14 Dec 2020 10:57:23 -0800 (PST) Received: from localhost ([::1]:52794 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kot09-0006h4-2q for importer@patchew.org; Mon, 14 Dec 2020 13:55:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34626) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1koskG-0000Jj-6L for qemu-devel@nongnu.org; Mon, 14 Dec 2020 13:38:53 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:56225) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kosk9-0007Tw-1L for qemu-devel@nongnu.org; Mon, 14 Dec 2020 13:38:47 -0500 Received: by mail-wm1-x335.google.com with SMTP id x22so14682933wmc.5 for ; Mon, 14 Dec 2020 10:38:44 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id v7sm31858058wma.26.2020.12.14.10.38.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:38:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=z4msl+4E6QtN6RCQD089Ehf2sv+vjVAWY6z4uBcfgdk=; b=DrDZm/9e0lVMSvZGjsIYjHK94ow+Jg5D8TItRlY9LizKyMcpKEvRgNUACXmaxqgSm/ rG16dqW9KtMQQ4EUwmY6ebTXQC+UAAV9zxqB8CoaYZx1l8VuToAuCWUjxhlYvabVB1X8 L1rdGB4P1fUIPm+pYAfsNjlG/iicbg6rAkFKGNcTqzpQm0c8sdLJerwqElgw1M3tJ6G6 xnZ44g/I12U9vLGVJbrctPB3k8joVqHIcOjVvfRUZ3cHezjvT+bPTbuOylBVikUyu3N8 FlFKlM98G+kNm1e7mr9DPkOVWKHbfuvCkQp07yVSDl9dCzdPbJJmTYQaFnJhJFFbfSkZ tHMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=z4msl+4E6QtN6RCQD089Ehf2sv+vjVAWY6z4uBcfgdk=; b=UxA5Se82TN/WgIfe0Q+7y7peiAbWBbcrv36hJg9bhrd/An0B5Z4kS/F1qqQ7gqPU1Z r6AEuvHgXtvtjQS5GpJCe9nQHmYoZAVuhtS5K7+W76KLA/+mO25yYMxHTL7x1m5Dyyde QMXQ1uXxKX92l1bgNx8C2oYrU/fHO3xusQ0ohv5YVQC2adkUhDtsPYvG9jRZNSKZ/SeK SRq+mcIV5YEN9xXYPdKZNdQjvNV3PpWquXuwCuWFUYN2xcLn3q5Ur7cwpxS3ASBMmLH9 yjPCajLLAf7rfqmUX/ERXwCdManPK3GLDcs9NpcEpBT91WmInDQanMH1rd9H4auQif94 W+ww== X-Gm-Message-State: AOAM532T3W1e0sFcYSqBNEr7qlnUVMCH49NvDIoEVnYoUkimO1yhonw1 QmDetI/dDs4mTA2KBozXNhquSlbvLKU= X-Google-Smtp-Source: ABdhPJwl6pcDop1GdGO4Cb9M9Dsjwa8SEcn5CnQdkLcnNoCGQzV5Bj0mR7LYdZNaxsMtDUxaCAAh4A== X-Received: by 2002:a7b:cb93:: with SMTP id m19mr30063317wmi.45.1607971123469; Mon, 14 Dec 2020 10:38:43 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 12/16] target/mips/translate: Extract DisasContext structure Date: Mon, 14 Dec 2020 19:37:35 +0100 Message-Id: <20201214183739.500368-13-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x335.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , kvm@vger.kernel.org, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Extract DisasContext to a new 'translate.h' header so different translation files (ISA, ASE, extensions) can use it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201207235539.4070364-2-f4bug@amsat.org> --- target/mips/translate.h | 50 +++++++++++++++++++++++++++++++++++++++++ target/mips/translate.c | 38 +------------------------------ 2 files changed, 51 insertions(+), 37 deletions(-) create mode 100644 target/mips/translate.h diff --git a/target/mips/translate.h b/target/mips/translate.h new file mode 100644 index 00000000000..fcda1a99001 --- /dev/null +++ b/target/mips/translate.h @@ -0,0 +1,50 @@ +/* + * MIPS translation routines. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#ifndef TARGET_MIPS_TRANSLATE_H +#define TARGET_MIPS_TRANSLATE_H + +#include "exec/translator.h" + +typedef struct DisasContext { + DisasContextBase base; + target_ulong saved_pc; + target_ulong page_start; + uint32_t opcode; + uint64_t insn_flags; + int32_t CP0_Config1; + int32_t CP0_Config2; + int32_t CP0_Config3; + int32_t CP0_Config5; + /* Routine used to access memory */ + int mem_idx; + MemOp default_tcg_memop_mask; + uint32_t hflags, saved_hflags; + target_ulong btarget; + bool ulri; + int kscrexist; + bool rxi; + int ie; + bool bi; + bool bp; + uint64_t PAMask; + bool mvh; + bool eva; + bool sc; + int CP0_LLAddr_shift; + bool ps; + bool vp; + bool cmgcr; + bool mrp; + bool nan2008; + bool abs2008; + bool saar; + bool mi; + int gi; +} DisasContext; + +#endif diff --git a/target/mips/translate.c b/target/mips/translate.c index 49570a95615..0db0fce3789 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -36,6 +36,7 @@ #include "exec/log.h" #include "qemu/qemu-print.h" #include "fpu_helper.h" +#include "translate.h" =20 #define MIPS_DEBUG_DISAS 0 =20 @@ -2554,43 +2555,6 @@ static TCGv mxu_CR; tcg_temp_free_i32(helper_tmp); \ } while (0) =20 -typedef struct DisasContext { - DisasContextBase base; - target_ulong saved_pc; - target_ulong page_start; - uint32_t opcode; - uint64_t insn_flags; - int32_t CP0_Config1; - int32_t CP0_Config2; - int32_t CP0_Config3; - int32_t CP0_Config5; - /* Routine used to access memory */ - int mem_idx; - MemOp default_tcg_memop_mask; - uint32_t hflags, saved_hflags; - target_ulong btarget; - bool ulri; - int kscrexist; - bool rxi; - int ie; - bool bi; - bool bp; - uint64_t PAMask; - bool mvh; - bool eva; - bool sc; - int CP0_LLAddr_shift; - bool ps; - bool vp; - bool cmgcr; - bool mrp; - bool nan2008; - bool abs2008; - bool saar; - bool mi; - int gi; -} DisasContext; - #define DISAS_STOP DISAS_TARGET_0 #define DISAS_EXIT DISAS_TARGET_1 =20 --=20 2.26.2 From nobody Sun May 5 06:21:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.65 as permitted sender) client-ip=209.85.128.65; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f65.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.65 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1607971130; cv=none; d=zohomail.com; s=zohoarc; b=YxhBS0LiaVbDybMCVZ4D5pH1Ive32EiLAkCnnC1phvWKqrT+Xla6QXf3Yd9W9ELCIist/rfD/mKxSw85RIH5eDRTjr6ydnJZPtoOIZ/npcfxLodKLQYhK6ecv1mP60575SR0LDdAnwhJOPVA+qBLlkRFIytm+x9W6N8+5wfA/Uw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607971130; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sGSxHagedQ+yelQida/tJJ2/RA7bkSvNOfSJ4MvCHXk=; b=frMJ+AGkAEGnld+HSvAujSZKAj8VDFB8StfjQErMLz1MCupxz+Wtxjenpxic7qiQW8Ff9lJ/Ehmwm0sYWVJO1Q1e4uiJ37DUQEwX6Stb+YxGsaEGtEvMy5OL0ARcs/RQgLt4ApdAjc8rwnZJx/51Z5+Il9JWCDYx+85AlO3qccg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.65 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f65.google.com (mail-wm1-f65.google.com [209.85.128.65]) by mx.zohomail.com with SMTPS id 16079711304352.567691847179276; Mon, 14 Dec 2020 10:38:50 -0800 (PST) Received: by mail-wm1-f65.google.com with SMTP id g185so16202462wmf.3 for ; Mon, 14 Dec 2020 10:38:49 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id q1sm31550246wrj.8.2020.12.14.10.38.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:38:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sGSxHagedQ+yelQida/tJJ2/RA7bkSvNOfSJ4MvCHXk=; b=PdSHiahu3St5VPIxw5aGKQa7K7soukaPOYYVdf/QPSoLLOBPUeVCn0gowQsQAr7YYE NLJhufzfKz0zIQTMtTCQ+ocR6odMrWjCl5njCq8vxlTqVrRn7MLPY/bj13uxoVZks4kZ lI+YMmJ87KZKix9XH12FDURZPfZooNyoIpqMNq9ZxMbdsm+QEKq+CJDzIkxxELwFrKdc 2E0yD6cHl61TCXsXrz+BOta+Rv8tB4cV1GGBwt2tggbizC7hTjEKeXgtgwreqtgmi4hx a7fLRTp+OcP0pDMU7cfusvzEfSGdMGQ34/dd+RypzUSU5dvpgFmrqMNDzVV8svgQVGkM wKxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=sGSxHagedQ+yelQida/tJJ2/RA7bkSvNOfSJ4MvCHXk=; b=XIoGieLmLEtuOBQ8HkBj05WHR3/bpuROPXu1Ww30/yczOC2/xPRBuRVUEaIqykTdKf 2I0P4ecQcT5wbdYj8rFR9N9rTbloDSuPI8mw55u9+tJI23583BgNU663HsWZI+KdNNF7 g83wuQs+s8/UcQ28z/Hpn2DwBb/+kIyJLpGk7UPFEH+08DZxf7L3/msNAhJFxi4iXjBh 1FfXkET98cKUZ3uHN7mIoNaS4+PFTi7w+B/TGrOc/5oaquE7/j2xtq3pyJ88i8vNkWS6 bGNfKKiopPe6JAm2JlHs5L6jdZb2j+zh0VRFYfyb/Z4Aa5MAE7ltiXJkIisV/H1vKIz3 psHQ== X-Gm-Message-State: AOAM5333EPsEcRmo1R9Pf5gCeejJMs7CPpSisrG3H9Axvg934NJLetJH y7fuIOWQIPnM2jrN9OG1MQU= X-Google-Smtp-Source: ABdhPJwlWmaCfmRQI8uZTvnZeWtXOWcn1UpyDEcuDiHJq+ZLXK9T69n/wJpn/e+Xd/au+GiANqM0BA== X-Received: by 2002:a05:600c:2255:: with SMTP id a21mr29697641wmm.122.1607971128564; Mon, 14 Dec 2020 10:38:48 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v2 13/16] target/mips/translate: Add declarations for generic code Date: Mon, 14 Dec 2020 19:37:36 +0100 Message-Id: <20201214183739.500368-14-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Some CPU translation functions / registers / macros and definitions can be used by ISA / ASE / extensions out of the big translate.c file. Declare them in "translate.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201207235539.4070364-3-f4bug@amsat.org> --- target/mips/translate.h | 38 ++++++++++++++++++++++++++++++++ target/mips/translate.c | 48 +++++++++++++---------------------------- 2 files changed, 53 insertions(+), 33 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index fcda1a99001..989d6c43207 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -10,6 +10,8 @@ =20 #include "exec/translator.h" =20 +#define MIPS_DEBUG_DISAS 0 + typedef struct DisasContext { DisasContextBase base; target_ulong saved_pc; @@ -47,4 +49,40 @@ typedef struct DisasContext { int gi; } DisasContext; =20 +/* MIPS major opcodes */ +#define MASK_OP_MAJOR(op) (op & (0x3F << 26)) + +void generate_exception_err(DisasContext *ctx, int excp, int err); +void generate_exception_end(DisasContext *ctx, int excp); +void gen_reserved_instruction(DisasContext *ctx); +void check_insn(DisasContext *ctx, uint64_t flags); +#ifdef TARGET_MIPS64 +void check_mips_64(DisasContext *ctx); +#endif + +void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offs= et); +void gen_load_gpr(TCGv t, int reg); +void gen_store_gpr(TCGv t, int reg); + +extern TCGv cpu_gpr[32], cpu_PC; +extern TCGv bcond; + +#define LOG_DISAS(...) = \ + do { = \ + if (MIPS_DEBUG_DISAS) { = \ + qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); = \ + } = \ + } while (0) + +#define MIPS_INVAL(op) = \ + do { = \ + if (MIPS_DEBUG_DISAS) { = \ + qemu_log_mask(CPU_LOG_TB_IN_ASM, = \ + TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\= n", \ + ctx->base.pc_next, ctx->opcode, op, = \ + ctx->opcode >> 26, ctx->opcode & 0x3F, = \ + ((ctx->opcode >> 16) & 0x1F)); = \ + } = \ + } while (0) + #endif diff --git a/target/mips/translate.c b/target/mips/translate.c index 0db0fce3789..318642cbcfe 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -38,11 +38,6 @@ #include "fpu_helper.h" #include "translate.h" =20 -#define MIPS_DEBUG_DISAS 0 - -/* MIPS major opcodes */ -#define MASK_OP_MAJOR(op) (op & (0x3F << 26)) - enum { /* indirect opcode tables */ OPC_SPECIAL =3D (0x00 << 26), @@ -2491,9 +2486,10 @@ enum { }; =20 /* global register indices */ -static TCGv cpu_gpr[32], cpu_PC; +TCGv cpu_gpr[32], cpu_PC; static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; -static TCGv cpu_dspctrl, btarget, bcond; +static TCGv cpu_dspctrl, btarget; +TCGv bcond; static TCGv cpu_lladdr, cpu_llval; static TCGv_i32 hflags; static TCGv_i32 fpu_fcr0, fpu_fcr31; @@ -2606,26 +2602,8 @@ static const char * const mxuregnames[] =3D { }; #endif =20 -#define LOG_DISAS(...) = \ - do { = \ - if (MIPS_DEBUG_DISAS) { = \ - qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); = \ - } = \ - } while (0) - -#define MIPS_INVAL(op) = \ - do { = \ - if (MIPS_DEBUG_DISAS) { = \ - qemu_log_mask(CPU_LOG_TB_IN_ASM, = \ - TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\= n", \ - ctx->base.pc_next, ctx->opcode, op, = \ - ctx->opcode >> 26, ctx->opcode & 0x3F, = \ - ((ctx->opcode >> 16) & 0x1F)); = \ - } = \ - } while (0) - /* General purpose registers moves. */ -static inline void gen_load_gpr(TCGv t, int reg) +void gen_load_gpr(TCGv t, int reg) { if (reg =3D=3D 0) { tcg_gen_movi_tl(t, 0); @@ -2634,7 +2612,7 @@ static inline void gen_load_gpr(TCGv t, int reg) } } =20 -static inline void gen_store_gpr(TCGv t, int reg) +void gen_store_gpr(TCGv t, int reg) { if (reg !=3D 0) { tcg_gen_mov_tl(cpu_gpr[reg], t); @@ -2763,7 +2741,7 @@ static inline void restore_cpu_state(CPUMIPSState *en= v, DisasContext *ctx) } } =20 -static inline void generate_exception_err(DisasContext *ctx, int excp, int= err) +void generate_exception_err(DisasContext *ctx, int excp, int err) { TCGv_i32 texcp =3D tcg_const_i32(excp); TCGv_i32 terr =3D tcg_const_i32(err); @@ -2779,11 +2757,16 @@ static inline void generate_exception(DisasContext = *ctx, int excp) gen_helper_0e0i(raise_exception, excp); } =20 -static inline void generate_exception_end(DisasContext *ctx, int excp) +void generate_exception_end(DisasContext *ctx, int excp) { generate_exception_err(ctx, excp, 0); } =20 +void gen_reserved_instruction(DisasContext *ctx) +{ + generate_exception_end(ctx, EXCP_RI); +} + /* Floating point register moves. */ static void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg) { @@ -3013,7 +2996,7 @@ static inline void check_dsp_r3(DisasContext *ctx) * This code generates a "reserved instruction" exception if the * CPU does not support the instruction set corresponding to flags. */ -static inline void check_insn(DisasContext *ctx, uint64_t flags) +void check_insn(DisasContext *ctx, uint64_t flags) { if (unlikely(!(ctx->insn_flags & flags))) { gen_reserved_instruction(ctx); @@ -3064,7 +3047,7 @@ static inline void check_ps(DisasContext *ctx) * This code generates a "reserved instruction" exception if 64-bit * instructions are not enabled. */ -static inline void check_mips_64(DisasContext *ctx) +void check_mips_64(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) { gen_reserved_instruction(ctx); @@ -3390,8 +3373,7 @@ OP_LD_ATOMIC(lld, ld64); #endif #undef OP_LD_ATOMIC =20 -static void gen_base_offset_addr(DisasContext *ctx, TCGv addr, - int base, int offset) +void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offs= et) { if (base =3D=3D 0) { tcg_gen_movi_tl(addr, offset); --=20 2.26.2 From nobody Sun May 5 06:21:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.66 as permitted sender) client-ip=209.85.221.66; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f66.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.66 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1607971136; cv=none; d=zohomail.com; s=zohoarc; b=MJ45Q+A9m+PdeTVT5Bn7/1c6qfAr0NPKQwQ2wkvdko+gejhXFCEbE4Et5LcjIGFmvypb08Jb1TMUMnZGdYSV+YKZIWLsFQTm7ZADREzINZTCj6CKUbyIyZ9aWyfsm8N8jwjFM0UiPZ5RWXxfjS/dgzFg+mdQ5xm9zlpL4xjHaro= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607971136; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4dvt8U31xdW0cLzHQK5e0FLr4aqxGweAhaJ4Nz2TOOo=; b=JauqKBGWiMbvCXdh2eVoNMBtvQkxNMBtd9exL9uSQZAl+5e2BuiCXtjY8ZpE9zdK/dgS1l4m0NWzq9PxLF2wazwnHOmxSpz+m8wZPVotxVH51Qqx0Z3iKG/zVzPH9uM8G5hhgcrC8hv1srXIBoMDf6Lo6t2WkRomfU3SP1KWiWA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.66 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f66.google.com (mail-wr1-f66.google.com [209.85.221.66]) by mx.zohomail.com with SMTPS id 1607971136257806.3378179084627; Mon, 14 Dec 2020 10:38:56 -0800 (PST) Received: by mail-wr1-f66.google.com with SMTP id m5so17435738wrx.9 for ; Mon, 14 Dec 2020 10:38:54 -0800 (PST) Return-Path: Return-Path: Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id a14sm24486383wrn.3.2020.12.14.10.38.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:38:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4dvt8U31xdW0cLzHQK5e0FLr4aqxGweAhaJ4Nz2TOOo=; b=hi2tvYJlNB2vVj/lqp0JJjXfK3CvJ7mehCA1FtaoWdKDufzQvsDfSCVf3jyk8G49Cz tBmTbzbVW4TDuX1TeQNHmUecO955GzCKrjWUEL0F8iecc8tCZoTd9wga/fbi6FPB+80S wWBUTrf5ELxXImCwrAxTyHtCp4efMMyhES2VLGdoU/OvKx62LMXwZz15LVQe9a/MxLIu FK0t/mhdM0Q1eyABr50xUvdk2iaQOFUsl6lzMRsPeCx5JKd7Fwwyniob6p7mlrdSsWGb chLoIZT5Z0aOeqrVELzRwWtjNET5NEJtsMA370qsJuxxhJLbhS2J7hMqXZ3c6rJeWmHK 0UBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=4dvt8U31xdW0cLzHQK5e0FLr4aqxGweAhaJ4Nz2TOOo=; b=f/fYCBVAojjUEe+tx1kWr1HlFB4yAa2Si02qd6oqeteRt5pYTt5jpBCMnooKSjDOWU fuUfnb8FVgNA9WpXFj0MKaTRXw0Sy8/NFRkUhg4RE4G+FFfZTkbYWPKK9LuyE3I6PAyg GWaaV+M1AsfTz3mJjBAhKNnfZ1nSVOGfNyGQyNJZHcgCpnvgTSEV04xTjy1zLhE2sGAG VTmvqxnjrj5XnUZsI4VfxZn7CHZfw01R0543ZjzKcT06blGJwM7DMuQjmF9GtlmL5LRU Iytlc3mJ/XYTsQJ7r2+hoU8SLxeElZNiDNH+HK/pmbQnFGtLBB7LcCJ16qRfwwT0K/+h Px4g== X-Gm-Message-State: AOAM530BcTO0Kq6dZSnGsOAPsZBQsyUq0AEApXTrgMMGbdQN6R4T9TP4 PjBa6yawvs/cacbQnHMrBGU= X-Google-Smtp-Source: ABdhPJxUp2BskZWfBzm4IefQycmoihlnmFcsBXXeNIHnDPr0rau5I3Eek3v+shwfWtIwbQYSopXo1Q== X-Received: by 2002:adf:f7d2:: with SMTP id a18mr8729982wrq.47.1607971133399; Mon, 14 Dec 2020 10:38:53 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 14/16] target/mips: Declare generic FPU functions in 'translate.h' Date: Mon, 14 Dec 2020 19:37:37 +0100 Message-Id: <20201214183739.500368-15-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Some FPU translation functions / registers can be used by ISA / ASE / extensions out of the big translate.c file. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/translate.h | 7 +++++++ target/mips/translate.c | 12 ++++++------ 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index 989d6c43207..a30fbf21ff9 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -59,12 +59,19 @@ void check_insn(DisasContext *ctx, uint64_t flags); #ifdef TARGET_MIPS64 void check_mips_64(DisasContext *ctx); #endif +void check_cp1_enabled(DisasContext *ctx); =20 void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offs= et); void gen_load_gpr(TCGv t, int reg); void gen_store_gpr(TCGv t, int reg); =20 +void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg); +void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg); +int get_fp_bit(int cc); + extern TCGv cpu_gpr[32], cpu_PC; +extern TCGv_i32 fpu_fcr0, fpu_fcr31; +extern TCGv_i64 fpu_f64[32]; extern TCGv bcond; =20 #define LOG_DISAS(...) = \ diff --git a/target/mips/translate.c b/target/mips/translate.c index 318642cbcfe..08ed542f4d4 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2492,8 +2492,8 @@ static TCGv cpu_dspctrl, btarget; TCGv bcond; static TCGv cpu_lladdr, cpu_llval; static TCGv_i32 hflags; -static TCGv_i32 fpu_fcr0, fpu_fcr31; -static TCGv_i64 fpu_f64[32]; +TCGv_i32 fpu_fcr0, fpu_fcr31; +TCGv_i64 fpu_f64[32]; static TCGv_i64 msa_wr_d[64]; =20 #if defined(TARGET_MIPS64) @@ -2809,7 +2809,7 @@ static void gen_store_fpr32h(DisasContext *ctx, TCGv_= i32 t, int reg) } } =20 -static void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) +void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) { if (ctx->hflags & MIPS_HFLAG_F64) { tcg_gen_mov_i64(t, fpu_f64[reg]); @@ -2818,7 +2818,7 @@ static void gen_load_fpr64(DisasContext *ctx, TCGv_i6= 4 t, int reg) } } =20 -static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) +void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) { if (ctx->hflags & MIPS_HFLAG_F64) { tcg_gen_mov_i64(fpu_f64[reg], t); @@ -2832,7 +2832,7 @@ static void gen_store_fpr64(DisasContext *ctx, TCGv_i= 64 t, int reg) } } =20 -static inline int get_fp_bit(int cc) +int get_fp_bit(int cc) { if (cc) { return 24 + cc; @@ -2907,7 +2907,7 @@ static inline void check_cp0_enabled(DisasContext *ct= x) } } =20 -static inline void check_cp1_enabled(DisasContext *ctx) +void check_cp1_enabled(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) { generate_exception_err(ctx, EXCP_CpU, 1); --=20 2.26.2 From nobody Sun May 5 06:21:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607972301; cv=none; d=zohomail.com; s=zohoarc; b=RIYQG3hChwLDLUpSnecCz33O+b8kdrr/AyUb4sqNGJZoiR44pzeckyLsJ7Ar+nvqKzCzvQ7zCF8swSt0FkhRsQ1FlZCLk5w2eZU4CQXzkbkyEcBCHVmIgd3/7n4h0VnFLqQFPrB4Rw92Nsi6zinEKtsB1sgbb+FMhPvG7pCMm/4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607972301; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Jefk5hCY2L0gsAzOu9EGNf66rlI9awBw/Q4VvUHWHU8=; b=Z51b693USSVIctYnNbynlJC9f1JBy+P5W+HCO7capBmhr2LQ/LsSC+C/fg8i3rQJbGsd8U/pk/iJDiNTC40jJTipFQPyrGvwOs2QcauDsDfYRwmZb+kEP/BnVT8rx7OwovyurLwKUSv03GNNZudoOhtXydppBJGvf0hLNvCVQmU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607972301824905.4414328889482; Mon, 14 Dec 2020 10:58:21 -0800 (PST) Received: from localhost ([::1]:60974 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kot35-0001wJ-6t for importer@patchew.org; Mon, 14 Dec 2020 13:58:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34702) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1koskS-0000Li-2R for qemu-devel@nongnu.org; Mon, 14 Dec 2020 13:39:06 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:34713) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1koskO-0007VK-Ul for qemu-devel@nongnu.org; Mon, 14 Dec 2020 13:39:03 -0500 Received: by mail-wr1-x444.google.com with SMTP id q18so9931235wrn.1 for ; Mon, 14 Dec 2020 10:38:59 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id m81sm33713025wmf.29.2020.12.14.10.38.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:38:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Jefk5hCY2L0gsAzOu9EGNf66rlI9awBw/Q4VvUHWHU8=; b=KRSqAzfDqntubLnrV7+aVcM6D85jfLoU1v3jbobJLTB5GK3AYEZsr0xO95KGZ5eUpu uOfAlROUvUKFHg9I0ZEwe8i9Qp0pUebmfbO/ZmsI0swpyVYtfxfBAHozlXHWVLxaIUkR 2ioe/BepV616gMyfXag+Gls7EJ3fkl5UCrmUWE7hsPHN4dbj+UsQWJ5yZnrYNlddj48e qh8Hggj7FFpT76phdy83AmWRdbJMsxzg4+bk3SsEaodxsQGEsiMZSFjLdr3VbyHGZu+J QmemRydem9eGnDIFCKmCgxRsZOj6DoSHfWagUZ+TVtIibgftPPUGA9eO5riGGjTdymQd MlVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Jefk5hCY2L0gsAzOu9EGNf66rlI9awBw/Q4VvUHWHU8=; b=rCLOXs+S8bQ+5bCOAJNzyRXiuEtXMg7SmSeqXH8WDzHbhg2a79kbJfQgfVdvHi6KyX 7ww7Sz8a+drncfhA9CahVmiRfXvQy6DSuoxUsWB8l6XG3IpOfysqVP6TMX/+/BbGdh78 LpZNHiKTbYxMya5X1MbqXLPuisbh4jlkv+IsltMhWiOegbvevgAQkEY3WvFpW3qJU2YH 0oH+2dSNAxlKVqAPEVwsAUWk/PywvkyXA0GY4dpyuue/jxVeVU8e+4WGGvhzwVJzwFBm yR05sarWyDwcg5aM/yE2CTlMd4hwylhxICfa5dA58yXAqFepaPtPxnJmGPkCI1TnfG/r 0+WA== X-Gm-Message-State: AOAM531LbU+86i1JCCkoJp8ybQjF+Ns1wUyYSrN2TNp240xQ/KNLVFgu JirB+JJN/59PNskdYlZf1Hzo6Tbc3V4= X-Google-Smtp-Source: ABdhPJx1mbrTlly834vs9hW8IPNk2JYQANfQHJCwKpzwL+rkNH34bZ9lDG+EmoX+BTQiXr+/H68p3Q== X-Received: by 2002:adf:e48d:: with SMTP id i13mr30341474wrm.48.1607971138397; Mon, 14 Dec 2020 10:38:58 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 15/16] target/mips: Extract FPU specific definitions to translate.h Date: Mon, 14 Dec 2020 19:37:38 +0100 Message-Id: <20201214183739.500368-16-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x444.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , kvm@vger.kernel.org, Huacai Chen , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Extract FPU specific definitions that can be used by ISA / ASE / extensions to translate.h header. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/translate.h | 71 +++++++++++++++++++++++++++++++++++++++++ target/mips/translate.c | 70 ---------------------------------------- 2 files changed, 71 insertions(+), 70 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index a30fbf21ff9..a9eab69249f 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -52,6 +52,77 @@ typedef struct DisasContext { /* MIPS major opcodes */ #define MASK_OP_MAJOR(op) (op & (0x3F << 26)) =20 +#define OPC_CP1 (0x11 << 26) + +/* Coprocessor 1 (rs field) */ +#define MASK_CP1(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21= ))) + +/* Values for the fmt field in FP instructions */ +enum { + /* 0 - 15 are reserved */ + FMT_S =3D 16, /* single fp */ + FMT_D =3D 17, /* double fp */ + FMT_E =3D 18, /* extended fp */ + FMT_Q =3D 19, /* quad fp */ + FMT_W =3D 20, /* 32-bit fixed */ + FMT_L =3D 21, /* 64-bit fixed */ + FMT_PS =3D 22, /* paired single fp */ + /* 23 - 31 are reserved */ +}; + +enum { + OPC_MFC1 =3D (0x00 << 21) | OPC_CP1, + OPC_DMFC1 =3D (0x01 << 21) | OPC_CP1, + OPC_CFC1 =3D (0x02 << 21) | OPC_CP1, + OPC_MFHC1 =3D (0x03 << 21) | OPC_CP1, + OPC_MTC1 =3D (0x04 << 21) | OPC_CP1, + OPC_DMTC1 =3D (0x05 << 21) | OPC_CP1, + OPC_CTC1 =3D (0x06 << 21) | OPC_CP1, + OPC_MTHC1 =3D (0x07 << 21) | OPC_CP1, + OPC_BC1 =3D (0x08 << 21) | OPC_CP1, /* bc */ + OPC_BC1ANY2 =3D (0x09 << 21) | OPC_CP1, + OPC_BC1ANY4 =3D (0x0A << 21) | OPC_CP1, + OPC_BZ_V =3D (0x0B << 21) | OPC_CP1, + OPC_BNZ_V =3D (0x0F << 21) | OPC_CP1, + OPC_S_FMT =3D (FMT_S << 21) | OPC_CP1, + OPC_D_FMT =3D (FMT_D << 21) | OPC_CP1, + OPC_E_FMT =3D (FMT_E << 21) | OPC_CP1, + OPC_Q_FMT =3D (FMT_Q << 21) | OPC_CP1, + OPC_W_FMT =3D (FMT_W << 21) | OPC_CP1, + OPC_L_FMT =3D (FMT_L << 21) | OPC_CP1, + OPC_PS_FMT =3D (FMT_PS << 21) | OPC_CP1, + OPC_BC1EQZ =3D (0x09 << 21) | OPC_CP1, + OPC_BC1NEZ =3D (0x0D << 21) | OPC_CP1, + OPC_BZ_B =3D (0x18 << 21) | OPC_CP1, + OPC_BZ_H =3D (0x19 << 21) | OPC_CP1, + OPC_BZ_W =3D (0x1A << 21) | OPC_CP1, + OPC_BZ_D =3D (0x1B << 21) | OPC_CP1, + OPC_BNZ_B =3D (0x1C << 21) | OPC_CP1, + OPC_BNZ_H =3D (0x1D << 21) | OPC_CP1, + OPC_BNZ_W =3D (0x1E << 21) | OPC_CP1, + OPC_BNZ_D =3D (0x1F << 21) | OPC_CP1, +}; + +#define MASK_CP1_FUNC(op) (MASK_CP1(op) | (op & 0x3F)) +#define MASK_BC1(op) (MASK_CP1(op) | (op & (0x3 << 16))) + +enum { + OPC_BC1F =3D (0x00 << 16) | OPC_BC1, + OPC_BC1T =3D (0x01 << 16) | OPC_BC1, + OPC_BC1FL =3D (0x02 << 16) | OPC_BC1, + OPC_BC1TL =3D (0x03 << 16) | OPC_BC1, +}; + +enum { + OPC_BC1FANY2 =3D (0x00 << 16) | OPC_BC1ANY2, + OPC_BC1TANY2 =3D (0x01 << 16) | OPC_BC1ANY2, +}; + +enum { + OPC_BC1FANY4 =3D (0x00 << 16) | OPC_BC1ANY4, + OPC_BC1TANY4 =3D (0x01 << 16) | OPC_BC1ANY4, +}; + void generate_exception_err(DisasContext *ctx, int excp, int err); void generate_exception_end(DisasContext *ctx, int excp); void gen_reserved_instruction(DisasContext *ctx); diff --git a/target/mips/translate.c b/target/mips/translate.c index 08ed542f4d4..cc876019bf7 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -43,7 +43,6 @@ enum { OPC_SPECIAL =3D (0x00 << 26), OPC_REGIMM =3D (0x01 << 26), OPC_CP0 =3D (0x10 << 26), - OPC_CP1 =3D (0x11 << 26), OPC_CP2 =3D (0x12 << 26), OPC_CP3 =3D (0x13 << 26), OPC_SPECIAL2 =3D (0x1C << 26), @@ -996,75 +995,6 @@ enum { OPC_WAIT =3D 0x20 | OPC_C0, }; =20 -/* Coprocessor 1 (rs field) */ -#define MASK_CP1(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21= ))) - -/* Values for the fmt field in FP instructions */ -enum { - /* 0 - 15 are reserved */ - FMT_S =3D 16, /* single fp */ - FMT_D =3D 17, /* double fp */ - FMT_E =3D 18, /* extended fp */ - FMT_Q =3D 19, /* quad fp */ - FMT_W =3D 20, /* 32-bit fixed */ - FMT_L =3D 21, /* 64-bit fixed */ - FMT_PS =3D 22, /* paired single fp */ - /* 23 - 31 are reserved */ -}; - -enum { - OPC_MFC1 =3D (0x00 << 21) | OPC_CP1, - OPC_DMFC1 =3D (0x01 << 21) | OPC_CP1, - OPC_CFC1 =3D (0x02 << 21) | OPC_CP1, - OPC_MFHC1 =3D (0x03 << 21) | OPC_CP1, - OPC_MTC1 =3D (0x04 << 21) | OPC_CP1, - OPC_DMTC1 =3D (0x05 << 21) | OPC_CP1, - OPC_CTC1 =3D (0x06 << 21) | OPC_CP1, - OPC_MTHC1 =3D (0x07 << 21) | OPC_CP1, - OPC_BC1 =3D (0x08 << 21) | OPC_CP1, /* bc */ - OPC_BC1ANY2 =3D (0x09 << 21) | OPC_CP1, - OPC_BC1ANY4 =3D (0x0A << 21) | OPC_CP1, - OPC_BZ_V =3D (0x0B << 21) | OPC_CP1, - OPC_BNZ_V =3D (0x0F << 21) | OPC_CP1, - OPC_S_FMT =3D (FMT_S << 21) | OPC_CP1, - OPC_D_FMT =3D (FMT_D << 21) | OPC_CP1, - OPC_E_FMT =3D (FMT_E << 21) | OPC_CP1, - OPC_Q_FMT =3D (FMT_Q << 21) | OPC_CP1, - OPC_W_FMT =3D (FMT_W << 21) | OPC_CP1, - OPC_L_FMT =3D (FMT_L << 21) | OPC_CP1, - OPC_PS_FMT =3D (FMT_PS << 21) | OPC_CP1, - OPC_BC1EQZ =3D (0x09 << 21) | OPC_CP1, - OPC_BC1NEZ =3D (0x0D << 21) | OPC_CP1, - OPC_BZ_B =3D (0x18 << 21) | OPC_CP1, - OPC_BZ_H =3D (0x19 << 21) | OPC_CP1, - OPC_BZ_W =3D (0x1A << 21) | OPC_CP1, - OPC_BZ_D =3D (0x1B << 21) | OPC_CP1, - OPC_BNZ_B =3D (0x1C << 21) | OPC_CP1, - OPC_BNZ_H =3D (0x1D << 21) | OPC_CP1, - OPC_BNZ_W =3D (0x1E << 21) | OPC_CP1, - OPC_BNZ_D =3D (0x1F << 21) | OPC_CP1, -}; - -#define MASK_CP1_FUNC(op) (MASK_CP1(op) | (op & 0x3F)) -#define MASK_BC1(op) (MASK_CP1(op) | (op & (0x3 << 16))) - -enum { - OPC_BC1F =3D (0x00 << 16) | OPC_BC1, - OPC_BC1T =3D (0x01 << 16) | OPC_BC1, - OPC_BC1FL =3D (0x02 << 16) | OPC_BC1, - OPC_BC1TL =3D (0x03 << 16) | OPC_BC1, -}; - -enum { - OPC_BC1FANY2 =3D (0x00 << 16) | OPC_BC1ANY2, - OPC_BC1TANY2 =3D (0x01 << 16) | OPC_BC1ANY2, -}; - -enum { - OPC_BC1FANY4 =3D (0x00 << 16) | OPC_BC1ANY4, - OPC_BC1TANY4 =3D (0x01 << 16) | OPC_BC1ANY4, -}; - #define MASK_CP2(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21= ))) =20 enum { --=20 2.26.2 From nobody Sun May 5 06:21:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1607972292; cv=none; d=zohomail.com; s=zohoarc; b=FT9BteQWxyOyVRfwhoA7EUE5X1lrtXqL6fjazVBEhT2lpaZKhlNmVjqfz9E8z+VaYjcBmLRQHfxSp6gF274vUQtsQLGmwyP7Y7P773dtG2ho2evI8RovJT7mwfu9JaH6aGX9jzAFP0rG0WfIwzKxOiHo3OuBg26PGzA3V6nhHks= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607972292; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3jTmKcmmqBWLYbQ1cWD989jXI7AUr/FtqoKPQ00ZpaA=; b=JsVN5eLm2wxEu88fMHuobpmM3MMJTmgh0IuSVNsuIjo22ZsFTjHH6Z2ThVv+5wZ/gGbLaQhkXFvufotsXdKv5vj02BmauNyVE5WB1wypz0CkClyvzzvkZUZptwuZ9Cv3IJJP/JHpyvuApLzOhXbbyMtdieHujeqzFNxRAZo+4EI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607972292917114.80577118885526; Mon, 14 Dec 2020 10:58:12 -0800 (PST) Received: from localhost ([::1]:51932 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kosnz-0002Fo-1t for importer@patchew.org; Mon, 14 Dec 2020 13:42:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34716) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1koskY-0000MO-KZ for qemu-devel@nongnu.org; Mon, 14 Dec 2020 13:39:12 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:45659) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1koskU-0007VW-5v for qemu-devel@nongnu.org; Mon, 14 Dec 2020 13:39:07 -0500 Received: by mail-wr1-x432.google.com with SMTP id d26so4231783wrb.12 for ; Mon, 14 Dec 2020 10:39:04 -0800 (PST) Received: from localhost.localdomain (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id 94sm33793630wrq.22.2020.12.14.10.39.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:39:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3jTmKcmmqBWLYbQ1cWD989jXI7AUr/FtqoKPQ00ZpaA=; b=DmvDAgVDk3rT6vilBmhNkckxULBIzzOM7iPzs+1pqtzygklCVwU2Nf/bxGPV3xiUth 716+qran5MG77Z410nif++Lkg66Vu6HV4Xq4NSFh7RIJHdIPP2KN2AqGn8x373KuVU60 IJu7NyQ7ckS3ymP9XbkN4e8aLmRUY9BJsX8J4PgRvbgvyu2B4olGlZjUeJOzhyndGU6c DgUeUkq1XIPAsOSlTvBNoTfr6yOlYBV2dVHq4+3SlwRwM6waQWSKpiX6/gk9EewantFS jSuVyYsL0wEy2640e0xlUkGzQ5tVXWR8Gi2/+WLarpBdiW5+zpahNBBf/kp2uPwLmarH cdrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=3jTmKcmmqBWLYbQ1cWD989jXI7AUr/FtqoKPQ00ZpaA=; b=CmMyh9IFV6kUegfiS5PsCr6eW9OI/vj14e4ojtrQ43aJl/ys3I79z18RBzqEycIMOI 7ZCHx0lqUNeCFZhBc6t+nspH/ucQfygRzMKd5Csr60g+4uNNoJxw7+qPL969tPOQ47ft 5pQad9tHxM8EP4RzaBT0sezS5fllsVhgQxjtyZT/836uyDJuI4FVHCCn3sePwWnMcEZg SOTOHb6o6gmM2uYaqZBi/nXOfYSDqBoC7u9C0jzKhh0vozgsOdQynLoYZ4gMZ4c5T4T/ o06sRMYX6RWK0oKmj+lZ8NHqUlpFmwGNWyqM5EIgBrBw5ecy7HYIBZPQYS59ckpDx9z0 1dWw== X-Gm-Message-State: AOAM531mg89YfJ9WZctSQsnq4iRiWZOHzWMCMLW9pKCkwpltf8IjicMW ki2uEfLBAN05rUSHkpvqfv1Umu2E+GE= X-Google-Smtp-Source: ABdhPJylZEZ27Ecah1UpEhdOM3kNCewD+xZzhYtp7CCr76vb0A0zPGaLnGaH25igd87RXx73ckqSKw== X-Received: by 2002:adf:dc8d:: with SMTP id r13mr30567261wrj.325.1607971143337; Mon, 14 Dec 2020 10:39:03 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 16/16] target/mips: Only build TCG code when CONFIG_TCG is set Date: Mon, 14 Dec 2020 19:37:39 +0100 Message-Id: <20201214183739.500368-17-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , kvm@vger.kernel.org, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-20-f4bug@amsat.org> --- target/mips/meson.build | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/target/mips/meson.build b/target/mips/meson.build index 5a49951c6d7..596eb1aeeb3 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -1,9 +1,11 @@ mips_ss =3D ss.source_set() mips_ss.add(files( 'cpu.c', + 'gdbstub.c', +)) +mips_ss.add(when: 'CONFIG_TCG', if_true: files( 'dsp_helper.c', 'fpu_helper.c', - 'gdbstub.c', 'lmmi_helper.c', 'msa_helper.c', 'op_helper.c', @@ -15,11 +17,13 @@ mips_softmmu_ss =3D ss.source_set() mips_softmmu_ss.add(files( 'addr.c', - 'cp0_helper.c', 'cp0_timer.c', 'machine.c', 'mips-semi.c', )) +mips_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files( + 'cp0_helper.c', +)) =20 target_arch +=3D {'mips': mips_ss} target_softmmu_arch +=3D {'mips': mips_softmmu_ss} --=20 2.26.2