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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id v189sm28388850wmg.14.2020.12.13.12.21.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:21:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IDtGX2egqT20QSVpEfuV5BUBIdAjxxq0FJmWInmLOws=; b=Rxe8/tK8x4o7R657Ex50CPpjB7/EeLZSFOP/XW+Mp4GBXVOrmqCRbWCxCDTTx9gQik x0rBQFDVRBfCSceRMW6vr0zWpwdDCV5lTNHemp/PDmd2xIab4knatraB71vETXn7AK7P RaNYEktPRVo/AgDkUZkmq+4gZV7c0YwWEqxeNLxTR7RWm5qW/1YAY7u+bn3Syll+J/G/ qr5Onq688Qk5UTFBdCX/MytWg0Esf5gND5ozdRUZFhagfjUrlaf79+cD6Sr+9UyKaJqk GDbwH1buILB/J3O50q+c6kXzfv2nc/cn2hPveeyXR0JTBMuhp0slv+HJywc43jEmgZta /X/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=IDtGX2egqT20QSVpEfuV5BUBIdAjxxq0FJmWInmLOws=; b=RoS8jEvuCG8IHOKmf1oFBDERA1dpqGKIBYwnhpfn2rPgkTbOV8QltVGGLuCB4aSVRX T3bHxaaZIIbCPtrsppN+RUB1HIcugztoK4oXnvWmZg6OUoHsX0tpVY4crZcHxI7PlTB5 gwjhz6KaVPGHxY4h9b22CGUvcPkouKkkak22H0xn2bqFzE4tu0GvUyQ0cPOv9Prjw/yJ 86fW3ZIkQpNnQh78Mr+bOAgOocuJs26+xrQ+SaYoJBqOVQ6Y/WoTqQY3mlDe8ztQSrCo NRtSVfUvtNM+7e9ETQYsSvs2xHN0xK3bMtlRsScJLyo36iS4+OUJaNo/VzmgWtlZE7ri ATDQ== X-Gm-Message-State: AOAM530xMtZKODPOnLDxBYpjUM48XiIUnpgaVX6PGdonp/7fvfuU48Al F4mC8dczSXwQboleU5m6tM8= X-Google-Smtp-Source: ABdhPJw978QeLLZUhsM1IEM53GS3n3KXCYYFMbTvhHOFyz2/tV3RpsUG9gPyUqOu8SIdUbYNfVOzxA== X-Received: by 2002:a05:600c:211:: with SMTP id 17mr24471325wmi.84.1607890893645; Sun, 13 Dec 2020 12:21:33 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Richard Henderson Subject: [PULL 21/26] target/mips: Extract cpu_supports*/cpu_set* translate.c Date: Sun, 13 Dec 2020 21:19:41 +0100 Message-Id: <20201213201946.236123-22-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Move cpu_supports*() and cpu_set_exception_base() from translate.c to cpu.c. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201206233949.3783184-9-f4bug@amsat.org> --- target/mips/cpu.c | 18 ++++++++++++++++++ target/mips/translate.c | 18 ------------------ 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 9d7edc1ca21..3024c51a211 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -315,3 +315,21 @@ bool cpu_supports_isa(const CPUMIPSState *env, uint64_= t isa_mask) { return (env->cpu_model->insn_flags & isa_mask) !=3D 0; } + +bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa) +{ + const MIPSCPUClass *mcc =3D MIPS_CPU_CLASS(object_class_by_name(cpu_ty= pe)); + return (mcc->cpu_def->insn_flags & isa) !=3D 0; +} + +bool cpu_type_supports_cps_smp(const char *cpu_type) +{ + const MIPSCPUClass *mcc =3D MIPS_CPU_CLASS(object_class_by_name(cpu_ty= pe)); + return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) !=3D 0; +} + +void cpu_set_exception_base(int vp_index, target_ulong address) +{ + MIPSCPU *vp =3D MIPS_CPU(qemu_get_cpu(vp_index)); + vp->env.exception_base =3D address; +} diff --git a/target/mips/translate.c b/target/mips/translate.c index ccc82abce04..84d2d44e5d5 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31766,24 +31766,6 @@ void cpu_mips_realize_env(CPUMIPSState *env) mvp_init(env); } =20 -bool cpu_type_supports_cps_smp(const char *cpu_type) -{ - const MIPSCPUClass *mcc =3D MIPS_CPU_CLASS(object_class_by_name(cpu_ty= pe)); - return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) !=3D 0; -} - -bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa) -{ - const MIPSCPUClass *mcc =3D MIPS_CPU_CLASS(object_class_by_name(cpu_ty= pe)); - return (mcc->cpu_def->insn_flags & isa) !=3D 0; -} - -void cpu_set_exception_base(int vp_index, target_ulong address) -{ - MIPSCPU *vp =3D MIPS_CPU(qemu_get_cpu(vp_index)); - vp->env.exception_base =3D address; -} - void cpu_state_reset(CPUMIPSState *env) { CPUState *cs =3D env_cpu(env); --=20 2.26.2