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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id h184sm28789455wmh.23.2020.12.13.12.21.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Dec 2020 12:21:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BwBCSJKUs74AgI90rgGgJ5DnyTy76Cwmh6AmTQxT6D8=; b=mrwpFWGC/8qrenEQFhf/VblmOHmQoA6rejjcRRVDeYwpRb49BQO8vN8IeucQNyvrtF f8YuxMsC/iKs1KnLM42AK032qwQW6l08i6+WiyZDZK6g6QWF4NM+9+VGOd3vLxmT/7Qi ccFby7l/TiVjCbtXYXFPy+2pgJoFqeSrI59iqIwfv3HsS6nVHPMaVXFf5lZVFu7AX39r jWGdRsJxAltvakb4Mt5uDaC8KH3wT0ikuaV+GraTYk0xm8X5YbCOlXXnM2oGq16xiT8y vnVMGbcFrCJe28hJIbBHmyESd2jtuTxLLL7rxUCjjEMqKleKO1LzwlpHA9T4SRG4Yxtb dHww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=BwBCSJKUs74AgI90rgGgJ5DnyTy76Cwmh6AmTQxT6D8=; b=bb3bNh3o1ZXS6Cxht7xdc7KzCrSflzgtqJ+Y2uD217m09r+pJxhBj+qMt/CPsKdDPj P0q3QFWw5gHZFbVGJuLa7YbPoTAVMLu4QOavsUbDUl+JeIeU7boeVCgkT0cHIZr5CZm6 b+lqa+JWrQ0C/OiPwaD9a+3PVm5QyRCeLgjdYKiQu/RuQt13jGdZTaFoT06PUvlhyzyO gr9MpCOq1X+CG/LhZpceo7SXR+Be4SDdz5/7+cBuvEVxfr/bAbzqpVo5sw0TW0gruot5 eU7UOonGLWlZDD2FqHQgouU0DxmZiJ9TH4ZmnpPJxcNAK1z6bhMt294A86AhcETEGhTK xcmQ== X-Gm-Message-State: AOAM532acnkz8In94j3Gw3j5flBtCSEDFXuNWpS5Drhlzzzu4HnpY8Yu v0lAv9iEKqcmF/zPxqeL79Q= X-Google-Smtp-Source: ABdhPJyjCdeXDlFSxrZSqJn/AgC7v3c15fguzRGYdbHseBQtSeIjGz1sP0ZJiYfQIPcPfGi/6wFVDw== X-Received: by 2002:a1c:2288:: with SMTP id i130mr24700600wmi.78.1607890873572; Sun, 13 Dec 2020 12:21:13 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno , Aleksandar Rikalo , kvm@vger.kernel.org, Jiaxun Yang , Huacai Chen , Paul Burton , Richard Henderson Subject: [PULL 17/26] target/mips: Introduce ase_mt_available() helper Date: Sun, 13 Dec 2020 21:19:37 +0100 Message-Id: <20201213201946.236123-18-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201213201946.236123-1-f4bug@amsat.org> References: <20201213201946.236123-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Instead of accessing CP0_Config3 directly and checking the 'Multi-Threading Present' bit, introduce an helper to simplify code review. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201204222622.2743175-3-f4bug@amsat.org> --- target/mips/cpu.h | 7 +++++++ hw/mips/cps.c | 3 +-- target/mips/cp0_helper.c | 2 +- target/mips/cpu.c | 2 +- target/mips/helper.c | 2 +- target/mips/translate.c | 2 +- 6 files changed, 12 insertions(+), 6 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 5d3b2a01c01..3ac21d0e9c0 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1289,6 +1289,13 @@ int cpu_mips_signal_handler(int host_signum, void *p= info, void *puc); bool cpu_type_supports_cps_smp(const char *cpu_type); bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask); bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa); + +/* Check presence of multi-threading ASE implementation */ +static inline bool ase_mt_available(CPUMIPSState *env) +{ + return env->CP0_Config3 & (1 << CP0C3_MT); +} + void cpu_set_exception_base(int vp_index, target_ulong address); =20 /* addr.c */ diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 962b1b0b87c..7a0d289efaf 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -58,8 +58,7 @@ static void main_cpu_reset(void *opaque) =20 static bool cpu_mips_itu_supported(CPUMIPSState *env) { - bool is_mt =3D (env->CP0_Config5 & (1 << CP0C5_VP)) || - (env->CP0_Config3 & (1 << CP0C3_MT)); + bool is_mt =3D (env->CP0_Config5 & (1 << CP0C5_VP)) || ase_mt_availabl= e(env); =20 return is_mt && !kvm_enabled(); } diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c index cb899fe3d73..36a92857bfb 100644 --- a/target/mips/cp0_helper.c +++ b/target/mips/cp0_helper.c @@ -1164,7 +1164,7 @@ void helper_mtc0_entryhi(CPUMIPSState *env, target_ul= ong arg1) old =3D env->CP0_EntryHi; val =3D (arg1 & mask) | (old & ~mask); env->CP0_EntryHi =3D val; - if (env->CP0_Config3 & (1 << CP0C3_MT)) { + if (ase_mt_available(env)) { sync_c0_entryhi(env, env->current_tc); } /* If the ASID changes, flush qemu's TLB. */ diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 687e2680dd1..9d7edc1ca21 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -74,7 +74,7 @@ static bool mips_cpu_has_work(CPUState *cs) } =20 /* MIPS-MT has the ability to halt the CPU. */ - if (env->CP0_Config3 & (1 << CP0C3_MT)) { + if (ase_mt_available(env)) { /* * The QEMU model will issue an _WAKE request whenever the CPUs * should be woken up. diff --git a/target/mips/helper.c b/target/mips/helper.c index 59de58fcbc9..0c657865793 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -419,7 +419,7 @@ void cpu_mips_store_status(CPUMIPSState *env, target_ul= ong val) tlb_flush(env_cpu(env)); } #endif - if (env->CP0_Config3 & (1 << CP0C3_MT)) { + if (ase_mt_available(env)) { sync_c0_status(env, env, env->current_tc); } else { compute_hflags(env); diff --git a/target/mips/translate.c b/target/mips/translate.c index f218997f049..ccc82abce04 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31917,7 +31917,7 @@ void cpu_state_reset(CPUMIPSState *env) =20 cpu_mips_store_count(env, 1); =20 - if (env->CP0_Config3 & (1 << CP0C3_MT)) { + if (ase_mt_available(env)) { int i; =20 /* Only TC0 on VPE 0 starts as active. */ --=20 2.26.2