From nobody Fri May 17 10:34:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607732448; cv=none; d=zohomail.com; s=zohoarc; b=NiYhYTc665jsPLafOpgIK1v41r/tMZUaJT6sOQuHsxQH88Pf7dfwG//fCFa3qgvmjQH4okHQXwRGvqYEYWWXDKl/OSVWDgrV3w5LGvdJYWCCLgDJDSTFW1G+SVJtFbmO6hX+VCreojPCHeIP+K/m+kTnOlnEQj+ypA6UzGNl8z4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607732448; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=otGyI9nN7HYyHPl1jamkl/dEV8++zNkKNYJN5ml5WUc=; b=dQjDCvEtFFy3m5XIVGK4ErNB6ULj6fyugwVDgVbHg/jAPTxIStYk4aOPLMbkHtESgLfTHvHCe/Y3IRxaP6Y5r5ccxt44YfawGwnMBzEt0MsXafVX2ar3s6pLREm0OKU6BDKLwmyp4HOeaeHsxIa+m35FiKZW6JApe5Qg7WtL0d8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607732448738276.7651718759016; Fri, 11 Dec 2020 16:20:48 -0800 (PST) Received: from localhost ([::1]:45966 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knseV-0005aG-K5 for importer@patchew.org; Fri, 11 Dec 2020 19:20:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36466) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knsZe-0002ZN-Bl for qemu-devel@nongnu.org; Fri, 11 Dec 2020 19:15:46 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:36680) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knsZb-0005cl-IA for qemu-devel@nongnu.org; Fri, 11 Dec 2020 19:15:46 -0500 Received: by mail-wr1-x441.google.com with SMTP id t16so10686683wra.3 for ; Fri, 11 Dec 2020 16:15:43 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d8sm16306001wmb.11.2020.12.11.16.15.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Dec 2020 16:15:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=otGyI9nN7HYyHPl1jamkl/dEV8++zNkKNYJN5ml5WUc=; b=gtfpk4xp3kE049J6nTjEo2fKokcEwjkVZyQJsXocYL+xbHpU59nmru0HePMcS/+jLv Z8yrzQ6zvr8ytBQ9LI45PP/twfO8U8BN36zmVelGWjcQLX4KzkNtP83JBMkR7HIK1sMi WZHlflH5p78mb2zDC9BSTG5dso3YgjNuKXTJpYyRgeV579I2T4rRroHf5RIfQ2QU8i2M zFemYkMg0L4rmnGXyA29pXJFb8xLILBpu/oFMdl8BEihItWL+nfyQkpXJwatmh3+Gwd5 KKkWNa2MUXV6s6nFzExbQyCAf0yNgDAdJiDZu8uR7mnUa/DnD9cp/TSUPadNcuyiIY27 dE6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=otGyI9nN7HYyHPl1jamkl/dEV8++zNkKNYJN5ml5WUc=; b=BLSCUi9mNTO7EKAhZl54klskZAWzyxzwt1Jp+BnLG3DcxXvSuaQq6k743JM8/MaFUq yNp1njsXmzJwPpdKiK706pVaxse3JGQk0p+Z6MJWrpev2IfD3Te0tm87LFjJ9PVOb5q+ KUaXNaMa4zU0XKJBNwwTl4bVjL7Tc8Jcg7WmGSUwZlelZ+nnSJPmxevUlXLRaswWESdU Yo00HsccQ4VN+y6YXHOH1b7tOnMlqb/01tPgC92tUrSBQMM21lK1W0I6sjoYKOTQ9aYS qG+jS/co6k0wvmmJNjxY7JIELbamKcnrMkVyMh0mc1rIyaS3MWxcgFmz0VxffJt7RjTv NqMg== X-Gm-Message-State: AOAM533Bwr22TIH4Q8BkYK7/qgZhcQk83dLEO4bY9HstkxhYuwCSEl1t o6LSyf9mA+0+D9XnWkkJ6P2dktkQI8ithQ== X-Google-Smtp-Source: ABdhPJzFN/r2eYROOAEVr30/k1Pru23Cb6PYpxwq4FL8YPjtCxUdFKP0DtGPRbTFu+Po4yxS0Fz5SQ== X-Received: by 2002:adf:cd8f:: with SMTP id q15mr16028694wrj.79.1607732141592; Fri, 11 Dec 2020 16:15:41 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 1/8] hw/ppc/ppc4xx_devs: Make code style fixes to UIC code Date: Sat, 12 Dec 2020 00:15:30 +0000 Message-Id: <20201212001537.24520-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201212001537.24520-1-peter.maydell@linaro.org> References: <20201212001537.24520-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x441.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" In a following commit we will move the PPC UIC implementation to its own file in hw/intc. To prevent checkpatch complaining about that code-motion, fix up the minor style issues first. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth Tested-by: Edgar E. Iglesias --- hw/ppc/ppc4xx_devs.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index f1651e04d9a..f2f9ca4ffec 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -105,7 +105,7 @@ struct ppcuic_t { qemu_irq *irqs; }; =20 -static void ppcuic_trigger_irq (ppcuic_t *uic) +static void ppcuic_trigger_irq(ppcuic_t *uic) { uint32_t ir, cr; int start, end, inc, i; @@ -156,26 +156,28 @@ static void ppcuic_trigger_irq (ppcuic_t *uic) } } =20 -static void ppcuic_set_irq (void *opaque, int irq_num, int level) +static void ppcuic_set_irq(void *opaque, int irq_num, int level) { ppcuic_t *uic; uint32_t mask, sr; =20 uic =3D opaque; - mask =3D 1U << (31-irq_num); + mask =3D 1U << (31 - irq_num); LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32 " mask %08" PRIx32 " =3D> %08" PRIx32 " %08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, mask, uic->uicsr & mask, level << irq_num); - if (irq_num < 0 || irq_num > 31) + if (irq_num < 0 || irq_num > 31) { return; + } sr =3D uic->uicsr; =20 /* Update status register */ if (uic->uictr & mask) { /* Edge sensitive interrupt */ - if (level =3D=3D 1) + if (level =3D=3D 1) { uic->uicsr |=3D mask; + } } else { /* Level sensitive interrupt */ if (level =3D=3D 1) { @@ -188,11 +190,12 @@ static void ppcuic_set_irq (void *opaque, int irq_num= , int level) } LOG_UIC("%s: irq %d level %d sr %" PRIx32 " =3D> " "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, s= r); - if (sr !=3D uic->uicsr) + if (sr !=3D uic->uicsr) { ppcuic_trigger_irq(uic); + } } =20 -static uint32_t dcr_read_uic (void *opaque, int dcrn) +static uint32_t dcr_read_uic(void *opaque, int dcrn) { ppcuic_t *uic; uint32_t ret; @@ -220,13 +223,15 @@ static uint32_t dcr_read_uic (void *opaque, int dcrn) ret =3D uic->uicsr & uic->uicer; break; case DCR_UICVR: - if (!uic->use_vectors) + if (!uic->use_vectors) { goto no_read; + } ret =3D uic->uicvr; break; case DCR_UICVCR: - if (!uic->use_vectors) + if (!uic->use_vectors) { goto no_read; + } ret =3D uic->uicvcr; break; default: @@ -238,7 +243,7 @@ static uint32_t dcr_read_uic (void *opaque, int dcrn) return ret; } =20 -static void dcr_write_uic (void *opaque, int dcrn, uint32_t val) +static void dcr_write_uic(void *opaque, int dcrn, uint32_t val) { ppcuic_t *uic; =20 --=20 2.20.1 From nobody Fri May 17 10:34:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607732383; cv=none; d=zohomail.com; s=zohoarc; b=bLMeUsvcOVunLRi2/IV9Qz6pceuNo2EoZAY2Teg7UBGMX6N+XqNM6nJdNo6EYalN/E+7WDxY+Fv/2Ya0smbF5j7N5UFRaPO9HCudtJj3ST2cqyaczm7OlnehzVaBzMUSZYEY7OgHjp1YjciJdZqe3P918afk3MiFhF4qkrBXlIQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607732383; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=g0YzhKcRU24hbedNmOgpxPIUxP0O8MS4t/jU8bagqDc=; b=dYu36IHwxjZj/DEJWFxINM+WZd8rKj98h1SI4vxt2v9Ug6nXvvtKOMNN0tgfQtqUi7nThTVk1ebDgTj40hQ1CeimQVySrGYdjRqdlSt6BcybfNljjjMGWTIuwaUNsnKAtlCqLy0RJVf0qBLjV7wYeXgRTyXrlxBYCtNtdbB1gro= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607732383062800.4962981627331; Fri, 11 Dec 2020 16:19:43 -0800 (PST) Received: from localhost ([::1]:43820 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knsdQ-0004eB-Mf for importer@patchew.org; Fri, 11 Dec 2020 19:19:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36556) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knsZm-0002bl-WF for qemu-devel@nongnu.org; Fri, 11 Dec 2020 19:15:56 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:46600) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knsZe-0005dy-9o for qemu-devel@nongnu.org; Fri, 11 Dec 2020 19:15:54 -0500 Received: by mail-wr1-x432.google.com with SMTP id a11so2953072wrr.13 for ; Fri, 11 Dec 2020 16:15:44 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d8sm16306001wmb.11.2020.12.11.16.15.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Dec 2020 16:15:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=g0YzhKcRU24hbedNmOgpxPIUxP0O8MS4t/jU8bagqDc=; b=eT79VJkqspRQHKN3/iD2NJBuY2WkIk02+ysF71wDNOcmUKSE4lTsJu53ZwLBGwDOTJ iWbgpe1jMs4O5cnDkZUzTc+REwSzBd1hplUJsZ4ZT6+lu08UURF1yBT2l4rK2Zav9GLY 6gQOC74/hIj0cw5OjpdAj+e0QBsRCYG1BLCzYe/sJl/CCoF7v/FWQAhlIy2VZ7L8wNgg bGE+zlNCtPWQdLFT5EORVKk4ppybIiVcAbei4Uu7bjCgHJ/H1GNIiRKc4MfEKXwPUEsx tXRGnGefafOeuFfe79N2yyXFJX8dqUh1YBvYRYs3Z1S8jQFflgYUptp5cCtnq3vGRlLJ Nglw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=g0YzhKcRU24hbedNmOgpxPIUxP0O8MS4t/jU8bagqDc=; b=N0V75/AVPAa3ijKvX+kCvu1fSA86QkZ7TONiE78ox2C4znDvkwZGI+Dx5/H03ZcQAW +1vji4Js4qRbSXzA9Km0HU1ZTH7HgaphTiFEY2SMvCwCCU/2ZTreTuj6s1r/fEpLTkK2 H6sQc8fCX4cPKJeGl5ENqzRBpLslhWWC8u515xnkKLQ3CYRRSB3S6QOLx3G8/pCua/5v /wjbRhrZTL2rQ2fCutxhHM1C/taqWI3A7Ph/YitTauN5jT3JmHLLC5/pKDfzPV0BRs1x 9BBg15OWPaA07W9vwHlsMiwmUNFcGbSX5J+gPqkWFSAor1TQ961PZV6BrLxvqj/Z177d t2Vw== X-Gm-Message-State: AOAM533qN7/bPuIdtl2C7/pRtWAYUaJTbeeuFxmFbNOuyIRhNCZbLlGv teEHoyaIQDxkBQ2+8Bb61K/LKZuRh+J8jg== X-Google-Smtp-Source: ABdhPJx94nmYaDWFBcDB1IFPkTa+lRvEaiiSZWtWCDNa2REAC6qK0e0lkVvy/ccDdivQ2tpfUeAkrg== X-Received: by 2002:a05:6000:185:: with SMTP id p5mr15559360wrx.403.1607732143155; Fri, 11 Dec 2020 16:15:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 2/8] ppc: Convert PPC UIC to a QOM device Date: Sat, 12 Dec 2020 00:15:31 +0000 Message-Id: <20201212001537.24520-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201212001537.24520-1-peter.maydell@linaro.org> References: <20201212001537.24520-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Currently the PPC UIC ("Universal Interrupt Controller") is implemented as a non-QOM device in ppc4xx_devs.c. Convert it to a proper QOM device in hw/intc. The ppcuic_init() function is retained for the moment with its current interface; in subsequent commits this will be tidied up to avoid the allocation of an irq array. This conversion adds VMState support. It leaves the LOG_UIC() macro as-is to maximise the extent to which this is simply code-movement rather than a rewrite (in new code it would be better to use tracepoints). The default property values for dcr-base and use-vectors are set to match those use by most of our boards with a UIC. Signed-off-by: Peter Maydell Reviewed-by: BALATON Zoltan Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias --- include/hw/intc/ppc-uic.h | 73 +++++++++ hw/intc/ppc-uic.c | 321 ++++++++++++++++++++++++++++++++++++++ hw/ppc/ppc4xx_devs.c | 267 ++++--------------------------- MAINTAINERS | 2 + hw/intc/Kconfig | 3 + hw/intc/meson.build | 1 + hw/ppc/Kconfig | 1 + 7 files changed, 431 insertions(+), 237 deletions(-) create mode 100644 include/hw/intc/ppc-uic.h create mode 100644 hw/intc/ppc-uic.c diff --git a/include/hw/intc/ppc-uic.h b/include/hw/intc/ppc-uic.h new file mode 100644 index 00000000000..e614e2ffd80 --- /dev/null +++ b/include/hw/intc/ppc-uic.h @@ -0,0 +1,73 @@ +/* + * "Universal" Interrupt Controller for PowerPPC 4xx embedded processors + * + * Copyright (c) 2007 Jocelyn Mayer + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HW_INTC_PPC_UIC_H +#define HW_INTC_PPC_UIC_H + +#include "hw/sysbus.h" +#include "qom/object.h" + +#define TYPE_PPC_UIC "ppc-uic" +OBJECT_DECLARE_SIMPLE_TYPE(PPCUIC, PPC_UIC) + +/* + * QEMU interface: + * QOM property "cpu": link to the PPC CPU + * (no default, must be set) + * QOM property "dcr-base": base of the bank of DCR registers for the UIC + * (default 0x30) + * QOM property "use-vectors": true if the UIC has vector registers + * (default true) + * unnamed GPIO inputs 0..UIC_MAX_IRQ: input IRQ lines + * sysbus IRQs: + * 0 (PPCUIC_OUTPUT_INT): output INT line to the CPU + * 1 (PPCUIC_OUTPUT_CINT): output CINT line to the CPU + */ + +#define UIC_MAX_IRQ 32 + +struct PPCUIC { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + qemu_irq output_int; + qemu_irq output_cint; + + /* properties */ + CPUState *cpu; + uint32_t dcr_base; + bool use_vectors; + + uint32_t level; /* Remembers the state of level-triggered interrupts.= */ + uint32_t uicsr; /* Status register */ + uint32_t uicer; /* Enable register */ + uint32_t uiccr; /* Critical register */ + uint32_t uicpr; /* Polarity register */ + uint32_t uictr; /* Triggering register */ + uint32_t uicvcr; /* Vector configuration register */ + uint32_t uicvr; +}; + +#endif diff --git a/hw/intc/ppc-uic.c b/hw/intc/ppc-uic.c new file mode 100644 index 00000000000..b21951eea83 --- /dev/null +++ b/hw/intc/ppc-uic.c @@ -0,0 +1,321 @@ +/* + * "Universal" Interrupt Controller for PowerPPC 4xx embedded processors + * + * Copyright (c) 2007 Jocelyn Mayer + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "include/hw/intc/ppc-uic.h" +#include "hw/irq.h" +#include "cpu.h" +#include "hw/ppc/ppc.h" +#include "hw/qdev-properties.h" +#include "migration/vmstate.h" +#include "qapi/error.h" + +enum { + DCR_UICSR =3D 0x000, + DCR_UICSRS =3D 0x001, + DCR_UICER =3D 0x002, + DCR_UICCR =3D 0x003, + DCR_UICPR =3D 0x004, + DCR_UICTR =3D 0x005, + DCR_UICMSR =3D 0x006, + DCR_UICVR =3D 0x007, + DCR_UICVCR =3D 0x008, + DCR_UICMAX =3D 0x009, +}; + +/*#define DEBUG_UIC*/ + +#ifdef DEBUG_UIC +# define LOG_UIC(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__) +#else +# define LOG_UIC(...) do { } while (0) +#endif + +static void ppcuic_trigger_irq(PPCUIC *uic) +{ + uint32_t ir, cr; + int start, end, inc, i; + + /* Trigger interrupt if any is pending */ + ir =3D uic->uicsr & uic->uicer & (~uic->uiccr); + cr =3D uic->uicsr & uic->uicer & uic->uiccr; + LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32 + " uiccr %08" PRIx32 "\n" + " %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n", + __func__, uic->uicsr, uic->uicer, uic->uiccr, + uic->uicsr & uic->uicer, ir, cr); + if (ir !=3D 0x0000000) { + LOG_UIC("Raise UIC interrupt\n"); + qemu_irq_raise(uic->output_int); + } else { + LOG_UIC("Lower UIC interrupt\n"); + qemu_irq_lower(uic->output_int); + } + /* Trigger critical interrupt if any is pending and update vector */ + if (cr !=3D 0x0000000) { + qemu_irq_raise(uic->output_cint); + if (uic->use_vectors) { + /* Compute critical IRQ vector */ + if (uic->uicvcr & 1) { + start =3D 31; + end =3D 0; + inc =3D -1; + } else { + start =3D 0; + end =3D 31; + inc =3D 1; + } + uic->uicvr =3D uic->uicvcr & 0xFFFFFFFC; + for (i =3D start; i <=3D end; i +=3D inc) { + if (cr & (1 << i)) { + uic->uicvr +=3D (i - start) * 512 * inc; + break; + } + } + } + LOG_UIC("Raise UIC critical interrupt - " + "vector %08" PRIx32 "\n", uic->uicvr); + } else { + LOG_UIC("Lower UIC critical interrupt\n"); + qemu_irq_lower(uic->output_cint); + uic->uicvr =3D 0x00000000; + } +} + +static void ppcuic_set_irq(void *opaque, int irq_num, int level) +{ + PPCUIC *uic; + uint32_t mask, sr; + + uic =3D opaque; + mask =3D 1U << (31 - irq_num); + LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32 + " mask %08" PRIx32 " =3D> %08" PRIx32 " %08" PRIx32 "\n", + __func__, irq_num, level, + uic->uicsr, mask, uic->uicsr & mask, level << irq_num); + if (irq_num < 0 || irq_num > 31) { + return; + } + sr =3D uic->uicsr; + + /* Update status register */ + if (uic->uictr & mask) { + /* Edge sensitive interrupt */ + if (level =3D=3D 1) { + uic->uicsr |=3D mask; + } + } else { + /* Level sensitive interrupt */ + if (level =3D=3D 1) { + uic->uicsr |=3D mask; + uic->level |=3D mask; + } else { + uic->uicsr &=3D ~mask; + uic->level &=3D ~mask; + } + } + LOG_UIC("%s: irq %d level %d sr %" PRIx32 " =3D> " + "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, s= r); + if (sr !=3D uic->uicsr) { + ppcuic_trigger_irq(uic); + } +} + +static uint32_t dcr_read_uic(void *opaque, int dcrn) +{ + PPCUIC *uic; + uint32_t ret; + + uic =3D opaque; + dcrn -=3D uic->dcr_base; + switch (dcrn) { + case DCR_UICSR: + case DCR_UICSRS: + ret =3D uic->uicsr; + break; + case DCR_UICER: + ret =3D uic->uicer; + break; + case DCR_UICCR: + ret =3D uic->uiccr; + break; + case DCR_UICPR: + ret =3D uic->uicpr; + break; + case DCR_UICTR: + ret =3D uic->uictr; + break; + case DCR_UICMSR: + ret =3D uic->uicsr & uic->uicer; + break; + case DCR_UICVR: + if (!uic->use_vectors) { + goto no_read; + } + ret =3D uic->uicvr; + break; + case DCR_UICVCR: + if (!uic->use_vectors) { + goto no_read; + } + ret =3D uic->uicvcr; + break; + default: + no_read: + ret =3D 0x00000000; + break; + } + + return ret; +} + +static void dcr_write_uic(void *opaque, int dcrn, uint32_t val) +{ + PPCUIC *uic; + + uic =3D opaque; + dcrn -=3D uic->dcr_base; + LOG_UIC("%s: dcr %d val 0x%x\n", __func__, dcrn, val); + switch (dcrn) { + case DCR_UICSR: + uic->uicsr &=3D ~val; + uic->uicsr |=3D uic->level; + ppcuic_trigger_irq(uic); + break; + case DCR_UICSRS: + uic->uicsr |=3D val; + ppcuic_trigger_irq(uic); + break; + case DCR_UICER: + uic->uicer =3D val; + ppcuic_trigger_irq(uic); + break; + case DCR_UICCR: + uic->uiccr =3D val; + ppcuic_trigger_irq(uic); + break; + case DCR_UICPR: + uic->uicpr =3D val; + break; + case DCR_UICTR: + uic->uictr =3D val; + ppcuic_trigger_irq(uic); + break; + case DCR_UICMSR: + break; + case DCR_UICVR: + break; + case DCR_UICVCR: + uic->uicvcr =3D val & 0xFFFFFFFD; + ppcuic_trigger_irq(uic); + break; + } +} + +static void ppc_uic_reset(DeviceState *dev) +{ + PPCUIC *uic =3D PPC_UIC(dev); + + uic->uiccr =3D 0x00000000; + uic->uicer =3D 0x00000000; + uic->uicpr =3D 0x00000000; + uic->uicsr =3D 0x00000000; + uic->uictr =3D 0x00000000; + if (uic->use_vectors) { + uic->uicvcr =3D 0x00000000; + uic->uicvr =3D 0x0000000; + } +} + +static void ppc_uic_realize(DeviceState *dev, Error **errp) +{ + PPCUIC *uic =3D PPC_UIC(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + PowerPCCPU *cpu; + int i; + + if (!uic->cpu) { + /* This is a programming error in the code using this device */ + error_setg(errp, "ppc-uic 'cpu' link property was not set"); + return; + } + + cpu =3D POWERPC_CPU(uic->cpu); + for (i =3D 0; i < DCR_UICMAX; i++) { + ppc_dcr_register(&cpu->env, uic->dcr_base + i, uic, + &dcr_read_uic, &dcr_write_uic); + } + + sysbus_init_irq(sbd, &uic->output_int); + sysbus_init_irq(sbd, &uic->output_cint); + qdev_init_gpio_in(dev, ppcuic_set_irq, UIC_MAX_IRQ); +} + +static Property ppc_uic_properties[] =3D { + DEFINE_PROP_LINK("cpu", PPCUIC, cpu, TYPE_CPU, CPUState *), + DEFINE_PROP_UINT32("dcr-base", PPCUIC, dcr_base, 0x30), + DEFINE_PROP_BOOL("use-vectors", PPCUIC, use_vectors, true), + DEFINE_PROP_END_OF_LIST() +}; + +static const VMStateDescription ppc_uic_vmstate =3D { + .name =3D "ppc-uic", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(level, PPCUIC), + VMSTATE_UINT32(uicsr, PPCUIC), + VMSTATE_UINT32(uicer, PPCUIC), + VMSTATE_UINT32(uiccr, PPCUIC), + VMSTATE_UINT32(uicpr, PPCUIC), + VMSTATE_UINT32(uictr, PPCUIC), + VMSTATE_UINT32(uicvcr, PPCUIC), + VMSTATE_UINT32(uicvr, PPCUIC), + VMSTATE_END_OF_LIST() + }, +}; + +static void ppc_uic_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->reset =3D ppc_uic_reset; + dc->realize =3D ppc_uic_realize; + dc->vmsd =3D &ppc_uic_vmstate; + device_class_set_props(dc, ppc_uic_properties); +} + +static const TypeInfo ppc_uic_info =3D { + .name =3D TYPE_PPC_UIC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(PPCUIC), + .class_init =3D ppc_uic_class_init, +}; + +static void ppc_uic_register_types(void) +{ + type_register_static(&ppc_uic_info); +} + +type_init(ppc_uic_register_types); diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index f2f9ca4ffec..ffe4cf43e88 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -30,9 +30,12 @@ #include "hw/ppc/ppc.h" #include "hw/ppc/ppc4xx.h" #include "hw/boards.h" +#include "hw/intc/ppc-uic.h" +#include "hw/qdev-properties.h" #include "qemu/log.h" #include "exec/address-spaces.h" #include "qemu/error-report.h" +#include "qapi/error.h" =20 /*#define DEBUG_UIC*/ =20 @@ -76,250 +79,40 @@ PowerPCCPU *ppc4xx_init(const char *cpu_type, =20 /*************************************************************************= ****/ /* "Universal" Interrupt controller */ -enum { - DCR_UICSR =3D 0x000, - DCR_UICSRS =3D 0x001, - DCR_UICER =3D 0x002, - DCR_UICCR =3D 0x003, - DCR_UICPR =3D 0x004, - DCR_UICTR =3D 0x005, - DCR_UICMSR =3D 0x006, - DCR_UICVR =3D 0x007, - DCR_UICVCR =3D 0x008, - DCR_UICMAX =3D 0x009, -}; - -#define UIC_MAX_IRQ 32 -typedef struct ppcuic_t ppcuic_t; -struct ppcuic_t { - uint32_t dcr_base; - int use_vectors; - uint32_t level; /* Remembers the state of level-triggered interrupts.= */ - uint32_t uicsr; /* Status register */ - uint32_t uicer; /* Enable register */ - uint32_t uiccr; /* Critical register */ - uint32_t uicpr; /* Polarity register */ - uint32_t uictr; /* Triggering register */ - uint32_t uicvcr; /* Vector configuration register */ - uint32_t uicvr; - qemu_irq *irqs; -}; - -static void ppcuic_trigger_irq(ppcuic_t *uic) -{ - uint32_t ir, cr; - int start, end, inc, i; - - /* Trigger interrupt if any is pending */ - ir =3D uic->uicsr & uic->uicer & (~uic->uiccr); - cr =3D uic->uicsr & uic->uicer & uic->uiccr; - LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32 - " uiccr %08" PRIx32 "\n" - " %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n", - __func__, uic->uicsr, uic->uicer, uic->uiccr, - uic->uicsr & uic->uicer, ir, cr); - if (ir !=3D 0x0000000) { - LOG_UIC("Raise UIC interrupt\n"); - qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]); - } else { - LOG_UIC("Lower UIC interrupt\n"); - qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]); - } - /* Trigger critical interrupt if any is pending and update vector */ - if (cr !=3D 0x0000000) { - qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]); - if (uic->use_vectors) { - /* Compute critical IRQ vector */ - if (uic->uicvcr & 1) { - start =3D 31; - end =3D 0; - inc =3D -1; - } else { - start =3D 0; - end =3D 31; - inc =3D 1; - } - uic->uicvr =3D uic->uicvcr & 0xFFFFFFFC; - for (i =3D start; i <=3D end; i +=3D inc) { - if (cr & (1 << i)) { - uic->uicvr +=3D (i - start) * 512 * inc; - break; - } - } - } - LOG_UIC("Raise UIC critical interrupt - " - "vector %08" PRIx32 "\n", uic->uicvr); - } else { - LOG_UIC("Lower UIC critical interrupt\n"); - qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]); - uic->uicvr =3D 0x00000000; - } -} - -static void ppcuic_set_irq(void *opaque, int irq_num, int level) -{ - ppcuic_t *uic; - uint32_t mask, sr; - - uic =3D opaque; - mask =3D 1U << (31 - irq_num); - LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32 - " mask %08" PRIx32 " =3D> %08" PRIx32 " %08" PRIx32 "\n", - __func__, irq_num, level, - uic->uicsr, mask, uic->uicsr & mask, level << irq_num); - if (irq_num < 0 || irq_num > 31) { - return; - } - sr =3D uic->uicsr; - - /* Update status register */ - if (uic->uictr & mask) { - /* Edge sensitive interrupt */ - if (level =3D=3D 1) { - uic->uicsr |=3D mask; - } - } else { - /* Level sensitive interrupt */ - if (level =3D=3D 1) { - uic->uicsr |=3D mask; - uic->level |=3D mask; - } else { - uic->uicsr &=3D ~mask; - uic->level &=3D ~mask; - } - } - LOG_UIC("%s: irq %d level %d sr %" PRIx32 " =3D> " - "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, s= r); - if (sr !=3D uic->uicsr) { - ppcuic_trigger_irq(uic); - } -} - -static uint32_t dcr_read_uic(void *opaque, int dcrn) -{ - ppcuic_t *uic; - uint32_t ret; - - uic =3D opaque; - dcrn -=3D uic->dcr_base; - switch (dcrn) { - case DCR_UICSR: - case DCR_UICSRS: - ret =3D uic->uicsr; - break; - case DCR_UICER: - ret =3D uic->uicer; - break; - case DCR_UICCR: - ret =3D uic->uiccr; - break; - case DCR_UICPR: - ret =3D uic->uicpr; - break; - case DCR_UICTR: - ret =3D uic->uictr; - break; - case DCR_UICMSR: - ret =3D uic->uicsr & uic->uicer; - break; - case DCR_UICVR: - if (!uic->use_vectors) { - goto no_read; - } - ret =3D uic->uicvr; - break; - case DCR_UICVCR: - if (!uic->use_vectors) { - goto no_read; - } - ret =3D uic->uicvcr; - break; - default: - no_read: - ret =3D 0x00000000; - break; - } - - return ret; -} - -static void dcr_write_uic(void *opaque, int dcrn, uint32_t val) -{ - ppcuic_t *uic; - - uic =3D opaque; - dcrn -=3D uic->dcr_base; - LOG_UIC("%s: dcr %d val 0x%x\n", __func__, dcrn, val); - switch (dcrn) { - case DCR_UICSR: - uic->uicsr &=3D ~val; - uic->uicsr |=3D uic->level; - ppcuic_trigger_irq(uic); - break; - case DCR_UICSRS: - uic->uicsr |=3D val; - ppcuic_trigger_irq(uic); - break; - case DCR_UICER: - uic->uicer =3D val; - ppcuic_trigger_irq(uic); - break; - case DCR_UICCR: - uic->uiccr =3D val; - ppcuic_trigger_irq(uic); - break; - case DCR_UICPR: - uic->uicpr =3D val; - break; - case DCR_UICTR: - uic->uictr =3D val; - ppcuic_trigger_irq(uic); - break; - case DCR_UICMSR: - break; - case DCR_UICVR: - break; - case DCR_UICVCR: - uic->uicvcr =3D val & 0xFFFFFFFD; - ppcuic_trigger_irq(uic); - break; - } -} - -static void ppcuic_reset (void *opaque) -{ - ppcuic_t *uic; - - uic =3D opaque; - uic->uiccr =3D 0x00000000; - uic->uicer =3D 0x00000000; - uic->uicpr =3D 0x00000000; - uic->uicsr =3D 0x00000000; - uic->uictr =3D 0x00000000; - if (uic->use_vectors) { - uic->uicvcr =3D 0x00000000; - uic->uicvr =3D 0x0000000; - } -} =20 qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs, uint32_t dcr_base, int has_ssr, int has_vr) { - ppcuic_t *uic; + DeviceState *uicdev =3D qdev_new(TYPE_PPC_UIC); + SysBusDevice *uicsbd =3D SYS_BUS_DEVICE(uicdev); + qemu_irq *uic_irqs; int i; =20 - uic =3D g_malloc0(sizeof(ppcuic_t)); - uic->dcr_base =3D dcr_base; - uic->irqs =3D irqs; - if (has_vr) - uic->use_vectors =3D 1; - for (i =3D 0; i < DCR_UICMAX; i++) { - ppc_dcr_register(env, dcr_base + i, uic, - &dcr_read_uic, &dcr_write_uic); - } - qemu_register_reset(ppcuic_reset, uic); + qdev_prop_set_uint32(uicdev, "dcr-base", dcr_base); + qdev_prop_set_bit(uicdev, "use-vectors", has_vr); + object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(env_cpu(env)), + &error_fatal); + sysbus_realize_and_unref(uicsbd, &error_fatal); =20 - return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ); + sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, irqs[PPCUIC_OUTPUT_INT]); + sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, irqs[PPCUIC_OUTPUT_CINT= ]); + + /* + * Return an allocated array of the UIC's input IRQ lines. + * This is an ugly temporary API to retain compatibility with + * the ppcuic_init() interface from the pre-QOM-conversion UIC. + * None of the callers free this array, so it is leaked -- but + * so was the array allocated by qemu_allocate_irqs() in the + * old code. + * + * The callers should just instantiate the UIC and wire it up + * themselves rather than passing qemu_irq* in and out of this functio= n. + */ + uic_irqs =3D g_new0(qemu_irq, UIC_MAX_IRQ); + for (i =3D 0; i < UIC_MAX_IRQ; i++) { + uic_irqs[i] =3D qdev_get_gpio_in(uicdev, i); + } + return uic_irqs; } =20 /*************************************************************************= ****/ diff --git a/MAINTAINERS b/MAINTAINERS index aa39490a244..24218800b16 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1671,6 +1671,8 @@ F: hw/ppc/ppc4*.c F: hw/i2c/ppc4xx_i2c.c F: include/hw/ppc/ppc4xx.h F: include/hw/i2c/ppc4xx_i2c.h +F: hw/intc/ppc-uic.c +F: include/hw/intc/ppc-uic.h =20 Character devices M: Marc-Andr=C3=A9 Lureau diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index d07954086a5..468d548ca77 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -62,6 +62,9 @@ config S390_FLIC_KVM config OMPIC bool =20 +config PPC_UIC + bool + config RX_ICU bool =20 diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 3f82cc230ad..d7dadbe5034 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -42,6 +42,7 @@ specific_ss.add(when: 'CONFIG_OMAP', if_true: files('omap= _intc.c')) specific_ss.add(when: 'CONFIG_OMPIC', if_true: files('ompic.c')) specific_ss.add(when: 'CONFIG_OPENPIC_KVM', if_true: files('openpic_kvm.c'= )) specific_ss.add(when: 'CONFIG_POWERNV', if_true: files('xics_pnv.c', 'pnv_= xive.c')) +specific_ss.add(when: 'CONFIG_PPC_UIC', if_true: files('ppc-uic.c')) specific_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_ic.c', 'bcm2= 836_control.c')) specific_ss.add(when: 'CONFIG_RX_ICU', if_true: files('rx_icu.c')) specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c')) diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig index dd86e664d21..982d55f5875 100644 --- a/hw/ppc/Kconfig +++ b/hw/ppc/Kconfig @@ -53,6 +53,7 @@ config PPC4XX bool select BITBANG_I2C select PCI + select PPC_UIC =20 config SAM460EX bool --=20 2.20.1 From nobody Fri May 17 10:34:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id d8sm16306001wmb.11.2020.12.11.16.15.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Dec 2020 16:15:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zroCLEiICIgvxuK7ZREbHz2wYPanCNf9f/IoLbAJmp8=; b=Mc536N9XW31qdTTtam3RRnyCgViwZDzYS/stIECTtCD7Ugg3hO52EAGYUxR+mb+Ojl /Ejofn1iqDFJg1RouSvjNy9SKE0t/yKNAIwfIl7RT+2u386/jQSkCbNvNtn8V5tbqZIU /G1hlqLTHEvHk6nGYL+q3uUfLGQ1qXW0/HeDL/D7FBgyy///Ko55FOifiwclrJ/8MU7m m66JDN7SETJUkFk06OnOpcLOp7cgaKJIs0G9dvf1sFtQXTSHkEiUPBCLnpzo9nrj8KP4 nkYIefhEvb6S09C7O+hrfDx4P5sH7JdzcuRZGYG8jSSW6dDcWQlkjoMwWAWMeJz4IfNn 95Fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zroCLEiICIgvxuK7ZREbHz2wYPanCNf9f/IoLbAJmp8=; b=pHe0uqxAwrtkFCQvMd/kyExGb4i4jyRvmJndPFUEUopscie3lZLHxUVxllc9vE8znP P5nF+yIBL9+fKR+PThC6iN6ZGy06Sx+Z2MUb+KVkOmnFR4x6h58thjEh1tY3f4i+p9Zu e6UN1UfR+T3CYJ+u937ynA4Q1sBBYZunzw1UQKWOBeu+9992Fep9z2AaGwGy3J3Y5Ut2 r2GKbYvpfuhxqC7U4ymP2Ov1JBjCYqeOMVmK80kTWKouy3ozZR1ixJy0Aw2PAcao5GQ6 QO6qmiY5lS5yB9if1sVsyIdG2myr+5ZjrJSnjG5F+j49ydpkf/JB7GPyzmKPBset/4HW iTkQ== X-Gm-Message-State: AOAM533fClRHVLmgOfnwvn2RF9qxdx1FtMTV68L/OXZ9WHocD/YIFKqv eK+SqIQqdHvSZGYan9PeIwU4mUoktFkUbw== X-Google-Smtp-Source: ABdhPJxkGItSaPaTaY6m95DhNOGMUiDdCujkGNrqpydgtquiKiDm576PZc6kM9zfq5ON2NWUAbYLDA== X-Received: by 2002:a1c:7909:: with SMTP id l9mr15984917wme.120.1607732144042; Fri, 11 Dec 2020 16:15:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 3/8] hw/ppc/virtex_ml507: Drop use of ppcuic_init() Date: Sat, 12 Dec 2020 00:15:32 +0000 Message-Id: <20201212001537.24520-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201212001537.24520-1-peter.maydell@linaro.org> References: <20201212001537.24520-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x344.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Switch the virtex_ml507 board to directly creating and configuring the UIC, rather than doing it via the old ppcuic_init() helper function. This fixes a trivial Coverity-detected memory leak where we were leaking the array of IRQs returned by ppcuic_init(). Fixes: Coverity CID 1421992 Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias --- hw/ppc/virtex_ml507.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c index 7f1bca928c1..34767b11cad 100644 --- a/hw/ppc/virtex_ml507.c +++ b/hw/ppc/virtex_ml507.c @@ -43,6 +43,7 @@ #include "qemu/option.h" #include "exec/address-spaces.h" =20 +#include "hw/intc/ppc-uic.h" #include "hw/ppc/ppc.h" #include "hw/ppc/ppc4xx.h" #include "hw/qdev-properties.h" @@ -95,7 +96,8 @@ static PowerPCCPU *ppc440_init_xilinx(const char *cpu_typ= e, uint32_t sysclk) { PowerPCCPU *cpu; CPUPPCState *env; - qemu_irq *irqs; + DeviceState *uicdev; + SysBusDevice *uicsbd; =20 cpu =3D POWERPC_CPU(cpu_create(cpu_type)); env =3D &cpu->env; @@ -105,10 +107,19 @@ static PowerPCCPU *ppc440_init_xilinx(const char *cpu= _type, uint32_t sysclk) ppc_dcr_init(env, NULL, NULL); =20 /* interrupt controller */ - irqs =3D g_new0(qemu_irq, PPCUIC_OUTPUT_NB); - irqs[PPCUIC_OUTPUT_INT] =3D ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT= _INT]; - irqs[PPCUIC_OUTPUT_CINT] =3D ((qemu_irq *)env->irq_inputs)[PPC40x_INPU= T_CINT]; - ppcuic_init(env, irqs, 0x0C0, 0, 1); + uicdev =3D qdev_new(TYPE_PPC_UIC); + uicsbd =3D SYS_BUS_DEVICE(uicdev); + + object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu), + &error_fatal); + sysbus_realize_and_unref(uicsbd, &error_fatal); + + sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, + ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]); + sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, + ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]); + + /* This board doesn't wire anything up to the inputs of the UIC. */ return cpu; } =20 --=20 2.20.1 From nobody Fri May 17 10:34:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607732747; cv=none; d=zohomail.com; s=zohoarc; b=fRXLzd8QyIilEGo1ze26rJmlNgUxPF+9LHMfXGyvgMRTqkiOxzJXCK64caLdbDrMK8nWhJpHzqBaE9ZzQ9WMdcPHbbeDASsnT8H7rBzgAMpXOMUgS7z1VvVh5mej7guoW4u3OB31h/JP3xZyREWcOWouSTA+hUpmMekDTtppvCA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607732747; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Pq8tAYkftQKbp7EDg1kA3sFd2xF8+eQ9f55vXuE8Qj8=; b=aUdw3c8kc9jYo1NM6BYBWQFP4VMSV7PVULhjmxbm6VIiaJmIy0G77Bq2b8tTXjoJ7p59BlE3AIFu6DX9lvVEmZdKPqwVLFBXDC2V8G1ywYbMy4BopA7CkuF2PztbzUofcMqxsJSdZeOsBTc6uOiPfMOWFNa/9XcQiKM3Y8tATuQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16077327477241017.803529607951; Fri, 11 Dec 2020 16:25:47 -0800 (PST) Received: from localhost ([::1]:54816 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knsjK-00012V-IU for importer@patchew.org; Fri, 11 Dec 2020 19:25:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36630) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knsZr-0002cY-CM for qemu-devel@nongnu.org; Fri, 11 Dec 2020 19:16:04 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:33698) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knsZe-0005eK-RG for qemu-devel@nongnu.org; Fri, 11 Dec 2020 19:15:59 -0500 Received: by mail-wm1-x342.google.com with SMTP id w206so5588881wma.0 for ; Fri, 11 Dec 2020 16:15:46 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d8sm16306001wmb.11.2020.12.11.16.15.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Dec 2020 16:15:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Pq8tAYkftQKbp7EDg1kA3sFd2xF8+eQ9f55vXuE8Qj8=; b=j9SU9nQKD/to5jCWhh7GmN1LxNnHmc5pp+4dGzuCJBU4UjSE1v/zneMsgPA5IbcZhb WTcZdjS/lNYKdl3szU14FDfZ5pAiqbsfxTQoC/2wTKJNiTYDJLifwNfWBL4Dh5hIwbnv mrAIkdkQMaOQPW1r2GNIgjLxMhRLw3Tlw8J79TdWPtBzMVuGRe+OFrI8XvQxzyVmxlnq V5YDpJvQbCKNo1G0yrnGp1DlxLvnCtoWEHH40iR1xb5PqcogjS3TWJfEUIYZIZiQQSvC HZ5oqstV4uXDeNhO68Ni+C2Guis0G3X4amCsTNvq3kT2yRsMru8+UZBULtaXMSgsmGIV rMww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Pq8tAYkftQKbp7EDg1kA3sFd2xF8+eQ9f55vXuE8Qj8=; b=Tq1/dqlocY5OZ1+2ehGt+I6G4Ywe9FV1xlfMQRVULHVWgtDn+16ACryuVxz9QC2lSe zQyC6tmWTAV/SiZ9nWbE71NhmnllP8oFZyTeohdr32c/hH7tEkCLS2CJuNLfvm/PVHIG bR5v9il55m9cHq/s09TO5ppZBmBrp7CPJsNgJEk0LWogRDI1kqqsiEKr0dRUUjQ7Uo+L 10VMEOrRcsKhvOSgXGuC5PJXiTrprRC6wqbGUWBvauzAJd8s9qES/jEU3lwmLGO0Y2rV ouiy5cxKx8CG2ixyOhLKfG+bGmn/3nKx7Clz6eUbrsMJAzF36KWPp/47Ro+45nxO0U19 FDuA== X-Gm-Message-State: AOAM530ndKVUm55FuuNjttvyoKdhoRERT955wndlp1AHPpHHaM1SbCH9 QwmpeJc5k+68HKSz+8aUBrOoRDEh3o0NlA== X-Google-Smtp-Source: ABdhPJxk5/BDHPlRm5tEwpYNwyN8vYF4NY7lZiEvLnH+xGNXFORBHyFdtlSOzDrpD85YKVQzxMXl8Q== X-Received: by 2002:a1c:4e0a:: with SMTP id g10mr16072029wmh.51.1607732145134; Fri, 11 Dec 2020 16:15:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 4/8] hw/ppc/ppc440_bamboo: Drop use of ppcuic_init() Date: Sat, 12 Dec 2020 00:15:33 +0000 Message-Id: <20201212001537.24520-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201212001537.24520-1-peter.maydell@linaro.org> References: <20201212001537.24520-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x342.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Switch the bamboo board to directly creating and configuring the UIC, rather than doing it via the old ppcuic_init() helper function. Signed-off-by: Peter Maydell --- hw/ppc/ppc440_bamboo.c | 38 +++++++++++++++++++++++++++----------- 1 file changed, 27 insertions(+), 11 deletions(-) diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index 665bc1784e1..b156bcb9990 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -33,6 +33,9 @@ #include "sysemu/qtest.h" #include "sysemu/reset.h" #include "hw/sysbus.h" +#include "hw/intc/ppc-uic.h" +#include "hw/qdev-properties.h" +#include "qapi/error.h" =20 #define BINARY_DEVICE_TREE_FILE "bamboo.dtb" =20 @@ -168,13 +171,13 @@ static void bamboo_init(MachineState *machine) MemoryRegion *ram_memories =3D g_new(MemoryRegion, PPC440EP_SDRAM_NR_B= ANKS); hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS]; hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS]; - qemu_irq *pic; - qemu_irq *irqs; PCIBus *pcibus; PowerPCCPU *cpu; CPUPPCState *env; target_long initrd_size =3D 0; DeviceState *dev; + DeviceState *uicdev; + SysBusDevice *uicsbd; int success; int i; =20 @@ -192,10 +195,17 @@ static void bamboo_init(MachineState *machine) ppc_dcr_init(env, NULL, NULL); =20 /* interrupt controller */ - irqs =3D g_new0(qemu_irq, PPCUIC_OUTPUT_NB); - irqs[PPCUIC_OUTPUT_INT] =3D ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT= _INT]; - irqs[PPCUIC_OUTPUT_CINT] =3D ((qemu_irq *)env->irq_inputs)[PPC40x_INPU= T_CINT]; - pic =3D ppcuic_init(env, irqs, 0x0C0, 0, 1); + uicdev =3D qdev_new(TYPE_PPC_UIC); + uicsbd =3D SYS_BUS_DEVICE(uicdev); + + object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu), + &error_fatal); + sysbus_realize_and_unref(uicsbd, &error_fatal); + + sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, + ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]); + sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, + ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]); =20 /* SDRAM controller */ memset(ram_bases, 0, sizeof(ram_bases)); @@ -203,14 +213,18 @@ static void bamboo_init(MachineState *machine) ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_memories, ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes); /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0= . */ - ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories, + ppc4xx_sdram_init(env, + qdev_get_gpio_in(uicdev, 14), + PPC440EP_SDRAM_NR_BANKS, ram_memories, ram_bases, ram_sizes, 1); =20 /* PCI */ dev =3D sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE, PPC440EP_PCI_CONFIG, - pic[pci_irq_nrs[0]], pic[pci_irq_nrs[1]], - pic[pci_irq_nrs[2]], pic[pci_irq_nrs[3]], + qdev_get_gpio_in(uicdev, pci_irq_nrs[0]), + qdev_get_gpio_in(uicdev, pci_irq_nrs[1]), + qdev_get_gpio_in(uicdev, pci_irq_nrs[2]), + qdev_get_gpio_in(uicdev, pci_irq_nrs[3]), NULL); pcibus =3D (PCIBus *)qdev_get_child_bus(dev, "pci.0"); if (!pcibus) { @@ -223,12 +237,14 @@ static void bamboo_init(MachineState *machine) memory_region_add_subregion(get_system_memory(), PPC440EP_PCI_IO, isa); =20 if (serial_hd(0) !=3D NULL) { - serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], + serial_mm_init(address_space_mem, 0xef600300, 0, + qdev_get_gpio_in(uicdev, 0), PPC_SERIAL_MM_BAUDBASE, serial_hd(0), DEVICE_BIG_ENDIAN); } if (serial_hd(1) !=3D NULL) { - serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], + serial_mm_init(address_space_mem, 0xef600400, 0, + qdev_get_gpio_in(uicdev, 1), PPC_SERIAL_MM_BAUDBASE, serial_hd(1), DEVICE_BIG_ENDIAN); } --=20 2.20.1 From nobody Fri May 17 10:34:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607732712; cv=none; d=zohomail.com; s=zohoarc; b=Zi5AAi2k4zhEN2McCGk0m4SNB3zYeWjH1x9jJYqMEnrUt1AGX+FL2OlNTXBkscCXWyT9+qdBlnlj+IOCREMl9mph790cHmlQXheCevxX4qbiPktyggCBD2J4eEUhyHcnhydXsEZN2kFJIq0T261bMIniWEE7MBExWxzlKQevm1g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607732712; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Sy8GTMLrANGCKa2I6q8N2rwI9l+Phoy4vAofP+Z/xdw=; b=TWKqis/gtCO2Ut3P2q2/UTEMCrOzB7jRHHLfdPkE4jRbe5U3ele4bh3IlZJCAtDDUGc3RSUQspu2rRcEKpjfjBmzujweCe4enxT56AJeOOg7zs0lUEydjg7S7ETwo7F3cX8s5jr4a5pkSTvI2Ax7vCsbUpWsKc7t0jf/p9l1Rug= ARC-Authentication-Results: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id d8sm16306001wmb.11.2020.12.11.16.15.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Dec 2020 16:15:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Sy8GTMLrANGCKa2I6q8N2rwI9l+Phoy4vAofP+Z/xdw=; b=kY8PiCaBCZ7SYQrD+bbDXotTqXm44ANQzTX29FZO7CoTBEFNczH8xxb9W/OYP4FH/b z4vV7rTMBW/eLsr/fOGMCuLBFZzCaijjGGntP0WX0HuTq5a3cmEtTmTBnGR8MU18sl3h S8K1749g39pnd7pHqH5KpK1bhzhkMacKlrV4bFawkPdVi+xunFNkIYkyl2iapmOBKaaY JRKOYy9pnCxdg/+LwzRot6nK9E5cLcZqlzOcWlw6qmm0Q4G/2fxzV//ANTXokY5UL7w4 ngS8K4+kw3L66bWNZgjdQSZL0HbaXb64603EL3p4L03O58ARltMyOC3BMUY9u/3OJNDB eNyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Sy8GTMLrANGCKa2I6q8N2rwI9l+Phoy4vAofP+Z/xdw=; b=mtM+bJ6DReJqQ7QaH3xJDvtcHhXVoIQfXOsbJpEZyG/3e9ufCLj6EGhmJolYxZZyC9 a6H86afyf3Ulj2iZPb0kWUCaC1cDSnEJOK0KlPKj0frKocvBIObZVn+3Lnbx0Ah0Yw3M WJC9yAl+THNLTrYkcOEXvQuGMCUGP0K/+5jjAgcbz1y+MjSVK/yBiJ3z4ENnVP5d8HdC +CsS3Z4wwH9k68Cbfrr0/Wfuko2WpCUQnkcBqnvX6lcWWzQ2kLbJKAazoZbTwLaw4xgQ jN47DpfInt1D9kzGCtMtVZZhIemrIA+1MqU8/O0sWYCb4xn5t7nZxi3wdO+xSpav4n3d eGIQ== X-Gm-Message-State: AOAM531/lz6ifurKH0wtzT45MiiWXoX5IWozXwrs4dkXgkoNQKrW5AQy /5R3UpbOfwIUezm8lUizqcJ+mXTSqUyFCA== X-Google-Smtp-Source: ABdhPJw+x/So/m6h/Hju5oW3s0dYhkssu3EW2X0rWXivgldeb5r1pQBI7cnkZMqwo8TivntByQFSyg== X-Received: by 2002:a1c:55ca:: with SMTP id j193mr16201950wmb.87.1607732146315; Fri, 11 Dec 2020 16:15:46 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 5/8] hw/ppc/sam460ex: Drop use of ppcuic_init() Date: Sat, 12 Dec 2020 00:15:34 +0000 Message-Id: <20201212001537.24520-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201212001537.24520-1-peter.maydell@linaro.org> References: <20201212001537.24520-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x344.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Switch the sam460ex board to directly creating and configuring the UIC, rather than doing it via the old ppcuic_init() helper function. Signed-off-by: Peter Maydell --- hw/ppc/sam460ex.c | 70 ++++++++++++++++++++++++++++++++++++----------- 1 file changed, 54 insertions(+), 16 deletions(-) diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index 14e6583eb0d..9cf7aad3833 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -39,6 +39,7 @@ #include "hw/usb/hcd-ehci.h" #include "hw/ppc/fdt.h" #include "hw/qdev-properties.h" +#include "hw/intc/ppc-uic.h" =20 #include =20 @@ -281,7 +282,6 @@ static void sam460ex_init(MachineState *machine) hwaddr ram_bases[SDRAM_NR_BANKS] =3D {0}; hwaddr ram_sizes[SDRAM_NR_BANKS] =3D {0}; MemoryRegion *l2cache_ram =3D g_new(MemoryRegion, 1); - qemu_irq *irqs, *uic[4]; PCIBus *pci_bus; PowerPCCPU *cpu; CPUPPCState *env; @@ -293,6 +293,9 @@ static void sam460ex_init(MachineState *machine) struct boot_info *boot_info; uint8_t *spd_data; int success; + qemu_irq mal_irqs[4]; + DeviceState *uic[4]; + int i; =20 cpu =3D POWERPC_CPU(cpu_create(machine->cpu_type)); env =3D &cpu->env; @@ -312,13 +315,35 @@ static void sam460ex_init(MachineState *machine) ppc4xx_plb_init(env); =20 /* interrupt controllers */ - irqs =3D g_new0(qemu_irq, PPCUIC_OUTPUT_NB); - irqs[PPCUIC_OUTPUT_INT] =3D ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT= _INT]; - irqs[PPCUIC_OUTPUT_CINT] =3D ((qemu_irq *)env->irq_inputs)[PPC40x_INPU= T_CINT]; - uic[0] =3D ppcuic_init(env, irqs, 0xc0, 0, 1); - uic[1] =3D ppcuic_init(env, &uic[0][30], 0xd0, 0, 1); - uic[2] =3D ppcuic_init(env, &uic[0][10], 0xe0, 0, 1); - uic[3] =3D ppcuic_init(env, &uic[0][16], 0xf0, 0, 1); + for (i =3D 0; i < ARRAY_SIZE(uic); i++) { + SysBusDevice *sbd; + /* + * Number of the first of the two consecutive IRQ inputs on UIC 0 + * to connect the INT and CINT outputs of UIC n to. The entry + * for UIC 0 is ignored, because it connects to the CPU. + */ + const int input_ints[] =3D { -1, 30, 10, 16 }; + + uic[i] =3D qdev_new(TYPE_PPC_UIC); + sbd =3D SYS_BUS_DEVICE(uic[i]); + + qdev_prop_set_uint32(uic[i], "dcr-base", 0xc0 + i * 0x10); + object_property_set_link(OBJECT(uic[i]), "cpu", OBJECT(cpu), + &error_fatal); + sysbus_realize_and_unref(sbd, &error_fatal); + + if (i =3D=3D 0) { + sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT, + ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_= INT]); + sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT, + ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_= CINT]); + } else { + sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT, + qdev_get_gpio_in(uic[0], input_ints[i])); + sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT, + qdev_get_gpio_in(uic[0], input_ints[i] + 1)= ); + } + } =20 /* SDRAM controller */ /* put all RAM on first bank because board has one slot @@ -331,7 +356,8 @@ static void sam460ex_init(MachineState *machine) ram_bases, ram_sizes, 1); =20 /* IIC controllers and devices */ - dev =3D sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, uic[0][2]); + dev =3D sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, + qdev_get_gpio_in(uic[0], 2)); i2c =3D PPC4xx_I2C(dev)->bus; /* SPD EEPROM on RAM module */ spd_data =3D spd_data_generate(ram_sizes[0] < 128 * MiB ? DDR : DDR2, @@ -341,7 +367,8 @@ static void sam460ex_init(MachineState *machine) /* RTC */ i2c_slave_create_simple(i2c, "m41t80", 0x68); =20 - dev =3D sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800, uic[0][3]); + dev =3D sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800, + qdev_get_gpio_in(uic[0], 3)); =20 /* External bus controller */ ppc405_ebc_init(env); @@ -356,7 +383,14 @@ static void sam460ex_init(MachineState *machine) ppc4xx_sdr_init(env); =20 /* MAL */ - ppc4xx_mal_init(env, 4, 16, &uic[2][3]); + /* + * TODO if the MAL were a proper QOM device we would not need to + * copy its qemu_irqs into an array for ppc4xx_mal_init()'s benefit. + */ + for (i =3D 0; i < ARRAY_SIZE(mal_irqs); i++) { + mal_irqs[0] =3D qdev_get_gpio_in(uic[2], 3 + i); + } + ppc4xx_mal_init(env, 4, 16, mal_irqs); =20 /* DMA */ ppc4xx_dma_init(env, 0x200); @@ -369,21 +403,23 @@ static void sam460ex_init(MachineState *machine) memory_region_add_subregion(address_space_mem, 0x400000000LL, l2cache_= ram); =20 /* USB */ - sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400, uic[2][29]); + sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400, + qdev_get_gpio_in(uic[2], 29)); dev =3D qdev_new("sysbus-ohci"); qdev_prop_set_string(dev, "masterbus", "usb-bus.0"); qdev_prop_set_uint32(dev, "num-ports", 6); sbdev =3D SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(sbdev, &error_fatal); sysbus_mmio_map(sbdev, 0, 0x4bffd0000); - sysbus_connect_irq(sbdev, 0, uic[2][30]); + sysbus_connect_irq(sbdev, 0, qdev_get_gpio_in(uic[2], 30)); usb_create_simple(usb_bus_find(-1), "usb-kbd"); usb_create_simple(usb_bus_find(-1), "usb-mouse"); =20 /* PCI bus */ ppc460ex_pcie_init(env); /* All PCI irqs are connected to the same UIC pin (cf. UBoot source) */ - dev =3D sysbus_create_simple("ppc440-pcix-host", 0xc0ec00000, uic[1][0= ]); + dev =3D sysbus_create_simple("ppc440-pcix-host", 0xc0ec00000, + qdev_get_gpio_in(uic[1], 0)); pci_bus =3D (PCIBus *)qdev_get_child_bus(dev, "pci.0"); if (!pci_bus) { error_report("couldn't create PCI controller!"); @@ -405,12 +441,14 @@ static void sam460ex_init(MachineState *machine) /* SoC has 4 UARTs * but board has only one wired and two are present in fdt */ if (serial_hd(0) !=3D NULL) { - serial_mm_init(address_space_mem, 0x4ef600300, 0, uic[1][1], + serial_mm_init(address_space_mem, 0x4ef600300, 0, + qdev_get_gpio_in(uic[1], 1), PPC_SERIAL_MM_BAUDBASE, serial_hd(0), DEVICE_BIG_ENDIAN); } if (serial_hd(1) !=3D NULL) { - serial_mm_init(address_space_mem, 0x4ef600400, 0, uic[0][1], + serial_mm_init(address_space_mem, 0x4ef600400, 0, + qdev_get_gpio_in(uic[0], 1), PPC_SERIAL_MM_BAUDBASE, serial_hd(1), DEVICE_BIG_ENDIAN); } --=20 2.20.1 From nobody Fri May 17 10:34:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607732797; cv=none; d=zohomail.com; s=zohoarc; b=WPnsPDY9XlrE3ftwybuX/xbT+DwaqEVYDV8uYlvhM82PKod/KOpBjNysYaWUPYK0R2YyCAlLQyuPJfLn4f+1kYhifb+sVc23h8ozjHYagwTqnzOZJ2iWvhOTmBaNuT8DqkTMa7fbxzz+y9NoUIiauG1/Ihcr8vd2QmAh/l2xhKU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607732797; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=E3wLZ5ZQgEBY3BL5WGa0zC+m36hgQAMvpdbWNLUcHrw=; b=DtvwTtGgfNwRMlnSvc0oZE+d8lBI+WSQYGqeCiJ2d2sJ/U6k4L8kNtD6AQkfGIT30QnC9SFptqcjcSnrR0yAjBgU0uzQ82VKjoY/bKLEQErYnX6HG1BZJnNoBD/N9yrclIfh1T94An1WiBnG7DK5r1KHdnH+0yR3eRRg97HDWGA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607732797660661.2261784564544; Fri, 11 Dec 2020 16:26:37 -0800 (PST) Received: from localhost ([::1]:55584 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knsk8-0001My-Go for importer@patchew.org; Fri, 11 Dec 2020 19:26:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36662) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knsZx-0002f4-SV for qemu-devel@nongnu.org; Fri, 11 Dec 2020 19:16:05 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:54947) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knsZl-0005fZ-2m for qemu-devel@nongnu.org; Fri, 11 Dec 2020 19:16:04 -0500 Received: by mail-wm1-x341.google.com with SMTP id d3so8886028wmb.4 for ; Fri, 11 Dec 2020 16:15:48 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d8sm16306001wmb.11.2020.12.11.16.15.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Dec 2020 16:15:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E3wLZ5ZQgEBY3BL5WGa0zC+m36hgQAMvpdbWNLUcHrw=; b=Z8G5FWtmxHrezUpk5YqEu9yCdmpErRqqPMfENr4EohV4sOHkByfoeAkwaq2ug1fr8P QOhqpRPdM6kv7O9J5TX2yiF6zh/C4pQMZJXFmAx+Bji0P9QyFyGoJjf+ET7Um7dMc+y+ ts+gBYRxAkxfDTuMXVitn2rdm2xZhSyWYyEEAIs6lBMjDBkXHf+KhlogSokv85m/h+E7 YuTbCtXuJ3YWmHcrC7idAzKjLCmllWWe3cFy++bkgaDIvDSAg1yvP3Q6uL8t/YNhJaUw BkV44bFvNVTWEbPMMlrp9EA8U8I0PYygZwMitO2F28E0FMRU66Z3vslZakZ9hLGlYs4b IKjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E3wLZ5ZQgEBY3BL5WGa0zC+m36hgQAMvpdbWNLUcHrw=; b=RjeCzZ2JC6HkEcFSTvNtDqGVlqvx2+Z1zIfTxDJ8p67tGvx8855gx3OVfJZ7IlmWTC yqf5pCeSLpVyMR+5rWdX6xE7YBWZxjqtPbndHx7qxE/Nh7KAvZp0r6BupnVvT5ZonOHs F9kcKIiqwqazOqK230k7y0DdEzSJINgEP6mZm66Sa4uUxmBtYP/nkEaiHlwjYDZUEHpT MJXMH2WqJiiM8C9eTfgknvbA9XYsPKNgVAKiOKJsHSuZhfx5KbF0YOECh5jJkCabcESh Rc7UCiVoN6HSuOh0x7mZ+vddVcIBEajYQJRdSLgL2SLdssMIIptGp/FWtBvYrkhGjALZ hr+A== X-Gm-Message-State: AOAM5330WAJ73qzb5YvZeAXgHOc4M1r2RjSVA8PTmbcVGlyj13tohXZS LycNE0u/ZR2ki/Pz/5yhUk3oBLU2/aGQYw== X-Google-Smtp-Source: ABdhPJxJC466eU//j+D9WcEOlYR6D3LySWcyjhiQ5306MbVp+Wt7e+EUlWX7QmOjYumHF+78EEZsVg== X-Received: by 2002:a1c:e084:: with SMTP id x126mr15855776wmg.109.1607732147477; Fri, 11 Dec 2020 16:15:47 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 6/8] hw/ppc: Delete unused ppc405cr_init() code Date: Sat, 12 Dec 2020 00:15:35 +0000 Message-Id: <20201212001537.24520-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201212001537.24520-1-peter.maydell@linaro.org> References: <20201212001537.24520-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x341.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The function ppc405cr_init() has apparently been unused since it was added in commit 8ecc7913525ecb in 2007. Remove this dead code, so we don't have to convert it away from using ppcuic_init(). Signed-off-by: Peter Maydell --- hw/ppc/ppc405.h | 6 - hw/ppc/ppc405_uc.c | 345 --------------------------------------------- 2 files changed, 351 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index 7ed25cfa1bf..e6c702f7e0d 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -62,12 +62,6 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx= _bd_info_t *bd, void ppc4xx_plb_init(CPUPPCState *env); void ppc405_ebc_init(CPUPPCState *env); =20 -CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem, - MemoryRegion ram_memories[4], - hwaddr ram_bases[4], - hwaddr ram_sizes[4], - uint32_t sysclk, qemu_irq **picp, - int do_init); CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, MemoryRegion ram_memories[2], hwaddr ram_bases[2], diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 381720aced9..3e191ae4af5 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -1155,351 +1155,6 @@ static void ppc4xx_gpt_init(hwaddr base, qemu_irq i= rqs[5]) qemu_register_reset(ppc4xx_gpt_reset, gpt); } =20 -/*************************************************************************= ****/ -/* PowerPC 405CR */ -enum { - PPC405CR_CPC0_PLLMR =3D 0x0B0, - PPC405CR_CPC0_CR0 =3D 0x0B1, - PPC405CR_CPC0_CR1 =3D 0x0B2, - PPC405CR_CPC0_PSR =3D 0x0B4, - PPC405CR_CPC0_JTAGID =3D 0x0B5, - PPC405CR_CPC0_ER =3D 0x0B9, - PPC405CR_CPC0_FR =3D 0x0BA, - PPC405CR_CPC0_SR =3D 0x0BB, -}; - -enum { - PPC405CR_CPU_CLK =3D 0, - PPC405CR_TMR_CLK =3D 1, - PPC405CR_PLB_CLK =3D 2, - PPC405CR_SDRAM_CLK =3D 3, - PPC405CR_OPB_CLK =3D 4, - PPC405CR_EXT_CLK =3D 5, - PPC405CR_UART_CLK =3D 6, - PPC405CR_CLK_NB =3D 7, -}; - -typedef struct ppc405cr_cpc_t ppc405cr_cpc_t; -struct ppc405cr_cpc_t { - clk_setup_t clk_setup[PPC405CR_CLK_NB]; - uint32_t sysclk; - uint32_t psr; - uint32_t cr0; - uint32_t cr1; - uint32_t jtagid; - uint32_t pllmr; - uint32_t er; - uint32_t fr; -}; - -static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc) -{ - uint64_t VCO_out, PLL_out; - uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_= clk; - int M, D0, D1, D2; - - D0 =3D ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */ - if (cpc->pllmr & 0x80000000) { - D1 =3D (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */ - D2 =3D 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */ - M =3D D0 * D1 * D2; - VCO_out =3D (uint64_t)cpc->sysclk * M; - if (VCO_out < 400000000 || VCO_out > 800000000) { - /* PLL cannot lock */ - cpc->pllmr &=3D ~0x80000000; - goto bypass_pll; - } - PLL_out =3D VCO_out / D2; - } else { - /* Bypass PLL */ - bypass_pll: - M =3D D0; - PLL_out =3D (uint64_t)cpc->sysclk * M; - } - CPU_clk =3D PLL_out; - if (cpc->cr1 & 0x00800000) - TMR_clk =3D cpc->sysclk; /* Should have a separate clock */ - else - TMR_clk =3D CPU_clk; - PLB_clk =3D CPU_clk / D0; - SDRAM_clk =3D PLB_clk; - D0 =3D ((cpc->pllmr >> 10) & 0x3) + 1; - OPB_clk =3D PLB_clk / D0; - D0 =3D ((cpc->pllmr >> 24) & 0x3) + 2; - EXT_clk =3D PLB_clk / D0; - D0 =3D ((cpc->cr0 >> 1) & 0x1F) + 1; - UART_clk =3D CPU_clk / D0; - /* Setup CPU clocks */ - clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk); - /* Setup time-base clock */ - clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk); - /* Setup PLB clock */ - clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk); - /* Setup SDRAM clock */ - clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk); - /* Setup OPB clock */ - clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk); - /* Setup external clock */ - clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk); - /* Setup UART clock */ - clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk); -} - -static uint32_t dcr_read_crcpc (void *opaque, int dcrn) -{ - ppc405cr_cpc_t *cpc; - uint32_t ret; - - cpc =3D opaque; - switch (dcrn) { - case PPC405CR_CPC0_PLLMR: - ret =3D cpc->pllmr; - break; - case PPC405CR_CPC0_CR0: - ret =3D cpc->cr0; - break; - case PPC405CR_CPC0_CR1: - ret =3D cpc->cr1; - break; - case PPC405CR_CPC0_PSR: - ret =3D cpc->psr; - break; - case PPC405CR_CPC0_JTAGID: - ret =3D cpc->jtagid; - break; - case PPC405CR_CPC0_ER: - ret =3D cpc->er; - break; - case PPC405CR_CPC0_FR: - ret =3D cpc->fr; - break; - case PPC405CR_CPC0_SR: - ret =3D ~(cpc->er | cpc->fr) & 0xFFFF0000; - break; - default: - /* Avoid gcc warning */ - ret =3D 0; - break; - } - - return ret; -} - -static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val) -{ - ppc405cr_cpc_t *cpc; - - cpc =3D opaque; - switch (dcrn) { - case PPC405CR_CPC0_PLLMR: - cpc->pllmr =3D val & 0xFFF77C3F; - break; - case PPC405CR_CPC0_CR0: - cpc->cr0 =3D val & 0x0FFFFFFE; - break; - case PPC405CR_CPC0_CR1: - cpc->cr1 =3D val & 0x00800000; - break; - case PPC405CR_CPC0_PSR: - /* Read-only */ - break; - case PPC405CR_CPC0_JTAGID: - /* Read-only */ - break; - case PPC405CR_CPC0_ER: - cpc->er =3D val & 0xBFFC0000; - break; - case PPC405CR_CPC0_FR: - cpc->fr =3D val & 0xBFFC0000; - break; - case PPC405CR_CPC0_SR: - /* Read-only */ - break; - } -} - -static void ppc405cr_cpc_reset (void *opaque) -{ - ppc405cr_cpc_t *cpc; - int D; - - cpc =3D opaque; - /* Compute PLLMR value from PSR settings */ - cpc->pllmr =3D 0x80000000; - /* PFWD */ - switch ((cpc->psr >> 30) & 3) { - case 0: - /* Bypass */ - cpc->pllmr &=3D ~0x80000000; - break; - case 1: - /* Divide by 3 */ - cpc->pllmr |=3D 5 << 16; - break; - case 2: - /* Divide by 4 */ - cpc->pllmr |=3D 4 << 16; - break; - case 3: - /* Divide by 6 */ - cpc->pllmr |=3D 2 << 16; - break; - } - /* PFBD */ - D =3D (cpc->psr >> 28) & 3; - cpc->pllmr |=3D (D + 1) << 20; - /* PT */ - D =3D (cpc->psr >> 25) & 7; - switch (D) { - case 0x2: - cpc->pllmr |=3D 0x13; - break; - case 0x4: - cpc->pllmr |=3D 0x15; - break; - case 0x5: - cpc->pllmr |=3D 0x16; - break; - default: - break; - } - /* PDC */ - D =3D (cpc->psr >> 23) & 3; - cpc->pllmr |=3D D << 26; - /* ODP */ - D =3D (cpc->psr >> 21) & 3; - cpc->pllmr |=3D D << 10; - /* EBPD */ - D =3D (cpc->psr >> 17) & 3; - cpc->pllmr |=3D D << 24; - cpc->cr0 =3D 0x0000003C; - cpc->cr1 =3D 0x2B0D8800; - cpc->er =3D 0x00000000; - cpc->fr =3D 0x00000000; - ppc405cr_clk_setup(cpc); -} - -static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc) -{ - int D; - - /* XXX: this should be read from IO pins */ - cpc->psr =3D 0x00000000; /* 8 bits ROM */ - /* PFWD */ - D =3D 0x2; /* Divide by 4 */ - cpc->psr |=3D D << 30; - /* PFBD */ - D =3D 0x1; /* Divide by 2 */ - cpc->psr |=3D D << 28; - /* PDC */ - D =3D 0x1; /* Divide by 2 */ - cpc->psr |=3D D << 23; - /* PT */ - D =3D 0x5; /* M =3D 16 */ - cpc->psr |=3D D << 25; - /* ODP */ - D =3D 0x1; /* Divide by 2 */ - cpc->psr |=3D D << 21; - /* EBDP */ - D =3D 0x2; /* Divide by 4 */ - cpc->psr |=3D D << 17; -} - -static void ppc405cr_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[7], - uint32_t sysclk) -{ - ppc405cr_cpc_t *cpc; - - cpc =3D g_malloc0(sizeof(ppc405cr_cpc_t)); - memcpy(cpc->clk_setup, clk_setup, - PPC405CR_CLK_NB * sizeof(clk_setup_t)); - cpc->sysclk =3D sysclk; - cpc->jtagid =3D 0x42051049; - ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc, - &dcr_read_crcpc, &dcr_write_crcpc); - ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc, - &dcr_read_crcpc, &dcr_write_crcpc); - ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc, - &dcr_read_crcpc, &dcr_write_crcpc); - ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc, - &dcr_read_crcpc, &dcr_write_crcpc); - ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc, - &dcr_read_crcpc, &dcr_write_crcpc); - ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc, - &dcr_read_crcpc, &dcr_write_crcpc); - ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc, - &dcr_read_crcpc, &dcr_write_crcpc); - ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc, - &dcr_read_crcpc, &dcr_write_crcpc); - ppc405cr_clk_init(cpc); - qemu_register_reset(ppc405cr_cpc_reset, cpc); -} - -CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem, - MemoryRegion ram_memories[4], - hwaddr ram_bases[4], - hwaddr ram_sizes[4], - uint32_t sysclk, qemu_irq **picp, - int do_init) -{ - clk_setup_t clk_setup[PPC405CR_CLK_NB]; - qemu_irq dma_irqs[4]; - PowerPCCPU *cpu; - CPUPPCState *env; - qemu_irq *pic, *irqs; - - memset(clk_setup, 0, sizeof(clk_setup)); - cpu =3D ppc4xx_init(POWERPC_CPU_TYPE_NAME("405crc"), - &clk_setup[PPC405CR_CPU_CLK], - &clk_setup[PPC405CR_TMR_CLK], sysclk); - env =3D &cpu->env; - /* Memory mapped devices registers */ - /* PLB arbitrer */ - ppc4xx_plb_init(env); - /* PLB to OPB bridge */ - ppc4xx_pob_init(env); - /* OBP arbitrer */ - ppc4xx_opba_init(0xef600600); - /* Universal interrupt controller */ - irqs =3D g_new0(qemu_irq, PPCUIC_OUTPUT_NB); - irqs[PPCUIC_OUTPUT_INT] =3D - ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; - irqs[PPCUIC_OUTPUT_CINT] =3D - ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; - pic =3D ppcuic_init(env, irqs, 0x0C0, 0, 1); - *picp =3D pic; - /* SDRAM controller */ - ppc4xx_sdram_init(env, pic[14], 1, ram_memories, - ram_bases, ram_sizes, do_init); - /* External bus controller */ - ppc405_ebc_init(env); - /* DMA controller */ - dma_irqs[0] =3D pic[26]; - dma_irqs[1] =3D pic[25]; - dma_irqs[2] =3D pic[24]; - dma_irqs[3] =3D pic[23]; - ppc405_dma_init(env, dma_irqs); - /* Serial ports */ - if (serial_hd(0) !=3D NULL) { - serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], - PPC_SERIAL_MM_BAUDBASE, serial_hd(0), - DEVICE_BIG_ENDIAN); - } - if (serial_hd(1) !=3D NULL) { - serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], - PPC_SERIAL_MM_BAUDBASE, serial_hd(1), - DEVICE_BIG_ENDIAN); - } - /* IIC controller */ - sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]); - /* GPIO */ - ppc405_gpio_init(0xef600700); - /* CPU control */ - ppc405cr_cpc_init(env, clk_setup, sysclk); - - return env; -} - /*************************************************************************= ****/ /* PowerPC 405EP */ /* CPU control */ --=20 2.20.1 From nobody Fri May 17 10:34:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607733089; cv=none; d=zohomail.com; s=zohoarc; b=e+Xr7IzBOL90TuQMFlFZV1hBm88InXlrP+iHuh1gMCRn333Dcy7+GPHV6XG3LaPY3fOSKRBxU7eEeGeQnVjVdwWwBwqQp/m+A/Ogz1EmBmidTyAIijlwhe86xtVYgcrlCzg1ByPf3S5nzCn9Qgc+JxLeJaduw7B2FWkunO+NwfA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id d8sm16306001wmb.11.2020.12.11.16.15.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Dec 2020 16:15:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9vrnHXTMsZjfdHKV6SCdqqT25waiXTd0JncR/beyVqQ=; b=DXy24s1cghUMFxggCgFCIpvb53WshR5YIqXV6IiQkFETIDpBepJtbOhDyjeYhViHQI GqPuxd2OU0C8KSZnA1hWU06GpogoKev9mIdrBYqgb05kLRjchYfNZj5bLJylLJDRuKYN +JYqX/B0CMLY46o084Ee4pAhAglSsBcPlR/fiz8xiF9GhlFkcr8znmU/ZwXLwTcBFSib +i+tBExLk2nhrpmK73QZX5v3QtVx8tKPo24wCXHeRL8CM0pawXcox3mtG/73pkLjJ7SO nxAw0Vqg3Ky9kTyCYT7UwXAkxsP+5qUQ8CF7/s1y68H+cOcSJ64X4bXM5M3Ya5u3juXU PSHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9vrnHXTMsZjfdHKV6SCdqqT25waiXTd0JncR/beyVqQ=; b=cJUu3Ad+NGqAyPYj+WqwKAvI1QdGH+4oRY5sY4im76TL/BFY8+gJc/QnSIywRL5Qx6 D0s9KkiyyBA5HO2TaF/4pWmQKG+Jg/C3ePpBIHB2Xu3qfiYVhpUcnMlWLe5u45TJOhFT VBxuSh4v5jGU3BIBrJxbN7Rty2PZ7m4P1hIjs42hC/qBYLGhaUxbZKjWH5T2+Vk9NObM PfNZycKGWpnu5M6A06yD6bL1GpPW5izs/SgUa+D12LSxSL7+f2HdDHy6R5Oumm6VKkdI +0+3ytSfSDqr5IOAu74xq5REh0C8mqGo0AN7vpOqZIen1eVHXRj1xLTSrOCRIW0EsfcI alSA== X-Gm-Message-State: AOAM531ih+NvpEQ3BaVSJcPi/Nm8yDwh9IsNuvi9awm/1u1TaMil4HuW O9vuF8D1r6jFnroN6jHlAvj5pkWtST1LUA== X-Google-Smtp-Source: ABdhPJyh73FpIUs9YDYcLhzVfovaYPaK0CH9Y/b1WLF6LtvJsZvIqdTM14IjFDysq0vEvmdyFnJykg== X-Received: by 2002:a1c:c305:: with SMTP id t5mr16263646wmf.63.1607732148639; Fri, 11 Dec 2020 16:15:48 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 7/8] hw/ppc/ppc405_uc: Drop use of ppcuic_init() Date: Sat, 12 Dec 2020 00:15:36 +0000 Message-Id: <20201212001537.24520-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201212001537.24520-1-peter.maydell@linaro.org> References: <20201212001537.24520-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x341.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Switch the ppc405_uc boards to directly creating and configuring the UIC, rather than doing it via the old ppcuic_init() helper function. We retain the API feature of ppc405ep_init() where it passes back something allowing the callers to wire up devices to the UIC if they need to, even though neither of the callsites currently makes use of this ability -- instead of passing back the qemu_irq array we pass back the UIC DeviceState. This fixes a trivial Coverity-detected memory leak where we were leaking the array of IRQs returned by ppcuic_init(). Fixes: Coverity CID 1421922 Signed-off-by: Peter Maydell --- hw/ppc/ppc405.h | 2 +- hw/ppc/ppc405_boards.c | 8 ++--- hw/ppc/ppc405_uc.c | 70 +++++++++++++++++++++++++----------------- 3 files changed, 47 insertions(+), 33 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index e6c702f7e0d..c58f739886a 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -66,7 +66,7 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_space_me= m, MemoryRegion ram_memories[2], hwaddr ram_bases[2], hwaddr ram_sizes[2], - uint32_t sysclk, qemu_irq **picp, + uint32_t sysclk, DeviceState **uicdev, int do_init); =20 #endif /* PPC405_H */ diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index b7249f21cf2..8f77887fb18 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -151,7 +151,6 @@ static void ref405ep_init(MachineState *machine) CPUPPCState *env; DeviceState *dev; SysBusDevice *s; - qemu_irq *pic; MemoryRegion *bios; MemoryRegion *sram =3D g_new(MemoryRegion, 1); ram_addr_t bdloc; @@ -167,6 +166,7 @@ static void ref405ep_init(MachineState *machine) int len; DriveInfo *dinfo; MemoryRegion *sysmem =3D get_system_memory(); + DeviceState *uicdev; =20 if (machine->ram_size !=3D mc->default_ram_size) { char *sz =3D size_to_str(mc->default_ram_size); @@ -184,7 +184,7 @@ static void ref405ep_init(MachineState *machine) ram_bases[1] =3D 0x00000000; ram_sizes[1] =3D 0x00000000; env =3D ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, - 33333333, &pic, kernel_filename =3D=3D NULL ? 0 : = 1); + 33333333, &uicdev, kernel_filename =3D=3D NULL ? 0= : 1); /* allocate SRAM */ sram_size =3D 512 * KiB; memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size, @@ -429,7 +429,6 @@ static void taihu_405ep_init(MachineState *machine) const char *kernel_filename =3D machine->kernel_filename; const char *initrd_filename =3D machine->initrd_filename; char *filename; - qemu_irq *pic; MemoryRegion *sysmem =3D get_system_memory(); MemoryRegion *bios; MemoryRegion *ram_memories =3D g_new(MemoryRegion, 2); @@ -440,6 +439,7 @@ static void taihu_405ep_init(MachineState *machine) int linux_boot; int fl_idx; DriveInfo *dinfo; + DeviceState *uicdev; =20 if (machine->ram_size !=3D mc->default_ram_size) { char *sz =3D size_to_str(mc->default_ram_size); @@ -459,7 +459,7 @@ static void taihu_405ep_init(MachineState *machine) "taihu_405ep.ram-1", machine->ram, ram_bases[= 1], ram_sizes[1]); ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, - 33333333, &pic, kernel_filename =3D=3D NULL ? 0 : 1); + 33333333, &uicdev, kernel_filename =3D=3D NULL ? 0 : 1); /* allocate and load BIOS */ fl_idx =3D 0; #if defined(USE_FLASH_BIOS) diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 3e191ae4af5..fe047074a17 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -36,6 +36,9 @@ #include "sysemu/sysemu.h" #include "qemu/log.h" #include "exec/address-spaces.h" +#include "hw/intc/ppc-uic.h" +#include "hw/qdev-properties.h" +#include "qapi/error.h" =20 //#define DEBUG_OPBA //#define DEBUG_SDRAM @@ -1446,14 +1449,15 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_sp= ace_mem, MemoryRegion ram_memories[2], hwaddr ram_bases[2], hwaddr ram_sizes[2], - uint32_t sysclk, qemu_irq **picp, + uint32_t sysclk, DeviceState **uicdevp, int do_init) { clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; PowerPCCPU *cpu; CPUPPCState *env; - qemu_irq *pic, *irqs; + DeviceState *uicdev; + SysBusDevice *uicsbd; =20 memset(clk_setup, 0, sizeof(clk_setup)); /* init CPUs */ @@ -1474,59 +1478,69 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_sp= ace_mem, /* Initialize timers */ ppc_booke_timers_init(cpu, sysclk, 0); /* Universal interrupt controller */ - irqs =3D g_new0(qemu_irq, PPCUIC_OUTPUT_NB); - irqs[PPCUIC_OUTPUT_INT] =3D - ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; - irqs[PPCUIC_OUTPUT_CINT] =3D - ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; - pic =3D ppcuic_init(env, irqs, 0x0C0, 0, 1); - *picp =3D pic; + uicdev =3D qdev_new(TYPE_PPC_UIC); + uicsbd =3D SYS_BUS_DEVICE(uicdev); + + object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu), + &error_fatal); + sysbus_realize_and_unref(uicsbd, &error_fatal); + + sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, + ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]); + sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, + ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]); + + *uicdevp =3D uicdev; + /* SDRAM controller */ /* XXX 405EP has no ECC interrupt */ - ppc4xx_sdram_init(env, pic[17], 2, ram_memories, + ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 17), 2, ram_memories, ram_bases, ram_sizes, do_init); /* External bus controller */ ppc405_ebc_init(env); /* DMA controller */ - dma_irqs[0] =3D pic[5]; - dma_irqs[1] =3D pic[6]; - dma_irqs[2] =3D pic[7]; - dma_irqs[3] =3D pic[8]; + dma_irqs[0] =3D qdev_get_gpio_in(uicdev, 5); + dma_irqs[1] =3D qdev_get_gpio_in(uicdev, 6); + dma_irqs[2] =3D qdev_get_gpio_in(uicdev, 7); + dma_irqs[3] =3D qdev_get_gpio_in(uicdev, 8); ppc405_dma_init(env, dma_irqs); /* IIC controller */ - sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]); + sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, + qdev_get_gpio_in(uicdev, 2)); /* GPIO */ ppc405_gpio_init(0xef600700); /* Serial ports */ if (serial_hd(0) !=3D NULL) { - serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], + serial_mm_init(address_space_mem, 0xef600300, 0, + qdev_get_gpio_in(uicdev, 0), PPC_SERIAL_MM_BAUDBASE, serial_hd(0), DEVICE_BIG_ENDIAN); } if (serial_hd(1) !=3D NULL) { - serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], + serial_mm_init(address_space_mem, 0xef600400, 0, + qdev_get_gpio_in(uicdev, 1), PPC_SERIAL_MM_BAUDBASE, serial_hd(1), DEVICE_BIG_ENDIAN); } /* OCM */ ppc405_ocm_init(env); /* GPT */ - gpt_irqs[0] =3D pic[19]; - gpt_irqs[1] =3D pic[20]; - gpt_irqs[2] =3D pic[21]; - gpt_irqs[3] =3D pic[22]; - gpt_irqs[4] =3D pic[23]; + gpt_irqs[0] =3D qdev_get_gpio_in(uicdev, 19); + gpt_irqs[1] =3D qdev_get_gpio_in(uicdev, 20); + gpt_irqs[2] =3D qdev_get_gpio_in(uicdev, 21); + gpt_irqs[3] =3D qdev_get_gpio_in(uicdev, 22); + gpt_irqs[4] =3D qdev_get_gpio_in(uicdev, 23); ppc4xx_gpt_init(0xef600000, gpt_irqs); /* PCI */ - /* Uses pic[3], pic[16], pic[18] */ + /* Uses UIC IRQs 3, 16, 18 */ /* MAL */ - mal_irqs[0] =3D pic[11]; - mal_irqs[1] =3D pic[12]; - mal_irqs[2] =3D pic[13]; - mal_irqs[3] =3D pic[14]; + mal_irqs[0] =3D qdev_get_gpio_in(uicdev, 11); + mal_irqs[1] =3D qdev_get_gpio_in(uicdev, 12); + mal_irqs[2] =3D qdev_get_gpio_in(uicdev, 13); + mal_irqs[3] =3D qdev_get_gpio_in(uicdev, 14); ppc4xx_mal_init(env, 4, 2, mal_irqs); /* Ethernet */ - /* Uses pic[9], pic[15], pic[17] */ + /* Uses UIC IRQs 9, 15, 17 */ /* CPU control */ ppc405ep_cpc_init(env, clk_setup, sysclk); =20 --=20 2.20.1 From nobody Fri May 17 10:34:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607732984; cv=none; d=zohomail.com; s=zohoarc; b=e+s7pCSxzZ1PZg+T5A5TsOR/xsCZJA4E8LEXwqB7Z9IBxD/eUgHFmr164Y8GL9IuPdTkTqAKVBo2FJHdGi95uTmvnlEiRnA363tKDxKqyQxGt+vGE8WnYz+Kf+TSzrRTpVvMBOyFN4uR5Db2vGJonrIabJJyyCi4itMkDtgI5Ys= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607732984; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id d8sm16306001wmb.11.2020.12.11.16.15.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Dec 2020 16:15:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SGfBJkjN2qAUyeuQd9Lf8jfyzTE2r7nAxi7Nqw5b6RE=; b=WfylVfh4yPpqykbIRNfGyk2UD6MPF7XL7Ojt9ngtD94CxRUAwMrF+g7Kux4K+t5OvT VGDmrdkHfrFFGbOlyLj3A6v6VIO8M0YuHVYwysFLvK9YzEzdSDPtIosqoZRXVfWaMMjK kE9OacKPIumFldxV3Dsqjvytkn9XIfzoXGnm49UY4uqj/EiqwZ7ubbGVkDFsUGKT/k2P znsFe5pd5XdSbtrx1hH3fSRYWXcgfGkkcShXhdAfusl4tixUi/P8VDg5bLSOcIgMebyM l2cctErE6+Y9xbnsxbp472no2YU0tFR0xSUR+PGmjJRTfmei4QqRkjUZtOJPh0wAl7nR QGSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SGfBJkjN2qAUyeuQd9Lf8jfyzTE2r7nAxi7Nqw5b6RE=; b=Gh4OSdejVPQ58G1sEFDWL3yDwbCiLS2JDcuxr7fw5vckQiJ+z7/TXzZp+zE1WOXugn zYEkLeAy+D9KafVEEES/FP5edg7id87AmNjMw04u63ENj+abZA9PGtv81pnDvz+56uW8 0vpVBl2ZcgHksxgr+w0UankuwvpgmlUJYhjnJwrci0r8q6c8a6EgLthDf1vFdI/M4agN akcyKMS6PkbjKph4x+hoslCo49JPDNnx/mm5Pk7CAFr6xx9jh5HLmvvF1T8CmoOhFuoM wWqwlQIeLPiGXmtnEfGaJa2gT0r+aq6hfYpYr+r6RlpBR3UtZE1pvy8z+5AuFYHZBYok B/Wg== X-Gm-Message-State: AOAM530vXqW7UcsPoGfEaiUqVLhcPIIXZh7LwGdGo+0gPRQC5EVacctn /yNcHN5LlGAJYnpeNb9qSl9TuIfHb48D/A== X-Google-Smtp-Source: ABdhPJyAhXClQlyEZ+IL3yZ4pde6VHGqEMkgmgsHfQV/xuopOHh54mXAO6tNZ6MrqKyWkr2Ous7VVQ== X-Received: by 2002:a1c:5459:: with SMTP id p25mr15340565wmi.19.1607732149911; Fri, 11 Dec 2020 16:15:49 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 8/8] hw/ppc: Remove unused ppcuic_init() Date: Sat, 12 Dec 2020 00:15:37 +0000 Message-Id: <20201212001537.24520-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201212001537.24520-1-peter.maydell@linaro.org> References: <20201212001537.24520-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x343.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , qemu-ppc@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Now we've converted all the callsites to directly create the QOM UIC device themselves, the ppcuic_init() function is unused and can be removed. The enum defining PPCUIC symbolic constants can be moved to the ppc-uic.h header where it more naturally belongs. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias --- include/hw/intc/ppc-uic.h | 7 +++++++ include/hw/ppc/ppc4xx.h | 9 --------- hw/ppc/ppc4xx_devs.c | 38 -------------------------------------- 3 files changed, 7 insertions(+), 47 deletions(-) diff --git a/include/hw/intc/ppc-uic.h b/include/hw/intc/ppc-uic.h index e614e2ffd80..22dd5e5ac2c 100644 --- a/include/hw/intc/ppc-uic.h +++ b/include/hw/intc/ppc-uic.h @@ -47,6 +47,13 @@ OBJECT_DECLARE_SIMPLE_TYPE(PPCUIC, PPC_UIC) =20 #define UIC_MAX_IRQ 32 =20 +/* Symbolic constants for the sysbus IRQ outputs */ +enum { + PPCUIC_OUTPUT_INT =3D 0, + PPCUIC_OUTPUT_CINT =3D 1, + PPCUIC_OUTPUT_NB, +}; + struct PPCUIC { /*< private >*/ SysBusDevice parent_obj; diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index cc19c8da5be..980f964b5a9 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -33,15 +33,6 @@ PowerPCCPU *ppc4xx_init(const char *cpu_model, clk_setup_t *cpu_clk, clk_setup_t *tb_clk, uint32_t sysclk); =20 -/* PowerPC 4xx universal interrupt controller */ -enum { - PPCUIC_OUTPUT_INT =3D 0, - PPCUIC_OUTPUT_CINT =3D 1, - PPCUIC_OUTPUT_NB, -}; -qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs, - uint32_t dcr_base, int has_ssr, int has_vr); - void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, MemoryRegion ram_memories[], hwaddr ram_bases[], hwaddr ram_sizes[], diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index ffe4cf43e88..fe9d4f7155e 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -77,44 +77,6 @@ PowerPCCPU *ppc4xx_init(const char *cpu_type, return cpu; } =20 -/*************************************************************************= ****/ -/* "Universal" Interrupt controller */ - -qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs, - uint32_t dcr_base, int has_ssr, int has_vr) -{ - DeviceState *uicdev =3D qdev_new(TYPE_PPC_UIC); - SysBusDevice *uicsbd =3D SYS_BUS_DEVICE(uicdev); - qemu_irq *uic_irqs; - int i; - - qdev_prop_set_uint32(uicdev, "dcr-base", dcr_base); - qdev_prop_set_bit(uicdev, "use-vectors", has_vr); - object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(env_cpu(env)), - &error_fatal); - sysbus_realize_and_unref(uicsbd, &error_fatal); - - sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, irqs[PPCUIC_OUTPUT_INT]); - sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, irqs[PPCUIC_OUTPUT_CINT= ]); - - /* - * Return an allocated array of the UIC's input IRQ lines. - * This is an ugly temporary API to retain compatibility with - * the ppcuic_init() interface from the pre-QOM-conversion UIC. - * None of the callers free this array, so it is leaked -- but - * so was the array allocated by qemu_allocate_irqs() in the - * old code. - * - * The callers should just instantiate the UIC and wire it up - * themselves rather than passing qemu_irq* in and out of this functio= n. - */ - uic_irqs =3D g_new0(qemu_irq, UIC_MAX_IRQ); - for (i =3D 0; i < UIC_MAX_IRQ; i++) { - uic_irqs[i] =3D qdev_get_gpio_in(uicdev, i); - } - return uic_irqs; -} - /*************************************************************************= ****/ /* SDRAM controller */ typedef struct ppc4xx_sdram_t ppc4xx_sdram_t; --=20 2.20.1