From nobody Mon Feb 9 22:24:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607700353; cv=none; d=zohomail.com; s=zohoarc; b=Hz0xt9sVftq1xbKIYIG/BTgy+ztgNRW5taedFXbDvP5NDl+67F5+pSeWQrlBdJsXRX+YLbvn2Oo/C7LhU0zZ7jBayyEiJe/4aBmzwzIun+HPtsQpD3TSgd6O7BwHpJ+cz5xSj6YartMurxHuRkR8XMdNqcgaAsFbY68RcIuNOV0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607700353; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=tr0ANDooR9FXqGxbOLs/+iBFGIrRH2K6/22MAyljRr0=; b=lLpbgxXNUnMR2Kikk2ni53eadZrEKqpZLfSMH2n0KTE6Yyo4rVixPpCL1SFM80V4jgsf3UMk3bOXsw4x+h25pmbWsQr8oMyr3UioZv9LAe//HA/Yhbw1QJopK/opS9/CbhGWnSrWUhdfe9qE4xLUqnz1UAeaZWqI4U3N0mCtsJ4= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607700353978448.6837740381836; Fri, 11 Dec 2020 07:25:53 -0800 (PST) Received: from localhost ([::1]:42916 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knkIq-0004sO-IB for importer@patchew.org; Fri, 11 Dec 2020 10:25:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50944) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knk6c-0007db-KV; Fri, 11 Dec 2020 10:13:14 -0500 Received: from mail.csgraf.de ([188.138.100.120]:36614 helo=zulu616.server4you.de) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knk6Y-0001vv-UA; Fri, 11 Dec 2020 10:13:14 -0500 Received: from localhost.localdomain (dynamic-077-007-081-179.77.7.pool.telefonica.de [77.7.81.179]) by csgraf.de (Postfix) with ESMTPSA id 49C7C3900553; Fri, 11 Dec 2020 16:13:07 +0100 (CET) From: Alexander Graf To: qemu-devel@nongnu.org Subject: [PATCH v5 10/11] hvf: arm: Add support for GICv3 Date: Fri, 11 Dec 2020 16:12:59 +0100 Message-Id: <20201211151300.85322-11-agraf@csgraf.de> X-Mailer: git-send-email 2.24.3 (Apple Git-128) In-Reply-To: <20201211151300.85322-1-agraf@csgraf.de> References: <20201211151300.85322-1-agraf@csgraf.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=188.138.100.120; envelope-from=agraf@csgraf.de; helo=zulu616.server4you.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Eduardo Habkost , Richard Henderson , Cameron Esfahani , Roman Bolshakov , qemu-arm@nongnu.org, Frank Yang , Paolo Bonzini , Peter Collingbourne Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" We currently only support GICv2 emulation. To also support GICv3, we will need to pass a few system registers into their respective handler functions. This patch adds handling for all of the required system registers, so that we can run with more than 8 vCPUs. Signed-off-by: Alexander Graf Acked-by: Roman Bolshakov --- target/arm/hvf/hvf.c | 141 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 141 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 979008e188..bc955c097f 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -22,6 +22,7 @@ =20 #include "exec/address-spaces.h" #include "hw/irq.h" +#include "hw/intc/gicv3_internal.h" #include "qemu/main-loop.h" #include "sysemu/accel.h" #include "sysemu/cpus.h" @@ -46,6 +47,33 @@ #define SYSREG_CNTPCT_EL0 SYSREG(3, 3, 1, 14, 0) #define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 0, 9, 13) =20 +#define SYSREG_ICC_AP0R0_EL1 SYSREG(3, 0, 4, 12, 8) +#define SYSREG_ICC_AP0R1_EL1 SYSREG(3, 0, 5, 12, 8) +#define SYSREG_ICC_AP0R2_EL1 SYSREG(3, 0, 6, 12, 8) +#define SYSREG_ICC_AP0R3_EL1 SYSREG(3, 0, 7, 12, 8) +#define SYSREG_ICC_AP1R0_EL1 SYSREG(3, 0, 0, 12, 9) +#define SYSREG_ICC_AP1R1_EL1 SYSREG(3, 0, 1, 12, 9) +#define SYSREG_ICC_AP1R2_EL1 SYSREG(3, 0, 2, 12, 9) +#define SYSREG_ICC_AP1R3_EL1 SYSREG(3, 0, 3, 12, 9) +#define SYSREG_ICC_ASGI1R_EL1 SYSREG(3, 0, 6, 12, 11) +#define SYSREG_ICC_BPR0_EL1 SYSREG(3, 0, 3, 12, 8) +#define SYSREG_ICC_BPR1_EL1 SYSREG(3, 0, 3, 12, 12) +#define SYSREG_ICC_CTLR_EL1 SYSREG(3, 0, 4, 12, 12) +#define SYSREG_ICC_DIR_EL1 SYSREG(3, 0, 1, 12, 11) +#define SYSREG_ICC_EOIR0_EL1 SYSREG(3, 0, 1, 12, 8) +#define SYSREG_ICC_EOIR1_EL1 SYSREG(3, 0, 1, 12, 12) +#define SYSREG_ICC_HPPIR0_EL1 SYSREG(3, 0, 2, 12, 8) +#define SYSREG_ICC_HPPIR1_EL1 SYSREG(3, 0, 2, 12, 12) +#define SYSREG_ICC_IAR0_EL1 SYSREG(3, 0, 0, 12, 8) +#define SYSREG_ICC_IAR1_EL1 SYSREG(3, 0, 0, 12, 12) +#define SYSREG_ICC_IGRPEN0_EL1 SYSREG(3, 0, 6, 12, 12) +#define SYSREG_ICC_IGRPEN1_EL1 SYSREG(3, 0, 7, 12, 12) +#define SYSREG_ICC_PMR_EL1 SYSREG(3, 0, 0, 4, 6) +#define SYSREG_ICC_RPR_EL1 SYSREG(3, 0, 3, 12, 11) +#define SYSREG_ICC_SGI0R_EL1 SYSREG(3, 0, 7, 12, 11) +#define SYSREG_ICC_SGI1R_EL1 SYSREG(3, 0, 5, 12, 11) +#define SYSREG_ICC_SRE_EL1 SYSREG(3, 0, 5, 12, 12) + #define WFX_IS_WFE (1 << 0) =20 struct hvf_reg_match { @@ -418,6 +446,38 @@ void hvf_kick_vcpu_thread(CPUState *cpu) hv_vcpus_exit(&cpu->hvf->fd, 1); } =20 +static uint32_t hvf_reg2cp_reg(uint32_t reg) +{ + return ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, + (reg >> 10) & 0xf, + (reg >> 1) & 0xf, + (reg >> 20) & 0x3, + (reg >> 14) & 0x7, + (reg >> 17) & 0x7); +} + +static uint64_t hvf_sysreg_read_cp(CPUState *cpu, uint32_t reg) +{ + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + const ARMCPRegInfo *ri; + uint64_t val =3D 0; + + ri =3D get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); + if (ri) { + if (ri->type & ARM_CP_CONST) { + val =3D ri->resetvalue; + } else if (ri->readfn) { + val =3D ri->readfn(env, ri); + } else { + val =3D CPREG_FIELD64(env, ri); + } + DPRINTF("vgic read from %s [val=3D%016llx]", ri->name, val); + } + + return val; +} + static uint64_t hvf_sysreg_read(CPUState *cpu, uint32_t reg) { ARMCPU *arm_cpu =3D ARM_CPU(cpu); @@ -431,6 +491,39 @@ static uint64_t hvf_sysreg_read(CPUState *cpu, uint32_= t reg) case SYSREG_PMCCNTR_EL0: val =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); break; + case SYSREG_ICC_AP0R0_EL1: + case SYSREG_ICC_AP0R1_EL1: + case SYSREG_ICC_AP0R2_EL1: + case SYSREG_ICC_AP0R3_EL1: + case SYSREG_ICC_AP1R0_EL1: + case SYSREG_ICC_AP1R1_EL1: + case SYSREG_ICC_AP1R2_EL1: + case SYSREG_ICC_AP1R3_EL1: + case SYSREG_ICC_ASGI1R_EL1: + case SYSREG_ICC_BPR0_EL1: + case SYSREG_ICC_BPR1_EL1: + case SYSREG_ICC_DIR_EL1: + case SYSREG_ICC_EOIR0_EL1: + case SYSREG_ICC_EOIR1_EL1: + case SYSREG_ICC_HPPIR0_EL1: + case SYSREG_ICC_HPPIR1_EL1: + case SYSREG_ICC_IAR0_EL1: + case SYSREG_ICC_IAR1_EL1: + case SYSREG_ICC_IGRPEN0_EL1: + case SYSREG_ICC_IGRPEN1_EL1: + case SYSREG_ICC_PMR_EL1: + case SYSREG_ICC_SGI0R_EL1: + case SYSREG_ICC_SGI1R_EL1: + case SYSREG_ICC_SRE_EL1: + val =3D hvf_sysreg_read_cp(cpu, reg); + break; + case SYSREG_ICC_CTLR_EL1: + val =3D hvf_sysreg_read_cp(cpu, reg); + + /* AP0R registers above 0 don't trap, expose less PRIs to fit */ + val &=3D ~ICC_CTLR_EL1_PRIBITS_MASK; + val |=3D 4 << ICC_CTLR_EL1_PRIBITS_SHIFT; + break; default: DPRINTF("unhandled sysreg read %08x (op0=3D%d op1=3D%d op2=3D%d " "crn=3D%d crm=3D%d)", reg, (reg >> 20) & 0x3, @@ -442,6 +535,24 @@ static uint64_t hvf_sysreg_read(CPUState *cpu, uint32_= t reg) return val; } =20 +static void hvf_sysreg_write_cp(CPUState *cpu, uint32_t reg, uint64_t val) +{ + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + const ARMCPRegInfo *ri; + + ri =3D get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); + + if (ri) { + if (ri->writefn) { + ri->writefn(env, ri, val); + } else { + CPREG_FIELD64(env, ri) =3D val; + } + DPRINTF("vgic write to %s [val=3D%016llx]", ri->name, val); + } +} + static void hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) { ARMCPU *arm_cpu =3D ARM_CPU(cpu); @@ -449,6 +560,36 @@ static void hvf_sysreg_write(CPUState *cpu, uint32_t r= eg, uint64_t val) switch (reg) { case SYSREG_CNTPCT_EL0: break; + case SYSREG_ICC_AP0R0_EL1: + case SYSREG_ICC_AP0R1_EL1: + case SYSREG_ICC_AP0R2_EL1: + case SYSREG_ICC_AP0R3_EL1: + case SYSREG_ICC_AP1R0_EL1: + case SYSREG_ICC_AP1R1_EL1: + case SYSREG_ICC_AP1R2_EL1: + case SYSREG_ICC_AP1R3_EL1: + case SYSREG_ICC_ASGI1R_EL1: + case SYSREG_ICC_BPR0_EL1: + case SYSREG_ICC_BPR1_EL1: + case SYSREG_ICC_CTLR_EL1: + case SYSREG_ICC_DIR_EL1: + case SYSREG_ICC_HPPIR0_EL1: + case SYSREG_ICC_HPPIR1_EL1: + case SYSREG_ICC_IAR0_EL1: + case SYSREG_ICC_IAR1_EL1: + case SYSREG_ICC_IGRPEN0_EL1: + case SYSREG_ICC_IGRPEN1_EL1: + case SYSREG_ICC_PMR_EL1: + case SYSREG_ICC_SGI0R_EL1: + case SYSREG_ICC_SGI1R_EL1: + case SYSREG_ICC_SRE_EL1: + hvf_sysreg_write_cp(cpu, reg, val); + break; + case SYSREG_ICC_EOIR0_EL1: + case SYSREG_ICC_EOIR1_EL1: + hvf_sysreg_write_cp(cpu, reg, val); + qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 0); + hv_vcpu_set_vtimer_mask(cpu->hvf->fd, false); default: DPRINTF("unhandled sysreg write %08x", reg); break; --=20 2.24.3 (Apple Git-128)