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bh=PPFJtbSBv+i6Pojocxl1ogP8lcJx0qqqxn/l7gT8Uqo=; b=gc+9o0zu7WKUSBvE5H8BMjb5/MWQo8RymbIwMxkwUKBK9iVKD0EYbpFnJI3E0p6BRhJxSt fEcuQ4DzvPS/qAjLgNyphu534A14E2kp9YNqrcBAxDB6x2vfGRauvydc/Wcp4jwAbxewhd nsBI+2AsmmAS7vuYQcaXLT067s04Ze4= X-MC-Unique: x8TZep__PrqQ7UMIv4egyA-1 From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PULL 001/113] target/i386: fix operand order for PDEP and PEXT Date: Fri, 11 Dec 2020 07:31:03 -0500 Message-Id: <20201211123103.615007-2-pbonzini@redhat.com> In-Reply-To: <20201211123103.615007-1-pbonzini@redhat.com> References: <20201211123103.615007-1-pbonzini@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=pbonzini@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=63.128.21.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lenard Szolnoki , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @redhat.com) Content-Type: text/plain; charset="utf-8" For PDEP and PEXT, the mask is provided in the memory (mod+r/m) operand, and therefore is loaded in s->T0 by gen_ldst_modrm. The source is provided in the second source operand (VEX.vvvv) and therefore is loaded in s->T1. Fix the order in which they are passed to the helpers. Reported-by: Lenard Szolnoki Analyzed-by: Lenard Szolnoki Fixes: https://bugs.launchpad.net/qemu/+bug/1605123 Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- target/i386/translate.c | 8 +++---- tests/tcg/i386/Makefile.target | 3 +++ tests/tcg/i386/test-i386-bmi2.c | 42 +++++++++++++++++++++++++++++++++ 3 files changed, 49 insertions(+), 4 deletions(-) create mode 100644 tests/tcg/i386/test-i386-bmi2.c diff --git a/target/i386/translate.c b/target/i386/translate.c index 4c57307e42..e8f5f5803a 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -3936,14 +3936,14 @@ static void gen_sse(CPUX86State *env, DisasContext = *s, int b, } ot =3D mo_64_32(s->dflag); gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); - /* Note that by zero-extending the mask operand, we + /* Note that by zero-extending the source operand, we automatically handle zero-extending the result. */ if (ot =3D=3D MO_64) { tcg_gen_mov_tl(s->T1, cpu_regs[s->vex_v]); } else { tcg_gen_ext32u_tl(s->T1, cpu_regs[s->vex_v]); } - gen_helper_pdep(cpu_regs[reg], s->T0, s->T1); + gen_helper_pdep(cpu_regs[reg], s->T1, s->T0); break; =20 case 0x2f5: /* pext Gy, By, Ey */ @@ -3954,14 +3954,14 @@ static void gen_sse(CPUX86State *env, DisasContext = *s, int b, } ot =3D mo_64_32(s->dflag); gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); - /* Note that by zero-extending the mask operand, we + /* Note that by zero-extending the source operand, we automatically handle zero-extending the result. */ if (ot =3D=3D MO_64) { tcg_gen_mov_tl(s->T1, cpu_regs[s->vex_v]); } else { tcg_gen_ext32u_tl(s->T1, cpu_regs[s->vex_v]); } - gen_helper_pext(cpu_regs[reg], s->T0, s->T1); + gen_helper_pext(cpu_regs[reg], s->T1, s->T0); break; =20 case 0x1f6: /* adcx Gy, Ey */ diff --git a/tests/tcg/i386/Makefile.target b/tests/tcg/i386/Makefile.target index a66232a67d..ad187cb2c9 100644 --- a/tests/tcg/i386/Makefile.target +++ b/tests/tcg/i386/Makefile.target @@ -18,6 +18,9 @@ test-i386-pcmpistri: CFLAGS +=3D -msse4.2 run-test-i386-pcmpistri: QEMU_OPTS +=3D -cpu max run-plugin-test-i386-pcmpistri-%: QEMU_OPTS +=3D -cpu max =20 +run-test-i386-bmi2: QEMU_OPTS +=3D -cpu max +run-plugin-test-i386-bmi2-%: QEMU_OPTS +=3D -cpu max + # # hello-i386 is a barebones app # diff --git a/tests/tcg/i386/test-i386-bmi2.c b/tests/tcg/i386/test-i386-bmi= 2.c new file mode 100644 index 0000000000..935a4d2a73 --- /dev/null +++ b/tests/tcg/i386/test-i386-bmi2.c @@ -0,0 +1,42 @@ +/* See if various BMI2 instructions give expected results */ +#include +#include + +int main(int argc, char *argv[]) { + uint64_t ehlo =3D 0x202020204f4c4845ull; + uint64_t mask =3D 0xa080800302020001ull; + uint32_t result32; + +#ifdef __x86_64 + uint64_t result64; + + /* 64 bits */ + asm volatile ("pextq %2, %1, %0" : "=3Dr"(result64) : "r"(ehlo), "m"= (mask)); + assert(result64 =3D=3D 133); + + asm volatile ("pdepq %2, %1, %0" : "=3Dr"(result64) : "r"(result64),= "m"(mask)); + assert(result64 =3D=3D (ehlo & mask)); + + asm volatile ("pextq %2, %1, %0" : "=3Dr"(result64) : "r"(-1ull), "m= "(mask)); + assert(result64 =3D=3D 511); /* mask has 9 bits set */ + + asm volatile ("pdepq %2, %1, %0" : "=3Dr"(result64) : "r"(-1ull), "m= "(mask)); + assert(result64 =3D=3D mask); +#endif + + /* 32 bits */ + asm volatile ("pextl %2, %k1, %k0" : "=3Dr"(result32) : "r"((uint32_= t) ehlo), "m"(mask)); + assert(result32 =3D=3D 5); + + asm volatile ("pdepl %2, %k1, %k0" : "=3Dr"(result32) : "r"(result32= ), "m"(mask)); + assert(result32 =3D=3D (uint32_t)(ehlo & mask)); + + asm volatile ("pextl %2, %k1, %k0" : "=3Dr"(result32) : "r"(-1ull), = "m"(mask)); + assert(result32 =3D=3D 7); /* mask has 3 bits set */ + + asm volatile ("pdepl %2, %k1, %k0" : "=3Dr"(result32) : "r"(-1ull), = "m"(mask)); + assert(result32 =3D=3D (uint32_t)mask); + + return 0; +} + --=20 2.26.2