From nobody Fri May 17 09:38:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607683006; cv=none; d=zohomail.com; s=zohoarc; b=ZS1FrmV7waA2IS8A3n37FT8JWFVgdERgimlIfiU/Avlm16LdJ8ymJwbfxOJsdbcWPBdCyMdGXvn2AROiLl7N0gNSiMN7hSVQHKraW2sfspTiv9XS96/JgoG6WdkgjlUwdVdOWbZDoxR8fv9YdGjU87JPEkRGYkh+2oVnw49elJU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607683006; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jJUXi9Dr8l1potkhMLF8zvtktAG0tJ/dwZMYtxNPRBo=; b=QarXh4DNZ9VQqJQj+F0tG460FPLm2O8pog6xUh82FLlYkHCak7WCqQ1Dfgjl8eTp2oK45TUG/6rc2+EH9nv7XnAL1PKj5iVZxism6Z+ZFEZwuUm5wjbB7TyeXchkhGG6vCYUhNNAOJoyIkMtz3lb8jgA2Pgi9kCiezMDwSVtslU= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 160768300644436.937371241549386; Fri, 11 Dec 2020 02:36:46 -0800 (PST) Received: from localhost ([::1]:45784 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knfNj-0007ni-UK for importer@patchew.org; Fri, 11 Dec 2020 05:10:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39140) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knfMR-0006cR-F2 for qemu-devel@nongnu.org; Fri, 11 Dec 2020 05:09:15 -0500 Received: from mx2.suse.de ([195.135.220.15]:49492) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knfMO-0007ap-OS for qemu-devel@nongnu.org; Fri, 11 Dec 2020 05:09:15 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 38C9BB16A; Fri, 11 Dec 2020 10:09:11 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 1/7] accel: extend AccelState and AccelClass to user-mode Date: Fri, 11 Dec 2020 11:09:02 +0100 Message-Id: <20201211100908.19696-2-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211100908.19696-1-cfontana@suse.de> References: <20201211100908.19696-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e --- include/hw/boards.h | 2 +- include/{sysemu =3D> qemu}/accel.h | 14 +++++---- include/sysemu/hvf.h | 2 +- include/sysemu/kvm.h | 2 +- include/sysemu/kvm_int.h | 2 +- target/i386/hvf/hvf-i386.h | 2 +- accel/accel-common.c | 50 ++++++++++++++++++++++++++++++ accel/{accel.c =3D> accel-softmmu.c} | 27 ++-------------- accel/accel-user.c | 24 ++++++++++++++ accel/qtest/qtest.c | 2 +- accel/tcg/tcg-all.c | 13 ++++++-- accel/xen/xen-all.c | 2 +- bsd-user/main.c | 6 +++- linux-user/main.c | 6 +++- softmmu/memory.c | 2 +- softmmu/qtest.c | 2 +- softmmu/vl.c | 2 +- target/i386/hax/hax-all.c | 2 +- target/i386/hvf/hvf.c | 2 +- target/i386/hvf/x86_task.c | 2 +- target/i386/whpx/whpx-all.c | 2 +- MAINTAINERS | 2 +- accel/meson.build | 4 ++- accel/tcg/meson.build | 2 +- 24 files changed, 124 insertions(+), 52 deletions(-) rename include/{sysemu =3D> qemu}/accel.h (95%) create mode 100644 accel/accel-common.c rename accel/{accel.c =3D> accel-softmmu.c} (75%) create mode 100644 accel/accel-user.c diff --git a/include/hw/boards.h b/include/hw/boards.h index f94f4ad5d8..f8ae50c49c 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -6,7 +6,7 @@ #include "exec/memory.h" #include "sysemu/hostmem.h" #include "sysemu/blockdev.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "qapi/qapi-types-machine.h" #include "qemu/module.h" #include "qom/object.h" diff --git a/include/sysemu/accel.h b/include/qemu/accel.h similarity index 95% rename from include/sysemu/accel.h rename to include/qemu/accel.h index e08b8ab8fa..fac4a18703 100644 --- a/include/sysemu/accel.h +++ b/include/qemu/accel.h @@ -20,8 +20,8 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN * THE SOFTWARE. */ -#ifndef HW_ACCEL_H -#define HW_ACCEL_H +#ifndef QEMU_ACCEL_H +#define QEMU_ACCEL_H =20 #include "qom/object.h" #include "exec/hwaddr.h" @@ -37,8 +37,8 @@ typedef struct AccelClass { /*< public >*/ =20 const char *name; -#ifndef CONFIG_USER_ONLY int (*init_machine)(MachineState *ms); +#ifndef CONFIG_USER_ONLY void (*setup_post)(MachineState *ms, AccelState *accel); bool (*has_memory)(MachineState *ms, AddressSpace *as, hwaddr start_addr, hwaddr size); @@ -67,11 +67,13 @@ typedef struct AccelClass { OBJECT_GET_CLASS(AccelClass, (obj), TYPE_ACCEL) =20 AccelClass *accel_find(const char *opt_name); +AccelState *current_accel(void); + +#ifndef CONFIG_USER_ONLY int accel_init_machine(AccelState *accel, MachineState *ms); =20 /* Called just before os_setup_post (ie just before drop OS privs) */ void accel_setup_post(MachineState *ms); +#endif /* !CONFIG_USER_ONLY */ =20 -AccelState *current_accel(void); - -#endif +#endif /* QEMU_ACCEL_H */ diff --git a/include/sysemu/hvf.h b/include/sysemu/hvf.h index f893768df9..c98636bc81 100644 --- a/include/sysemu/hvf.h +++ b/include/sysemu/hvf.h @@ -13,7 +13,7 @@ #ifndef HVF_H #define HVF_H =20 -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "qom/object.h" =20 #ifdef CONFIG_HVF diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index bb5d5cf497..739682f3c3 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -17,7 +17,7 @@ #include "qemu/queue.h" #include "hw/core/cpu.h" #include "exec/memattrs.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "qom/object.h" =20 #ifdef NEED_CPU_H diff --git a/include/sysemu/kvm_int.h b/include/sysemu/kvm_int.h index 65740806da..ccb8869f01 100644 --- a/include/sysemu/kvm_int.h +++ b/include/sysemu/kvm_int.h @@ -10,7 +10,7 @@ #define QEMU_KVM_INT_H =20 #include "exec/memory.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "sysemu/kvm.h" =20 typedef struct KVMSlot diff --git a/target/i386/hvf/hvf-i386.h b/target/i386/hvf/hvf-i386.h index e0edffd077..50b914fd67 100644 --- a/target/i386/hvf/hvf-i386.h +++ b/target/i386/hvf/hvf-i386.h @@ -16,7 +16,7 @@ #ifndef HVF_I386_H #define HVF_I386_H =20 -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "sysemu/hvf.h" #include "cpu.h" #include "x86.h" diff --git a/accel/accel-common.c b/accel/accel-common.c new file mode 100644 index 0000000000..ddec8cb5ae --- /dev/null +++ b/accel/accel-common.c @@ -0,0 +1,50 @@ +/* + * QEMU accel class, components common to system emulation and user mode + * + * Copyright (c) 2003-2008 Fabrice Bellard + * Copyright (c) 2014 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu/accel.h" + +static const TypeInfo accel_type =3D { + .name =3D TYPE_ACCEL, + .parent =3D TYPE_OBJECT, + .class_size =3D sizeof(AccelClass), + .instance_size =3D sizeof(AccelState), +}; + +/* Lookup AccelClass from opt_name. Returns NULL if not found */ +AccelClass *accel_find(const char *opt_name) +{ + char *class_name =3D g_strdup_printf(ACCEL_CLASS_NAME("%s"), opt_name); + AccelClass *ac =3D ACCEL_CLASS(object_class_by_name(class_name)); + g_free(class_name); + return ac; +} + +static void register_accel_types(void) +{ + type_register_static(&accel_type); +} + +type_init(register_accel_types); diff --git a/accel/accel.c b/accel/accel-softmmu.c similarity index 75% rename from accel/accel.c rename to accel/accel-softmmu.c index cb555e3b06..f89da8f9d1 100644 --- a/accel/accel.c +++ b/accel/accel-softmmu.c @@ -1,5 +1,5 @@ /* - * QEMU System Emulator, accelerator interfaces + * QEMU accel class, system emulation components * * Copyright (c) 2003-2008 Fabrice Bellard * Copyright (c) 2014 Red Hat Inc. @@ -24,28 +24,12 @@ */ =20 #include "qemu/osdep.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "hw/boards.h" #include "sysemu/arch_init.h" #include "sysemu/sysemu.h" #include "qom/object.h" =20 -static const TypeInfo accel_type =3D { - .name =3D TYPE_ACCEL, - .parent =3D TYPE_OBJECT, - .class_size =3D sizeof(AccelClass), - .instance_size =3D sizeof(AccelState), -}; - -/* Lookup AccelClass from opt_name. Returns NULL if not found */ -AccelClass *accel_find(const char *opt_name) -{ - char *class_name =3D g_strdup_printf(ACCEL_CLASS_NAME("%s"), opt_name); - AccelClass *ac =3D ACCEL_CLASS(object_class_by_name(class_name)); - g_free(class_name); - return ac; -} - int accel_init_machine(AccelState *accel, MachineState *ms) { AccelClass *acc =3D ACCEL_GET_CLASS(accel); @@ -76,10 +60,3 @@ void accel_setup_post(MachineState *ms) acc->setup_post(ms, accel); } } - -static void register_accel_types(void) -{ - type_register_static(&accel_type); -} - -type_init(register_accel_types); diff --git a/accel/accel-user.c b/accel/accel-user.c new file mode 100644 index 0000000000..26bdda6236 --- /dev/null +++ b/accel/accel-user.c @@ -0,0 +1,24 @@ +/* + * QEMU accel class, user-mode components + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/accel.h" + +AccelState *current_accel(void) +{ + static AccelState *accel; + + if (!accel) { + AccelClass *ac =3D accel_find("tcg"); + + g_assert(ac !=3D NULL); + accel =3D ACCEL(object_new_with_class(OBJECT_CLASS(ac))); + } + return accel; +} diff --git a/accel/qtest/qtest.c b/accel/qtest/qtest.c index b282cea5cf..b4e731cb2b 100644 --- a/accel/qtest/qtest.c +++ b/accel/qtest/qtest.c @@ -17,7 +17,7 @@ #include "qemu/module.h" #include "qemu/option.h" #include "qemu/config-file.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "sysemu/qtest.h" #include "sysemu/cpus.h" #include "sysemu/cpu-timers.h" diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 1ac0b76515..7125d0cc29 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -30,9 +30,12 @@ #include "tcg/tcg.h" #include "qapi/error.h" #include "qemu/error-report.h" -#include "hw/boards.h" +#include "qemu/accel.h" #include "qapi/qapi-builtin-visit.h" + +#ifndef CONFIG_USER_ONLY #include "tcg-cpus.h" +#endif /* CONFIG_USER_ONLY */ =20 struct TCGState { AccelState parent_obj; @@ -106,8 +109,12 @@ static int tcg_init(MachineState *ms) mttcg_enabled =3D s->mttcg_enabled; =20 /* - * Initialize TCG regions + * Initialize TCG regions only for softmmu. + * + * This needs to be done later for user mode, because the prologue + * generation needs to be delayed so that GUEST_BASE is already set. */ +#ifndef CONFIG_USER_ONLY tcg_region_init(); =20 if (mttcg_enabled) { @@ -117,6 +124,8 @@ static int tcg_init(MachineState *ms) } else { cpus_register_accel(&tcg_cpus_rr); } +#endif /* !CONFIG_USER_ONLY */ + return 0; } =20 diff --git a/accel/xen/xen-all.c b/accel/xen/xen-all.c index 878a4089d9..594aaf6b49 100644 --- a/accel/xen/xen-all.c +++ b/accel/xen/xen-all.c @@ -15,7 +15,7 @@ #include "hw/xen/xen-legacy-backend.h" #include "hw/xen/xen_pt.h" #include "chardev/char.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "sysemu/cpus.h" #include "sysemu/xen.h" #include "sysemu/runstate.h" diff --git a/bsd-user/main.c b/bsd-user/main.c index 0a918e8f74..ff295bcb29 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu-common.h" #include "qemu/units.h" +#include "qemu/accel.h" #include "sysemu/tcg.h" #include "qemu-version.h" #include @@ -908,8 +909,11 @@ int main(int argc, char **argv) } =20 /* init tcg before creating CPUs and to get qemu_host_page_size */ - tcg_exec_init(0); + { + AccelClass *ac =3D ACCEL_GET_CLASS(current_accel()); =20 + ac->init_machine(NULL); + } cpu_type =3D parse_cpu_option(cpu_model); cpu =3D cpu_create(cpu_type); env =3D cpu->env_ptr; diff --git a/linux-user/main.c b/linux-user/main.c index 24d1eb73ad..5c059a8445 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu-common.h" #include "qemu/units.h" +#include "qemu/accel.h" #include "sysemu/tcg.h" #include "qemu-version.h" #include @@ -703,8 +704,11 @@ int main(int argc, char **argv, char **envp) cpu_type =3D parse_cpu_option(cpu_model); =20 /* init tcg before creating CPUs and to get qemu_host_page_size */ - tcg_exec_init(0); + { + AccelClass *ac =3D ACCEL_GET_CLASS(current_accel()); =20 + ac->init_machine(NULL); + } cpu =3D cpu_create(cpu_type); env =3D cpu->env_ptr; cpu_reset(cpu); diff --git a/softmmu/memory.c b/softmmu/memory.c index 22bacbbc78..585ec6f8dc 100644 --- a/softmmu/memory.c +++ b/softmmu/memory.c @@ -32,7 +32,7 @@ #include "sysemu/kvm.h" #include "sysemu/runstate.h" #include "sysemu/tcg.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "hw/boards.h" #include "migration/vmstate.h" =20 diff --git a/softmmu/qtest.c b/softmmu/qtest.c index 7965dc9a16..130c366615 100644 --- a/softmmu/qtest.c +++ b/softmmu/qtest.c @@ -20,7 +20,7 @@ #include "exec/ioport.h" #include "exec/memory.h" #include "hw/irq.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "sysemu/cpu-timers.h" #include "qemu/config-file.h" #include "qemu/option.h" diff --git a/softmmu/vl.c b/softmmu/vl.c index e6e0ad5a92..bc20c526d2 100644 --- a/softmmu/vl.c +++ b/softmmu/vl.c @@ -40,7 +40,7 @@ =20 #include "qemu/error-report.h" #include "qemu/sockets.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "hw/usb.h" #include "hw/isa/isa.h" #include "hw/scsi/scsi.h" diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c index fecfe8cd6e..d7f4bb44a7 100644 --- a/target/i386/hax/hax-all.c +++ b/target/i386/hax/hax-all.c @@ -28,7 +28,7 @@ #include "exec/address-spaces.h" =20 #include "qemu-common.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" #include "hw/boards.h" diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index ed9356565c..ffc9efa40f 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -69,7 +69,7 @@ #include "exec/address-spaces.h" #include "hw/i386/apic_internal.h" #include "qemu/main-loop.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "target/i386/cpu.h" =20 #include "hvf-cpus.h" diff --git a/target/i386/hvf/x86_task.c b/target/i386/hvf/x86_task.c index 6f04478b3a..d66dfd7669 100644 --- a/target/i386/hvf/x86_task.c +++ b/target/i386/hvf/x86_task.c @@ -28,7 +28,7 @@ =20 #include "hw/i386/apic_internal.h" #include "qemu/main-loop.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "target/i386/cpu.h" =20 // TODO: taskswitch handling diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index f4f3e33eac..ee6b606194 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -13,7 +13,7 @@ #include "exec/address-spaces.h" #include "exec/ioport.h" #include "qemu-common.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "sysemu/whpx.h" #include "sysemu/cpus.h" #include "sysemu/runstate.h" diff --git a/MAINTAINERS b/MAINTAINERS index d876f504a6..6235dd3a9f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -434,7 +434,7 @@ Overall M: Richard Henderson R: Paolo Bonzini S: Maintained -F: include/sysemu/accel.h +F: include/qemu/accel.h F: accel/accel.c F: accel/Makefile.objs F: accel/stubs/Makefile.objs diff --git a/accel/meson.build b/accel/meson.build index b26cca227a..b44ba30c86 100644 --- a/accel/meson.build +++ b/accel/meson.build @@ -1,4 +1,6 @@ -softmmu_ss.add(files('accel.c')) +specific_ss.add(files('accel-common.c')) +softmmu_ss.add(files('accel-softmmu.c')) +user_ss.add(files('accel-user.c')) =20 subdir('qtest') subdir('kvm') diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index f39aab0a0c..424d9bb1fc 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -1,5 +1,6 @@ tcg_ss =3D ss.source_set() tcg_ss.add(files( + 'tcg-all.c', 'cpu-exec-common.c', 'cpu-exec.c', 'tcg-runtime-gvec.c', @@ -13,7 +14,6 @@ tcg_ss.add(when: 'CONFIG_PLUGIN', if_true: [files('plugin= -gen.c'), libdl]) specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss) =20 specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files( - 'tcg-all.c', 'cputlb.c', 'tcg-cpus.c', 'tcg-cpus-mttcg.c', --=20 2.26.2 From nobody Fri May 17 09:38:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 11 Dec 2020 02:22:42 -0800 (PST) Received: from localhost ([::1]:46290 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knfNq-00081d-Kh for importer@patchew.org; Fri, 11 Dec 2020 05:10:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39216) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knfMU-0006fu-Qx for qemu-devel@nongnu.org; Fri, 11 Dec 2020 05:09:18 -0500 Received: from mx2.suse.de ([195.135.220.15]:49536) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knfMP-0007bV-BN for qemu-devel@nongnu.org; Fri, 11 Dec 2020 05:09:18 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 0BBF9AC94; Fri, 11 Dec 2020 10:09:12 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 2/7] accel: replace struct CpusAccel with AccelOpsClass Date: Fri, 11 Dec 2020 11:09:03 +0100 Message-Id: <20201211100908.19696-3-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211100908.19696-1-cfontana@suse.de> References: <20201211100908.19696-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" also centralize the registration of the cpus.c module accelerator operations in accel/accel-softmmu.c Consequently, rename all tcg-cpus.c, kvm-cpus.c etc to tcg-accel-ops.c, kvm-accel-ops.c etc, also matching the object type names. Signed-off-by: Claudio Fontana --- accel/accel-softmmu.h | 15 ++++++ accel/kvm/kvm-cpus.h | 2 - ...g-cpus-icount.h =3D> tcg-accel-ops-icount.h} | 2 + accel/tcg/tcg-accel-ops-mttcg.h | 19 ++++++++ .../tcg/{tcg-cpus-rr.h =3D> tcg-accel-ops-rr.h} | 0 accel/tcg/{tcg-cpus.h =3D> tcg-accel-ops.h} | 6 +-- include/qemu/accel.h | 2 + include/sysemu/accel-ops.h | 45 ++++++++++++++++++ include/sysemu/cpus.h | 26 ++-------- .../i386/hax/{hax-cpus.h =3D> hax-accel-ops.h} | 2 - target/i386/hax/hax-windows.h | 2 +- .../i386/hvf/{hvf-cpus.h =3D> hvf-accel-ops.h} | 2 - .../whpx/{whpx-cpus.h =3D> whpx-accel-ops.h} | 2 - accel/accel-common.c | 11 +++++ accel/accel-softmmu.c | 43 +++++++++++++++-- accel/kvm/{kvm-cpus.c =3D> kvm-accel-ops.c} | 26 +++++++--- accel/kvm/kvm-all.c | 2 - accel/qtest/qtest.c | 23 ++++++--- ...g-cpus-icount.c =3D> tcg-accel-ops-icount.c} | 21 +++------ ...tcg-cpus-mttcg.c =3D> tcg-accel-ops-mttcg.c} | 14 ++---- .../tcg/{tcg-cpus-rr.c =3D> tcg-accel-ops-rr.c} | 13 ++--- accel/tcg/{tcg-cpus.c =3D> tcg-accel-ops.c} | 47 ++++++++++++++++++- accel/tcg/tcg-all.c | 12 ----- accel/xen/xen-all.c | 22 ++++++--- bsd-user/main.c | 3 +- linux-user/main.c | 1 + softmmu/cpus.c | 12 ++--- softmmu/vl.c | 6 ++- .../i386/hax/{hax-cpus.c =3D> hax-accel-ops.c} | 31 ++++++++---- target/i386/hax/hax-all.c | 5 +- target/i386/hax/hax-mem.c | 2 +- target/i386/hax/hax-posix.c | 2 +- target/i386/hax/hax-windows.c | 2 +- .../i386/hvf/{hvf-cpus.c =3D> hvf-accel-ops.c} | 29 +++++++++--- target/i386/hvf/hvf.c | 3 +- target/i386/hvf/x86hvf.c | 2 +- .../whpx/{whpx-cpus.c =3D> whpx-accel-ops.c} | 31 ++++++++---- target/i386/whpx/whpx-all.c | 4 +- MAINTAINERS | 3 +- accel/kvm/meson.build | 2 +- accel/tcg/meson.build | 8 ++-- target/i386/hax/meson.build | 2 +- target/i386/hvf/meson.build | 2 +- target/i386/whpx/meson.build | 2 +- 44 files changed, 349 insertions(+), 162 deletions(-) create mode 100644 accel/accel-softmmu.h rename accel/tcg/{tcg-cpus-icount.h =3D> tcg-accel-ops-icount.h} (88%) create mode 100644 accel/tcg/tcg-accel-ops-mttcg.h rename accel/tcg/{tcg-cpus-rr.h =3D> tcg-accel-ops-rr.h} (100%) rename accel/tcg/{tcg-cpus.h =3D> tcg-accel-ops.h} (72%) create mode 100644 include/sysemu/accel-ops.h rename target/i386/hax/{hax-cpus.h =3D> hax-accel-ops.h} (95%) rename target/i386/hvf/{hvf-cpus.h =3D> hvf-accel-ops.h} (94%) rename target/i386/whpx/{whpx-cpus.h =3D> whpx-accel-ops.h} (96%) rename accel/kvm/{kvm-cpus.c =3D> kvm-accel-ops.c} (72%) rename accel/tcg/{tcg-cpus-icount.c =3D> tcg-accel-ops-icount.c} (89%) rename accel/tcg/{tcg-cpus-mttcg.c =3D> tcg-accel-ops-mttcg.c} (92%) rename accel/tcg/{tcg-cpus-rr.c =3D> tcg-accel-ops-rr.c} (97%) rename accel/tcg/{tcg-cpus.c =3D> tcg-accel-ops.c} (63%) rename target/i386/hax/{hax-cpus.c =3D> hax-accel-ops.c} (69%) rename target/i386/hvf/{hvf-cpus.c =3D> hvf-accel-ops.c} (84%) rename target/i386/whpx/{whpx-cpus.c =3D> whpx-accel-ops.c} (72%) diff --git a/accel/accel-softmmu.h b/accel/accel-softmmu.h new file mode 100644 index 0000000000..2877b5c234 --- /dev/null +++ b/accel/accel-softmmu.h @@ -0,0 +1,15 @@ +/* + * QEMU System Emulation accel internal functions + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef ACCEL_SOFTMMU_H +#define ACCEL_SOFTMMU_H + +void accel_init_ops_interfaces(AccelClass *ac); + +#endif /* ACCEL_SOFTMMU_H */ diff --git a/accel/kvm/kvm-cpus.h b/accel/kvm/kvm-cpus.h index 3df732b816..bf0bd1bee4 100644 --- a/accel/kvm/kvm-cpus.h +++ b/accel/kvm/kvm-cpus.h @@ -12,8 +12,6 @@ =20 #include "sysemu/cpus.h" =20 -extern const CpusAccel kvm_cpus; - int kvm_init_vcpu(CPUState *cpu, Error **errp); int kvm_cpu_exec(CPUState *cpu); void kvm_destroy_vcpu(CPUState *cpu); diff --git a/accel/tcg/tcg-cpus-icount.h b/accel/tcg/tcg-accel-ops-icount.h similarity index 88% rename from accel/tcg/tcg-cpus-icount.h rename to accel/tcg/tcg-accel-ops-icount.h index b695939dfa..d884aa2aaa 100644 --- a/accel/tcg/tcg-cpus-icount.h +++ b/accel/tcg/tcg-accel-ops-icount.h @@ -14,4 +14,6 @@ void icount_handle_deadline(void); void icount_prepare_for_run(CPUState *cpu); void icount_process_data(CPUState *cpu); =20 +void icount_handle_interrupt(CPUState *cpu, int mask); + #endif /* TCG_CPUS_ICOUNT_H */ diff --git a/accel/tcg/tcg-accel-ops-mttcg.h b/accel/tcg/tcg-accel-ops-mttc= g.h new file mode 100644 index 0000000000..0af91dd3b3 --- /dev/null +++ b/accel/tcg/tcg-accel-ops-mttcg.h @@ -0,0 +1,19 @@ +/* + * QEMU TCG Multi Threaded vCPUs implementation + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef TCG_CPUS_MTTCG_H +#define TCG_CPUS_MTTCG_H + +/* kick MTTCG vCPU thread */ +void mttcg_kick_vcpu_thread(CPUState *cpu); + +/* start an mttcg vCPU thread */ +void mttcg_start_vcpu_thread(CPUState *cpu); + +#endif /* TCG_CPUS_MTTCG_H */ diff --git a/accel/tcg/tcg-cpus-rr.h b/accel/tcg/tcg-accel-ops-rr.h similarity index 100% rename from accel/tcg/tcg-cpus-rr.h rename to accel/tcg/tcg-accel-ops-rr.h diff --git a/accel/tcg/tcg-cpus.h b/accel/tcg/tcg-accel-ops.h similarity index 72% rename from accel/tcg/tcg-cpus.h rename to accel/tcg/tcg-accel-ops.h index d6893a32f8..48130006de 100644 --- a/accel/tcg/tcg-cpus.h +++ b/accel/tcg/tcg-accel-ops.h @@ -14,12 +14,8 @@ =20 #include "sysemu/cpus.h" =20 -extern const CpusAccel tcg_cpus_mttcg; -extern const CpusAccel tcg_cpus_icount; -extern const CpusAccel tcg_cpus_rr; - void tcg_cpus_destroy(CPUState *cpu); int tcg_cpus_exec(CPUState *cpu); -void tcg_cpus_handle_interrupt(CPUState *cpu, int mask); +void tcg_handle_interrupt(CPUState *cpu, int mask); =20 #endif /* TCG_CPUS_H */ diff --git a/include/qemu/accel.h b/include/qemu/accel.h index fac4a18703..b9d6d69eb8 100644 --- a/include/qemu/accel.h +++ b/include/qemu/accel.h @@ -69,6 +69,8 @@ typedef struct AccelClass { AccelClass *accel_find(const char *opt_name); AccelState *current_accel(void); =20 +void accel_init_interfaces(AccelClass *ac); + #ifndef CONFIG_USER_ONLY int accel_init_machine(AccelState *accel, MachineState *ms); =20 diff --git a/include/sysemu/accel-ops.h b/include/sysemu/accel-ops.h new file mode 100644 index 0000000000..6102d2f80d --- /dev/null +++ b/include/sysemu/accel-ops.h @@ -0,0 +1,45 @@ +/* + * Accelerator OPS, used for cpus.c module + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef ACCEL_OPS_H +#define ACCEL_OPS_H + +#include "qom/object.h" + +#define ACCEL_OPS_SUFFIX "-ops" +#define TYPE_ACCEL_OPS "accel" ACCEL_OPS_SUFFIX +#define ACCEL_OPS_NAME(name) (name "-" TYPE_ACCEL_OPS) + +typedef struct AccelOpsClass AccelOpsClass; +DECLARE_CLASS_CHECKERS(AccelOpsClass, ACCEL_OPS, TYPE_ACCEL_OPS) + +/* cpus.c operations interface */ +struct AccelOpsClass { + /*< private >*/ + ObjectClass parent_class; + /*< public >*/ + + /* initialization function called when accel is chosen */ + void (*ops_init)(AccelOpsClass *ops); + + void (*create_vcpu_thread)(CPUState *cpu); /* MANDATORY NON-NULL */ + void (*kick_vcpu_thread)(CPUState *cpu); + + void (*synchronize_post_reset)(CPUState *cpu); + void (*synchronize_post_init)(CPUState *cpu); + void (*synchronize_state)(CPUState *cpu); + void (*synchronize_pre_loadvm)(CPUState *cpu); + + void (*handle_interrupt)(CPUState *cpu, int mask); + + int64_t (*get_virtual_clock)(void); + int64_t (*get_elapsed_ticks)(void); +}; + +#endif /* ACCEL_OPS_H */ diff --git a/include/sysemu/cpus.h b/include/sysemu/cpus.h index e8156728c6..2cd74392e0 100644 --- a/include/sysemu/cpus.h +++ b/include/sysemu/cpus.h @@ -2,30 +2,14 @@ #define QEMU_CPUS_H =20 #include "qemu/timer.h" +#include "sysemu/accel-ops.h" =20 -/* cpus.c */ +/* register accel-specific operations */ +void cpus_register_accel(const AccelOpsClass *i); =20 -/* CPU execution threads */ +/* accel/dummy-cpus.c */ =20 -typedef struct CpusAccel { - void (*create_vcpu_thread)(CPUState *cpu); /* MANDATORY */ - void (*kick_vcpu_thread)(CPUState *cpu); - - void (*synchronize_post_reset)(CPUState *cpu); - void (*synchronize_post_init)(CPUState *cpu); - void (*synchronize_state)(CPUState *cpu); - void (*synchronize_pre_loadvm)(CPUState *cpu); - - void (*handle_interrupt)(CPUState *cpu, int mask); - - int64_t (*get_virtual_clock)(void); - int64_t (*get_elapsed_ticks)(void); -} CpusAccel; - -/* register accel-specific cpus interface implementation */ -void cpus_register_accel(const CpusAccel *i); - -/* Create a dummy vcpu for CpusAccel->create_vcpu_thread */ +/* Create a dummy vcpu for AccelOpsClass->create_vcpu_thread */ void dummy_start_vcpu_thread(CPUState *); =20 /* interface available for cpus accelerator threads */ diff --git a/target/i386/hax/hax-cpus.h b/target/i386/hax/hax-accel-ops.h similarity index 95% rename from target/i386/hax/hax-cpus.h rename to target/i386/hax/hax-accel-ops.h index ee8ab7a631..c7698519cd 100644 --- a/target/i386/hax/hax-cpus.h +++ b/target/i386/hax/hax-accel-ops.h @@ -12,8 +12,6 @@ =20 #include "sysemu/cpus.h" =20 -extern const CpusAccel hax_cpus; - #include "hax-interface.h" #include "hax-i386.h" =20 diff --git a/target/i386/hax/hax-windows.h b/target/i386/hax/hax-windows.h index a5ce12d663..b1f5d4f32f 100644 --- a/target/i386/hax/hax-windows.h +++ b/target/i386/hax/hax-windows.h @@ -23,7 +23,7 @@ #include #include =20 -#include "hax-cpus.h" +#include "hax-accel-ops.h" =20 #define HAX_INVALID_FD INVALID_HANDLE_VALUE =20 diff --git a/target/i386/hvf/hvf-cpus.h b/target/i386/hvf/hvf-accel-ops.h similarity index 94% rename from target/i386/hvf/hvf-cpus.h rename to target/i386/hvf/hvf-accel-ops.h index ced31b82c0..8f992da168 100644 --- a/target/i386/hvf/hvf-cpus.h +++ b/target/i386/hvf/hvf-accel-ops.h @@ -12,8 +12,6 @@ =20 #include "sysemu/cpus.h" =20 -extern const CpusAccel hvf_cpus; - int hvf_init_vcpu(CPUState *); int hvf_vcpu_exec(CPUState *); void hvf_cpu_synchronize_state(CPUState *); diff --git a/target/i386/whpx/whpx-cpus.h b/target/i386/whpx/whpx-accel-ops= .h similarity index 96% rename from target/i386/whpx/whpx-cpus.h rename to target/i386/whpx/whpx-accel-ops.h index bdb367d1d0..2dee6d61ea 100644 --- a/target/i386/whpx/whpx-cpus.h +++ b/target/i386/whpx/whpx-accel-ops.h @@ -12,8 +12,6 @@ =20 #include "sysemu/cpus.h" =20 -extern const CpusAccel whpx_cpus; - int whpx_init_vcpu(CPUState *cpu); int whpx_vcpu_exec(CPUState *cpu); void whpx_destroy_vcpu(CPUState *cpu); diff --git a/accel/accel-common.c b/accel/accel-common.c index ddec8cb5ae..6b59873419 100644 --- a/accel/accel-common.c +++ b/accel/accel-common.c @@ -26,6 +26,10 @@ #include "qemu/osdep.h" #include "qemu/accel.h" =20 +#ifndef CONFIG_USER_ONLY +#include "accel-softmmu.h" +#endif /* !CONFIG_USER_ONLY */ + static const TypeInfo accel_type =3D { .name =3D TYPE_ACCEL, .parent =3D TYPE_OBJECT, @@ -42,6 +46,13 @@ AccelClass *accel_find(const char *opt_name) return ac; } =20 +void accel_init_interfaces(AccelClass *ac) +{ +#ifndef CONFIG_USER_ONLY + accel_init_ops_interfaces(ac); +#endif /* !CONFIG_USER_ONLY */ +} + static void register_accel_types(void) { type_register_static(&accel_type); diff --git a/accel/accel-softmmu.c b/accel/accel-softmmu.c index f89da8f9d1..2d15d3f2f4 100644 --- a/accel/accel-softmmu.c +++ b/accel/accel-softmmu.c @@ -26,9 +26,9 @@ #include "qemu/osdep.h" #include "qemu/accel.h" #include "hw/boards.h" -#include "sysemu/arch_init.h" -#include "sysemu/sysemu.h" -#include "qom/object.h" +#include "sysemu/cpus.h" + +#include "accel-softmmu.h" =20 int accel_init_machine(AccelState *accel, MachineState *ms) { @@ -60,3 +60,40 @@ void accel_setup_post(MachineState *ms) acc->setup_post(ms, accel); } } + +/* initialize the arch-independent accel operation interfaces */ +void accel_init_ops_interfaces(AccelClass *ac) +{ + const char *ac_name; + char *ops_name; + AccelOpsClass *ops; + + ac_name =3D object_class_get_name(OBJECT_CLASS(ac)); + g_assert(ac_name !=3D NULL); + + ops_name =3D g_strdup_printf("%s" ACCEL_OPS_SUFFIX, ac_name); + ops =3D ACCEL_OPS_CLASS(object_class_by_name(ops_name)); + g_free(ops_name); + + /* + * all accelerators need to define ops, providing at least a mandatory + * non-NULL create_vcpu_thread operation. + */ + g_assert(ops !=3D NULL); + if (ops->ops_init) { + ops->ops_init(ops); + } + cpus_register_accel(ops); +} + +static const TypeInfo accel_ops_type_info =3D { + .name =3D TYPE_ACCEL_OPS, + .parent =3D TYPE_OBJECT, + .abstract =3D true, + .class_size =3D sizeof(AccelOpsClass), +}; +static void accel_softmmu_register_types(void) +{ + type_register_static(&accel_ops_type_info); +} +type_init(accel_softmmu_register_types); diff --git a/accel/kvm/kvm-cpus.c b/accel/kvm/kvm-accel-ops.c similarity index 72% rename from accel/kvm/kvm-cpus.c rename to accel/kvm/kvm-accel-ops.c index d809b1e74c..430d09de03 100644 --- a/accel/kvm/kvm-cpus.c +++ b/accel/kvm/kvm-accel-ops.c @@ -74,11 +74,25 @@ static void kvm_start_vcpu_thread(CPUState *cpu) cpu, QEMU_THREAD_JOINABLE); } =20 -const CpusAccel kvm_cpus =3D { - .create_vcpu_thread =3D kvm_start_vcpu_thread, +static void kvm_accel_ops_class_init(ObjectClass *oc, void *data) +{ + AccelOpsClass *ops =3D ACCEL_OPS_CLASS(oc); =20 - .synchronize_post_reset =3D kvm_cpu_synchronize_post_reset, - .synchronize_post_init =3D kvm_cpu_synchronize_post_init, - .synchronize_state =3D kvm_cpu_synchronize_state, - .synchronize_pre_loadvm =3D kvm_cpu_synchronize_pre_loadvm, + ops->create_vcpu_thread =3D kvm_start_vcpu_thread; + ops->synchronize_post_reset =3D kvm_cpu_synchronize_post_reset; + ops->synchronize_post_init =3D kvm_cpu_synchronize_post_init; + ops->synchronize_state =3D kvm_cpu_synchronize_state; + ops->synchronize_pre_loadvm =3D kvm_cpu_synchronize_pre_loadvm; }; +static const TypeInfo kvm_accel_ops_type =3D { + .name =3D ACCEL_OPS_NAME("kvm"), + + .parent =3D TYPE_ACCEL_OPS, + .class_init =3D kvm_accel_ops_class_init, + .abstract =3D true, +}; +static void kvm_accel_ops_register_types(void) +{ + type_register_static(&kvm_accel_ops_type); +} +type_init(kvm_accel_ops_register_types); diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index baaa54249d..18be3cd113 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -2253,8 +2253,6 @@ static int kvm_init(MachineState *ms) ret =3D ram_block_discard_disable(true); assert(!ret); } - - cpus_register_accel(&kvm_cpus); return 0; =20 err: diff --git a/accel/qtest/qtest.c b/accel/qtest/qtest.c index b4e731cb2b..edb29f6fa4 100644 --- a/accel/qtest/qtest.c +++ b/accel/qtest/qtest.c @@ -25,14 +25,8 @@ #include "qemu/main-loop.h" #include "hw/core/cpu.h" =20 -const CpusAccel qtest_cpus =3D { - .create_vcpu_thread =3D dummy_start_vcpu_thread, - .get_virtual_clock =3D qtest_get_virtual_clock, -}; - static int qtest_init_accel(MachineState *ms) { - cpus_register_accel(&qtest_cpus); return 0; } =20 @@ -52,9 +46,26 @@ static const TypeInfo qtest_accel_type =3D { .class_init =3D qtest_accel_class_init, }; =20 +static void qtest_accel_ops_class_init(ObjectClass *oc, void *data) +{ + AccelOpsClass *ops =3D ACCEL_OPS_CLASS(oc); + + ops->create_vcpu_thread =3D dummy_start_vcpu_thread; + ops->get_virtual_clock =3D qtest_get_virtual_clock; +}; + +static const TypeInfo qtest_accel_ops_type =3D { + .name =3D ACCEL_OPS_NAME("qtest"), + + .parent =3D TYPE_ACCEL_OPS, + .class_init =3D qtest_accel_ops_class_init, + .abstract =3D true, +}; + static void qtest_type_init(void) { type_register_static(&qtest_accel_type); + type_register_static(&qtest_accel_ops_type); } =20 type_init(qtest_type_init); diff --git a/accel/tcg/tcg-cpus-icount.c b/accel/tcg/tcg-accel-ops-icount.c similarity index 89% rename from accel/tcg/tcg-cpus-icount.c rename to accel/tcg/tcg-accel-ops-icount.c index 9f45432275..87762b469c 100644 --- a/accel/tcg/tcg-cpus-icount.c +++ b/accel/tcg/tcg-accel-ops-icount.c @@ -32,9 +32,9 @@ #include "exec/exec-all.h" #include "hw/boards.h" =20 -#include "tcg-cpus.h" -#include "tcg-cpus-icount.h" -#include "tcg-cpus-rr.h" +#include "tcg-accel-ops.h" +#include "tcg-accel-ops-icount.h" +#include "tcg-accel-ops-rr.h" =20 static int64_t icount_get_limit(void) { @@ -93,7 +93,7 @@ void icount_prepare_for_run(CPUState *cpu) /* * These should always be cleared by icount_process_data after * each vCPU execution. However u16.high can be raised - * asynchronously by cpu_exit/cpu_interrupt/tcg_cpus_handle_interrupt + * asynchronously by cpu_exit/cpu_interrupt/tcg_handle_interrupt */ g_assert(cpu_neg(cpu)->icount_decr.u16.low =3D=3D 0); g_assert(cpu->icount_extra =3D=3D 0); @@ -125,23 +125,14 @@ void icount_process_data(CPUState *cpu) replay_mutex_unlock(); } =20 -static void icount_handle_interrupt(CPUState *cpu, int mask) +void icount_handle_interrupt(CPUState *cpu, int mask) { int old_mask =3D cpu->interrupt_request; =20 - tcg_cpus_handle_interrupt(cpu, mask); + tcg_handle_interrupt(cpu, mask); if (qemu_cpu_is_self(cpu) && !cpu->can_do_io && (mask & ~old_mask) !=3D 0) { cpu_abort(cpu, "Raised interrupt while not in I/O function"); } } - -const CpusAccel tcg_cpus_icount =3D { - .create_vcpu_thread =3D rr_start_vcpu_thread, - .kick_vcpu_thread =3D rr_kick_vcpu_thread, - - .handle_interrupt =3D icount_handle_interrupt, - .get_virtual_clock =3D icount_get, - .get_elapsed_ticks =3D icount_get, -}; diff --git a/accel/tcg/tcg-cpus-mttcg.c b/accel/tcg/tcg-accel-ops-mttcg.c similarity index 92% rename from accel/tcg/tcg-cpus-mttcg.c rename to accel/tcg/tcg-accel-ops-mttcg.c index 9c3767d260..42973fb062 100644 --- a/accel/tcg/tcg-cpus-mttcg.c +++ b/accel/tcg/tcg-accel-ops-mttcg.c @@ -32,7 +32,8 @@ #include "exec/exec-all.h" #include "hw/boards.h" =20 -#include "tcg-cpus.h" +#include "tcg-accel-ops.h" +#include "tcg-accel-ops-mttcg.h" =20 /* * In the multi-threaded case each vCPU has its own thread. The TLS @@ -103,12 +104,12 @@ static void *mttcg_cpu_thread_fn(void *arg) return NULL; } =20 -static void mttcg_kick_vcpu_thread(CPUState *cpu) +void mttcg_kick_vcpu_thread(CPUState *cpu) { cpu_exit(cpu); } =20 -static void mttcg_start_vcpu_thread(CPUState *cpu) +void mttcg_start_vcpu_thread(CPUState *cpu) { char thread_name[VCPU_THREAD_NAME_SIZE]; =20 @@ -131,10 +132,3 @@ static void mttcg_start_vcpu_thread(CPUState *cpu) cpu->hThread =3D qemu_thread_get_handle(cpu->thread); #endif } - -const CpusAccel tcg_cpus_mttcg =3D { - .create_vcpu_thread =3D mttcg_start_vcpu_thread, - .kick_vcpu_thread =3D mttcg_kick_vcpu_thread, - - .handle_interrupt =3D tcg_cpus_handle_interrupt, -}; diff --git a/accel/tcg/tcg-cpus-rr.c b/accel/tcg/tcg-accel-ops-rr.c similarity index 97% rename from accel/tcg/tcg-cpus-rr.c rename to accel/tcg/tcg-accel-ops-rr.c index 0181d2e4eb..4a66055e0d 100644 --- a/accel/tcg/tcg-cpus-rr.c +++ b/accel/tcg/tcg-accel-ops-rr.c @@ -32,9 +32,9 @@ #include "exec/exec-all.h" #include "hw/boards.h" =20 -#include "tcg-cpus.h" -#include "tcg-cpus-rr.h" -#include "tcg-cpus-icount.h" +#include "tcg-accel-ops.h" +#include "tcg-accel-ops-rr.h" +#include "tcg-accel-ops-icount.h" =20 /* Kick all RR vCPUs */ void rr_kick_vcpu_thread(CPUState *unused) @@ -296,10 +296,3 @@ void rr_start_vcpu_thread(CPUState *cpu) cpu->created =3D true; } } - -const CpusAccel tcg_cpus_rr =3D { - .create_vcpu_thread =3D rr_start_vcpu_thread, - .kick_vcpu_thread =3D rr_kick_vcpu_thread, - - .handle_interrupt =3D tcg_cpus_handle_interrupt, -}; diff --git a/accel/tcg/tcg-cpus.c b/accel/tcg/tcg-accel-ops.c similarity index 63% rename from accel/tcg/tcg-cpus.c rename to accel/tcg/tcg-accel-ops.c index e335f9f155..3017f66dd7 100644 --- a/accel/tcg/tcg-cpus.c +++ b/accel/tcg/tcg-accel-ops.c @@ -34,7 +34,10 @@ #include "exec/exec-all.h" #include "hw/boards.h" =20 -#include "tcg-cpus.h" +#include "tcg-accel-ops.h" +#include "tcg-accel-ops-mttcg.h" +#include "tcg-accel-ops-rr.h" +#include "tcg-accel-ops-icount.h" =20 /* common functionality among all TCG variants */ =20 @@ -64,7 +67,7 @@ int tcg_cpus_exec(CPUState *cpu) } =20 /* mask must never be zero, except for A20 change call */ -void tcg_cpus_handle_interrupt(CPUState *cpu, int mask) +void tcg_handle_interrupt(CPUState *cpu, int mask) { g_assert(qemu_mutex_iothread_locked()); =20 @@ -80,3 +83,43 @@ void tcg_cpus_handle_interrupt(CPUState *cpu, int mask) qatomic_set(&cpu_neg(cpu)->icount_decr.u16.high, -1); } } + +static void tcg_accel_ops_init(AccelOpsClass *ops) +{ + if (qemu_tcg_mttcg_enabled()) { + ops->create_vcpu_thread =3D mttcg_start_vcpu_thread; + ops->kick_vcpu_thread =3D mttcg_kick_vcpu_thread; + ops->handle_interrupt =3D tcg_handle_interrupt; + + } else if (icount_enabled()) { + ops->create_vcpu_thread =3D rr_start_vcpu_thread; + ops->kick_vcpu_thread =3D rr_kick_vcpu_thread; + ops->handle_interrupt =3D icount_handle_interrupt; + ops->get_virtual_clock =3D icount_get; + ops->get_elapsed_ticks =3D icount_get; + + } else { + ops->create_vcpu_thread =3D rr_start_vcpu_thread; + ops->kick_vcpu_thread =3D rr_kick_vcpu_thread; + ops->handle_interrupt =3D tcg_handle_interrupt; + } +} + +static void tcg_accel_ops_class_init(ObjectClass *oc, void *data) +{ + AccelOpsClass *ops =3D ACCEL_OPS_CLASS(oc); + + ops->ops_init =3D tcg_accel_ops_init; +}; +static const TypeInfo tcg_accel_ops_type =3D { + .name =3D ACCEL_OPS_NAME("tcg"), + + .parent =3D TYPE_ACCEL_OPS, + .class_init =3D tcg_accel_ops_class_init, + .abstract =3D true, +}; +static void tcg_accel_ops_register_types(void) +{ + type_register_static(&tcg_accel_ops_type); +} +type_init(tcg_accel_ops_register_types); diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 7125d0cc29..f0d97b4b21 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -33,10 +33,6 @@ #include "qemu/accel.h" #include "qapi/qapi-builtin-visit.h" =20 -#ifndef CONFIG_USER_ONLY -#include "tcg-cpus.h" -#endif /* CONFIG_USER_ONLY */ - struct TCGState { AccelState parent_obj; =20 @@ -116,14 +112,6 @@ static int tcg_init(MachineState *ms) */ #ifndef CONFIG_USER_ONLY tcg_region_init(); - - if (mttcg_enabled) { - cpus_register_accel(&tcg_cpus_mttcg); - } else if (icount_enabled()) { - cpus_register_accel(&tcg_cpus_icount); - } else { - cpus_register_accel(&tcg_cpus_rr); - } #endif /* !CONFIG_USER_ONLY */ =20 return 0; diff --git a/accel/xen/xen-all.c b/accel/xen/xen-all.c index 594aaf6b49..82fc21f1ce 100644 --- a/accel/xen/xen-all.c +++ b/accel/xen/xen-all.c @@ -154,10 +154,6 @@ static void xen_setup_post(MachineState *ms, AccelStat= e *accel) } } =20 -const CpusAccel xen_cpus =3D { - .create_vcpu_thread =3D dummy_start_vcpu_thread, -}; - static int xen_init(MachineState *ms) { MachineClass *mc =3D MACHINE_GET_CLASS(ms); @@ -185,9 +181,6 @@ static int xen_init(MachineState *ms) * opt out of system RAM being allocated by generic code */ mc->default_ram_id =3D NULL; - - cpus_register_accel(&xen_cpus); - return 0; } =20 @@ -222,9 +215,24 @@ static const TypeInfo xen_accel_type =3D { .class_init =3D xen_accel_class_init, }; =20 +static void xen_accel_ops_class_init(ObjectClass *oc, void *data) +{ + AccelOpsClass *ops =3D ACCEL_OPS_CLASS(oc); + + ops->create_vcpu_thread =3D dummy_start_vcpu_thread; +}; +static const TypeInfo xen_accel_ops_type =3D { + .name =3D ACCEL_OPS_NAME("xen"), + + .parent =3D TYPE_ACCEL_OPS, + .class_init =3D xen_accel_ops_class_init, + .abstract =3D true, +}; + static void xen_type_init(void) { type_register_static(&xen_accel_type); + type_register_static(&xen_accel_ops_type); } =20 type_init(xen_type_init); diff --git a/bsd-user/main.c b/bsd-user/main.c index ff295bcb29..a68ce5f446 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -908,13 +908,14 @@ int main(int argc, char **argv) #endif } =20 + cpu_type =3D parse_cpu_option(cpu_model); /* init tcg before creating CPUs and to get qemu_host_page_size */ { AccelClass *ac =3D ACCEL_GET_CLASS(current_accel()); =20 ac->init_machine(NULL); + accel_init_interfaces(ac); } - cpu_type =3D parse_cpu_option(cpu_model); cpu =3D cpu_create(cpu_type); env =3D cpu->env_ptr; #if defined(TARGET_SPARC) || defined(TARGET_PPC) diff --git a/linux-user/main.c b/linux-user/main.c index 5c059a8445..e28d016c6f 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -708,6 +708,7 @@ int main(int argc, char **argv, char **envp) AccelClass *ac =3D ACCEL_GET_CLASS(current_accel()); =20 ac->init_machine(NULL); + accel_init_interfaces(ac); } cpu =3D cpu_create(cpu_type); env =3D cpu->env_ptr; diff --git a/softmmu/cpus.c b/softmmu/cpus.c index e46ac68ad0..659617e7ef 100644 --- a/softmmu/cpus.c +++ b/softmmu/cpus.c @@ -127,7 +127,7 @@ void hw_error(const char *fmt, ...) /* * The chosen accelerator is supposed to register this. */ -static const CpusAccel *cpus_accel; +static const AccelOpsClass *cpus_accel; =20 void cpu_synchronize_all_states(void) { @@ -593,11 +593,11 @@ void cpu_remove_sync(CPUState *cpu) qemu_mutex_lock_iothread(); } =20 -void cpus_register_accel(const CpusAccel *ca) +void cpus_register_accel(const AccelOpsClass *ops) { - assert(ca !=3D NULL); - assert(ca->create_vcpu_thread !=3D NULL); /* mandatory */ - cpus_accel =3D ca; + assert(ops !=3D NULL); + assert(ops->create_vcpu_thread !=3D NULL); /* mandatory */ + cpus_accel =3D ops; } =20 void qemu_init_vcpu(CPUState *cpu) @@ -617,7 +617,7 @@ void qemu_init_vcpu(CPUState *cpu) cpu_address_space_init(cpu, 0, "cpu-memory", cpu->memory); } =20 - /* accelerators all implement the CpusAccel interface */ + /* accelerators all implement the AccelOpsClass */ g_assert(cpus_accel !=3D NULL && cpus_accel->create_vcpu_thread !=3D N= ULL); cpus_accel->create_vcpu_thread(cpu); =20 diff --git a/softmmu/vl.c b/softmmu/vl.c index bc20c526d2..b97708300e 100644 --- a/softmmu/vl.c +++ b/softmmu/vl.c @@ -2558,7 +2558,7 @@ static bool object_create_initial(const char *type, Q= emuOpts *opts) } =20 /* Memory allocation by backends needs to be done - * after configure_accelerator() (due to the tcg_enabled() + * after do_configure_accelerator() (due to the tcg_enabled() * checks at memory_region_init_*()). * * Also, allocation of large amounts of memory may delay @@ -4186,7 +4186,7 @@ void qemu_init(int argc, char **argv, char **envp) * * Machine compat properties: object_set_machine_compat_props(). * Accelerator compat props: object_set_accelerator_compat_props(), - * called from configure_accelerator(). + * called from do_configure_accelerator(). */ =20 if (!qtest_enabled() && machine_class->deprecation_reason) { @@ -4321,6 +4321,8 @@ void qemu_init(int argc, char **argv, char **envp) if (cpu_option) { current_machine->cpu_type =3D parse_cpu_option(cpu_option); } + /* NB: for machine none cpu_type could STILL be NULL here! */ + accel_init_interfaces(ACCEL_GET_CLASS(current_machine->accelerator)); =20 if (current_machine->ram_memdev_id) { Object *backend; diff --git a/target/i386/hax/hax-cpus.c b/target/i386/hax/hax-accel-ops.c similarity index 69% rename from target/i386/hax/hax-cpus.c rename to target/i386/hax/hax-accel-ops.c index f72c85bd49..f66042c61e 100644 --- a/target/i386/hax/hax-cpus.c +++ b/target/i386/hax/hax-accel-ops.c @@ -26,7 +26,7 @@ #include "sysemu/cpus.h" #include "qemu/guest-random.h" =20 -#include "hax-cpus.h" +#include "hax-accel-ops.h" =20 static void *hax_cpu_thread_fn(void *arg) { @@ -74,12 +74,27 @@ static void hax_start_vcpu_thread(CPUState *cpu) #endif } =20 -const CpusAccel hax_cpus =3D { - .create_vcpu_thread =3D hax_start_vcpu_thread, - .kick_vcpu_thread =3D hax_kick_vcpu_thread, +static void hax_accel_ops_class_init(ObjectClass *oc, void *data) +{ + AccelOpsClass *ops =3D ACCEL_OPS_CLASS(oc); =20 - .synchronize_post_reset =3D hax_cpu_synchronize_post_reset, - .synchronize_post_init =3D hax_cpu_synchronize_post_init, - .synchronize_state =3D hax_cpu_synchronize_state, - .synchronize_pre_loadvm =3D hax_cpu_synchronize_pre_loadvm, + ops->create_vcpu_thread =3D hax_start_vcpu_thread; + ops->kick_vcpu_thread =3D hax_kick_vcpu_thread; + + ops->synchronize_post_reset =3D hax_cpu_synchronize_post_reset; + ops->synchronize_post_init =3D hax_cpu_synchronize_post_init; + ops->synchronize_state =3D hax_cpu_synchronize_state; + ops->synchronize_pre_loadvm =3D hax_cpu_synchronize_pre_loadvm; +}; +static const TypeInfo hax_accel_ops_type =3D { + .name =3D ACCEL_OPS_NAME("hax"), + + .parent =3D TYPE_ACCEL_OPS, + .class_init =3D hax_accel_ops_class_init, + .abstract =3D true, }; +static void hax_accel_ops_register_types(void) +{ + type_register_static(&hax_accel_ops_type); +} +type_init(hax_accel_ops_register_types); diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c index d7f4bb44a7..bf65ed6fa9 100644 --- a/target/i386/hax/hax-all.c +++ b/target/i386/hax/hax-all.c @@ -33,7 +33,7 @@ #include "sysemu/runstate.h" #include "hw/boards.h" =20 -#include "hax-cpus.h" +#include "hax-accel-ops.h" =20 #define DEBUG_HAX 0 =20 @@ -364,9 +364,6 @@ static int hax_accel_init(MachineState *ms) !ret ? "working" : "not working", !ret ? "fast virt" : "emulation"); } - if (ret =3D=3D 0) { - cpus_register_accel(&hax_cpus); - } return ret; } =20 diff --git a/target/i386/hax/hax-mem.c b/target/i386/hax/hax-mem.c index 71e637cf16..35495f5e82 100644 --- a/target/i386/hax/hax-mem.c +++ b/target/i386/hax/hax-mem.c @@ -13,7 +13,7 @@ #include "exec/address-spaces.h" #include "qemu/error-report.h" =20 -#include "hax-cpus.h" +#include "hax-accel-ops.h" #include "qemu/queue.h" =20 #define DEBUG_HAX_MEM 0 diff --git a/target/i386/hax/hax-posix.c b/target/i386/hax/hax-posix.c index 735a749d4b..ac1a51096e 100644 --- a/target/i386/hax/hax-posix.c +++ b/target/i386/hax/hax-posix.c @@ -15,7 +15,7 @@ #include =20 #include "sysemu/cpus.h" -#include "hax-cpus.h" +#include "hax-accel-ops.h" =20 hax_fd hax_mod_open(void) { diff --git a/target/i386/hax/hax-windows.c b/target/i386/hax/hax-windows.c index 6c82dfb54f..59afa213a6 100644 --- a/target/i386/hax/hax-windows.c +++ b/target/i386/hax/hax-windows.c @@ -12,7 +12,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "hax-cpus.h" +#include "hax-accel-ops.h" =20 /* * return 0 when success, -1 when driver not loaded, diff --git a/target/i386/hvf/hvf-cpus.c b/target/i386/hvf/hvf-accel-ops.c similarity index 84% rename from target/i386/hvf/hvf-cpus.c rename to target/i386/hvf/hvf-accel-ops.c index 817b3d7452..cbaad238e0 100644 --- a/target/i386/hvf/hvf-cpus.c +++ b/target/i386/hvf/hvf-accel-ops.c @@ -55,7 +55,7 @@ #include "target/i386/cpu.h" #include "qemu/guest-random.h" =20 -#include "hvf-cpus.h" +#include "hvf-accel-ops.h" =20 /* * The HVF-specific vCPU thread function. This one should only run when th= e host @@ -121,11 +121,26 @@ static void hvf_start_vcpu_thread(CPUState *cpu) cpu, QEMU_THREAD_JOINABLE); } =20 -const CpusAccel hvf_cpus =3D { - .create_vcpu_thread =3D hvf_start_vcpu_thread, +static void hvf_accel_ops_class_init(ObjectClass *oc, void *data) +{ + AccelOpsClass *ops =3D ACCEL_OPS_CLASS(oc); =20 - .synchronize_post_reset =3D hvf_cpu_synchronize_post_reset, - .synchronize_post_init =3D hvf_cpu_synchronize_post_init, - .synchronize_state =3D hvf_cpu_synchronize_state, - .synchronize_pre_loadvm =3D hvf_cpu_synchronize_pre_loadvm, + ops->create_vcpu_thread =3D hvf_start_vcpu_thread; + + ops->synchronize_post_reset =3D hvf_cpu_synchronize_post_reset; + ops->synchronize_post_init =3D hvf_cpu_synchronize_post_init; + ops->synchronize_state =3D hvf_cpu_synchronize_state; + ops->synchronize_pre_loadvm =3D hvf_cpu_synchronize_pre_loadvm; +}; +static const TypeInfo hvf_accel_ops_type =3D { + .name =3D ACCEL_OPS_NAME("hvf"), + + .parent =3D TYPE_ACCEL_OPS, + .class_init =3D hvf_accel_ops_class_init, + .abstract =3D true, }; +static void hvf_accel_ops_register_types(void) +{ + type_register_static(&hvf_accel_ops_type); +} +type_init(hvf_accel_ops_register_types); diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index ffc9efa40f..5b90dcdf88 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -72,7 +72,7 @@ #include "qemu/accel.h" #include "target/i386/cpu.h" =20 -#include "hvf-cpus.h" +#include "hvf-accel-ops.h" =20 HVFState *hvf_state; =20 @@ -887,7 +887,6 @@ static int hvf_accel_init(MachineState *ms) =20 hvf_state =3D s; memory_listener_register(&hvf_memory_listener, &address_space_memory); - cpus_register_accel(&hvf_cpus); return 0; } =20 diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c index bbec412b6c..0d7533742e 100644 --- a/target/i386/hvf/x86hvf.c +++ b/target/i386/hvf/x86hvf.c @@ -32,7 +32,7 @@ #include #include =20 -#include "hvf-cpus.h" +#include "hvf-accel-ops.h" =20 void hvf_set_segment(struct CPUState *cpu, struct vmx_segment *vmx_seg, SegmentCache *qseg, bool is_tr) diff --git a/target/i386/whpx/whpx-cpus.c b/target/i386/whpx/whpx-accel-ops= .c similarity index 72% rename from target/i386/whpx/whpx-cpus.c rename to target/i386/whpx/whpx-accel-ops.c index d9bd5a2d36..b880947cc2 100644 --- a/target/i386/whpx/whpx-cpus.c +++ b/target/i386/whpx/whpx-accel-ops.c @@ -15,7 +15,7 @@ #include "qemu/guest-random.h" =20 #include "sysemu/whpx.h" -#include "whpx-cpus.h" +#include "whpx-accel-ops.h" =20 #include #include @@ -85,12 +85,27 @@ static void whpx_kick_vcpu_thread(CPUState *cpu) } } =20 -const CpusAccel whpx_cpus =3D { - .create_vcpu_thread =3D whpx_start_vcpu_thread, - .kick_vcpu_thread =3D whpx_kick_vcpu_thread, +static void whpx_accel_ops_class_init(ObjectClass *oc, void *data) +{ + AccelOpsClass *ops =3D ACCEL_OPS_CLASS(oc); =20 - .synchronize_post_reset =3D whpx_cpu_synchronize_post_reset, - .synchronize_post_init =3D whpx_cpu_synchronize_post_init, - .synchronize_state =3D whpx_cpu_synchronize_state, - .synchronize_pre_loadvm =3D whpx_cpu_synchronize_pre_loadvm, + ops->create_vcpu_thread =3D whpx_start_vcpu_thread; + ops->kick_vcpu_thread =3D whpx_kick_vcpu_thread; + + ops->synchronize_post_reset =3D whpx_cpu_synchronize_post_reset; + ops->synchronize_post_init =3D whpx_cpu_synchronize_post_init; + ops->synchronize_state =3D whpx_cpu_synchronize_state; + ops->synchronize_pre_loadvm =3D whpx_cpu_synchronize_pre_loadvm; +}; +static const TypeInfo whpx_accel_ops_type =3D { + .name =3D ACCEL_OPS_NAME("whpx"), + + .parent =3D TYPE_ACCEL_OPS, + .class_init =3D whpx_accel_ops_class_init, + .abstract =3D true, }; +static void whpx_accel_ops_register_types(void) +{ + type_register_static(&whpx_accel_ops_type); +} +type_init(whpx_accel_ops_register_types); diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index ee6b606194..fbac300ada 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -24,7 +24,7 @@ #include "migration/blocker.h" #include "whp-dispatch.h" =20 -#include "whpx-cpus.h" +#include "whpx-accel-ops.h" =20 #include #include @@ -1642,8 +1642,6 @@ static int whpx_accel_init(MachineState *ms) =20 whpx_memory_init(); =20 - cpus_register_accel(&whpx_cpus); - printf("Windows Hypervisor Platform accelerator is operational\n"); return 0; =20 diff --git a/MAINTAINERS b/MAINTAINERS index 6235dd3a9f..8f0e773a47 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -435,7 +435,8 @@ M: Richard Henderson R: Paolo Bonzini S: Maintained F: include/qemu/accel.h -F: accel/accel.c +F: include/sysemu/accel-ops.h +F: accel/accel-*.c F: accel/Makefile.objs F: accel/stubs/Makefile.objs =20 diff --git a/accel/kvm/meson.build b/accel/kvm/meson.build index 7e9dafe24c..8d219bea50 100644 --- a/accel/kvm/meson.build +++ b/accel/kvm/meson.build @@ -1,7 +1,7 @@ kvm_ss =3D ss.source_set() kvm_ss.add(files( 'kvm-all.c', - 'kvm-cpus.c', + 'kvm-accel-ops.c', )) kvm_ss.add(when: 'CONFIG_SEV', if_false: files('sev-stub.c')) =20 diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 424d9bb1fc..1236ac7b91 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -15,8 +15,8 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss) =20 specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files( 'cputlb.c', - 'tcg-cpus.c', - 'tcg-cpus-mttcg.c', - 'tcg-cpus-icount.c', - 'tcg-cpus-rr.c' + 'tcg-accel-ops.c', + 'tcg-accel-ops-mttcg.c', + 'tcg-accel-ops-icount.c', + 'tcg-accel-ops-rr.c' )) diff --git a/target/i386/hax/meson.build b/target/i386/hax/meson.build index 77ea431b30..d6c520fb6b 100644 --- a/target/i386/hax/meson.build +++ b/target/i386/hax/meson.build @@ -1,7 +1,7 @@ i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files( 'hax-all.c', 'hax-mem.c', - 'hax-cpus.c', + 'hax-accel-ops.c', )) i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('= hax-posix.c')) i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('= hax-windows.c')) diff --git a/target/i386/hvf/meson.build b/target/i386/hvf/meson.build index 409c9a3f14..e9eb5a5da8 100644 --- a/target/i386/hvf/meson.build +++ b/target/i386/hvf/meson.build @@ -1,6 +1,6 @@ i386_softmmu_ss.add(when: [hvf, 'CONFIG_HVF'], if_true: files( 'hvf.c', - 'hvf-cpus.c', + 'hvf-accel-ops.c', 'x86.c', 'x86_cpuid.c', 'x86_decode.c', diff --git a/target/i386/whpx/meson.build b/target/i386/whpx/meson.build index 94a72c8efc..e790b42992 100644 --- a/target/i386/whpx/meson.build +++ b/target/i386/whpx/meson.build @@ -1,4 +1,4 @@ i386_softmmu_ss.add(when: 'CONFIG_WHPX', if_true: files( 'whpx-all.c', - 'whpx-cpus.c', + 'whpx-accel-ops.c', )) --=20 2.26.2 From nobody Fri May 17 09:38:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" add a new optional interface to CPUClass, which allows accelerators to extend the CPUClass with additional accelerator-specific initializations. Signed-off-by: Claudio Fontana --- include/hw/core/accel-cpu.h | 25 +++++++++++++++++++++ include/hw/core/cpu.h | 13 +++++++++++ accel/accel-common.c | 44 +++++++++++++++++++++++++++++++++++++ MAINTAINERS | 1 + 4 files changed, 83 insertions(+) create mode 100644 include/hw/core/accel-cpu.h diff --git a/include/hw/core/accel-cpu.h b/include/hw/core/accel-cpu.h new file mode 100644 index 0000000000..dce08a9100 --- /dev/null +++ b/include/hw/core/accel-cpu.h @@ -0,0 +1,25 @@ +/* + * Accelerator interface, specializes CPUClass + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef ACCEL_CPU_H +#define ACCEL_CPU_H + +/* + * these defines cannot be in cpu.h, because we are using + * CPU_RESOLVING_TYPE here. + * Use this header to define your accelerator-specific + * cpu-specific accelerator interfaces. + */ + +#define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE +#define ACCEL_CPU_NAME(name) (name "-" TYPE_ACCEL_CPU) +typedef struct AccelCPUClass AccelCPUClass; +DECLARE_CLASS_CHECKERS(AccelCPUClass, ACCEL_CPU, TYPE_ACCEL_CPU) + +#endif /* ACCEL_CPU_H */ diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index db54223983..97e1dd8279 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -76,6 +76,17 @@ typedef struct CPUWatchpoint CPUWatchpoint; =20 struct TranslationBlock; =20 +/* see also accel-cpu.h */ +typedef struct AccelCPUClass { + /*< private >*/ + ObjectClass parent_class; + /*< public >*/ + + void (*cpu_class_init)(CPUClass *cc); + void (*cpu_instance_init)(CPUState *cpu); + void (*cpu_realizefn)(CPUState *cpu, Error **errp); +} AccelCPUClass; + #ifdef CONFIG_TCG #include "tcg-cpu-ops.h" #endif /* CONFIG_TCG */ @@ -196,6 +207,8 @@ struct CPUClass { #ifdef CONFIG_TCG TcgCpuOperations tcg_ops; #endif /* CONFIG_TCG */ + + AccelCPUClass *accel_cpu_interface; }; =20 /* diff --git a/accel/accel-common.c b/accel/accel-common.c index 6b59873419..ef73c761fc 100644 --- a/accel/accel-common.c +++ b/accel/accel-common.c @@ -26,6 +26,9 @@ #include "qemu/osdep.h" #include "qemu/accel.h" =20 +#include "cpu.h" +#include "hw/core/accel-cpu.h" + #ifndef CONFIG_USER_ONLY #include "accel-softmmu.h" #endif /* !CONFIG_USER_ONLY */ @@ -46,16 +49,57 @@ AccelClass *accel_find(const char *opt_name) return ac; } =20 +static void accel_init_cpu_int_aux(ObjectClass *klass, void *opaque) +{ + CPUClass *cc =3D CPU_CLASS(klass); + AccelCPUClass *accel_cpu_interface =3D opaque; + + cc->accel_cpu_interface =3D accel_cpu_interface; + if (accel_cpu_interface->cpu_class_init) { + accel_cpu_interface->cpu_class_init(cc); + } +} + +/* initialize the arch-specific accel CpuClass interfaces */ +static void accel_init_cpu_interfaces(AccelClass *ac) +{ + const char *ac_name; /* AccelClass name */ + char *acc_name; /* AccelCPUClass name */ + ObjectClass *acc; /* AccelCPUClass */ + + ac_name =3D object_class_get_name(OBJECT_CLASS(ac)); + g_assert(ac_name !=3D NULL); + + acc_name =3D g_strdup_printf("%s-%s", ac_name, CPU_RESOLVING_TYPE); + acc =3D object_class_by_name(acc_name); + g_free(acc_name); + + if (acc) { + object_class_foreach(accel_init_cpu_int_aux, + CPU_RESOLVING_TYPE, false, acc); + } +} + void accel_init_interfaces(AccelClass *ac) { #ifndef CONFIG_USER_ONLY accel_init_ops_interfaces(ac); #endif /* !CONFIG_USER_ONLY */ + + accel_init_cpu_interfaces(ac); } =20 +static const TypeInfo accel_cpu_type =3D { + .name =3D TYPE_ACCEL_CPU, + .parent =3D TYPE_OBJECT, + .abstract =3D true, + .class_size =3D sizeof(AccelCPUClass), +}; + static void register_accel_types(void) { type_register_static(&accel_type); + type_register_static(&accel_cpu_type); } =20 type_init(register_accel_types); diff --git a/MAINTAINERS b/MAINTAINERS index 8f0e773a47..f084d73f6b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -436,6 +436,7 @@ R: Paolo Bonzini S: Maintained F: include/qemu/accel.h F: include/sysemu/accel-ops.h +F: include/hw/core/accel-cpu.h F: accel/accel-*.c F: accel/Makefile.objs F: accel/stubs/Makefile.objs --=20 2.26.2 From nobody Fri May 17 09:38:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607682219; cv=none; d=zohomail.com; s=zohoarc; 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Fri, 11 Dec 2020 02:23:39 -0800 (PST) Received: from localhost ([::1]:52862 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knfPt-0002Ov-Lu for importer@patchew.org; Fri, 11 Dec 2020 05:12:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39224) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knfMV-0006hk-QY for qemu-devel@nongnu.org; Fri, 11 Dec 2020 05:09:19 -0500 Received: from mx2.suse.de ([195.135.220.15]:49652) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knfMQ-0007c2-V7 for qemu-devel@nongnu.org; Fri, 11 Dec 2020 05:09:19 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id AA558B173; Fri, 11 Dec 2020 10:09:13 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 4/7] i386: split cpu accelerators from cpu.c, using AccelCPUClass Date: Fri, 11 Dec 2020 11:09:05 +0100 Message-Id: <20201211100908.19696-5-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211100908.19696-1-cfontana@suse.de> References: <20201211100908.19696-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" i386 is the first user of AccelCPUClass, allowing to split cpu.c into: cpu.c cpuid and common x86 cpu functionality host-cpu.c host x86 cpu functions and "host" cpu type kvm/kvm-cpu.c KVM x86 AccelCPUClass hvf/hvf-cpu.c HVF x86 AccelCPUClass tcg/tcg-cpu.c TCG x86 AccelCPUClass Signed-off-by: Claudio Fontana --- target/i386/cpu.h | 20 +- target/i386/host-cpu.h | 19 ++ target/i386/kvm/kvm-cpu.h | 41 ++++ target/i386/tcg/tcg-cpu.h | 15 -- hw/i386/pc_piix.c | 1 + target/i386/cpu.c | 386 ++++-------------------------------- target/i386/host-cpu.c | 198 ++++++++++++++++++ target/i386/hvf/hvf-cpu.c | 65 ++++++ target/i386/kvm/kvm-cpu.c | 148 ++++++++++++++ target/i386/kvm/kvm.c | 3 +- target/i386/tcg/tcg-cpu.c | 116 ++++++++++- MAINTAINERS | 2 +- target/i386/hvf/meson.build | 1 + target/i386/kvm/meson.build | 7 +- target/i386/meson.build | 6 +- 15 files changed, 644 insertions(+), 384 deletions(-) create mode 100644 target/i386/host-cpu.h create mode 100644 target/i386/kvm/kvm-cpu.h delete mode 100644 target/i386/tcg/tcg-cpu.h create mode 100644 target/i386/host-cpu.c create mode 100644 target/i386/hvf/hvf-cpu.c create mode 100644 target/i386/kvm/kvm-cpu.c diff --git a/target/i386/cpu.h b/target/i386/cpu.h index a0d64613dc..b3e39fc631 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1905,13 +1905,20 @@ int cpu_x86_signal_handler(int host_signum, void *p= info, void *puc); =20 /* cpu.c */ +void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, + uint32_t vendor2, uint32_t vendor3); +typedef struct PropValue { + const char *prop, *value; +} PropValue; +void x86_cpu_apply_props(X86CPU *cpu, PropValue *props); + +/* cpu.c other functions (cpuid) */ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); void cpu_clear_apic_feature(CPUX86State *env); void host_cpuid(uint32_t function, uint32_t count, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx= ); -void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); =20 /* helper.c */ void x86_cpu_set_a20(X86CPU *cpu, int a20_state); @@ -2111,17 +2118,6 @@ void cpu_report_tpr_access(CPUX86State *env, TPRAcce= ss access); void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, TPRAccess access); =20 - -/* Change the value of a KVM-specific default - * - * If value is NULL, no default will be set and the original - * value from the CPU model table will be kept. - * - * It is valid to call this function only for properties that - * are already present in the kvm_default_props table. - */ -void x86_cpu_change_kvm_default(const char *prop, const char *value); - /* Special values for X86CPUVersion: */ =20 /* Resolve to latest CPU version */ diff --git a/target/i386/host-cpu.h b/target/i386/host-cpu.h new file mode 100644 index 0000000000..d1f2644422 --- /dev/null +++ b/target/i386/host-cpu.h @@ -0,0 +1,19 @@ +/* + * x86 host CPU type initialization and host CPU functions + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef HOST_CPU_H +#define HOST_CPU_H + +void host_cpu_instance_init(X86CPU *cpu); +void host_cpu_max_instance_init(X86CPU *cpu); +void host_cpu_realizefn(CPUState *cs, Error **errp); + +void host_cpu_vendor_fms(char *vendor, int *family, int *model, int *stepp= ing); + +#endif /* HOST_CPU_H */ diff --git a/target/i386/kvm/kvm-cpu.h b/target/i386/kvm/kvm-cpu.h new file mode 100644 index 0000000000..e858ca21e5 --- /dev/null +++ b/target/i386/kvm/kvm-cpu.h @@ -0,0 +1,41 @@ +/* + * i386 KVM CPU type and functions + * + * Copyright (c) 2003 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef KVM_CPU_H +#define KVM_CPU_H + +#ifdef CONFIG_KVM +/* + * Change the value of a KVM-specific default + * + * If value is NULL, no default will be set and the original + * value from the CPU model table will be kept. + * + * It is valid to call this function only for properties that + * are already present in the kvm_default_props table. + */ +void x86_cpu_change_kvm_default(const char *prop, const char *value); + +#else /* !CONFIG_KVM */ + +#define x86_cpu_change_kvm_default(a, b) + +#endif /* CONFIG_KVM */ + +#endif /* KVM_CPU_H */ diff --git a/target/i386/tcg/tcg-cpu.h b/target/i386/tcg/tcg-cpu.h deleted file mode 100644 index 81f02e562e..0000000000 --- a/target/i386/tcg/tcg-cpu.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * i386 TCG CPU class initialization - * - * Copyright 2020 SUSE LLC - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - */ - -#ifndef TCG_CPU_H -#define TCG_CPU_H - -void tcg_cpu_common_class_init(CPUClass *cc); - -#endif /* TCG_CPU_H */ diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 6188c3e97e..3abcb425bb 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -64,6 +64,7 @@ #include "hw/hyperv/vmbus-bridge.h" #include "hw/mem/nvdimm.h" #include "hw/i386/acpi-build.h" +#include "kvm/kvm-cpu.h" =20 #define MAX_IDE_BUS 2 =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f0aa6d1841..5414523651 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -22,37 +22,24 @@ #include "qemu/cutils.h" #include "qemu/bitops.h" #include "qemu/qemu-print.h" - #include "cpu.h" -#include "tcg/tcg-cpu.h" #include "tcg/helper-tcg.h" #include "exec/exec-all.h" #include "sysemu/kvm.h" #include "sysemu/reset.h" #include "sysemu/hvf.h" -#include "sysemu/cpus.h" +#include "hw/core/accel-cpu.h" #include "sysemu/xen.h" #include "kvm/kvm_i386.h" #include "sev_i386.h" - -#include "qemu/error-report.h" #include "qemu/module.h" -#include "qemu/option.h" -#include "qemu/config-file.h" -#include "qapi/error.h" #include "qapi/qapi-visit-machine.h" #include "qapi/qapi-visit-run-state.h" #include "qapi/qmp/qdict.h" #include "qapi/qmp/qerror.h" -#include "qapi/visitor.h" #include "qom/qom-qobject.h" -#include "sysemu/arch_init.h" #include "qapi/qapi-commands-machine-target.h" - #include "standard-headers/asm-x86/kvm_para.h" - -#include "sysemu/sysemu.h" -#include "sysemu/tcg.h" #include "hw/qdev-properties.h" #include "hw/i386/topology.h" #ifndef CONFIG_USER_ONLY @@ -594,8 +581,8 @@ static CPUCacheInfo legacy_l3_cache =3D { #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32= K,64K */ =20 -static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, - uint32_t vendor2, uint32_t vendor3) +void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, + uint32_t vendor2, uint32_t vendor3) { int i; for (i =3D 0; i < 4; i++) { @@ -1563,25 +1550,6 @@ void host_cpuid(uint32_t function, uint32_t count, *edx =3D vec[3]; } =20 -void host_vendor_fms(char *vendor, int *family, int *model, int *stepping) -{ - uint32_t eax, ebx, ecx, edx; - - host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx); - x86_cpu_vendor_words2str(vendor, ebx, edx, ecx); - - host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx); - if (family) { - *family =3D ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF); - } - if (model) { - *model =3D ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12); - } - if (stepping) { - *stepping =3D eax & 0x0F; - } -} - /* CPU class name definitions: */ =20 /* Return type name for a given CPU model name @@ -1606,10 +1574,6 @@ static char *x86_cpu_class_get_model_name(X86CPUClas= s *cc) strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX)); } =20 -typedef struct PropValue { - const char *prop, *value; -} PropValue; - typedef struct X86CPUVersionDefinition { X86CPUVersion version; const char *alias; @@ -4106,31 +4070,6 @@ static X86CPUDefinition builtin_x86_defs[] =3D { }, }; =20 -/* KVM-specific features that are automatically added/removed - * from all CPU models when KVM is enabled. - */ -static PropValue kvm_default_props[] =3D { - { "kvmclock", "on" }, - { "kvm-nopiodelay", "on" }, - { "kvm-asyncpf", "on" }, - { "kvm-steal-time", "on" }, - { "kvm-pv-eoi", "on" }, - { "kvmclock-stable-bit", "on" }, - { "x2apic", "on" }, - { "acpi", "off" }, - { "monitor", "off" }, - { "svm", "off" }, - { NULL, NULL }, -}; - -/* TCG-specific defaults that override all CPU models when using TCG - */ -static PropValue tcg_default_props[] =3D { - { "vme", "off" }, - { NULL, NULL }, -}; - - /* * We resolve CPU model aliases using -v1 when using "-machine * none", but this is just for compatibility while libvirt isn't @@ -4172,61 +4111,6 @@ static X86CPUVersion x86_cpu_model_resolve_version(c= onst X86CPUModel *model) return v; } =20 -void x86_cpu_change_kvm_default(const char *prop, const char *value) -{ - PropValue *pv; - for (pv =3D kvm_default_props; pv->prop; pv++) { - if (!strcmp(pv->prop, prop)) { - pv->value =3D value; - break; - } - } - - /* It is valid to call this function only for properties that - * are already present in the kvm_default_props table. - */ - assert(pv->prop); -} - -static bool lmce_supported(void) -{ - uint64_t mce_cap =3D 0; - -#ifdef CONFIG_KVM - if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0)= { - return false; - } -#endif - - return !!(mce_cap & MCG_LMCE_P); -} - -#define CPUID_MODEL_ID_SZ 48 - -/** - * cpu_x86_fill_model_id: - * Get CPUID model ID string from host CPU. - * - * @str should have at least CPUID_MODEL_ID_SZ bytes - * - * The function does NOT add a null terminator to the string - * automatically. - */ -static int cpu_x86_fill_model_id(char *str) -{ - uint32_t eax =3D 0, ebx =3D 0, ecx =3D 0, edx =3D 0; - int i; - - for (i =3D 0; i < 3; i++) { - host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx); - memcpy(str + i * 16 + 0, &eax, 4); - memcpy(str + i * 16 + 4, &ebx, 4); - memcpy(str + i * 16 + 8, &ecx, 4); - memcpy(str + i * 16 + 12, &edx, 4); - } - return 0; -} - static Property max_x86_cpu_properties[] =3D { DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, fa= lse), @@ -4249,61 +4133,25 @@ static void max_x86_cpu_class_init(ObjectClass *oc,= void *data) static void max_x86_cpu_initfn(Object *obj) { X86CPU *cpu =3D X86_CPU(obj); - CPUX86State *env =3D &cpu->env; - KVMState *s =3D kvm_state; =20 /* We can't fill the features array here because we don't know yet if * "migratable" is true or false. */ cpu->max_features =3D true; - - if (accel_uses_host_cpuid()) { - char vendor[CPUID_VENDOR_SZ + 1] =3D { 0 }; - char model_id[CPUID_MODEL_ID_SZ + 1] =3D { 0 }; - int family, model, stepping; - - host_vendor_fms(vendor, &family, &model, &stepping); - cpu_x86_fill_model_id(model_id); - - object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abor= t); - object_property_set_int(OBJECT(cpu), "family", family, &error_abor= t); - object_property_set_int(OBJECT(cpu), "model", model, &error_abort); - object_property_set_int(OBJECT(cpu), "stepping", stepping, - &error_abort); - object_property_set_str(OBJECT(cpu), "model-id", model_id, - &error_abort); - - if (kvm_enabled()) { - env->cpuid_min_level =3D - kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX); - env->cpuid_min_xlevel =3D - kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX); - env->cpuid_min_xlevel2 =3D - kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX); - } else { - env->cpuid_min_level =3D - hvf_get_supported_cpuid(0x0, 0, R_EAX); - env->cpuid_min_xlevel =3D - hvf_get_supported_cpuid(0x80000000, 0, R_EAX); - env->cpuid_min_xlevel2 =3D - hvf_get_supported_cpuid(0xC0000000, 0, R_EAX); - } - - if (lmce_supported()) { - object_property_set_bool(OBJECT(cpu), "lmce", true, &error_abo= rt); - } - } else { - object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, - &error_abort); - object_property_set_int(OBJECT(cpu), "family", 6, &error_abort); - object_property_set_int(OBJECT(cpu), "model", 6, &error_abort); - object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort); - object_property_set_str(OBJECT(cpu), "model-id", - "QEMU TCG CPU version " QEMU_HW_VERSION, - &error_abort); - } - object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); + + /* + * these defaults are used for TCG and all other accelerators + * besides KVM and HVF, which overwrite these values + */ + object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, + &error_abort); + object_property_set_int(OBJECT(cpu), "family", 6, &error_abort); + object_property_set_int(OBJECT(cpu), "model", 6, &error_abort); + object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort); + object_property_set_str(OBJECT(cpu), "model-id", + "QEMU TCG CPU version " QEMU_HW_VERSION, + &error_abort); } =20 static const TypeInfo max_x86_cpu_type_info =3D { @@ -4313,31 +4161,6 @@ static const TypeInfo max_x86_cpu_type_info =3D { .class_init =3D max_x86_cpu_class_init, }; =20 -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) -static void host_x86_cpu_class_init(ObjectClass *oc, void *data) -{ - X86CPUClass *xcc =3D X86_CPU_CLASS(oc); - - xcc->host_cpuid_required =3D true; - xcc->ordering =3D 8; - -#if defined(CONFIG_KVM) - xcc->model_description =3D - "KVM processor with all supported host features "; -#elif defined(CONFIG_HVF) - xcc->model_description =3D - "HVF processor with all supported host features "; -#endif -} - -static const TypeInfo host_x86_cpu_type_info =3D { - .name =3D X86_CPU_TYPE_NAME("host"), - .parent =3D X86_CPU_TYPE_NAME("max"), - .class_init =3D host_x86_cpu_class_init, -}; - -#endif - static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) { assert(f->type =3D=3D CPUID_FEATURE_WORD || f->type =3D=3D MSR_FEATURE= _WORD); @@ -5063,7 +4886,7 @@ static uint64_t x86_cpu_get_supported_feature_word(Fe= atureWord w, return r; } =20 -static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) +void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) { PropValue *pv; for (pv =3D props; pv->prop; pv++) { @@ -5110,8 +4933,6 @@ static void x86_cpu_load_model(X86CPU *cpu, X86CPUMod= el *model) { X86CPUDefinition *def =3D model->cpudef; CPUX86State *env =3D &cpu->env; - const char *vendor; - char host_vendor[CPUID_VENDOR_SZ + 1]; FeatureWord w; =20 /*NOTE: any property set by this function should be returned by @@ -5138,18 +4959,6 @@ static void x86_cpu_load_model(X86CPU *cpu, X86CPUMo= del *model) /* legacy-cache defaults to 'off' if CPU model provides cache info */ cpu->legacy_cache =3D !def->cache_info; =20 - /* Special cases not set in the X86CPUDefinition structs: */ - /* TODO: in-kernel irqchip for hvf */ - if (kvm_enabled()) { - if (!kvm_irqchip_in_kernel()) { - x86_cpu_change_kvm_default("x2apic", "off"); - } - - x86_cpu_apply_props(cpu, kvm_default_props); - } else if (tcg_enabled()) { - x86_cpu_apply_props(cpu, tcg_default_props); - } - env->features[FEAT_1_ECX] |=3D CPUID_EXT_HYPERVISOR; =20 /* sysenter isn't supported in compatibility mode on AMD, @@ -5159,15 +4968,12 @@ static void x86_cpu_load_model(X86CPU *cpu, X86CPUM= odel *model) * KVM's sysenter/syscall emulation in compatibility mode and * when doing cross vendor migration */ - vendor =3D def->vendor; - if (accel_uses_host_cpuid()) { - uint32_t ebx =3D 0, ecx =3D 0, edx =3D 0; - host_cpuid(0, 0, NULL, &ebx, &ecx, &edx); - x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx); - vendor =3D host_vendor; - } =20 - object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort); + /* + * vendor property is set here but then overloaded with the + * host cpu vendor for KVM and HVF. + */ + object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abo= rt); =20 x86_cpu_apply_version_props(cpu, model); =20 @@ -6192,53 +5998,12 @@ static void x86_cpu_apic_realize(X86CPU *cpu, Error= **errp) apic_mmio_map_once =3D true; } } - -static void x86_cpu_machine_done(Notifier *n, void *unused) -{ - X86CPU *cpu =3D container_of(n, X86CPU, machine_done); - MemoryRegion *smram =3D - (MemoryRegion *) object_resolve_path("/machine/smram", NULL); - - if (smram) { - cpu->smram =3D g_new(MemoryRegion, 1); - memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram", - smram, 0, 4 * GiB); - memory_region_set_enabled(cpu->smram, true); - memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smra= m, 1); - } -} #else static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp) { } #endif =20 -/* Note: Only safe for use on x86(-64) hosts */ -static uint32_t x86_host_phys_bits(void) -{ - uint32_t eax; - uint32_t host_phys_bits; - - host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL); - if (eax >=3D 0x80000008) { - host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL); - /* Note: According to AMD doc 25481 rev 2.34 they have a field - * at 23:16 that can specify a maximum physical address bits for - * the guest that can override this value; but I've not seen - * anything with that set. - */ - host_phys_bits =3D eax & 0xff; - } else { - /* It's an odd 64 bit machine that doesn't have the leaf for - * physical address bits; fall back to 36 that's most older - * Intel. - */ - host_phys_bits =3D 36; - } - - return host_phys_bits; -} - static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t valu= e) { if (*min < value) { @@ -6515,33 +6280,22 @@ static void x86_cpu_filter_features(X86CPU *cpu, bo= ol verbose) static void x86_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); + CPUClass *cc =3D CPU_GET_CLASS(cs); X86CPU *cpu =3D X86_CPU(dev); X86CPUClass *xcc =3D X86_CPU_GET_CLASS(dev); CPUX86State *env =3D &cpu->env; Error *local_err =3D NULL; static bool ht_warned; =20 - if (xcc->host_cpuid_required) { - if (!accel_uses_host_cpuid()) { - g_autofree char *name =3D x86_cpu_class_get_model_name(xcc); - error_setg(&local_err, "CPU model '%s' requires KVM", name); - goto out; - } + /* The accelerator realizefn needs to be called first. */ + if (cc->accel_cpu_interface) { + cc->accel_cpu_interface->cpu_realizefn(cs, errp); } =20 - if (cpu->max_features && accel_uses_host_cpuid()) { - if (enable_cpu_pm) { - host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx, - &cpu->mwait.ecx, &cpu->mwait.edx); - env->features[FEAT_1_ECX] |=3D CPUID_EXT_MONITOR; - if (kvm_enabled() && kvm_has_waitpkg()) { - env->features[FEAT_7_0_ECX] |=3D CPUID_7_0_ECX_WAITPKG; - } - } - if (kvm_enabled() && cpu->ucode_rev =3D=3D 0) { - cpu->ucode_rev =3D kvm_arch_get_supported_msr_feature(kvm_stat= e, - MSR_IA32_U= CODE_REV); - } + if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { + g_autofree char *name =3D x86_cpu_class_get_model_name(xcc); + error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); + goto out; } =20 if (cpu->ucode_rev =3D=3D 0) { @@ -6593,39 +6347,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) * consumer AMD devices but nothing else. */ if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { - if (accel_uses_host_cpuid()) { - uint32_t host_phys_bits =3D x86_host_phys_bits(); - static bool warned; - - /* Print a warning if the user set it to a value that's not the - * host value. - */ - if (cpu->phys_bits !=3D host_phys_bits && cpu->phys_bits !=3D = 0 && - !warned) { - warn_report("Host physical bits (%u)" - " does not match phys-bits property (%u)", - host_phys_bits, cpu->phys_bits); - warned =3D true; - } - - if (cpu->host_phys_bits) { - /* The user asked for us to use the host physical bits */ - cpu->phys_bits =3D host_phys_bits; - if (cpu->host_phys_bits_limit && - cpu->phys_bits > cpu->host_phys_bits_limit) { - cpu->phys_bits =3D cpu->host_phys_bits_limit; - } - } - - if (cpu->phys_bits && - (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || - cpu->phys_bits < 32)) { - error_setg(errp, "phys-bits should be between 32 and %u " - " (but is %u)", - TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bi= ts); - return; - } - } else { + if (!accel_uses_host_cpuid()) { if (cpu->phys_bits && cpu->phys_bits !=3D TCG_PHYS_ADDR_BITS) { error_setg(errp, "TCG only supports phys-bits=3D%u", TCG_PHYS_ADDR_BITS); @@ -6633,8 +6355,8 @@ static void x86_cpu_realizefn(DeviceState *dev, Error= **errp) } } /* 0 means it was not explicitly set by the user (or by machine - * compat_props or by the host code above). In this case, the defa= ult - * is the value used by TCG (40). + * compat_props or by the host code in host-cpu.c). + * In this case, the default is the value used by TCG (40). */ if (cpu->phys_bits =3D=3D 0) { cpu->phys_bits =3D TCG_PHYS_ADDR_BITS; @@ -6704,33 +6426,6 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) =20 mce_init(cpu); =20 -#ifndef CONFIG_USER_ONLY - if (tcg_enabled()) { - cpu->cpu_as_mem =3D g_new(MemoryRegion, 1); - cpu->cpu_as_root =3D g_new(MemoryRegion, 1); - - /* Outer container... */ - memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull); - memory_region_set_enabled(cpu->cpu_as_root, true); - - /* ... with two regions inside: normal system memory with low - * priority, and... - */ - memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory", - get_system_memory(), 0, ~0ull); - memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_= as_mem, 0); - memory_region_set_enabled(cpu->cpu_as_mem, true); - - cs->num_ases =3D 2; - cpu_address_space_init(cs, 0, "cpu-memory", cs->memory); - cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root); - - /* ... SMRAM with higher priority, linked from /machine/smram. */ - cpu->machine_done.notify =3D x86_cpu_machine_done; - qemu_add_machine_init_done_notifier(&cpu->machine_done); - } -#endif - qemu_init_vcpu(cs); =20 /* @@ -6936,6 +6631,8 @@ static void x86_cpu_initfn(Object *obj) { X86CPU *cpu =3D X86_CPU(obj); X86CPUClass *xcc =3D X86_CPU_GET_CLASS(obj); + CPUClass *cc =3D CPU_CLASS(xcc); + CPUX86State *env =3D &cpu->env; FeatureWord w; =20 @@ -6992,6 +6689,11 @@ static void x86_cpu_initfn(Object *obj) if (xcc->model) { x86_cpu_load_model(cpu, xcc->model); } + + /* if required, do the accelerator-specific cpu initialization */ + if (cc->accel_cpu_interface) { + cc->accel_cpu_interface->cpu_instance_init(CPU(obj)); + } } =20 static int64_t x86_cpu_get_arch_id(CPUState *cs) @@ -7248,11 +6950,6 @@ static void x86_cpu_common_class_init(ObjectClass *o= c, void *data) cc->class_by_name =3D x86_cpu_class_by_name; cc->parse_features =3D x86_cpu_parse_featurestr; cc->has_work =3D x86_cpu_has_work; - -#ifdef CONFIG_TCG - tcg_cpu_common_class_init(cc); -#endif /* CONFIG_TCG */ - cc->dump_state =3D x86_cpu_dump_state; cc->set_pc =3D x86_cpu_set_pc; cc->gdb_read_register =3D x86_cpu_gdb_read_register; @@ -7357,9 +7054,6 @@ static void x86_cpu_register_types(void) } type_register_static(&max_x86_cpu_type_info); type_register_static(&x86_base_cpu_type_info); -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) - type_register_static(&host_x86_cpu_type_info); -#endif } =20 type_init(x86_cpu_register_types) diff --git a/target/i386/host-cpu.c b/target/i386/host-cpu.c new file mode 100644 index 0000000000..3ce2bc9a84 --- /dev/null +++ b/target/i386/host-cpu.c @@ -0,0 +1,198 @@ +/* + * x86 host CPU functions, and "host" cpu type initialization + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "host-cpu.h" +#include "qapi/error.h" +#include "sysemu/sysemu.h" + +/* Note: Only safe for use on x86(-64) hosts */ +static uint32_t host_cpu_phys_bits(void) +{ + uint32_t eax; + uint32_t host_phys_bits; + + host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL); + if (eax >=3D 0x80000008) { + host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL); + /* + * Note: According to AMD doc 25481 rev 2.34 they have a field + * at 23:16 that can specify a maximum physical address bits for + * the guest that can override this value; but I've not seen + * anything with that set. + */ + host_phys_bits =3D eax & 0xff; + } else { + /* + * It's an odd 64 bit machine that doesn't have the leaf for + * physical address bits; fall back to 36 that's most older + * Intel. + */ + host_phys_bits =3D 36; + } + + return host_phys_bits; +} + +static void host_cpu_enable_cpu_pm(X86CPU *cpu) +{ + CPUX86State *env =3D &cpu->env; + + host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx, + &cpu->mwait.ecx, &cpu->mwait.edx); + env->features[FEAT_1_ECX] |=3D CPUID_EXT_MONITOR; +} + +static uint32_t host_cpu_adjust_phys_bits(X86CPU *cpu, Error **errp) +{ + uint32_t host_phys_bits =3D host_cpu_phys_bits(); + uint32_t phys_bits =3D cpu->phys_bits; + static bool warned; + + /* + * Print a warning if the user set it to a value that's not the + * host value. + */ + if (phys_bits !=3D host_phys_bits && phys_bits !=3D 0 && + !warned) { + warn_report("Host physical bits (%u)" + " does not match phys-bits property (%u)", + host_phys_bits, phys_bits); + warned =3D true; + } + + if (cpu->host_phys_bits) { + /* The user asked for us to use the host physical bits */ + phys_bits =3D host_phys_bits; + if (cpu->host_phys_bits_limit && + phys_bits > cpu->host_phys_bits_limit) { + phys_bits =3D cpu->host_phys_bits_limit; + } + } + + if (phys_bits && + (phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || + phys_bits < 32)) { + error_setg(errp, "phys-bits should be between 32 and %u " + " (but is %u)", + TARGET_PHYS_ADDR_SPACE_BITS, phys_bits); + } + + return phys_bits; +} + +void host_cpu_realizefn(CPUState *cs, Error **errp) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + + if (cpu->max_features && enable_cpu_pm) { + host_cpu_enable_cpu_pm(cpu); + } + if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { + cpu->phys_bits =3D host_cpu_adjust_phys_bits(cpu, errp); + } +} + +#define CPUID_MODEL_ID_SZ 48 +/** + * cpu_x86_fill_model_id: + * Get CPUID model ID string from host CPU. + * + * @str should have at least CPUID_MODEL_ID_SZ bytes + * + * The function does NOT add a null terminator to the string + * automatically. + */ +static int host_cpu_fill_model_id(char *str) +{ + uint32_t eax =3D 0, ebx =3D 0, ecx =3D 0, edx =3D 0; + int i; + + for (i =3D 0; i < 3; i++) { + host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx); + memcpy(str + i * 16 + 0, &eax, 4); + memcpy(str + i * 16 + 4, &ebx, 4); + memcpy(str + i * 16 + 8, &ecx, 4); + memcpy(str + i * 16 + 12, &edx, 4); + } + return 0; +} + +void host_cpu_vendor_fms(char *vendor, int *family, int *model, int *stepp= ing) +{ + uint32_t eax, ebx, ecx, edx; + + host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx); + x86_cpu_vendor_words2str(vendor, ebx, edx, ecx); + + host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx); + if (family) { + *family =3D ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF); + } + if (model) { + *model =3D ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12); + } + if (stepping) { + *stepping =3D eax & 0x0F; + } +} + +void host_cpu_instance_init(X86CPU *cpu) +{ + uint32_t ebx =3D 0, ecx =3D 0, edx =3D 0; + char vendor[CPUID_VENDOR_SZ + 1]; + + host_cpuid(0, 0, NULL, &ebx, &ecx, &edx); + x86_cpu_vendor_words2str(vendor, ebx, edx, ecx); + + object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort); +} + +void host_cpu_max_instance_init(X86CPU *cpu) +{ + char vendor[CPUID_VENDOR_SZ + 1] =3D { 0 }; + char model_id[CPUID_MODEL_ID_SZ + 1] =3D { 0 }; + int family, model, stepping; + + host_cpu_vendor_fms(vendor, &family, &model, &stepping); + host_cpu_fill_model_id(model_id); + + object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort); + object_property_set_int(OBJECT(cpu), "family", family, &error_abort); + object_property_set_int(OBJECT(cpu), "model", model, &error_abort); + object_property_set_int(OBJECT(cpu), "stepping", stepping, + &error_abort); + object_property_set_str(OBJECT(cpu), "model-id", model_id, + &error_abort); +} + +static void host_cpu_class_init(ObjectClass *oc, void *data) +{ + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); + + xcc->host_cpuid_required =3D true; + xcc->ordering =3D 8; + xcc->model_description =3D + g_strdup_printf("processor with all supported host features "); +} + +static const TypeInfo host_cpu_type_info =3D { + .name =3D X86_CPU_TYPE_NAME("host"), + .parent =3D X86_CPU_TYPE_NAME("max"), + .class_init =3D host_cpu_class_init, +}; + +static void host_cpu_type_init(void) +{ + type_register_static(&host_cpu_type_info); +} + +type_init(host_cpu_type_init); diff --git a/target/i386/hvf/hvf-cpu.c b/target/i386/hvf/hvf-cpu.c new file mode 100644 index 0000000000..d6579571f1 --- /dev/null +++ b/target/i386/hvf/hvf-cpu.c @@ -0,0 +1,65 @@ +/* + * x86 HVF CPU type initialization + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "host-cpu.h" +#include "qapi/error.h" +#include "sysemu/sysemu.h" +#include "hw/boards.h" +#include "sysemu/hvf.h" +#include "hw/core/accel-cpu.h" + +static void hvf_cpu_max_instance_init(X86CPU *cpu) +{ + CPUX86State *env =3D &cpu->env; + + host_cpu_max_instance_init(cpu); + + env->cpuid_min_level =3D + hvf_get_supported_cpuid(0x0, 0, R_EAX); + env->cpuid_min_xlevel =3D + hvf_get_supported_cpuid(0x80000000, 0, R_EAX); + env->cpuid_min_xlevel2 =3D + hvf_get_supported_cpuid(0xC0000000, 0, R_EAX); +} + +static void hvf_cpu_instance_init(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + + host_cpu_instance_init(cpu); + + /* Special cases not set in the X86CPUDefinition structs: */ + /* TODO: in-kernel irqchip for hvf */ + + if (cpu->max_features) { + hvf_cpu_max_instance_init(cpu); + } +} + +static void hvf_cpu_accel_class_init(ObjectClass *oc, void *data) +{ + AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); + + acc->cpu_realizefn =3D host_cpu_realizefn; + acc->cpu_instance_init =3D hvf_cpu_instance_init; +}; +static const TypeInfo hvf_cpu_accel_type_info =3D { + .name =3D ACCEL_CPU_NAME("hvf"), + + .parent =3D TYPE_ACCEL_CPU, + .class_init =3D hvf_cpu_accel_class_init, + .abstract =3D true, +}; +static void hvf_cpu_accel_register_types(void) +{ + type_register_static(&hvf_cpu_accel_type_info); +} +type_init(hvf_cpu_accel_register_types); diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c new file mode 100644 index 0000000000..adc5120cf6 --- /dev/null +++ b/target/i386/kvm/kvm-cpu.c @@ -0,0 +1,148 @@ +/* + * x86 KVM CPU type initialization + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "host-cpu.h" +#include "kvm-cpu.h" +#include "qapi/error.h" +#include "sysemu/sysemu.h" +#include "hw/boards.h" + +#include "kvm_i386.h" +#include "hw/core/accel-cpu.h" + +static void kvm_cpu_realizefn(CPUState *cs, Error **errp) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + + /* + * The realize order is important, since x86_cpu_realize() checks if + * nothing else has been set by the user (or by accelerators) in + * cpu->ucode_rev and cpu->phys_bits. + * + * realize order: + * kvm_cpu -> host_cpu -> x86_cpu + */ + if (cpu->max_features) { + if (enable_cpu_pm && kvm_has_waitpkg()) { + env->features[FEAT_7_0_ECX] |=3D CPUID_7_0_ECX_WAITPKG; + } + if (cpu->ucode_rev =3D=3D 0) { + cpu->ucode_rev =3D + kvm_arch_get_supported_msr_feature(kvm_state, + MSR_IA32_UCODE_REV); + } + } + host_cpu_realizefn(cs, errp); +} + +/* + * KVM-specific features that are automatically added/removed + * from all CPU models when KVM is enabled. + */ +static PropValue kvm_default_props[] =3D { + { "kvmclock", "on" }, + { "kvm-nopiodelay", "on" }, + { "kvm-asyncpf", "on" }, + { "kvm-steal-time", "on" }, + { "kvm-pv-eoi", "on" }, + { "kvmclock-stable-bit", "on" }, + { "x2apic", "on" }, + { "acpi", "off" }, + { "monitor", "off" }, + { "svm", "off" }, + { NULL, NULL }, +}; + +void x86_cpu_change_kvm_default(const char *prop, const char *value) +{ + PropValue *pv; + for (pv =3D kvm_default_props; pv->prop; pv++) { + if (!strcmp(pv->prop, prop)) { + pv->value =3D value; + break; + } + } + + /* + * It is valid to call this function only for properties that + * are already present in the kvm_default_props table. + */ + assert(pv->prop); +} + +static bool lmce_supported(void) +{ + uint64_t mce_cap =3D 0; + + if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0)= { + return false; + } + return !!(mce_cap & MCG_LMCE_P); +} + +static void kvm_cpu_max_instance_init(X86CPU *cpu) +{ + CPUX86State *env =3D &cpu->env; + KVMState *s =3D kvm_state; + + host_cpu_max_instance_init(cpu); + + if (lmce_supported()) { + object_property_set_bool(OBJECT(cpu), "lmce", true, &error_abort); + } + + env->cpuid_min_level =3D + kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX); + env->cpuid_min_xlevel =3D + kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX); + env->cpuid_min_xlevel2 =3D + kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX); +} + +static void kvm_cpu_instance_init(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + + host_cpu_instance_init(cpu); + + if (!kvm_irqchip_in_kernel()) { + x86_cpu_change_kvm_default("x2apic", "off"); + } + + /* Special cases not set in the X86CPUDefinition structs: */ + + x86_cpu_apply_props(cpu, kvm_default_props); + + if (cpu->max_features) { + kvm_cpu_max_instance_init(cpu); + } +} + +static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) +{ + AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); + + acc->cpu_realizefn =3D kvm_cpu_realizefn; + acc->cpu_instance_init =3D kvm_cpu_instance_init; +} +static const TypeInfo kvm_cpu_accel_type_info =3D { + .name =3D ACCEL_CPU_NAME("kvm"), + + .parent =3D TYPE_ACCEL_CPU, + .class_init =3D kvm_cpu_accel_class_init, + .abstract =3D true, +}; +static void kvm_cpu_accel_register_types(void) +{ + type_register_static(&kvm_cpu_accel_type_info); +} +type_init(kvm_cpu_accel_register_types); diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index a2934dda02..35c86fdba6 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -22,6 +22,7 @@ #include "standard-headers/asm-x86/kvm_para.h" =20 #include "cpu.h" +#include "host-cpu.h" #include "sysemu/sysemu.h" #include "sysemu/hw_accel.h" #include "sysemu/kvm_int.h" @@ -285,7 +286,7 @@ static bool host_tsx_broken(void) int family, model, stepping;\ char vendor[CPUID_VENDOR_SZ + 1]; =20 - host_vendor_fms(vendor, &family, &model, &stepping); + host_cpu_vendor_fms(vendor, &family, &model, &stepping); =20 /* Check if we are running on a Haswell host known to have broken TSX = */ return !strcmp(vendor, CPUID_VENDOR_INTEL) && diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index d2dd521612..45262de5fb 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -19,13 +19,14 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "tcg-cpu.h" -#include "exec/exec-all.h" -#include "sysemu/runstate.h" #include "helper-tcg.h" +#include "qemu/accel.h" +#include "hw/core/accel-cpu.h" =20 -#if !defined(CONFIG_USER_ONLY) -#include "hw/i386/apic.h" +#ifndef CONFIG_USER_ONLY +#include "sysemu/sysemu.h" +#include "qemu/units.h" +#include "exec/address-spaces.h" #endif =20 /* Frob eflags into and out of the CPU temporary format. */ @@ -56,7 +57,72 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, Tr= anslationBlock *tb) cpu->env.eip =3D tb->pc - tb->cs_base; } =20 -void tcg_cpu_common_class_init(CPUClass *cc) +#ifndef CONFIG_USER_ONLY + +static void x86_cpu_machine_done(Notifier *n, void *unused) +{ + X86CPU *cpu =3D container_of(n, X86CPU, machine_done); + MemoryRegion *smram =3D + (MemoryRegion *) object_resolve_path("/machine/smram", NULL); + + if (smram) { + cpu->smram =3D g_new(MemoryRegion, 1); + memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram", + smram, 0, 4 * GiB); + memory_region_set_enabled(cpu->smram, true); + memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, + cpu->smram, 1); + } +} + +static void tcg_cpu_realizefn(CPUState *cs, Error **errp) +{ + X86CPU *cpu =3D X86_CPU(cs); + + /* + * The realize order is important, since x86_cpu_realize() checks if + * nothing else has been set by the user (or by accelerators) in + * cpu->ucode_rev and cpu->phys_bits, and the memory regions + * initialized here are needed for the vcpu initialization. + * + * realize order: + * tcg_cpu -> host_cpu -> x86_cpu + */ + cpu->cpu_as_mem =3D g_new(MemoryRegion, 1); + cpu->cpu_as_root =3D g_new(MemoryRegion, 1); + + /* Outer container... */ + memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull); + memory_region_set_enabled(cpu->cpu_as_root, true); + + /* + * ... with two regions inside: normal system memory with low + * priority, and... + */ + memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory", + get_system_memory(), 0, ~0ull); + memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_m= em, 0); + memory_region_set_enabled(cpu->cpu_as_mem, true); + + cs->num_ases =3D 2; + cpu_address_space_init(cs, 0, "cpu-memory", cs->memory); + cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root); + + /* ... SMRAM with higher priority, linked from /machine/smram. */ + cpu->machine_done.notify =3D x86_cpu_machine_done; + qemu_add_machine_init_done_notifier(&cpu->machine_done); +} + +#else /* CONFIG_USER_ONLY */ + +static void tcg_cpu_realizefn(CPUState *cs, Error **errp) +{ +} + +#endif /* !CONFIG_USER_ONLY */ + + +static void tcg_cpu_class_init(CPUClass *cc) { cc->tcg_ops.do_interrupt =3D x86_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D x86_cpu_exec_interrupt; @@ -67,5 +133,41 @@ void tcg_cpu_common_class_init(CPUClass *cc) cc->tcg_ops.tlb_fill =3D x86_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->tcg_ops.debug_excp_handler =3D breakpoint_handler; -#endif +#endif /* !CONFIG_USER_ONLY */ } + +/* + * TCG-specific defaults that override all CPU models when using TCG + */ +static PropValue tcg_default_props[] =3D { + { "vme", "off" }, + { NULL, NULL }, +}; + +static void tcg_cpu_instance_init(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + /* Special cases not set in the X86CPUDefinition structs: */ + x86_cpu_apply_props(cpu, tcg_default_props); +} + +static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data) +{ + AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); + + acc->cpu_realizefn =3D tcg_cpu_realizefn; + acc->cpu_class_init =3D tcg_cpu_class_init; + acc->cpu_instance_init =3D tcg_cpu_instance_init; +} +static const TypeInfo tcg_cpu_accel_type_info =3D { + .name =3D ACCEL_CPU_NAME("tcg"), + + .parent =3D TYPE_ACCEL_CPU, + .class_init =3D tcg_cpu_accel_class_init, + .abstract =3D true, +}; +static void tcg_cpu_accel_register_types(void) +{ + type_register_static(&tcg_cpu_accel_type_info); +} +type_init(tcg_cpu_accel_register_types); diff --git a/MAINTAINERS b/MAINTAINERS index f084d73f6b..4f3f1e8b18 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -337,7 +337,7 @@ M: Paolo Bonzini M: Richard Henderson M: Eduardo Habkost S: Maintained -F: target/i386/ +F: target/i386/tcg/ F: tests/tcg/i386/ F: tests/tcg/x86_64/ F: hw/i386/ diff --git a/target/i386/hvf/meson.build b/target/i386/hvf/meson.build index e9eb5a5da8..d253d5fd10 100644 --- a/target/i386/hvf/meson.build +++ b/target/i386/hvf/meson.build @@ -10,4 +10,5 @@ i386_softmmu_ss.add(when: [hvf, 'CONFIG_HVF'], if_true: f= iles( 'x86_mmu.c', 'x86_task.c', 'x86hvf.c', + 'hvf-cpu.c', )) diff --git a/target/i386/kvm/meson.build b/target/i386/kvm/meson.build index 1d66559187..0a533411ca 100644 --- a/target/i386/kvm/meson.build +++ b/target/i386/kvm/meson.build @@ -1,3 +1,8 @@ i386_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) -i386_softmmu_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) + +i386_softmmu_ss.add(when: 'CONFIG_KVM', if_true: files( + 'kvm.c', + 'kvm-cpu.c', +)) + i386_softmmu_ss.add(when: 'CONFIG_HYPERV', if_true: files('hyperv.c'), if_= false: files('hyperv-stub.c')) diff --git a/target/i386/meson.build b/target/i386/meson.build index c4bf20b319..fd24479590 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -6,7 +6,11 @@ i386_ss.add(files( 'xsave_helper.c', 'cpu-dump.c', )) -i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('= sev-stub.c')) +i386_ss.add(when: 'CONFIG_SEV', if_true: files('host-cpu.c', 'sev.c'), if_= false: files('sev-stub.c')) + +# x86 cpu type +i386_ss.add(when: 'CONFIG_KVM', if_true: files('host-cpu.c')) +i386_ss.add(when: 'CONFIG_HVF', if_true: files('host-cpu.c')) =20 i386_softmmu_ss =3D ss.source_set() i386_softmmu_ss.add(files( --=20 2.26.2 From nobody Fri May 17 09:38:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 11 Dec 2020 02:23:45 -0800 (PST) Received: from localhost ([::1]:52326 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knfPd-0002A7-Sb for importer@patchew.org; Fri, 11 Dec 2020 05:12:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39184) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knfMT-0006dk-Hk for qemu-devel@nongnu.org; Fri, 11 Dec 2020 05:09:17 -0500 Received: from mx2.suse.de ([195.135.220.15]:49714) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knfMR-0007cq-S0 for qemu-devel@nongnu.org; Fri, 11 Dec 2020 05:09:17 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 7A60DB1A1; Fri, 11 Dec 2020 10:09:14 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 5/7] cpu: call AccelCPUClass::cpu_realizefn in cpu_exec_realizefn Date: Fri, 11 Dec 2020 11:09:06 +0100 Message-Id: <20201211100908.19696-6-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211100908.19696-1-cfontana@suse.de> References: <20201211100908.19696-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" move the call to the accel_cpu_interface method to the general cpu_exec_realizefn from target/i386, so it does not need to be called for every target explicitly as we enable more targets. Signed-off-by: Claudio Fontana --- cpu.c | 5 +++++ target/i386/cpu.c | 15 ++++----------- 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/cpu.c b/cpu.c index 5cc8f181be..a59a909cfe 100644 --- a/cpu.c +++ b/cpu.c @@ -130,6 +130,11 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp) =20 cpu_list_add(cpu); =20 + if (cc->accel_cpu_interface) { + /* NB: errp parameter is unused currently */ + cc->accel_cpu_interface->cpu_realizefn(cpu, errp); + } + #ifdef CONFIG_TCG /* NB: errp parameter is unused currently */ if (tcg_enabled()) { diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5414523651..0fedf6c160 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6280,16 +6280,16 @@ static void x86_cpu_filter_features(X86CPU *cpu, bo= ol verbose) static void x86_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); - CPUClass *cc =3D CPU_GET_CLASS(cs); X86CPU *cpu =3D X86_CPU(dev); X86CPUClass *xcc =3D X86_CPU_GET_CLASS(dev); CPUX86State *env =3D &cpu->env; Error *local_err =3D NULL; static bool ht_warned; =20 - /* The accelerator realizefn needs to be called first. */ - if (cc->accel_cpu_interface) { - cc->accel_cpu_interface->cpu_realizefn(cs, errp); + cpu_exec_realizefn(cs, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; } =20 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { @@ -6405,13 +6405,6 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) env->cache_info_amd.l3_cache =3D &legacy_l3_cache; } =20 - - cpu_exec_realizefn(cs, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; - } - #ifndef CONFIG_USER_ONLY MachineState *ms =3D MACHINE(qdev_get_machine()); qemu_register_reset(x86_cpu_machine_reset_cb, cpu); --=20 2.26.2 From nobody Fri May 17 09:38:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Fri, 11 Dec 2020 02:21:10 -0800 (PST) Received: from localhost ([::1]:58672 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knfSD-0004t5-R9 for importer@patchew.org; Fri, 11 Dec 2020 05:15:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39220) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knfMV-0006gY-7Q for qemu-devel@nongnu.org; Fri, 11 Dec 2020 05:09:19 -0500 Received: from mx2.suse.de ([195.135.220.15]:49736) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knfMS-0007dH-HR for qemu-devel@nongnu.org; Fri, 11 Dec 2020 05:09:18 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 4C4A5B13A; Fri, 11 Dec 2020 10:09:15 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 6/7] hw/core/cpu: call qemu_init_vcpu in cpu_common_realizefn Date: Fri, 11 Dec 2020 11:09:07 +0100 Message-Id: <20201211100908.19696-7-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211100908.19696-1-cfontana@suse.de> References: <20201211100908.19696-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" move the call to qemu_init_vcpu inside cpu_common_realizefn, so it does not need to be done explicitly in each target cpu. This makes it a little bit better, but still the way realize is done continues to be bad; ideally the cpu_list_add would be done in common_cpu, and in this case we could avoid even more additional calls in target/xxx/cpu.c, but this cannot happen because target cpu code, plugins, etc now all rely on cpu->index, since no particular order was defined previously, so we are stuck with the freak call order for the target cpu realizefn. After this patch the target/xxx/cpu.c realizefn body is now: void mycpu_realizefn(DeviceState *dev, Error **errp) { /* ... */ cpu_exec_realizefn(CPU_STATE(dev), errp); /* ... anything that needs done pre-qemu_vcpu_init */ xcc->parent_realize(dev, errp); /* does qemu_vcpu_init */ /* ... anything that needs to be done after qemu_vcpu_init */ } Note: better do some testing for all targets for this. Signed-off-by: Claudio Fontana --- hw/core/cpu.c | 2 ++ target/alpha/cpu.c | 5 +---- target/arm/cpu.c | 4 +--- target/avr/cpu.c | 3 +-- target/cris/cpu.c | 2 -- target/hppa/cpu.c | 1 - target/i386/cpu.c | 5 +---- target/lm32/cpu.c | 3 --- target/m68k/cpu.c | 2 -- target/microblaze/cpu.c | 9 +++------ target/mips/cpu.c | 2 -- target/moxie/cpu.c | 4 +--- target/nios2/cpu.c | 4 +--- target/openrisc/cpu.c | 4 +--- target/riscv/cpu.c | 8 +++----- target/rx/cpu.c | 8 +++----- target/s390x/cpu.c | 3 +-- target/sh4/cpu.c | 2 -- target/sparc/cpu.c | 4 +--- target/tilegx/cpu.c | 2 -- target/tricore/cpu.c | 2 -- target/unicore32/cpu.c | 6 +----- target/xtensa/cpu.c | 2 -- target/ppc/translate_init.c.inc | 5 ++--- 24 files changed, 23 insertions(+), 69 deletions(-) diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 1f04aab16b..f41c009e6c 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -318,6 +318,8 @@ static void cpu_common_realizefn(DeviceState *dev, Erro= r **errp) CPUState *cpu =3D CPU(dev); Object *machine =3D qdev_get_machine(); =20 + qemu_init_vcpu(cpu); + /* qdev_get_machine() can return something that's not TYPE_MACHINE * if this is one of the user-only emulators; in that case there's * no need to check the ignore_memory_transaction_failures board flag. diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 0710298e5a..97965308a4 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -56,18 +56,15 @@ static void alpha_cpu_disas_set_info(CPUState *cpu, dis= assemble_info *info) =20 static void alpha_cpu_realizefn(DeviceState *dev, Error **errp) { - CPUState *cs =3D CPU(dev); AlphaCPUClass *acc =3D ALPHA_CPU_GET_CLASS(dev); Error *local_err =3D NULL; =20 - cpu_exec_realizefn(cs, &local_err); + cpu_exec_realizefn(CPU(dev), &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); return; } =20 - qemu_init_vcpu(cs); - acc->parent_realize(dev, errp); } =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1ba11698eb..2472247ee5 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1859,10 +1859,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) } } =20 - qemu_init_vcpu(cs); - cpu_reset(cs); - acc->parent_realize(dev, errp); + cpu_reset(cs); } =20 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 5a5ae68444..43f91f650d 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -97,10 +97,9 @@ static void avr_cpu_realizefn(DeviceState *dev, Error **= errp) error_propagate(errp, local_err); return; } - qemu_init_vcpu(cs); - cpu_reset(cs); =20 mcc->parent_realize(dev, errp); + cpu_reset(cs); } =20 static void avr_cpu_set_int(void *opaque, int irq, int level) diff --git a/target/cris/cpu.c b/target/cris/cpu.c index b65743e8ca..42a497d9fe 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -135,8 +135,6 @@ static void cris_cpu_realizefn(DeviceState *dev, Error = **errp) } =20 cpu_reset(cs); - qemu_init_vcpu(cs); - ccc->parent_realize(dev, errp); } =20 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 0985b3661f..979714c62e 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -101,7 +101,6 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error = **errp) return; } =20 - qemu_init_vcpu(cs); acc->parent_realize(dev, errp); =20 #ifndef CONFIG_USER_ONLY diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0fedf6c160..5615d9e8bc 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6419,8 +6419,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error= **errp) =20 mce_init(cpu); =20 - qemu_init_vcpu(cs); - + xcc->parent_realize(dev, &local_err); /* * Most Intel and certain AMD CPUs support hyperthreading. Even though= QEMU * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_00= 08_ECX @@ -6447,8 +6446,6 @@ static void x86_cpu_realizefn(DeviceState *dev, Error= **errp) } cpu_reset(cs); =20 - xcc->parent_realize(dev, &local_err); - out: if (local_err !=3D NULL) { error_propagate(errp, local_err); diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index fb3761b749..99196c22a4 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -133,9 +133,6 @@ static void lm32_cpu_realizefn(DeviceState *dev, Error = **errp) } =20 cpu_reset(cs); - - qemu_init_vcpu(cs); - lcc->parent_realize(dev, errp); } =20 diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 3f60c99865..41d3b2c11e 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -248,8 +248,6 @@ static void m68k_cpu_realizefn(DeviceState *dev, Error = **errp) m68k_cpu_init_gdb(cpu); =20 cpu_reset(cs); - qemu_init_vcpu(cs); - mcc->parent_realize(dev, errp); } =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 395f4a300f..6e068b2ae0 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -145,15 +145,14 @@ static void mb_disas_set_info(CPUState *cpu, disassem= ble_info *info) =20 static void mb_cpu_realizefn(DeviceState *dev, Error **errp) { - CPUState *cs =3D CPU(dev); MicroBlazeCPUClass *mcc =3D MICROBLAZE_CPU_GET_CLASS(dev); - MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); + MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(dev); uint8_t version_code =3D 0; const char *version; int i =3D 0; Error *local_err =3D NULL; =20 - cpu_exec_realizefn(cs, &local_err); + cpu_exec_realizefn(CPU(dev), &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); return; @@ -165,7 +164,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **= errp) return; } =20 - qemu_init_vcpu(cs); + mcc->parent_realize(dev, errp); =20 version =3D cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION; for (i =3D 0; mb_cpu_lookup[i].name && version; i++) { @@ -231,8 +230,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **= errp) cpu->cfg.mmu_tlb_access =3D 3; cpu->cfg.mmu_zones =3D 16; cpu->cfg.addr_mask =3D MAKE_64BIT_MASK(0, cpu->cfg.addr_size); - - mcc->parent_realize(dev, errp); } =20 static void mb_cpu_initfn(Object *obj) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index e99c692e2d..87cc55f087 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -184,8 +184,6 @@ static void mips_cpu_realizefn(DeviceState *dev, Error = **errp) cpu_mips_realize_env(&cpu->env); =20 cpu_reset(cs); - qemu_init_vcpu(cs); - mcc->parent_realize(dev, errp); } =20 diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 36bef4d357..4dfd2936af 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -66,10 +66,8 @@ static void moxie_cpu_realizefn(DeviceState *dev, Error = **errp) return; } =20 - qemu_init_vcpu(cs); - cpu_reset(cs); - mcc->parent_realize(dev, errp); + cpu_reset(cs); } =20 static void moxie_cpu_initfn(Object *obj) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 059eea8c94..46440d6ad8 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -92,10 +92,8 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error = **errp) return; } =20 - qemu_init_vcpu(cs); - cpu_reset(cs); - ncc->parent_realize(dev, errp); + cpu_reset(cs); } =20 static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 27105c5c09..e16b66fd14 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -77,10 +77,8 @@ static void openrisc_cpu_realizefn(DeviceState *dev, Err= or **errp) return; } =20 - qemu_init_vcpu(cs); - cpu_reset(cs); - occ->parent_realize(dev, errp); + cpu_reset(cs); } =20 static void openrisc_cpu_initfn(Object *obj) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e5626862c2..6b4eadfdeb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -341,7 +341,7 @@ static void riscv_cpu_disas_set_info(CPUState *s, disas= semble_info *info) #endif } =20 -static void riscv_cpu_realize(DeviceState *dev, Error **errp) +static void riscv_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); RISCVCPU *cpu =3D RISCV_CPU(dev); @@ -486,10 +486,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) =20 riscv_cpu_register_gdb_regs_for_features(cs); =20 - qemu_init_vcpu(cs); - cpu_reset(cs); - mcc->parent_realize(dev, errp); + cpu_reset(cs); } =20 static void riscv_cpu_init(Object *obj) @@ -532,7 +530,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) CPUClass *cc =3D CPU_CLASS(c); DeviceClass *dc =3D DEVICE_CLASS(c); =20 - device_class_set_parent_realize(dc, riscv_cpu_realize, + device_class_set_parent_realize(dc, riscv_cpu_realizefn, &mcc->parent_realize); =20 device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); diff --git a/target/rx/cpu.c b/target/rx/cpu.c index dc7d1c3c57..75ee2866dc 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -105,7 +105,7 @@ static ObjectClass *rx_cpu_class_by_name(const char *cp= u_model) return oc; } =20 -static void rx_cpu_realize(DeviceState *dev, Error **errp) +static void rx_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); RXCPUClass *rcc =3D RX_CPU_GET_CLASS(dev); @@ -117,10 +117,8 @@ static void rx_cpu_realize(DeviceState *dev, Error **e= rrp) return; } =20 - qemu_init_vcpu(cs); - cpu_reset(cs); - rcc->parent_realize(dev, errp); + cpu_reset(cs); } =20 static void rx_cpu_set_irq(void *opaque, int no, int request) @@ -178,7 +176,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) CPUClass *cc =3D CPU_CLASS(klass); RXCPUClass *rcc =3D RX_CPU_CLASS(klass); =20 - device_class_set_parent_realize(dc, rx_cpu_realize, + device_class_set_parent_realize(dc, rx_cpu_realizefn, &rcc->parent_realize); device_class_set_parent_reset(dc, rx_cpu_reset, &rcc->parent_reset); diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 86f654fd6b..d67ae110af 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -232,8 +232,8 @@ static void s390_cpu_realizefn(DeviceState *dev, Error = **errp) qemu_register_reset(s390_cpu_machine_reset_cb, cpu); #endif s390_cpu_gdb_init(cs); - qemu_init_vcpu(cs); =20 + scc->parent_realize(dev, &err); /* * KVM requires the initial CPU reset ioctl to be executed on the targ= et * CPU thread. CPU hotplug under single-threaded TCG will not work with @@ -246,7 +246,6 @@ static void s390_cpu_realizefn(DeviceState *dev, Error = **errp) cpu_reset(cs); } =20 - scc->parent_realize(dev, &err); out: error_propagate(errp, err); } diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index fbd5f42675..b9380cce83 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -185,8 +185,6 @@ static void superh_cpu_realizefn(DeviceState *dev, Erro= r **errp) } =20 cpu_reset(cs); - qemu_init_vcpu(cs); - scc->parent_realize(dev, errp); } =20 diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 3b53ef2390..0b604372d3 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -738,9 +738,9 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error= **errp) { CPUState *cs =3D CPU(dev); SPARCCPUClass *scc =3D SPARC_CPU_GET_CLASS(dev); - Error *local_err =3D NULL; SPARCCPU *cpu =3D SPARC_CPU(dev); CPUSPARCState *env =3D &cpu->env; + Error *local_err =3D NULL; =20 #if defined(CONFIG_USER_ONLY) if ((env->def.features & CPU_FEATURE_FLOAT)) { @@ -768,8 +768,6 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error= **errp) return; } =20 - qemu_init_vcpu(cs); - scc->parent_realize(dev, errp); } =20 diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index 7d4ead4ef1..01db5bdbcf 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -93,8 +93,6 @@ static void tilegx_cpu_realizefn(DeviceState *dev, Error = **errp) } =20 cpu_reset(cs); - qemu_init_vcpu(cs); - tcc->parent_realize(dev, errp); } =20 diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 89a14f81d7..ac57239f87 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -93,8 +93,6 @@ static void tricore_cpu_realizefn(DeviceState *dev, Error= **errp) set_feature(env, TRICORE_FEATURE_13); } cpu_reset(cs); - qemu_init_vcpu(cs); - tcc->parent_realize(dev, errp); } =20 diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index e27ffc571a..fe4ae21700 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -84,18 +84,14 @@ static void uc32_any_cpu_initfn(Object *obj) =20 static void uc32_cpu_realizefn(DeviceState *dev, Error **errp) { - CPUState *cs =3D CPU(dev); UniCore32CPUClass *ucc =3D UNICORE32_CPU_GET_CLASS(dev); Error *local_err =3D NULL; =20 - cpu_exec_realizefn(cs, &local_err); + cpu_exec_realizefn(CPU(dev), &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); return; } - - qemu_init_vcpu(cs); - ucc->parent_realize(dev, errp); } =20 diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 4b6381569f..7387d90cc6 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -153,8 +153,6 @@ static void xtensa_cpu_realizefn(DeviceState *dev, Erro= r **errp) =20 cs->gdb_num_regs =3D xcc->config->gdb_regmap.num_regs; =20 - qemu_init_vcpu(cs); - xcc->parent_realize(dev, errp); } =20 diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 3fbec30a65..6a1eefae75 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10093,7 +10093,7 @@ static int ppc_fixup_cpu(PowerPCCPU *cpu) return 0; } =20 -static void ppc_cpu_realize(DeviceState *dev, Error **errp) +static void ppc_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); PowerPCCPU *cpu =3D POWERPC_CPU(dev); @@ -10143,7 +10143,6 @@ static void ppc_cpu_realize(DeviceState *dev, Error= **errp) gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg, pcc->gdb_num_sprs, "power-spr.xml", 0); #endif - qemu_init_vcpu(cs); =20 pcc->parent_realize(dev, errp); =20 @@ -10898,7 +10897,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) CPUClass *cc =3D CPU_CLASS(oc); DeviceClass *dc =3D DEVICE_CLASS(oc); =20 - device_class_set_parent_realize(dc, ppc_cpu_realize, + device_class_set_parent_realize(dc, ppc_cpu_realizefn, &pcc->parent_realize); device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, &pcc->parent_unrealize); --=20 2.26.2 From nobody Fri May 17 09:38:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607681961; cv=none; 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Fri, 11 Dec 2020 02:19:21 -0800 (PST) Received: from localhost ([::1]:59450 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knfSO-0005Ec-4l for importer@patchew.org; Fri, 11 Dec 2020 05:15:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39234) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knfMW-0006jN-Jy for qemu-devel@nongnu.org; Fri, 11 Dec 2020 05:09:20 -0500 Received: from mx2.suse.de ([195.135.220.15]:49778) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knfMT-0007dT-Ee for qemu-devel@nongnu.org; Fri, 11 Dec 2020 05:09:20 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 22565B16A; Fri, 11 Dec 2020 10:09:16 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 7/7] cpu: introduce cpu_accel_instance_init Date: Fri, 11 Dec 2020 11:09:08 +0100 Message-Id: <20201211100908.19696-8-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211100908.19696-1-cfontana@suse.de> References: <20201211100908.19696-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" centralize the calls to cpu->accel_cpu_interface Signed-off-by: Claudio Fontana --- include/hw/core/cpu.h | 6 ++++++ hw/core/cpu.c | 9 +++++++++ target/i386/cpu.c | 9 ++------- 3 files changed, 17 insertions(+), 7 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 97e1dd8279..cc05c8fc96 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -664,6 +664,12 @@ void cpu_list_remove(CPUState *cpu); */ void cpu_reset(CPUState *cpu); =20 +/** + * cpu_accel_instance_init: + * @cpu: The CPU that needs to do accel-specific object initializations. + */ +void cpu_accel_instance_init(CPUState *cpu); + /** * cpu_class_by_name: * @typename: The CPU base type. diff --git a/hw/core/cpu.c b/hw/core/cpu.c index f41c009e6c..873cf5e4ef 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -242,6 +242,15 @@ void cpu_reset(CPUState *cpu) trace_guest_cpu_reset(cpu); } =20 +void cpu_accel_instance_init(CPUState *cpu) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + if (cc->accel_cpu_interface) { + cc->accel_cpu_interface->cpu_instance_init(cpu); + } +} + static void cpu_common_reset(DeviceState *dev) { CPUState *cpu =3D CPU(dev); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5615d9e8bc..8ee39bea24 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -28,7 +28,6 @@ #include "sysemu/kvm.h" #include "sysemu/reset.h" #include "sysemu/hvf.h" -#include "hw/core/accel-cpu.h" #include "sysemu/xen.h" #include "kvm/kvm_i386.h" #include "sev_i386.h" @@ -6621,8 +6620,6 @@ static void x86_cpu_initfn(Object *obj) { X86CPU *cpu =3D X86_CPU(obj); X86CPUClass *xcc =3D X86_CPU_GET_CLASS(obj); - CPUClass *cc =3D CPU_CLASS(xcc); - CPUX86State *env =3D &cpu->env; FeatureWord w; =20 @@ -6680,10 +6677,8 @@ static void x86_cpu_initfn(Object *obj) x86_cpu_load_model(cpu, xcc->model); } =20 - /* if required, do the accelerator-specific cpu initialization */ - if (cc->accel_cpu_interface) { - cc->accel_cpu_interface->cpu_instance_init(CPU(obj)); - } + /* if required, do accelerator-specific cpu initializations */ + cpu_accel_instance_init(CPU(obj)); } =20 static int64_t x86_cpu_get_arch_id(CPUState *cs) --=20 2.26.2