From nobody Mon May 20 22:41:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607675658; cv=none; d=zohomail.com; s=zohoarc; b=E2vJI+ueklyj5WIkGSdmphtuhVww7Xdn69SWXmsTSdGlcgcPV8x/2mrLOEeL0L10ihek3C3LpYPCH4ffJF3xKEPt/EVx6yck1KRgvLbIIXnBkvS3oplrnjMjodiPdH4cc+Yzqk50RKx2E2eL5mIVwqyogoMTTt3xlPqBrr1tjuo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607675658; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cx6M4ge5TCAcIivCr+EWQRpDLKAVTq/s3OYCEqfskXY=; b=FPLzkfXUeBrHxzrRKzZqza2fxzrTQndbmWefpYX6G729I/+xsxztuZkCqLwvf0sXlfyUsrqQ95Clebb3ivTHd8CUDmE4Kz4Zxegib9VRdEAY/fAAmQqndcdudWiJC0kXt/mY+GHdNHEiEo7nETYZX7fP/xY2TuberEH49qh+blU= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607675658001850.1773516349461; Fri, 11 Dec 2020 00:34:18 -0800 (PST) Received: from localhost ([::1]:34902 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kndsW-0001q6-JZ for importer@patchew.org; Fri, 11 Dec 2020 03:34:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42340) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqB-00081E-Fy for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:31:51 -0500 Received: from mx2.suse.de ([195.135.220.15]:34650) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndq7-000264-Qb for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:31:51 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 24F42AFFA; Fri, 11 Dec 2020 08:31:46 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 01/25] accel/tcg: split CpusAccel into three TCG variants Date: Fri, 11 Dec 2020 09:31:19 +0100 Message-Id: <20201211083143.14350-2-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211083143.14350-1-cfontana@suse.de> References: <20201211083143.14350-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" split up the CpusAccel tcg_cpus into three TCG variants: tcg_cpus_rr (single threaded, round robin cpus) tcg_cpus_icount (same as rr, but with instruction counting enabled) tcg_cpus_mttcg (multi-threaded cpus) Suggested-by: Richard Henderson Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/tcg-cpus-icount.h | 17 ++ accel/tcg/tcg-cpus-mttcg.h | 21 ++ accel/tcg/tcg-cpus-rr.h | 20 ++ accel/tcg/tcg-cpus.h | 13 +- accel/tcg/tcg-all.c | 8 +- accel/tcg/tcg-cpus-icount.c | 147 +++++++++++ accel/tcg/tcg-cpus-mttcg.c | 117 +++++++++ accel/tcg/tcg-cpus-rr.c | 270 ++++++++++++++++++++ accel/tcg/tcg-cpus.c | 484 ++---------------------------------- softmmu/icount.c | 2 +- accel/tcg/meson.build | 9 +- 11 files changed, 646 insertions(+), 462 deletions(-) create mode 100644 accel/tcg/tcg-cpus-icount.h create mode 100644 accel/tcg/tcg-cpus-mttcg.h create mode 100644 accel/tcg/tcg-cpus-rr.h create mode 100644 accel/tcg/tcg-cpus-icount.c create mode 100644 accel/tcg/tcg-cpus-mttcg.c create mode 100644 accel/tcg/tcg-cpus-rr.c diff --git a/accel/tcg/tcg-cpus-icount.h b/accel/tcg/tcg-cpus-icount.h new file mode 100644 index 0000000000..cbcf76b413 --- /dev/null +++ b/accel/tcg/tcg-cpus-icount.h @@ -0,0 +1,17 @@ +/* + * QEMU TCG Single Threaded vCPUs implementation using instruction counting + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef TCG_CPUS_ICOUNT_H +#define TCG_CPUS_ICOUNT_H + +void handle_icount_deadline(void); +void prepare_icount_for_run(CPUState *cpu); +void process_icount_data(CPUState *cpu); + +#endif /* TCG_CPUS_ICOUNT_H */ diff --git a/accel/tcg/tcg-cpus-mttcg.h b/accel/tcg/tcg-cpus-mttcg.h new file mode 100644 index 0000000000..d1bd771f49 --- /dev/null +++ b/accel/tcg/tcg-cpus-mttcg.h @@ -0,0 +1,21 @@ +/* + * QEMU TCG Multi Threaded vCPUs implementation + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef TCG_CPUS_MTTCG_H +#define TCG_CPUS_MTTCG_H + +/* + * In the multi-threaded case each vCPU has its own thread. The TLS + * variable current_cpu can be used deep in the code to find the + * current CPUState for a given thread. + */ + +void *tcg_cpu_thread_fn(void *arg); + +#endif /* TCG_CPUS_MTTCG_H */ diff --git a/accel/tcg/tcg-cpus-rr.h b/accel/tcg/tcg-cpus-rr.h new file mode 100644 index 0000000000..1936fd16ab --- /dev/null +++ b/accel/tcg/tcg-cpus-rr.h @@ -0,0 +1,20 @@ +/* + * QEMU TCG Single Threaded vCPUs implementation + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef TCG_CPUS_RR_H +#define TCG_CPUS_RR_H + +#define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10) + +/* Kick all RR vCPUs. */ +void qemu_cpu_kick_rr_cpus(CPUState *unused); + +void *tcg_rr_cpu_thread_fn(void *arg); + +#endif /* TCG_CPUS_RR_H */ diff --git a/accel/tcg/tcg-cpus.h b/accel/tcg/tcg-cpus.h index 8b1d9d2abc..279ba72e1f 100644 --- a/accel/tcg/tcg-cpus.h +++ b/accel/tcg/tcg-cpus.h @@ -1,5 +1,7 @@ /* - * Accelerator CPUS Interface + * QEMU TCG vCPU common functionality + * + * Functionality common to all TCG vcpu variants: mttcg, rr and icount. * * Copyright 2020 SUSE LLC * @@ -12,6 +14,13 @@ =20 #include "sysemu/cpus.h" =20 -extern const CpusAccel tcg_cpus; +extern const CpusAccel tcg_cpus_mttcg; +extern const CpusAccel tcg_cpus_icount; +extern const CpusAccel tcg_cpus_rr; + +void tcg_start_vcpu_thread(CPUState *cpu); +void qemu_tcg_destroy_vcpu(CPUState *cpu); +int tcg_cpu_exec(CPUState *cpu); +void tcg_handle_interrupt(CPUState *cpu, int mask); =20 #endif /* TCG_CPUS_H */ diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index fa1208158f..e42a028043 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -104,8 +104,14 @@ static int tcg_init(MachineState *ms) =20 tcg_exec_init(s->tb_size * 1024 * 1024); mttcg_enabled =3D s->mttcg_enabled; - cpus_register_accel(&tcg_cpus); =20 + if (mttcg_enabled) { + cpus_register_accel(&tcg_cpus_mttcg); + } else if (icount_enabled()) { + cpus_register_accel(&tcg_cpus_icount); + } else { + cpus_register_accel(&tcg_cpus_rr); + } return 0; } =20 diff --git a/accel/tcg/tcg-cpus-icount.c b/accel/tcg/tcg-cpus-icount.c new file mode 100644 index 0000000000..d3af3afb6d --- /dev/null +++ b/accel/tcg/tcg-cpus-icount.c @@ -0,0 +1,147 @@ +/* + * QEMU TCG Single Threaded vCPUs implementation using instruction counting + * + * Copyright (c) 2003-2008 Fabrice Bellard + * Copyright (c) 2014 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "sysemu/tcg.h" +#include "sysemu/replay.h" +#include "qemu/main-loop.h" +#include "qemu/guest-random.h" +#include "exec/exec-all.h" +#include "hw/boards.h" + +#include "tcg-cpus.h" +#include "tcg-cpus-icount.h" +#include "tcg-cpus-rr.h" + +static int64_t tcg_get_icount_limit(void) +{ + int64_t deadline; + + if (replay_mode !=3D REPLAY_MODE_PLAY) { + /* + * Include all the timers, because they may need an attention. + * Too long CPU execution may create unnecessary delay in UI. + */ + deadline =3D qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL, + QEMU_TIMER_ATTR_ALL); + /* Check realtime timers, because they help with input processing = */ + deadline =3D qemu_soonest_timeout(deadline, + qemu_clock_deadline_ns_all(QEMU_CLOCK_REALTIME, + QEMU_TIMER_ATTR_ALL)); + + /* + * Maintain prior (possibly buggy) behaviour where if no deadline + * was set (as there is no QEMU_CLOCK_VIRTUAL timer) or it is more= than + * INT32_MAX nanoseconds ahead, we still use INT32_MAX + * nanoseconds. + */ + if ((deadline < 0) || (deadline > INT32_MAX)) { + deadline =3D INT32_MAX; + } + + return icount_round(deadline); + } else { + return replay_get_instructions(); + } +} + +static void notify_aio_contexts(void) +{ + /* Wake up other AioContexts. */ + qemu_clock_notify(QEMU_CLOCK_VIRTUAL); + qemu_clock_run_timers(QEMU_CLOCK_VIRTUAL); +} + +void handle_icount_deadline(void) +{ + assert(qemu_in_vcpu_thread()); + int64_t deadline =3D qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL, + QEMU_TIMER_ATTR_ALL); + + if (deadline =3D=3D 0) { + notify_aio_contexts(); + } +} + +void prepare_icount_for_run(CPUState *cpu) +{ + int insns_left; + + /* + * These should always be cleared by process_icount_data after + * each vCPU execution. However u16.high can be raised + * asynchronously by cpu_exit/cpu_interrupt/tcg_handle_interrupt + */ + g_assert(cpu_neg(cpu)->icount_decr.u16.low =3D=3D 0); + g_assert(cpu->icount_extra =3D=3D 0); + + cpu->icount_budget =3D tcg_get_icount_limit(); + insns_left =3D MIN(0xffff, cpu->icount_budget); + cpu_neg(cpu)->icount_decr.u16.low =3D insns_left; + cpu->icount_extra =3D cpu->icount_budget - insns_left; + + replay_mutex_lock(); + + if (cpu->icount_budget =3D=3D 0 && replay_has_checkpoint()) { + notify_aio_contexts(); + } +} + +void process_icount_data(CPUState *cpu) +{ + /* Account for executed instructions */ + icount_update(cpu); + + /* Reset the counters */ + cpu_neg(cpu)->icount_decr.u16.low =3D 0; + cpu->icount_extra =3D 0; + cpu->icount_budget =3D 0; + + replay_account_executed_instructions(); + + replay_mutex_unlock(); +} + +static void icount_handle_interrupt(CPUState *cpu, int mask) +{ + int old_mask =3D cpu->interrupt_request; + + tcg_handle_interrupt(cpu, mask); + if (qemu_cpu_is_self(cpu) && + !cpu->can_do_io + && (mask & ~old_mask) !=3D 0) { + cpu_abort(cpu, "Raised interrupt while not in I/O function"); + } +} + +const CpusAccel tcg_cpus_icount =3D { + .create_vcpu_thread =3D tcg_start_vcpu_thread, + .kick_vcpu_thread =3D qemu_cpu_kick_rr_cpus, + + .handle_interrupt =3D icount_handle_interrupt, + .get_virtual_clock =3D icount_get, + .get_elapsed_ticks =3D icount_get, +}; diff --git a/accel/tcg/tcg-cpus-mttcg.c b/accel/tcg/tcg-cpus-mttcg.c new file mode 100644 index 0000000000..dac724fc85 --- /dev/null +++ b/accel/tcg/tcg-cpus-mttcg.c @@ -0,0 +1,117 @@ +/* + * QEMU TCG Multi Threaded vCPUs implementation + * + * Copyright (c) 2003-2008 Fabrice Bellard + * Copyright (c) 2014 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "sysemu/tcg.h" +#include "sysemu/replay.h" +#include "qemu/main-loop.h" +#include "qemu/guest-random.h" +#include "exec/exec-all.h" +#include "hw/boards.h" + +#include "tcg-cpus.h" +#include "tcg-cpus-mttcg.h" + +/* + * In the multi-threaded case each vCPU has its own thread. The TLS + * variable current_cpu can be used deep in the code to find the + * current CPUState for a given thread. + */ + +void *tcg_cpu_thread_fn(void *arg) +{ + CPUState *cpu =3D arg; + + assert(tcg_enabled()); + g_assert(!icount_enabled()); + + rcu_register_thread(); + tcg_register_thread(); + + qemu_mutex_lock_iothread(); + qemu_thread_get_self(cpu->thread); + + cpu->thread_id =3D qemu_get_thread_id(); + cpu->can_do_io =3D 1; + current_cpu =3D cpu; + cpu_thread_signal_created(cpu); + qemu_guest_random_seed_thread_part2(cpu->random_seed); + + /* process any pending work */ + cpu->exit_request =3D 1; + + do { + if (cpu_can_run(cpu)) { + int r; + qemu_mutex_unlock_iothread(); + r =3D tcg_cpu_exec(cpu); + qemu_mutex_lock_iothread(); + switch (r) { + case EXCP_DEBUG: + cpu_handle_guest_debug(cpu); + break; + case EXCP_HALTED: + /* + * during start-up the vCPU is reset and the thread is + * kicked several times. If we don't ensure we go back + * to sleep in the halted state we won't cleanly + * start-up when the vCPU is enabled. + * + * cpu->halted should ensure we sleep in wait_io_event + */ + g_assert(cpu->halted); + break; + case EXCP_ATOMIC: + qemu_mutex_unlock_iothread(); + cpu_exec_step_atomic(cpu); + qemu_mutex_lock_iothread(); + default: + /* Ignore everything else? */ + break; + } + } + + qatomic_mb_set(&cpu->exit_request, 0); + qemu_wait_io_event(cpu); + } while (!cpu->unplug || cpu_can_run(cpu)); + + qemu_tcg_destroy_vcpu(cpu); + qemu_mutex_unlock_iothread(); + rcu_unregister_thread(); + return NULL; +} + +static void mttcg_kick_vcpu_thread(CPUState *cpu) +{ + cpu_exit(cpu); +} + +const CpusAccel tcg_cpus_mttcg =3D { + .create_vcpu_thread =3D tcg_start_vcpu_thread, + .kick_vcpu_thread =3D mttcg_kick_vcpu_thread, + + .handle_interrupt =3D tcg_handle_interrupt, +}; diff --git a/accel/tcg/tcg-cpus-rr.c b/accel/tcg/tcg-cpus-rr.c new file mode 100644 index 0000000000..ad50a3765f --- /dev/null +++ b/accel/tcg/tcg-cpus-rr.c @@ -0,0 +1,270 @@ +/* + * QEMU TCG Single Threaded vCPUs implementation + * + * Copyright (c) 2003-2008 Fabrice Bellard + * Copyright (c) 2014 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "sysemu/tcg.h" +#include "sysemu/replay.h" +#include "qemu/main-loop.h" +#include "qemu/guest-random.h" +#include "exec/exec-all.h" +#include "hw/boards.h" + +#include "tcg-cpus.h" +#include "tcg-cpus-rr.h" +#include "tcg-cpus-icount.h" + +/* Kick all RR vCPUs */ +void qemu_cpu_kick_rr_cpus(CPUState *unused) +{ + CPUState *cpu; + + CPU_FOREACH(cpu) { + cpu_exit(cpu); + }; +} + +/* + * TCG vCPU kick timer + * + * The kick timer is responsible for moving single threaded vCPU + * emulation on to the next vCPU. If more than one vCPU is running a + * timer event with force a cpu->exit so the next vCPU can get + * scheduled. + * + * The timer is removed if all vCPUs are idle and restarted again once + * idleness is complete. + */ + +static QEMUTimer *tcg_kick_vcpu_timer; +static CPUState *tcg_current_rr_cpu; + +#define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10) + +static inline int64_t qemu_tcg_next_kick(void) +{ + return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + TCG_KICK_PERIOD; +} + +/* Kick the currently round-robin scheduled vCPU to next */ +static void qemu_cpu_kick_rr_next_cpu(void) +{ + CPUState *cpu; + do { + cpu =3D qatomic_mb_read(&tcg_current_rr_cpu); + if (cpu) { + cpu_exit(cpu); + } + } while (cpu !=3D qatomic_mb_read(&tcg_current_rr_cpu)); +} + +static void kick_tcg_thread(void *opaque) +{ + timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick()); + qemu_cpu_kick_rr_next_cpu(); +} + +static void start_tcg_kick_timer(void) +{ + if (!tcg_kick_vcpu_timer && CPU_NEXT(first_cpu)) { + tcg_kick_vcpu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + kick_tcg_thread, NULL); + } + if (tcg_kick_vcpu_timer && !timer_pending(tcg_kick_vcpu_timer)) { + timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick()); + } +} + +static void stop_tcg_kick_timer(void) +{ + if (tcg_kick_vcpu_timer && timer_pending(tcg_kick_vcpu_timer)) { + timer_del(tcg_kick_vcpu_timer); + } +} + +static void qemu_tcg_rr_wait_io_event(void) +{ + CPUState *cpu; + + while (all_cpu_threads_idle()) { + stop_tcg_kick_timer(); + qemu_cond_wait_iothread(first_cpu->halt_cond); + } + + start_tcg_kick_timer(); + + CPU_FOREACH(cpu) { + qemu_wait_io_event_common(cpu); + } +} + +/* + * Destroy any remaining vCPUs which have been unplugged and have + * finished running + */ +static void deal_with_unplugged_cpus(void) +{ + CPUState *cpu; + + CPU_FOREACH(cpu) { + if (cpu->unplug && !cpu_can_run(cpu)) { + qemu_tcg_destroy_vcpu(cpu); + break; + } + } +} + +/* + * In the single-threaded case each vCPU is simulated in turn. If + * there is more than a single vCPU we create a simple timer to kick + * the vCPU and ensure we don't get stuck in a tight loop in one vCPU. + * This is done explicitly rather than relying on side-effects + * elsewhere. + */ + +void *tcg_rr_cpu_thread_fn(void *arg) +{ + CPUState *cpu =3D arg; + + assert(tcg_enabled()); + rcu_register_thread(); + tcg_register_thread(); + + qemu_mutex_lock_iothread(); + qemu_thread_get_self(cpu->thread); + + cpu->thread_id =3D qemu_get_thread_id(); + cpu->can_do_io =3D 1; + cpu_thread_signal_created(cpu); + qemu_guest_random_seed_thread_part2(cpu->random_seed); + + /* wait for initial kick-off after machine start */ + while (first_cpu->stopped) { + qemu_cond_wait_iothread(first_cpu->halt_cond); + + /* process any pending work */ + CPU_FOREACH(cpu) { + current_cpu =3D cpu; + qemu_wait_io_event_common(cpu); + } + } + + start_tcg_kick_timer(); + + cpu =3D first_cpu; + + /* process any pending work */ + cpu->exit_request =3D 1; + + while (1) { + qemu_mutex_unlock_iothread(); + replay_mutex_lock(); + qemu_mutex_lock_iothread(); + + if (icount_enabled()) { + /* Account partial waits to QEMU_CLOCK_VIRTUAL. */ + icount_account_warp_timer(); + /* + * Run the timers here. This is much more efficient than + * waking up the I/O thread and waiting for completion. + */ + handle_icount_deadline(); + } + + replay_mutex_unlock(); + + if (!cpu) { + cpu =3D first_cpu; + } + + while (cpu && cpu_work_list_empty(cpu) && !cpu->exit_request) { + + qatomic_mb_set(&tcg_current_rr_cpu, cpu); + current_cpu =3D cpu; + + qemu_clock_enable(QEMU_CLOCK_VIRTUAL, + (cpu->singlestep_enabled & SSTEP_NOTIMER) = =3D=3D 0); + + if (cpu_can_run(cpu)) { + int r; + + qemu_mutex_unlock_iothread(); + if (icount_enabled()) { + prepare_icount_for_run(cpu); + } + r =3D tcg_cpu_exec(cpu); + if (icount_enabled()) { + process_icount_data(cpu); + } + qemu_mutex_lock_iothread(); + + if (r =3D=3D EXCP_DEBUG) { + cpu_handle_guest_debug(cpu); + break; + } else if (r =3D=3D EXCP_ATOMIC) { + qemu_mutex_unlock_iothread(); + cpu_exec_step_atomic(cpu); + qemu_mutex_lock_iothread(); + break; + } + } else if (cpu->stop) { + if (cpu->unplug) { + cpu =3D CPU_NEXT(cpu); + } + break; + } + + cpu =3D CPU_NEXT(cpu); + } /* while (cpu && !cpu->exit_request).. */ + + /* Does not need qatomic_mb_set because a spurious wakeup is okay.= */ + qatomic_set(&tcg_current_rr_cpu, NULL); + + if (cpu && cpu->exit_request) { + qatomic_mb_set(&cpu->exit_request, 0); + } + + if (icount_enabled() && all_cpu_threads_idle()) { + /* + * When all cpus are sleeping (e.g in WFI), to avoid a deadlock + * in the main_loop, wake it up in order to start the warp tim= er. + */ + qemu_notify_event(); + } + + qemu_tcg_rr_wait_io_event(); + deal_with_unplugged_cpus(); + } + + rcu_unregister_thread(); + return NULL; +} + +const CpusAccel tcg_cpus_rr =3D { + .create_vcpu_thread =3D tcg_start_vcpu_thread, + .kick_vcpu_thread =3D qemu_cpu_kick_rr_cpus, + + .handle_interrupt =3D tcg_handle_interrupt, +}; diff --git a/accel/tcg/tcg-cpus.c b/accel/tcg/tcg-cpus.c index da1c63d8f6..f2b9bbf99e 100644 --- a/accel/tcg/tcg-cpus.c +++ b/accel/tcg/tcg-cpus.c @@ -1,5 +1,7 @@ /* - * QEMU System Emulator + * QEMU TCG vCPU common functionality + * + * Functionality common to all TCG vCPU variants: mttcg, rr and icount. * * Copyright (c) 2003-2008 Fabrice Bellard * Copyright (c) 2014 Red Hat Inc. @@ -33,436 +35,12 @@ #include "hw/boards.h" =20 #include "tcg-cpus.h" +#include "tcg-cpus-mttcg.h" +#include "tcg-cpus-rr.h" =20 -/* Kick all RR vCPUs */ -static void qemu_cpu_kick_rr_cpus(void) -{ - CPUState *cpu; +/* common functionality among all TCG variants */ =20 - CPU_FOREACH(cpu) { - cpu_exit(cpu); - }; -} - -static void tcg_kick_vcpu_thread(CPUState *cpu) -{ - if (qemu_tcg_mttcg_enabled()) { - cpu_exit(cpu); - } else { - qemu_cpu_kick_rr_cpus(); - } -} - -/* - * TCG vCPU kick timer - * - * The kick timer is responsible for moving single threaded vCPU - * emulation on to the next vCPU. If more than one vCPU is running a - * timer event with force a cpu->exit so the next vCPU can get - * scheduled. - * - * The timer is removed if all vCPUs are idle and restarted again once - * idleness is complete. - */ - -static QEMUTimer *tcg_kick_vcpu_timer; -static CPUState *tcg_current_rr_cpu; - -#define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10) - -static inline int64_t qemu_tcg_next_kick(void) -{ - return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + TCG_KICK_PERIOD; -} - -/* Kick the currently round-robin scheduled vCPU to next */ -static void qemu_cpu_kick_rr_next_cpu(void) -{ - CPUState *cpu; - do { - cpu =3D qatomic_mb_read(&tcg_current_rr_cpu); - if (cpu) { - cpu_exit(cpu); - } - } while (cpu !=3D qatomic_mb_read(&tcg_current_rr_cpu)); -} - -static void kick_tcg_thread(void *opaque) -{ - timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick()); - qemu_cpu_kick_rr_next_cpu(); -} - -static void start_tcg_kick_timer(void) -{ - assert(!mttcg_enabled); - if (!tcg_kick_vcpu_timer && CPU_NEXT(first_cpu)) { - tcg_kick_vcpu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, - kick_tcg_thread, NULL); - } - if (tcg_kick_vcpu_timer && !timer_pending(tcg_kick_vcpu_timer)) { - timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick()); - } -} - -static void stop_tcg_kick_timer(void) -{ - assert(!mttcg_enabled); - if (tcg_kick_vcpu_timer && timer_pending(tcg_kick_vcpu_timer)) { - timer_del(tcg_kick_vcpu_timer); - } -} - -static void qemu_tcg_destroy_vcpu(CPUState *cpu) -{ -} - -static void qemu_tcg_rr_wait_io_event(void) -{ - CPUState *cpu; - - while (all_cpu_threads_idle()) { - stop_tcg_kick_timer(); - qemu_cond_wait_iothread(first_cpu->halt_cond); - } - - start_tcg_kick_timer(); - - CPU_FOREACH(cpu) { - qemu_wait_io_event_common(cpu); - } -} - -static int64_t tcg_get_icount_limit(void) -{ - int64_t deadline; - - if (replay_mode !=3D REPLAY_MODE_PLAY) { - /* - * Include all the timers, because they may need an attention. - * Too long CPU execution may create unnecessary delay in UI. - */ - deadline =3D qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL, - QEMU_TIMER_ATTR_ALL); - /* Check realtime timers, because they help with input processing = */ - deadline =3D qemu_soonest_timeout(deadline, - qemu_clock_deadline_ns_all(QEMU_CLOCK_REALTIME, - QEMU_TIMER_ATTR_ALL)); - - /* - * Maintain prior (possibly buggy) behaviour where if no deadline - * was set (as there is no QEMU_CLOCK_VIRTUAL timer) or it is more= than - * INT32_MAX nanoseconds ahead, we still use INT32_MAX - * nanoseconds. - */ - if ((deadline < 0) || (deadline > INT32_MAX)) { - deadline =3D INT32_MAX; - } - - return icount_round(deadline); - } else { - return replay_get_instructions(); - } -} - -static void notify_aio_contexts(void) -{ - /* Wake up other AioContexts. */ - qemu_clock_notify(QEMU_CLOCK_VIRTUAL); - qemu_clock_run_timers(QEMU_CLOCK_VIRTUAL); -} - -static void handle_icount_deadline(void) -{ - assert(qemu_in_vcpu_thread()); - if (icount_enabled()) { - int64_t deadline =3D qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL, - QEMU_TIMER_ATTR_ALL); - - if (deadline =3D=3D 0) { - notify_aio_contexts(); - } - } -} - -static void prepare_icount_for_run(CPUState *cpu) -{ - if (icount_enabled()) { - int insns_left; - - /* - * These should always be cleared by process_icount_data after - * each vCPU execution. However u16.high can be raised - * asynchronously by cpu_exit/cpu_interrupt/tcg_handle_interrupt - */ - g_assert(cpu_neg(cpu)->icount_decr.u16.low =3D=3D 0); - g_assert(cpu->icount_extra =3D=3D 0); - - cpu->icount_budget =3D tcg_get_icount_limit(); - insns_left =3D MIN(0xffff, cpu->icount_budget); - cpu_neg(cpu)->icount_decr.u16.low =3D insns_left; - cpu->icount_extra =3D cpu->icount_budget - insns_left; - - replay_mutex_lock(); - - if (cpu->icount_budget =3D=3D 0 && replay_has_checkpoint()) { - notify_aio_contexts(); - } - } -} - -static void process_icount_data(CPUState *cpu) -{ - if (icount_enabled()) { - /* Account for executed instructions */ - icount_update(cpu); - - /* Reset the counters */ - cpu_neg(cpu)->icount_decr.u16.low =3D 0; - cpu->icount_extra =3D 0; - cpu->icount_budget =3D 0; - - replay_account_executed_instructions(); - - replay_mutex_unlock(); - } -} - -static int tcg_cpu_exec(CPUState *cpu) -{ - int ret; -#ifdef CONFIG_PROFILER - int64_t ti; -#endif - - assert(tcg_enabled()); -#ifdef CONFIG_PROFILER - ti =3D profile_getclock(); -#endif - cpu_exec_start(cpu); - ret =3D cpu_exec(cpu); - cpu_exec_end(cpu); -#ifdef CONFIG_PROFILER - qatomic_set(&tcg_ctx->prof.cpu_exec_time, - tcg_ctx->prof.cpu_exec_time + profile_getclock() - ti); -#endif - return ret; -} - -/* - * Destroy any remaining vCPUs which have been unplugged and have - * finished running - */ -static void deal_with_unplugged_cpus(void) -{ - CPUState *cpu; - - CPU_FOREACH(cpu) { - if (cpu->unplug && !cpu_can_run(cpu)) { - qemu_tcg_destroy_vcpu(cpu); - cpu_thread_signal_destroyed(cpu); - break; - } - } -} - -/* - * Single-threaded TCG - * - * In the single-threaded case each vCPU is simulated in turn. If - * there is more than a single vCPU we create a simple timer to kick - * the vCPU and ensure we don't get stuck in a tight loop in one vCPU. - * This is done explicitly rather than relying on side-effects - * elsewhere. - */ - -static void *tcg_rr_cpu_thread_fn(void *arg) -{ - CPUState *cpu =3D arg; - - assert(tcg_enabled()); - rcu_register_thread(); - tcg_register_thread(); - - qemu_mutex_lock_iothread(); - qemu_thread_get_self(cpu->thread); - - cpu->thread_id =3D qemu_get_thread_id(); - cpu->can_do_io =3D 1; - cpu_thread_signal_created(cpu); - qemu_guest_random_seed_thread_part2(cpu->random_seed); - - /* wait for initial kick-off after machine start */ - while (first_cpu->stopped) { - qemu_cond_wait_iothread(first_cpu->halt_cond); - - /* process any pending work */ - CPU_FOREACH(cpu) { - current_cpu =3D cpu; - qemu_wait_io_event_common(cpu); - } - } - - start_tcg_kick_timer(); - - cpu =3D first_cpu; - - /* process any pending work */ - cpu->exit_request =3D 1; - - while (1) { - qemu_mutex_unlock_iothread(); - replay_mutex_lock(); - qemu_mutex_lock_iothread(); - /* Account partial waits to QEMU_CLOCK_VIRTUAL. */ - icount_account_warp_timer(); - - /* - * Run the timers here. This is much more efficient than - * waking up the I/O thread and waiting for completion. - */ - handle_icount_deadline(); - - replay_mutex_unlock(); - - if (!cpu) { - cpu =3D first_cpu; - } - - while (cpu && cpu_work_list_empty(cpu) && !cpu->exit_request) { - - qatomic_mb_set(&tcg_current_rr_cpu, cpu); - current_cpu =3D cpu; - - qemu_clock_enable(QEMU_CLOCK_VIRTUAL, - (cpu->singlestep_enabled & SSTEP_NOTIMER) = =3D=3D 0); - - if (cpu_can_run(cpu)) { - int r; - - qemu_mutex_unlock_iothread(); - prepare_icount_for_run(cpu); - - r =3D tcg_cpu_exec(cpu); - - process_icount_data(cpu); - qemu_mutex_lock_iothread(); - - if (r =3D=3D EXCP_DEBUG) { - cpu_handle_guest_debug(cpu); - break; - } else if (r =3D=3D EXCP_ATOMIC) { - qemu_mutex_unlock_iothread(); - cpu_exec_step_atomic(cpu); - qemu_mutex_lock_iothread(); - break; - } - } else if (cpu->stop) { - if (cpu->unplug) { - cpu =3D CPU_NEXT(cpu); - } - break; - } - - cpu =3D CPU_NEXT(cpu); - } /* while (cpu && !cpu->exit_request).. */ - - /* Does not need qatomic_mb_set because a spurious wakeup is okay.= */ - qatomic_set(&tcg_current_rr_cpu, NULL); - - if (cpu && cpu->exit_request) { - qatomic_mb_set(&cpu->exit_request, 0); - } - - if (icount_enabled() && all_cpu_threads_idle()) { - /* - * When all cpus are sleeping (e.g in WFI), to avoid a deadlock - * in the main_loop, wake it up in order to start the warp tim= er. - */ - qemu_notify_event(); - } - - qemu_tcg_rr_wait_io_event(); - deal_with_unplugged_cpus(); - } - - rcu_unregister_thread(); - return NULL; -} - -/* - * Multi-threaded TCG - * - * In the multi-threaded case each vCPU has its own thread. The TLS - * variable current_cpu can be used deep in the code to find the - * current CPUState for a given thread. - */ - -static void *tcg_cpu_thread_fn(void *arg) -{ - CPUState *cpu =3D arg; - - assert(tcg_enabled()); - g_assert(!icount_enabled()); - - rcu_register_thread(); - tcg_register_thread(); - - qemu_mutex_lock_iothread(); - qemu_thread_get_self(cpu->thread); - - cpu->thread_id =3D qemu_get_thread_id(); - cpu->can_do_io =3D 1; - current_cpu =3D cpu; - cpu_thread_signal_created(cpu); - qemu_guest_random_seed_thread_part2(cpu->random_seed); - - /* process any pending work */ - cpu->exit_request =3D 1; - - do { - if (cpu_can_run(cpu)) { - int r; - qemu_mutex_unlock_iothread(); - r =3D tcg_cpu_exec(cpu); - qemu_mutex_lock_iothread(); - switch (r) { - case EXCP_DEBUG: - cpu_handle_guest_debug(cpu); - break; - case EXCP_HALTED: - /* - * during start-up the vCPU is reset and the thread is - * kicked several times. If we don't ensure we go back - * to sleep in the halted state we won't cleanly - * start-up when the vCPU is enabled. - * - * cpu->halted should ensure we sleep in wait_io_event - */ - g_assert(cpu->halted); - break; - case EXCP_ATOMIC: - qemu_mutex_unlock_iothread(); - cpu_exec_step_atomic(cpu); - qemu_mutex_lock_iothread(); - default: - /* Ignore everything else? */ - break; - } - } - - qatomic_mb_set(&cpu->exit_request, 0); - qemu_wait_io_event(cpu); - } while (!cpu->unplug || cpu_can_run(cpu)); - - qemu_tcg_destroy_vcpu(cpu); - cpu_thread_signal_destroyed(cpu); - qemu_mutex_unlock_iothread(); - rcu_unregister_thread(); - return NULL; -} - -static void tcg_start_vcpu_thread(CPUState *cpu) +void tcg_start_vcpu_thread(CPUState *cpu) { char thread_name[VCPU_THREAD_NAME_SIZE]; static QemuCond *single_tcg_halt_cond; @@ -518,29 +96,36 @@ static void tcg_start_vcpu_thread(CPUState *cpu) } } =20 -static int64_t tcg_get_virtual_clock(void) +void qemu_tcg_destroy_vcpu(CPUState *cpu) { - if (icount_enabled()) { - return icount_get(); - } - return cpu_get_clock(); + cpu_thread_signal_destroyed(cpu); } =20 -static int64_t tcg_get_elapsed_ticks(void) +int tcg_cpu_exec(CPUState *cpu) { - if (icount_enabled()) { - return icount_get(); - } - return cpu_get_ticks(); + int ret; +#ifdef CONFIG_PROFILER + int64_t ti; +#endif + assert(tcg_enabled()); +#ifdef CONFIG_PROFILER + ti =3D profile_getclock(); +#endif + cpu_exec_start(cpu); + ret =3D cpu_exec(cpu); + cpu_exec_end(cpu); +#ifdef CONFIG_PROFILER + qatomic_set(&tcg_ctx->prof.cpu_exec_time, + tcg_ctx->prof.cpu_exec_time + profile_getclock() - ti); +#endif + return ret; } =20 /* mask must never be zero, except for A20 change call */ -static void tcg_handle_interrupt(CPUState *cpu, int mask) +void tcg_handle_interrupt(CPUState *cpu, int mask) { - int old_mask; g_assert(qemu_mutex_iothread_locked()); =20 - old_mask =3D cpu->interrupt_request; cpu->interrupt_request |=3D mask; =20 /* @@ -551,20 +136,5 @@ static void tcg_handle_interrupt(CPUState *cpu, int ma= sk) qemu_cpu_kick(cpu); } else { qatomic_set(&cpu_neg(cpu)->icount_decr.u16.high, -1); - if (icount_enabled() && - !cpu->can_do_io - && (mask & ~old_mask) !=3D 0) { - cpu_abort(cpu, "Raised interrupt while not in I/O function"); - } } } - -const CpusAccel tcg_cpus =3D { - .create_vcpu_thread =3D tcg_start_vcpu_thread, - .kick_vcpu_thread =3D tcg_kick_vcpu_thread, - - .handle_interrupt =3D tcg_handle_interrupt, - - .get_virtual_clock =3D tcg_get_virtual_clock, - .get_elapsed_ticks =3D tcg_get_elapsed_ticks, -}; diff --git a/softmmu/icount.c b/softmmu/icount.c index 020a201a01..dbcd8c3594 100644 --- a/softmmu/icount.c +++ b/softmmu/icount.c @@ -396,7 +396,7 @@ void icount_start_warp_timer(void) =20 void icount_account_warp_timer(void) { - if (!icount_enabled() || !icount_sleep) { + if (!icount_sleep) { return; } =20 diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 19b9343d5b..f39aab0a0c 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -12,4 +12,11 @@ tcg_ss.add(when: 'CONFIG_SOFTMMU', if_false: files('user= -exec-stub.c')) tcg_ss.add(when: 'CONFIG_PLUGIN', if_true: [files('plugin-gen.c'), libdl]) specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss) =20 -specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files('tc= g-all.c', 'cputlb.c', 'tcg-cpus.c')) +specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files( + 'tcg-all.c', + 'cputlb.c', + 'tcg-cpus.c', + 'tcg-cpus-mttcg.c', + 'tcg-cpus-icount.c', + 'tcg-cpus-rr.c' +)) --=20 2.26.2 From nobody Mon May 20 22:41:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 11 Dec 2020 00:37:00 -0800 (PST) Received: from localhost ([::1]:43530 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kndv8-0005Xe-W8 for importer@patchew.org; Fri, 11 Dec 2020 03:36:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42342) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqC-00081r-0Y for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:31:52 -0500 Received: from mx2.suse.de ([195.135.220.15]:34688) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndq8-00026I-5E for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:31:51 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id DF167B04C; Fri, 11 Dec 2020 08:31:46 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 02/25] accel/tcg: split tcg_start_vcpu_thread Date: Fri, 11 Dec 2020 09:31:20 +0100 Message-Id: <20201211083143.14350-3-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211083143.14350-1-cfontana@suse.de> References: <20201211083143.14350-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" after the initial split into 3 tcg variants, we proceed to also split tcg_start_vcpu_thread. We actually split it in 2 this time, since the icount variant just uses the round robin function. Suggested-by: Richard Henderson Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson --- accel/tcg/tcg-cpus-mttcg.h | 21 -------------- accel/tcg/tcg-cpus-rr.h | 3 +- accel/tcg/tcg-cpus.h | 1 - accel/tcg/tcg-all.c | 5 ++++ accel/tcg/tcg-cpus-icount.c | 2 +- accel/tcg/tcg-cpus-mttcg.c | 29 +++++++++++++++++-- accel/tcg/tcg-cpus-rr.c | 39 +++++++++++++++++++++++-- accel/tcg/tcg-cpus.c | 58 ------------------------------------- 8 files changed, 71 insertions(+), 87 deletions(-) delete mode 100644 accel/tcg/tcg-cpus-mttcg.h diff --git a/accel/tcg/tcg-cpus-mttcg.h b/accel/tcg/tcg-cpus-mttcg.h deleted file mode 100644 index d1bd771f49..0000000000 --- a/accel/tcg/tcg-cpus-mttcg.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * QEMU TCG Multi Threaded vCPUs implementation - * - * Copyright 2020 SUSE LLC - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - */ - -#ifndef TCG_CPUS_MTTCG_H -#define TCG_CPUS_MTTCG_H - -/* - * In the multi-threaded case each vCPU has its own thread. The TLS - * variable current_cpu can be used deep in the code to find the - * current CPUState for a given thread. - */ - -void *tcg_cpu_thread_fn(void *arg); - -#endif /* TCG_CPUS_MTTCG_H */ diff --git a/accel/tcg/tcg-cpus-rr.h b/accel/tcg/tcg-cpus-rr.h index 1936fd16ab..2e5943eda9 100644 --- a/accel/tcg/tcg-cpus-rr.h +++ b/accel/tcg/tcg-cpus-rr.h @@ -15,6 +15,7 @@ /* Kick all RR vCPUs. */ void qemu_cpu_kick_rr_cpus(CPUState *unused); =20 -void *tcg_rr_cpu_thread_fn(void *arg); +/* start the round robin vcpu thread */ +void rr_start_vcpu_thread(CPUState *cpu); =20 #endif /* TCG_CPUS_RR_H */ diff --git a/accel/tcg/tcg-cpus.h b/accel/tcg/tcg-cpus.h index 279ba72e1f..b7ca954e13 100644 --- a/accel/tcg/tcg-cpus.h +++ b/accel/tcg/tcg-cpus.h @@ -18,7 +18,6 @@ extern const CpusAccel tcg_cpus_mttcg; extern const CpusAccel tcg_cpus_icount; extern const CpusAccel tcg_cpus_rr; =20 -void tcg_start_vcpu_thread(CPUState *cpu); void qemu_tcg_destroy_vcpu(CPUState *cpu); int tcg_cpu_exec(CPUState *cpu); void tcg_handle_interrupt(CPUState *cpu, int mask); diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index e42a028043..1ac0b76515 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -105,6 +105,11 @@ static int tcg_init(MachineState *ms) tcg_exec_init(s->tb_size * 1024 * 1024); mttcg_enabled =3D s->mttcg_enabled; =20 + /* + * Initialize TCG regions + */ + tcg_region_init(); + if (mttcg_enabled) { cpus_register_accel(&tcg_cpus_mttcg); } else if (icount_enabled()) { diff --git a/accel/tcg/tcg-cpus-icount.c b/accel/tcg/tcg-cpus-icount.c index d3af3afb6d..82dbe2cacf 100644 --- a/accel/tcg/tcg-cpus-icount.c +++ b/accel/tcg/tcg-cpus-icount.c @@ -138,7 +138,7 @@ static void icount_handle_interrupt(CPUState *cpu, int = mask) } =20 const CpusAccel tcg_cpus_icount =3D { - .create_vcpu_thread =3D tcg_start_vcpu_thread, + .create_vcpu_thread =3D rr_start_vcpu_thread, .kick_vcpu_thread =3D qemu_cpu_kick_rr_cpus, =20 .handle_interrupt =3D icount_handle_interrupt, diff --git a/accel/tcg/tcg-cpus-mttcg.c b/accel/tcg/tcg-cpus-mttcg.c index dac724fc85..f2b892a380 100644 --- a/accel/tcg/tcg-cpus-mttcg.c +++ b/accel/tcg/tcg-cpus-mttcg.c @@ -33,7 +33,6 @@ #include "hw/boards.h" =20 #include "tcg-cpus.h" -#include "tcg-cpus-mttcg.h" =20 /* * In the multi-threaded case each vCPU has its own thread. The TLS @@ -41,7 +40,7 @@ * current CPUState for a given thread. */ =20 -void *tcg_cpu_thread_fn(void *arg) +static void *tcg_cpu_thread_fn(void *arg) { CPUState *cpu =3D arg; =20 @@ -109,8 +108,32 @@ static void mttcg_kick_vcpu_thread(CPUState *cpu) cpu_exit(cpu); } =20 +static void mttcg_start_vcpu_thread(CPUState *cpu) +{ + char thread_name[VCPU_THREAD_NAME_SIZE]; + + g_assert(tcg_enabled()); + + parallel_cpus =3D (current_machine->smp.max_cpus > 1); + + cpu->thread =3D g_malloc0(sizeof(QemuThread)); + cpu->halt_cond =3D g_malloc0(sizeof(QemuCond)); + qemu_cond_init(cpu->halt_cond); + + /* create a thread per vCPU with TCG (MTTCG) */ + snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "CPU %d/TCG", + cpu->cpu_index); + + qemu_thread_create(cpu->thread, thread_name, tcg_cpu_thread_fn, + cpu, QEMU_THREAD_JOINABLE); + +#ifdef _WIN32 + cpu->hThread =3D qemu_thread_get_handle(cpu->thread); +#endif +} + const CpusAccel tcg_cpus_mttcg =3D { - .create_vcpu_thread =3D tcg_start_vcpu_thread, + .create_vcpu_thread =3D mttcg_start_vcpu_thread, .kick_vcpu_thread =3D mttcg_kick_vcpu_thread, =20 .handle_interrupt =3D tcg_handle_interrupt, diff --git a/accel/tcg/tcg-cpus-rr.c b/accel/tcg/tcg-cpus-rr.c index ad50a3765f..f3b262bec7 100644 --- a/accel/tcg/tcg-cpus-rr.c +++ b/accel/tcg/tcg-cpus-rr.c @@ -144,7 +144,7 @@ static void deal_with_unplugged_cpus(void) * elsewhere. */ =20 -void *tcg_rr_cpu_thread_fn(void *arg) +static void *tcg_rr_cpu_thread_fn(void *arg) { CPUState *cpu =3D arg; =20 @@ -262,8 +262,43 @@ void *tcg_rr_cpu_thread_fn(void *arg) return NULL; } =20 +void rr_start_vcpu_thread(CPUState *cpu) +{ + char thread_name[VCPU_THREAD_NAME_SIZE]; + static QemuCond *single_tcg_halt_cond; + static QemuThread *single_tcg_cpu_thread; + + g_assert(tcg_enabled()); + parallel_cpus =3D false; + + if (!single_tcg_cpu_thread) { + cpu->thread =3D g_malloc0(sizeof(QemuThread)); + cpu->halt_cond =3D g_malloc0(sizeof(QemuCond)); + qemu_cond_init(cpu->halt_cond); + + /* share a single thread for all cpus with TCG */ + snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "ALL CPUs/TCG"); + qemu_thread_create(cpu->thread, thread_name, + tcg_rr_cpu_thread_fn, + cpu, QEMU_THREAD_JOINABLE); + + single_tcg_halt_cond =3D cpu->halt_cond; + single_tcg_cpu_thread =3D cpu->thread; +#ifdef _WIN32 + cpu->hThread =3D qemu_thread_get_handle(cpu->thread); +#endif + } else { + /* we share the thread */ + cpu->thread =3D single_tcg_cpu_thread; + cpu->halt_cond =3D single_tcg_halt_cond; + cpu->thread_id =3D first_cpu->thread_id; + cpu->can_do_io =3D 1; + cpu->created =3D true; + } +} + const CpusAccel tcg_cpus_rr =3D { - .create_vcpu_thread =3D tcg_start_vcpu_thread, + .create_vcpu_thread =3D rr_start_vcpu_thread, .kick_vcpu_thread =3D qemu_cpu_kick_rr_cpus, =20 .handle_interrupt =3D tcg_handle_interrupt, diff --git a/accel/tcg/tcg-cpus.c b/accel/tcg/tcg-cpus.c index f2b9bbf99e..86fd09545a 100644 --- a/accel/tcg/tcg-cpus.c +++ b/accel/tcg/tcg-cpus.c @@ -35,67 +35,9 @@ #include "hw/boards.h" =20 #include "tcg-cpus.h" -#include "tcg-cpus-mttcg.h" -#include "tcg-cpus-rr.h" =20 /* common functionality among all TCG variants */ =20 -void tcg_start_vcpu_thread(CPUState *cpu) -{ - char thread_name[VCPU_THREAD_NAME_SIZE]; - static QemuCond *single_tcg_halt_cond; - static QemuThread *single_tcg_cpu_thread; - static int tcg_region_inited; - - assert(tcg_enabled()); - /* - * Initialize TCG regions--once. Now is a good time, because: - * (1) TCG's init context, prologue and target globals have been set u= p. - * (2) qemu_tcg_mttcg_enabled() works now (TCG init code runs before t= he - * -accel flag is processed, so the check doesn't work then). - */ - if (!tcg_region_inited) { - tcg_region_inited =3D 1; - tcg_region_init(); - parallel_cpus =3D qemu_tcg_mttcg_enabled() && current_machine->smp= .max_cpus > 1; - } - - if (qemu_tcg_mttcg_enabled() || !single_tcg_cpu_thread) { - cpu->thread =3D g_malloc0(sizeof(QemuThread)); - cpu->halt_cond =3D g_malloc0(sizeof(QemuCond)); - qemu_cond_init(cpu->halt_cond); - - if (qemu_tcg_mttcg_enabled()) { - /* create a thread per vCPU with TCG (MTTCG) */ - snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "CPU %d/TCG", - cpu->cpu_index); - - qemu_thread_create(cpu->thread, thread_name, tcg_cpu_thread_fn, - cpu, QEMU_THREAD_JOINABLE); - - } else { - /* share a single thread for all cpus with TCG */ - snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "ALL CPUs/TCG"); - qemu_thread_create(cpu->thread, thread_name, - tcg_rr_cpu_thread_fn, - cpu, QEMU_THREAD_JOINABLE); - - single_tcg_halt_cond =3D cpu->halt_cond; - single_tcg_cpu_thread =3D cpu->thread; - } -#ifdef _WIN32 - cpu->hThread =3D qemu_thread_get_handle(cpu->thread); -#endif - } else { - /* For non-MTTCG cases we share the thread */ - cpu->thread =3D single_tcg_cpu_thread; - cpu->halt_cond =3D single_tcg_halt_cond; - cpu->thread_id =3D first_cpu->thread_id; - cpu->can_do_io =3D 1; - cpu->created =3D true; - } -} - void qemu_tcg_destroy_vcpu(CPUState *cpu) { cpu_thread_signal_destroyed(cpu); --=20 2.26.2 From nobody Mon May 20 22:41:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607675803; cv=none; d=zohomail.com; s=zohoarc; b=U+cKVqT9XXoha6flh6O3Xo1k2SGU4RXA0U/3DbM8C1oFqLA6TPKGeZjJqV/bhwONWcOhcNoaQ4HZ47VSJio+S1uWsRxlJlhN5ft4rxcdxjlLGMwp34Nc15uprKzmczMGh48/tverDPpYa7hx0ZTz+cFnUCdjWmNEX/CwDq62Njk= ARC-Message-Signature: i=1; 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Fri, 11 Dec 2020 03:36:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42408) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqH-00087x-Su for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:31:59 -0500 Received: from mx2.suse.de ([195.135.220.15]:34736) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqA-00026z-V9 for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:31:57 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 8D047B066; Fri, 11 Dec 2020 08:31:47 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 03/25] accel/tcg: rename tcg-cpus functions to match module name Date: Fri, 11 Dec 2020 09:31:21 +0100 Message-Id: <20201211083143.14350-4-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211083143.14350-1-cfontana@suse.de> References: <20201211083143.14350-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; 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Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Claudio Fontana Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- accel/tcg/tcg-cpus-icount.h | 6 +-- accel/tcg/tcg-cpus-rr.h | 2 +- accel/tcg/tcg-cpus.h | 6 +-- accel/tcg/tcg-cpus-icount.c | 24 ++++++------ accel/tcg/tcg-cpus-mttcg.c | 10 ++--- accel/tcg/tcg-cpus-rr.c | 74 ++++++++++++++++++------------------- accel/tcg/tcg-cpus.c | 6 +-- 7 files changed, 64 insertions(+), 64 deletions(-) diff --git a/accel/tcg/tcg-cpus-icount.h b/accel/tcg/tcg-cpus-icount.h index cbcf76b413..b695939dfa 100644 --- a/accel/tcg/tcg-cpus-icount.h +++ b/accel/tcg/tcg-cpus-icount.h @@ -10,8 +10,8 @@ #ifndef TCG_CPUS_ICOUNT_H #define TCG_CPUS_ICOUNT_H =20 -void handle_icount_deadline(void); -void prepare_icount_for_run(CPUState *cpu); -void process_icount_data(CPUState *cpu); +void icount_handle_deadline(void); +void icount_prepare_for_run(CPUState *cpu); +void icount_process_data(CPUState *cpu); =20 #endif /* TCG_CPUS_ICOUNT_H */ diff --git a/accel/tcg/tcg-cpus-rr.h b/accel/tcg/tcg-cpus-rr.h index 2e5943eda9..54f6ae6e86 100644 --- a/accel/tcg/tcg-cpus-rr.h +++ b/accel/tcg/tcg-cpus-rr.h @@ -13,7 +13,7 @@ #define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10) =20 /* Kick all RR vCPUs. */ -void qemu_cpu_kick_rr_cpus(CPUState *unused); +void rr_kick_vcpu_thread(CPUState *unused); =20 /* start the round robin vcpu thread */ void rr_start_vcpu_thread(CPUState *cpu); diff --git a/accel/tcg/tcg-cpus.h b/accel/tcg/tcg-cpus.h index b7ca954e13..d6893a32f8 100644 --- a/accel/tcg/tcg-cpus.h +++ b/accel/tcg/tcg-cpus.h @@ -18,8 +18,8 @@ extern const CpusAccel tcg_cpus_mttcg; extern const CpusAccel tcg_cpus_icount; extern const CpusAccel tcg_cpus_rr; =20 -void qemu_tcg_destroy_vcpu(CPUState *cpu); -int tcg_cpu_exec(CPUState *cpu); -void tcg_handle_interrupt(CPUState *cpu, int mask); +void tcg_cpus_destroy(CPUState *cpu); +int tcg_cpus_exec(CPUState *cpu); +void tcg_cpus_handle_interrupt(CPUState *cpu, int mask); =20 #endif /* TCG_CPUS_H */ diff --git a/accel/tcg/tcg-cpus-icount.c b/accel/tcg/tcg-cpus-icount.c index 82dbe2cacf..9f45432275 100644 --- a/accel/tcg/tcg-cpus-icount.c +++ b/accel/tcg/tcg-cpus-icount.c @@ -36,7 +36,7 @@ #include "tcg-cpus-icount.h" #include "tcg-cpus-rr.h" =20 -static int64_t tcg_get_icount_limit(void) +static int64_t icount_get_limit(void) { int64_t deadline; =20 @@ -68,37 +68,37 @@ static int64_t tcg_get_icount_limit(void) } } =20 -static void notify_aio_contexts(void) +static void icount_notify_aio_contexts(void) { /* Wake up other AioContexts. */ qemu_clock_notify(QEMU_CLOCK_VIRTUAL); qemu_clock_run_timers(QEMU_CLOCK_VIRTUAL); } =20 -void handle_icount_deadline(void) +void icount_handle_deadline(void) { assert(qemu_in_vcpu_thread()); int64_t deadline =3D qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL, QEMU_TIMER_ATTR_ALL); =20 if (deadline =3D=3D 0) { - notify_aio_contexts(); + icount_notify_aio_contexts(); } } =20 -void prepare_icount_for_run(CPUState *cpu) +void icount_prepare_for_run(CPUState *cpu) { int insns_left; =20 /* - * These should always be cleared by process_icount_data after + * These should always be cleared by icount_process_data after * each vCPU execution. However u16.high can be raised - * asynchronously by cpu_exit/cpu_interrupt/tcg_handle_interrupt + * asynchronously by cpu_exit/cpu_interrupt/tcg_cpus_handle_interrupt */ g_assert(cpu_neg(cpu)->icount_decr.u16.low =3D=3D 0); g_assert(cpu->icount_extra =3D=3D 0); =20 - cpu->icount_budget =3D tcg_get_icount_limit(); + cpu->icount_budget =3D icount_get_limit(); insns_left =3D MIN(0xffff, cpu->icount_budget); cpu_neg(cpu)->icount_decr.u16.low =3D insns_left; cpu->icount_extra =3D cpu->icount_budget - insns_left; @@ -106,11 +106,11 @@ void prepare_icount_for_run(CPUState *cpu) replay_mutex_lock(); =20 if (cpu->icount_budget =3D=3D 0 && replay_has_checkpoint()) { - notify_aio_contexts(); + icount_notify_aio_contexts(); } } =20 -void process_icount_data(CPUState *cpu) +void icount_process_data(CPUState *cpu) { /* Account for executed instructions */ icount_update(cpu); @@ -129,7 +129,7 @@ static void icount_handle_interrupt(CPUState *cpu, int = mask) { int old_mask =3D cpu->interrupt_request; =20 - tcg_handle_interrupt(cpu, mask); + tcg_cpus_handle_interrupt(cpu, mask); if (qemu_cpu_is_self(cpu) && !cpu->can_do_io && (mask & ~old_mask) !=3D 0) { @@ -139,7 +139,7 @@ static void icount_handle_interrupt(CPUState *cpu, int = mask) =20 const CpusAccel tcg_cpus_icount =3D { .create_vcpu_thread =3D rr_start_vcpu_thread, - .kick_vcpu_thread =3D qemu_cpu_kick_rr_cpus, + .kick_vcpu_thread =3D rr_kick_vcpu_thread, =20 .handle_interrupt =3D icount_handle_interrupt, .get_virtual_clock =3D icount_get, diff --git a/accel/tcg/tcg-cpus-mttcg.c b/accel/tcg/tcg-cpus-mttcg.c index f2b892a380..9c3767d260 100644 --- a/accel/tcg/tcg-cpus-mttcg.c +++ b/accel/tcg/tcg-cpus-mttcg.c @@ -40,7 +40,7 @@ * current CPUState for a given thread. */ =20 -static void *tcg_cpu_thread_fn(void *arg) +static void *mttcg_cpu_thread_fn(void *arg) { CPUState *cpu =3D arg; =20 @@ -66,7 +66,7 @@ static void *tcg_cpu_thread_fn(void *arg) if (cpu_can_run(cpu)) { int r; qemu_mutex_unlock_iothread(); - r =3D tcg_cpu_exec(cpu); + r =3D tcg_cpus_exec(cpu); qemu_mutex_lock_iothread(); switch (r) { case EXCP_DEBUG: @@ -97,7 +97,7 @@ static void *tcg_cpu_thread_fn(void *arg) qemu_wait_io_event(cpu); } while (!cpu->unplug || cpu_can_run(cpu)); =20 - qemu_tcg_destroy_vcpu(cpu); + tcg_cpus_destroy(cpu); qemu_mutex_unlock_iothread(); rcu_unregister_thread(); return NULL; @@ -124,7 +124,7 @@ static void mttcg_start_vcpu_thread(CPUState *cpu) snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "CPU %d/TCG", cpu->cpu_index); =20 - qemu_thread_create(cpu->thread, thread_name, tcg_cpu_thread_fn, + qemu_thread_create(cpu->thread, thread_name, mttcg_cpu_thread_fn, cpu, QEMU_THREAD_JOINABLE); =20 #ifdef _WIN32 @@ -136,5 +136,5 @@ const CpusAccel tcg_cpus_mttcg =3D { .create_vcpu_thread =3D mttcg_start_vcpu_thread, .kick_vcpu_thread =3D mttcg_kick_vcpu_thread, =20 - .handle_interrupt =3D tcg_handle_interrupt, + .handle_interrupt =3D tcg_cpus_handle_interrupt, }; diff --git a/accel/tcg/tcg-cpus-rr.c b/accel/tcg/tcg-cpus-rr.c index f3b262bec7..0181d2e4eb 100644 --- a/accel/tcg/tcg-cpus-rr.c +++ b/accel/tcg/tcg-cpus-rr.c @@ -37,7 +37,7 @@ #include "tcg-cpus-icount.h" =20 /* Kick all RR vCPUs */ -void qemu_cpu_kick_rr_cpus(CPUState *unused) +void rr_kick_vcpu_thread(CPUState *unused) { CPUState *cpu; =20 @@ -58,62 +58,62 @@ void qemu_cpu_kick_rr_cpus(CPUState *unused) * idleness is complete. */ =20 -static QEMUTimer *tcg_kick_vcpu_timer; -static CPUState *tcg_current_rr_cpu; +static QEMUTimer *rr_kick_vcpu_timer; +static CPUState *rr_current_cpu; =20 #define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10) =20 -static inline int64_t qemu_tcg_next_kick(void) +static inline int64_t rr_next_kick_time(void) { return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + TCG_KICK_PERIOD; } =20 /* Kick the currently round-robin scheduled vCPU to next */ -static void qemu_cpu_kick_rr_next_cpu(void) +static void rr_kick_next_cpu(void) { CPUState *cpu; do { - cpu =3D qatomic_mb_read(&tcg_current_rr_cpu); + cpu =3D qatomic_mb_read(&rr_current_cpu); if (cpu) { cpu_exit(cpu); } - } while (cpu !=3D qatomic_mb_read(&tcg_current_rr_cpu)); + } while (cpu !=3D qatomic_mb_read(&rr_current_cpu)); } =20 -static void kick_tcg_thread(void *opaque) +static void rr_kick_thread(void *opaque) { - timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick()); - qemu_cpu_kick_rr_next_cpu(); + timer_mod(rr_kick_vcpu_timer, rr_next_kick_time()); + rr_kick_next_cpu(); } =20 -static void start_tcg_kick_timer(void) +static void rr_start_kick_timer(void) { - if (!tcg_kick_vcpu_timer && CPU_NEXT(first_cpu)) { - tcg_kick_vcpu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, - kick_tcg_thread, NULL); + if (!rr_kick_vcpu_timer && CPU_NEXT(first_cpu)) { + rr_kick_vcpu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + rr_kick_thread, NULL); } - if (tcg_kick_vcpu_timer && !timer_pending(tcg_kick_vcpu_timer)) { - timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick()); + if (rr_kick_vcpu_timer && !timer_pending(rr_kick_vcpu_timer)) { + timer_mod(rr_kick_vcpu_timer, rr_next_kick_time()); } } =20 -static void stop_tcg_kick_timer(void) +static void rr_stop_kick_timer(void) { - if (tcg_kick_vcpu_timer && timer_pending(tcg_kick_vcpu_timer)) { - timer_del(tcg_kick_vcpu_timer); + if (rr_kick_vcpu_timer && timer_pending(rr_kick_vcpu_timer)) { + timer_del(rr_kick_vcpu_timer); } } =20 -static void qemu_tcg_rr_wait_io_event(void) +static void rr_wait_io_event(void) { CPUState *cpu; =20 while (all_cpu_threads_idle()) { - stop_tcg_kick_timer(); + rr_stop_kick_timer(); qemu_cond_wait_iothread(first_cpu->halt_cond); } =20 - start_tcg_kick_timer(); + rr_start_kick_timer(); =20 CPU_FOREACH(cpu) { qemu_wait_io_event_common(cpu); @@ -124,13 +124,13 @@ static void qemu_tcg_rr_wait_io_event(void) * Destroy any remaining vCPUs which have been unplugged and have * finished running */ -static void deal_with_unplugged_cpus(void) +static void rr_deal_with_unplugged_cpus(void) { CPUState *cpu; =20 CPU_FOREACH(cpu) { if (cpu->unplug && !cpu_can_run(cpu)) { - qemu_tcg_destroy_vcpu(cpu); + tcg_cpus_destroy(cpu); break; } } @@ -144,7 +144,7 @@ static void deal_with_unplugged_cpus(void) * elsewhere. */ =20 -static void *tcg_rr_cpu_thread_fn(void *arg) +static void *rr_cpu_thread_fn(void *arg) { CPUState *cpu =3D arg; =20 @@ -171,7 +171,7 @@ static void *tcg_rr_cpu_thread_fn(void *arg) } } =20 - start_tcg_kick_timer(); + rr_start_kick_timer(); =20 cpu =3D first_cpu; =20 @@ -190,7 +190,7 @@ static void *tcg_rr_cpu_thread_fn(void *arg) * Run the timers here. This is much more efficient than * waking up the I/O thread and waiting for completion. */ - handle_icount_deadline(); + icount_handle_deadline(); } =20 replay_mutex_unlock(); @@ -201,7 +201,7 @@ static void *tcg_rr_cpu_thread_fn(void *arg) =20 while (cpu && cpu_work_list_empty(cpu) && !cpu->exit_request) { =20 - qatomic_mb_set(&tcg_current_rr_cpu, cpu); + qatomic_mb_set(&rr_current_cpu, cpu); current_cpu =3D cpu; =20 qemu_clock_enable(QEMU_CLOCK_VIRTUAL, @@ -212,11 +212,11 @@ static void *tcg_rr_cpu_thread_fn(void *arg) =20 qemu_mutex_unlock_iothread(); if (icount_enabled()) { - prepare_icount_for_run(cpu); + icount_prepare_for_run(cpu); } - r =3D tcg_cpu_exec(cpu); + r =3D tcg_cpus_exec(cpu); if (icount_enabled()) { - process_icount_data(cpu); + icount_process_data(cpu); } qemu_mutex_lock_iothread(); =20 @@ -240,7 +240,7 @@ static void *tcg_rr_cpu_thread_fn(void *arg) } /* while (cpu && !cpu->exit_request).. */ =20 /* Does not need qatomic_mb_set because a spurious wakeup is okay.= */ - qatomic_set(&tcg_current_rr_cpu, NULL); + qatomic_set(&rr_current_cpu, NULL); =20 if (cpu && cpu->exit_request) { qatomic_mb_set(&cpu->exit_request, 0); @@ -254,8 +254,8 @@ static void *tcg_rr_cpu_thread_fn(void *arg) qemu_notify_event(); } =20 - qemu_tcg_rr_wait_io_event(); - deal_with_unplugged_cpus(); + rr_wait_io_event(); + rr_deal_with_unplugged_cpus(); } =20 rcu_unregister_thread(); @@ -279,7 +279,7 @@ void rr_start_vcpu_thread(CPUState *cpu) /* share a single thread for all cpus with TCG */ snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "ALL CPUs/TCG"); qemu_thread_create(cpu->thread, thread_name, - tcg_rr_cpu_thread_fn, + rr_cpu_thread_fn, cpu, QEMU_THREAD_JOINABLE); =20 single_tcg_halt_cond =3D cpu->halt_cond; @@ -299,7 +299,7 @@ void rr_start_vcpu_thread(CPUState *cpu) =20 const CpusAccel tcg_cpus_rr =3D { .create_vcpu_thread =3D rr_start_vcpu_thread, - .kick_vcpu_thread =3D qemu_cpu_kick_rr_cpus, + .kick_vcpu_thread =3D rr_kick_vcpu_thread, =20 - .handle_interrupt =3D tcg_handle_interrupt, + .handle_interrupt =3D tcg_cpus_handle_interrupt, }; diff --git a/accel/tcg/tcg-cpus.c b/accel/tcg/tcg-cpus.c index 86fd09545a..e335f9f155 100644 --- a/accel/tcg/tcg-cpus.c +++ b/accel/tcg/tcg-cpus.c @@ -38,12 +38,12 @@ =20 /* common functionality among all TCG variants */ =20 -void qemu_tcg_destroy_vcpu(CPUState *cpu) +void tcg_cpus_destroy(CPUState *cpu) { cpu_thread_signal_destroyed(cpu); } =20 -int tcg_cpu_exec(CPUState *cpu) +int tcg_cpus_exec(CPUState *cpu) { int ret; #ifdef CONFIG_PROFILER @@ -64,7 +64,7 @@ int tcg_cpu_exec(CPUState *cpu) } =20 /* mask must never be zero, except for A20 change call */ -void tcg_handle_interrupt(CPUState *cpu, int mask) +void tcg_cpus_handle_interrupt(CPUState *cpu, int mask) { g_assert(qemu_mutex_iothread_locked()); =20 --=20 2.26.2 From nobody Mon May 20 22:41:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Fri, 11 Dec 2020 00:33:49 -0800 (PST) Received: from localhost ([::1]:33904 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kndrw-0001Pq-D0 for importer@patchew.org; Fri, 11 Dec 2020 03:33:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42346) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqC-000827-AL for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:31:52 -0500 Received: from mx2.suse.de ([195.135.220.15]:34754) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndq9-000273-HO for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:31:52 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 46C37B05C; Fri, 11 Dec 2020 08:31:48 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 04/25] i386: move kvm accel files into kvm/ Date: Fri, 11 Dec 2020 09:31:22 +0100 Message-Id: <20201211083143.14350-5-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211083143.14350-1-cfontana@suse.de> References: <20201211083143.14350-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- meson.build | 1 + target/i386/cpu.h | 2 +- target/i386/{ =3D> kvm}/hyperv-proto.h | 0 target/i386/{ =3D> kvm}/hyperv.h | 0 target/i386/{ =3D> kvm}/kvm_i386.h | 0 target/i386/kvm/trace.h | 1 + hw/i386/fw_cfg.c | 2 +- hw/i386/intel_iommu.c | 2 +- hw/i386/kvm/apic.c | 2 +- hw/i386/kvm/clock.c | 2 +- hw/i386/microvm.c | 2 +- hw/i386/pc.c | 2 +- hw/i386/x86.c | 2 +- target/i386/cpu.c | 2 +- target/i386/helper.c | 2 +- target/i386/{ =3D> kvm}/hyperv-stub.c | 0 target/i386/{ =3D> kvm}/hyperv.c | 0 target/i386/{ =3D> kvm}/kvm-stub.c | 0 target/i386/{ =3D> kvm}/kvm.c | 0 target/i386/machine.c | 4 ++-- MAINTAINERS | 2 +- target/i386/kvm/meson.build | 3 +++ target/i386/kvm/trace-events | 7 +++++++ target/i386/meson.build | 4 +--- target/i386/trace-events | 6 ------ 25 files changed, 26 insertions(+), 22 deletions(-) rename target/i386/{ =3D> kvm}/hyperv-proto.h (100%) rename target/i386/{ =3D> kvm}/hyperv.h (100%) rename target/i386/{ =3D> kvm}/kvm_i386.h (100%) create mode 100644 target/i386/kvm/trace.h rename target/i386/{ =3D> kvm}/hyperv-stub.c (100%) rename target/i386/{ =3D> kvm}/hyperv.c (100%) rename target/i386/{ =3D> kvm}/kvm-stub.c (100%) rename target/i386/{ =3D> kvm}/kvm.c (100%) create mode 100644 target/i386/kvm/meson.build create mode 100644 target/i386/kvm/trace-events diff --git a/meson.build b/meson.build index 732b29a1f3..d3f4aeeb32 100644 --- a/meson.build +++ b/meson.build @@ -1467,6 +1467,7 @@ trace_events_subdirs +=3D [ 'target/arm', 'target/hppa', 'target/i386', + 'target/i386/kvm', 'target/mips', 'target/ppc', 'target/riscv', diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 88e8586f8f..9ecda75aec 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -22,7 +22,7 @@ =20 #include "sysemu/tcg.h" #include "cpu-qom.h" -#include "hyperv-proto.h" +#include "kvm/hyperv-proto.h" #include "exec/cpu-defs.h" #include "qapi/qapi-types-common.h" =20 diff --git a/target/i386/hyperv-proto.h b/target/i386/kvm/hyperv-proto.h similarity index 100% rename from target/i386/hyperv-proto.h rename to target/i386/kvm/hyperv-proto.h diff --git a/target/i386/hyperv.h b/target/i386/kvm/hyperv.h similarity index 100% rename from target/i386/hyperv.h rename to target/i386/kvm/hyperv.h diff --git a/target/i386/kvm_i386.h b/target/i386/kvm/kvm_i386.h similarity index 100% rename from target/i386/kvm_i386.h rename to target/i386/kvm/kvm_i386.h diff --git a/target/i386/kvm/trace.h b/target/i386/kvm/trace.h new file mode 100644 index 0000000000..46b75c6942 --- /dev/null +++ b/target/i386/kvm/trace.h @@ -0,0 +1 @@ +#include "trace/trace-target_i386_kvm.h" diff --git a/hw/i386/fw_cfg.c b/hw/i386/fw_cfg.c index e06579490c..fae1bb380f 100644 --- a/hw/i386/fw_cfg.c +++ b/hw/i386/fw_cfg.c @@ -21,7 +21,7 @@ #include "hw/timer/hpet.h" #include "hw/nvram/fw_cfg.h" #include "e820_memory_layout.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include CONFIG_DEVICES =20 struct hpet_fw_config hpet_cfg =3D {.count =3D UINT8_MAX}; diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 0cc71e4057..b4f5094259 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -37,7 +37,7 @@ #include "sysemu/kvm.h" #include "sysemu/sysemu.h" #include "hw/i386/apic_internal.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include "migration/vmstate.h" #include "trace.h" =20 diff --git a/hw/i386/kvm/apic.c b/hw/i386/kvm/apic.c index dd29906061..07bebc1282 100644 --- a/hw/i386/kvm/apic.c +++ b/hw/i386/kvm/apic.c @@ -17,7 +17,7 @@ #include "hw/pci/msi.h" #include "sysemu/hw_accel.h" #include "sysemu/kvm.h" -#include "target/i386/kvm_i386.h" +#include "kvm/kvm_i386.h" =20 static inline void kvm_apic_set_reg(struct kvm_lapic_state *kapic, int reg_id, uint32_t val) diff --git a/hw/i386/kvm/clock.c b/hw/i386/kvm/clock.c index 24fe5091b6..2d8a366369 100644 --- a/hw/i386/kvm/clock.c +++ b/hw/i386/kvm/clock.c @@ -20,7 +20,7 @@ #include "sysemu/kvm.h" #include "sysemu/runstate.h" #include "sysemu/hw_accel.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include "migration/vmstate.h" #include "hw/sysbus.h" #include "hw/kvm/clock.h" diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index 5428448b70..3ed6adff83 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -51,7 +51,7 @@ =20 #include "cpu.h" #include "elf.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include "hw/xen/start_info.h" =20 #define MICROVM_QBOOT_FILENAME "qboot.rom" diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 9e29f3792b..e562f5e190 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -61,7 +61,7 @@ #include "sysemu/qtest.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include "hw/xen/xen.h" #include "hw/xen/start_info.h" #include "ui/qemu-spice.h" diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 5944fc44ed..88d0c70e12 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -52,7 +52,7 @@ #include "elf.h" #include "standard-headers/asm-x86/bootparam.h" #include CONFIG_DEVICES -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" =20 #define BIOS_FILENAME "bios.bin" =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5a8c96072e..b9bd249c8f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -30,7 +30,7 @@ #include "sysemu/hvf.h" #include "sysemu/cpus.h" #include "sysemu/xen.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include "sev_i386.h" =20 #include "qemu/error-report.h" diff --git a/target/i386/helper.c b/target/i386/helper.c index 034f46bcc2..a1b3367ab2 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -24,7 +24,7 @@ #include "qemu/qemu-print.h" #include "sysemu/kvm.h" #include "sysemu/runstate.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #ifndef CONFIG_USER_ONLY #include "sysemu/tcg.h" #include "sysemu/hw_accel.h" diff --git a/target/i386/hyperv-stub.c b/target/i386/kvm/hyperv-stub.c similarity index 100% rename from target/i386/hyperv-stub.c rename to target/i386/kvm/hyperv-stub.c diff --git a/target/i386/hyperv.c b/target/i386/kvm/hyperv.c similarity index 100% rename from target/i386/hyperv.c rename to target/i386/kvm/hyperv.c diff --git a/target/i386/kvm-stub.c b/target/i386/kvm/kvm-stub.c similarity index 100% rename from target/i386/kvm-stub.c rename to target/i386/kvm/kvm-stub.c diff --git a/target/i386/kvm.c b/target/i386/kvm/kvm.c similarity index 100% rename from target/i386/kvm.c rename to target/i386/kvm/kvm.c diff --git a/target/i386/machine.c b/target/i386/machine.c index 233e46bb70..1614e8c2f8 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -3,9 +3,9 @@ #include "exec/exec-all.h" #include "hw/isa/isa.h" #include "migration/cpu.h" -#include "hyperv.h" +#include "kvm/hyperv.h" #include "hw/i386/x86.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" =20 #include "sysemu/kvm.h" #include "sysemu/tcg.h" diff --git a/MAINTAINERS b/MAINTAINERS index 68bc160f41..5b3eced829 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -425,7 +425,7 @@ M: Paolo Bonzini M: Marcelo Tosatti L: kvm@vger.kernel.org S: Supported -F: target/i386/kvm.c +F: target/i386/kvm/ F: scripts/kvm/vmxcap =20 Guest CPU Cores (other accelerators) diff --git a/target/i386/kvm/meson.build b/target/i386/kvm/meson.build new file mode 100644 index 0000000000..1d66559187 --- /dev/null +++ b/target/i386/kvm/meson.build @@ -0,0 +1,3 @@ +i386_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) +i386_softmmu_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) +i386_softmmu_ss.add(when: 'CONFIG_HYPERV', if_true: files('hyperv.c'), if_= false: files('hyperv-stub.c')) diff --git a/target/i386/kvm/trace-events b/target/i386/kvm/trace-events new file mode 100644 index 0000000000..b4e2d9e4ea --- /dev/null +++ b/target/i386/kvm/trace-events @@ -0,0 +1,7 @@ +# See docs/devel/tracing.txt for syntax documentation. + +# kvm.c +kvm_x86_fixup_msi_error(uint32_t gsi) "VT-d failed to remap interrupt for = GSI %" PRIu32 +kvm_x86_add_msi_route(int virq) "Adding route entry for virq %d" +kvm_x86_remove_msi_route(int virq) "Removing route entry for virq %d" +kvm_x86_update_msi_routes(int num) "Updated %d MSI routes" diff --git a/target/i386/meson.build b/target/i386/meson.build index a1a02f3e99..0209542a8a 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -18,7 +18,6 @@ i386_ss.add(when: 'CONFIG_TCG', if_true: files( 'smm_helper.c', 'svm_helper.c', 'translate.c'), if_false: files('tcg-stub.c')) -i386_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('= sev-stub.c')) =20 i386_softmmu_ss =3D ss.source_set() @@ -28,8 +27,6 @@ i386_softmmu_ss.add(files( 'machine.c', 'monitor.c', )) -i386_softmmu_ss.add(when: 'CONFIG_HYPERV', if_true: files('hyperv.c'), if_= false: files('hyperv-stub.c')) -i386_softmmu_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) i386_softmmu_ss.add(when: 'CONFIG_WHPX', if_true: files( 'whpx-all.c', 'whpx-cpus.c', @@ -42,6 +39,7 @@ i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files( i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('= hax-posix.c')) i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('= hax-windows.c')) =20 +subdir('kvm') subdir('hvf') =20 target_arch +=3D {'i386': i386_ss} diff --git a/target/i386/trace-events b/target/i386/trace-events index 789c700d4a..d166f9d5e0 100644 --- a/target/i386/trace-events +++ b/target/i386/trace-events @@ -1,11 +1,5 @@ # See docs/devel/tracing.txt for syntax documentation. =20 -# kvm.c -kvm_x86_fixup_msi_error(uint32_t gsi) "VT-d failed to remap interrupt for = GSI %" PRIu32 -kvm_x86_add_msi_route(int virq) "Adding route entry for virq %d" -kvm_x86_remove_msi_route(int virq) "Removing route entry for virq %d" -kvm_x86_update_msi_routes(int num) "Updated %d MSI routes" - # sev.c kvm_sev_init(void) "" kvm_memcrypt_register_region(void *addr, size_t len) "addr %p len 0x%zu" --=20 2.26.2 From nobody Mon May 20 22:41:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607675981; cv=none; d=zohomail.com; s=zohoarc; b=Ns5HGT9NwQXKQNNA9nKkxNgLiUtLr3Wg/C6hjk24lA9OgP4oJ0y1+Yb7GuewXJeUxWgx9R2KoCkkohHoenMFKkmW40O8wdEbnz1c1cb2VJQ/vINBhHN9urgCNkL51K6TVBjVrW2LPc6xf6JoJzW17wsxBLua1Lbu2l42a25B20c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607675981; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:31:55 -0500 Received: from mx2.suse.de ([195.135.220.15]:34888) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqC-000283-8h for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:31:54 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 03FDCB113; Fri, 11 Dec 2020 08:31:49 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 05/25] i386: move whpx accel files into whpx/ Date: Fri, 11 Dec 2020 09:31:23 +0100 Message-Id: <20201211083143.14350-6-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211083143.14350-1-cfontana@suse.de> References: <20201211083143.14350-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/i386/{ =3D> whpx}/whp-dispatch.h | 0 target/i386/{ =3D> whpx}/whpx-cpus.h | 0 target/i386/{ =3D> whpx}/whpx-all.c | 0 target/i386/{ =3D> whpx}/whpx-cpus.c | 0 MAINTAINERS | 5 +---- target/i386/meson.build | 5 +---- target/i386/whpx/meson.build | 4 ++++ 7 files changed, 6 insertions(+), 8 deletions(-) rename target/i386/{ =3D> whpx}/whp-dispatch.h (100%) rename target/i386/{ =3D> whpx}/whpx-cpus.h (100%) rename target/i386/{ =3D> whpx}/whpx-all.c (100%) rename target/i386/{ =3D> whpx}/whpx-cpus.c (100%) create mode 100644 target/i386/whpx/meson.build diff --git a/target/i386/whp-dispatch.h b/target/i386/whpx/whp-dispatch.h similarity index 100% rename from target/i386/whp-dispatch.h rename to target/i386/whpx/whp-dispatch.h diff --git a/target/i386/whpx-cpus.h b/target/i386/whpx/whpx-cpus.h similarity index 100% rename from target/i386/whpx-cpus.h rename to target/i386/whpx/whpx-cpus.h diff --git a/target/i386/whpx-all.c b/target/i386/whpx/whpx-all.c similarity index 100% rename from target/i386/whpx-all.c rename to target/i386/whpx/whpx-all.c diff --git a/target/i386/whpx-cpus.c b/target/i386/whpx/whpx-cpus.c similarity index 100% rename from target/i386/whpx-cpus.c rename to target/i386/whpx/whpx-cpus.c diff --git a/MAINTAINERS b/MAINTAINERS index 5b3eced829..20e079f40c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -451,10 +451,7 @@ F: include/sysemu/hvf.h WHPX CPUs M: Sunil Muthuswamy S: Supported -F: target/i386/whpx-all.c -F: target/i386/whpx-cpus.c -F: target/i386/whp-dispatch.h -F: accel/stubs/whpx-stub.c +F: target/i386/whpx/ F: include/sysemu/whpx.h =20 Guest CPU Cores (Xen) diff --git a/target/i386/meson.build b/target/i386/meson.build index 0209542a8a..62cd042915 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -27,10 +27,6 @@ i386_softmmu_ss.add(files( 'machine.c', 'monitor.c', )) -i386_softmmu_ss.add(when: 'CONFIG_WHPX', if_true: files( - 'whpx-all.c', - 'whpx-cpus.c', -)) i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files( 'hax-all.c', 'hax-mem.c', @@ -40,6 +36,7 @@ i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'],= if_true: files('hax-po i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('= hax-windows.c')) =20 subdir('kvm') +subdir('whpx') subdir('hvf') =20 target_arch +=3D {'i386': i386_ss} diff --git a/target/i386/whpx/meson.build b/target/i386/whpx/meson.build new file mode 100644 index 0000000000..94a72c8efc --- /dev/null +++ b/target/i386/whpx/meson.build @@ -0,0 +1,4 @@ +i386_softmmu_ss.add(when: 'CONFIG_WHPX', if_true: files( + 'whpx-all.c', + 'whpx-cpus.c', +)) --=20 2.26.2 From nobody Mon May 20 22:41:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 11 Dec 2020 00:42:28 -0800 (PST) Received: from localhost ([::1]:59752 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kne0Q-00046e-RO for importer@patchew.org; Fri, 11 Dec 2020 03:42:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42398) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqF-00087B-RS for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:31:55 -0500 Received: from mx2.suse.de ([195.135.220.15]:34890) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqC-000285-8n for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:31:55 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id B6733B13A; Fri, 11 Dec 2020 08:31:49 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 06/25] i386: move hax accel files into hax/ Date: Fri, 11 Dec 2020 09:31:24 +0100 Message-Id: <20201211083143.14350-7-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211083143.14350-1-cfontana@suse.de> References: <20201211083143.14350-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/i386/{ =3D> hax}/hax-cpus.h | 0 target/i386/{ =3D> hax}/hax-i386.h | 6 +++--- target/i386/{ =3D> hax}/hax-interface.h | 0 target/i386/{ =3D> hax}/hax-posix.h | 0 target/i386/{ =3D> hax}/hax-windows.h | 0 target/i386/{ =3D> hax}/hax-all.c | 0 target/i386/{ =3D> hax}/hax-cpus.c | 0 target/i386/{ =3D> hax}/hax-mem.c | 0 target/i386/{ =3D> hax}/hax-posix.c | 0 target/i386/{ =3D> hax}/hax-windows.c | 0 MAINTAINERS | 2 +- target/i386/hax/meson.build | 7 +++++++ target/i386/meson.build | 8 +------- 13 files changed, 12 insertions(+), 11 deletions(-) rename target/i386/{ =3D> hax}/hax-cpus.h (100%) rename target/i386/{ =3D> hax}/hax-i386.h (95%) rename target/i386/{ =3D> hax}/hax-interface.h (100%) rename target/i386/{ =3D> hax}/hax-posix.h (100%) rename target/i386/{ =3D> hax}/hax-windows.h (100%) rename target/i386/{ =3D> hax}/hax-all.c (100%) rename target/i386/{ =3D> hax}/hax-cpus.c (100%) rename target/i386/{ =3D> hax}/hax-mem.c (100%) rename target/i386/{ =3D> hax}/hax-posix.c (100%) rename target/i386/{ =3D> hax}/hax-windows.c (100%) create mode 100644 target/i386/hax/meson.build diff --git a/target/i386/hax-cpus.h b/target/i386/hax/hax-cpus.h similarity index 100% rename from target/i386/hax-cpus.h rename to target/i386/hax/hax-cpus.h diff --git a/target/i386/hax-i386.h b/target/i386/hax/hax-i386.h similarity index 95% rename from target/i386/hax-i386.h rename to target/i386/hax/hax-i386.h index 48c4abe14e..efbb346238 100644 --- a/target/i386/hax-i386.h +++ b/target/i386/hax/hax-i386.h @@ -84,13 +84,13 @@ void hax_memory_init(void); =20 =20 #ifdef CONFIG_POSIX -#include "target/i386/hax-posix.h" +#include "hax-posix.h" #endif =20 #ifdef CONFIG_WIN32 -#include "target/i386/hax-windows.h" +#include "hax-windows.h" #endif =20 -#include "target/i386/hax-interface.h" +#include "hax-interface.h" =20 #endif diff --git a/target/i386/hax-interface.h b/target/i386/hax/hax-interface.h similarity index 100% rename from target/i386/hax-interface.h rename to target/i386/hax/hax-interface.h diff --git a/target/i386/hax-posix.h b/target/i386/hax/hax-posix.h similarity index 100% rename from target/i386/hax-posix.h rename to target/i386/hax/hax-posix.h diff --git a/target/i386/hax-windows.h b/target/i386/hax/hax-windows.h similarity index 100% rename from target/i386/hax-windows.h rename to target/i386/hax/hax-windows.h diff --git a/target/i386/hax-all.c b/target/i386/hax/hax-all.c similarity index 100% rename from target/i386/hax-all.c rename to target/i386/hax/hax-all.c diff --git a/target/i386/hax-cpus.c b/target/i386/hax/hax-cpus.c similarity index 100% rename from target/i386/hax-cpus.c rename to target/i386/hax/hax-cpus.c diff --git a/target/i386/hax-mem.c b/target/i386/hax/hax-mem.c similarity index 100% rename from target/i386/hax-mem.c rename to target/i386/hax/hax-mem.c diff --git a/target/i386/hax-posix.c b/target/i386/hax/hax-posix.c similarity index 100% rename from target/i386/hax-posix.c rename to target/i386/hax/hax-posix.c diff --git a/target/i386/hax-windows.c b/target/i386/hax/hax-windows.c similarity index 100% rename from target/i386/hax-windows.c rename to target/i386/hax/hax-windows.c diff --git a/MAINTAINERS b/MAINTAINERS index 20e079f40c..448593c904 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -491,7 +491,7 @@ W: https://github.com/intel/haxm/issues S: Maintained F: accel/stubs/hax-stub.c F: include/sysemu/hax.h -F: target/i386/hax-* +F: target/i386/hax/ =20 Hosts ----- diff --git a/target/i386/hax/meson.build b/target/i386/hax/meson.build new file mode 100644 index 0000000000..77ea431b30 --- /dev/null +++ b/target/i386/hax/meson.build @@ -0,0 +1,7 @@ +i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files( + 'hax-all.c', + 'hax-mem.c', + 'hax-cpus.c', +)) +i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('= hax-posix.c')) +i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('= hax-windows.c')) diff --git a/target/i386/meson.build b/target/i386/meson.build index 62cd042915..284d52ab81 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -27,15 +27,9 @@ i386_softmmu_ss.add(files( 'machine.c', 'monitor.c', )) -i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files( - 'hax-all.c', - 'hax-mem.c', - 'hax-cpus.c', -)) -i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('= hax-posix.c')) -i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('= hax-windows.c')) =20 subdir('kvm') +subdir('hax') subdir('whpx') subdir('hvf') =20 --=20 2.26.2 From nobody Mon May 20 22:41:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 11 Dec 2020 00:39:03 -0800 (PST) Received: from localhost ([::1]:50630 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kndx8-00005a-JP for importer@patchew.org; Fri, 11 Dec 2020 03:39:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42410) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqJ-00088z-Ih for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:31:59 -0500 Received: from mx2.suse.de ([195.135.220.15]:34894) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqC-00028A-Cj for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:31:59 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 6BBEEB13D; Fri, 11 Dec 2020 08:31:50 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 07/25] i386: hvf: remove stale MAINTAINERS entry for old hvf stubs Date: Fri, 11 Dec 2020 09:31:25 +0100 Message-Id: <20201211083143.14350-8-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211083143.14350-1-cfontana@suse.de> References: <20201211083143.14350-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; 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Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Claudio Fontana Reviewed-by: Roman Bolshakov Reviewed-by: Alex Benn=C3=A9e --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 448593c904..f53f2678d8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -444,7 +444,6 @@ M: Cameron Esfahani M: Roman Bolshakov W: https://wiki.qemu.org/Features/HVF S: Maintained -F: accel/stubs/hvf-stub.c F: target/i386/hvf/ F: include/sysemu/hvf.h =20 --=20 2.26.2 From nobody Mon May 20 22:41:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607675680; cv=none; d=zohomail.com; s=zohoarc; b=GZrhGcEGYaEbWFcgla/5F4/+Vw38XD8R6C9hl5H8otunMveQsFDP5PGX3kVOSYra/eMXAs2/qZNDQYduJkNezZkEcuviPBhobxr818PS6Lcgy1fb7YNUqtq2Xgf+muO0Pds/HTogOeuKHw3UGP+YZYOPz6hW7Ps528qfvy9IFGQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607675680; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2SzwDrTszu7JxM9GP+uEaQ22m9Wgvz4VCHDyCkqGo/I=; b=TEJfVjJPb1dPRrEgCn/zPbrTr/65e+8ozgf/4/B6k21p6byCuopALB999WCpyu0qu4zcD5EzGUtHGiQW1Uv8HpGbJh1QP6MDSvrjzKy4vt6VNA/ZAHVMA93IOkV87r13NVE/Zv+qFZz9t20dRpaJtSAxS4XNJgMPrrUh3IgBDZY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607675680949382.1080758319848; Fri, 11 Dec 2020 00:34:40 -0800 (PST) Received: from localhost ([::1]:36852 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kndst-0002fx-RA for importer@patchew.org; Fri, 11 Dec 2020 03:34:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42412) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqL-00089N-1c for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:32:01 -0500 Received: from mx2.suse.de ([195.135.220.15]:34898) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqC-00028C-FK for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:32:00 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 27D90B16A; Fri, 11 Dec 2020 08:31:51 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 08/25] i386: move TCG accel files into tcg/ Date: Fri, 11 Dec 2020 09:31:26 +0100 Message-Id: <20201211083143.14350-9-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211083143.14350-1-cfontana@suse.de> References: <20201211083143.14350-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/i386/{ =3D> tcg}/bpt_helper.c | 0 target/i386/{ =3D> tcg}/cc_helper.c | 0 target/i386/{ =3D> tcg}/excp_helper.c | 0 target/i386/{ =3D> tcg}/fpu_helper.c | 0 target/i386/{ =3D> tcg}/int_helper.c | 0 target/i386/{ =3D> tcg}/mem_helper.c | 0 target/i386/{ =3D> tcg}/misc_helper.c | 0 target/i386/{ =3D> tcg}/mpx_helper.c | 0 target/i386/{ =3D> tcg}/seg_helper.c | 0 target/i386/{ =3D> tcg}/smm_helper.c | 0 target/i386/{ =3D> tcg}/svm_helper.c | 0 target/i386/{ =3D> tcg}/tcg-stub.c | 0 target/i386/{ =3D> tcg}/translate.c | 0 target/i386/meson.build | 14 +------------- target/i386/tcg/meson.build | 13 +++++++++++++ 15 files changed, 14 insertions(+), 13 deletions(-) rename target/i386/{ =3D> tcg}/bpt_helper.c (100%) rename target/i386/{ =3D> tcg}/cc_helper.c (100%) rename target/i386/{ =3D> tcg}/excp_helper.c (100%) rename target/i386/{ =3D> tcg}/fpu_helper.c (100%) rename target/i386/{ =3D> tcg}/int_helper.c (100%) rename target/i386/{ =3D> tcg}/mem_helper.c (100%) rename target/i386/{ =3D> tcg}/misc_helper.c (100%) rename target/i386/{ =3D> tcg}/mpx_helper.c (100%) rename target/i386/{ =3D> tcg}/seg_helper.c (100%) rename target/i386/{ =3D> tcg}/smm_helper.c (100%) rename target/i386/{ =3D> tcg}/svm_helper.c (100%) rename target/i386/{ =3D> tcg}/tcg-stub.c (100%) rename target/i386/{ =3D> tcg}/translate.c (100%) create mode 100644 target/i386/tcg/meson.build diff --git a/target/i386/bpt_helper.c b/target/i386/tcg/bpt_helper.c similarity index 100% rename from target/i386/bpt_helper.c rename to target/i386/tcg/bpt_helper.c diff --git a/target/i386/cc_helper.c b/target/i386/tcg/cc_helper.c similarity index 100% rename from target/i386/cc_helper.c rename to target/i386/tcg/cc_helper.c diff --git a/target/i386/excp_helper.c b/target/i386/tcg/excp_helper.c similarity index 100% rename from target/i386/excp_helper.c rename to target/i386/tcg/excp_helper.c diff --git a/target/i386/fpu_helper.c b/target/i386/tcg/fpu_helper.c similarity index 100% rename from target/i386/fpu_helper.c rename to target/i386/tcg/fpu_helper.c diff --git a/target/i386/int_helper.c b/target/i386/tcg/int_helper.c similarity index 100% rename from target/i386/int_helper.c rename to target/i386/tcg/int_helper.c diff --git a/target/i386/mem_helper.c b/target/i386/tcg/mem_helper.c similarity index 100% rename from target/i386/mem_helper.c rename to target/i386/tcg/mem_helper.c diff --git a/target/i386/misc_helper.c b/target/i386/tcg/misc_helper.c similarity index 100% rename from target/i386/misc_helper.c rename to target/i386/tcg/misc_helper.c diff --git a/target/i386/mpx_helper.c b/target/i386/tcg/mpx_helper.c similarity index 100% rename from target/i386/mpx_helper.c rename to target/i386/tcg/mpx_helper.c diff --git a/target/i386/seg_helper.c b/target/i386/tcg/seg_helper.c similarity index 100% rename from target/i386/seg_helper.c rename to target/i386/tcg/seg_helper.c diff --git a/target/i386/smm_helper.c b/target/i386/tcg/smm_helper.c similarity index 100% rename from target/i386/smm_helper.c rename to target/i386/tcg/smm_helper.c diff --git a/target/i386/svm_helper.c b/target/i386/tcg/svm_helper.c similarity index 100% rename from target/i386/svm_helper.c rename to target/i386/tcg/svm_helper.c diff --git a/target/i386/tcg-stub.c b/target/i386/tcg/tcg-stub.c similarity index 100% rename from target/i386/tcg-stub.c rename to target/i386/tcg/tcg-stub.c diff --git a/target/i386/translate.c b/target/i386/tcg/translate.c similarity index 100% rename from target/i386/translate.c rename to target/i386/tcg/translate.c diff --git a/target/i386/meson.build b/target/i386/meson.build index 284d52ab81..750471c9f3 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -5,19 +5,6 @@ i386_ss.add(files( 'helper.c', 'xsave_helper.c', )) -i386_ss.add(when: 'CONFIG_TCG', if_true: files( - 'bpt_helper.c', - 'cc_helper.c', - 'excp_helper.c', - 'fpu_helper.c', - 'int_helper.c', - 'mem_helper.c', - 'misc_helper.c', - 'mpx_helper.c', - 'seg_helper.c', - 'smm_helper.c', - 'svm_helper.c', - 'translate.c'), if_false: files('tcg-stub.c')) i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('= sev-stub.c')) =20 i386_softmmu_ss =3D ss.source_set() @@ -32,6 +19,7 @@ subdir('kvm') subdir('hax') subdir('whpx') subdir('hvf') +subdir('tcg') =20 target_arch +=3D {'i386': i386_ss} target_softmmu_arch +=3D {'i386': i386_softmmu_ss} diff --git a/target/i386/tcg/meson.build b/target/i386/tcg/meson.build new file mode 100644 index 0000000000..02794226c2 --- /dev/null +++ b/target/i386/tcg/meson.build @@ -0,0 +1,13 @@ +i386_ss.add(when: 'CONFIG_TCG', if_true: files( + 'bpt_helper.c', + 'cc_helper.c', + 'excp_helper.c', + 'fpu_helper.c', + 'int_helper.c', + 'mem_helper.c', + 'misc_helper.c', + 'mpx_helper.c', + 'seg_helper.c', + 'smm_helper.c', + 'svm_helper.c', + 'translate.c'), if_false: files('tcg-stub.c')) --=20 2.26.2 From nobody Mon May 20 22:41:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607676277; cv=none; d=zohomail.com; s=zohoarc; b=m4Fn6MeIbrWyfL8DwSrHBcZ/iBMh/y7Tun6OmDwYfO0TdYOZYTpc0FEXdnSr3SAxBvTYnOgEMZd5Zb34qlYLbgBxASz0vusa3B9l/7q86RFaP28WSMWGNVHIuJttmUjED3NAstB4NY8FLfVdeAwxJFSJhLrAitxBUeN8WfIC0+s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607676277; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=D7AdUssWaUWltmh2bCcae/77WpzLneRCK+6CfNqyqNI=; b=Z64VPmizLkFYQH1+qsM3P+t8dQxCUd/xheWLVgaBKTW+8N8lLKvej80nAunm+afMSMD3RoA+4qns+kMCqKvfYZylnmoMLSHxI6RROzcPdhok11WqZCDKyUnT3DL4WLe7FV5cgRypwK3VDwIeiv3YyU5HEszaeLzvbCXxBEuXbcM= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607676277426204.54241389790343; Fri, 11 Dec 2020 00:44:37 -0800 (PST) Received: from localhost ([::1]:39414 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kne2W-0007Rb-69 for importer@patchew.org; Fri, 11 Dec 2020 03:44:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42416) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqN-0008B3-KM for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:32:05 -0500 Received: from mx2.suse.de ([195.135.220.15]:34942) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqD-00028U-AT for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:32:03 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id E44CCAFFA; Fri, 11 Dec 2020 08:31:51 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 09/25] i386: move cpu dump out of helper.c into cpu-dump.c Date: Fri, 11 Dec 2020 09:31:27 +0100 Message-Id: <20201211083143.14350-10-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211083143.14350-1-cfontana@suse.de> References: <20201211083143.14350-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/i386/cpu.h | 1 + target/i386/cpu-dump.c | 537 ++++++++++++++++++++++++++++++++++++++++ target/i386/helper.c | 514 -------------------------------------- target/i386/meson.build | 1 + 4 files changed, 539 insertions(+), 514 deletions(-) create mode 100644 target/i386/cpu-dump.c diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9ecda75aec..d6ed45c5d7 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2232,6 +2232,7 @@ void enable_compat_apic_id_mode(void); #define APIC_DEFAULT_ADDRESS 0xfee00000 #define APIC_SPACE_SIZE 0x100000 =20 +/* cpu-dump.c */ void x86_cpu_dump_local_apic_state(CPUState *cs, int flags); =20 /* cpu.c */ diff --git a/target/i386/cpu-dump.c b/target/i386/cpu-dump.c new file mode 100644 index 0000000000..aac21f1f60 --- /dev/null +++ b/target/i386/cpu-dump.c @@ -0,0 +1,537 @@ +/* + * i386 CPU dump to FILE + * + * Copyright (c) 2003 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "qemu/qemu-print.h" +#ifndef CONFIG_USER_ONLY +#include "hw/i386/apic_internal.h" +#endif + +/***********************************************************/ +/* x86 debug */ + +static const char *cc_op_str[CC_OP_NB] =3D { + "DYNAMIC", + "EFLAGS", + + "MULB", + "MULW", + "MULL", + "MULQ", + + "ADDB", + "ADDW", + "ADDL", + "ADDQ", + + "ADCB", + "ADCW", + "ADCL", + "ADCQ", + + "SUBB", + "SUBW", + "SUBL", + "SUBQ", + + "SBBB", + "SBBW", + "SBBL", + "SBBQ", + + "LOGICB", + "LOGICW", + "LOGICL", + "LOGICQ", + + "INCB", + "INCW", + "INCL", + "INCQ", + + "DECB", + "DECW", + "DECL", + "DECQ", + + "SHLB", + "SHLW", + "SHLL", + "SHLQ", + + "SARB", + "SARW", + "SARL", + "SARQ", + + "BMILGB", + "BMILGW", + "BMILGL", + "BMILGQ", + + "ADCX", + "ADOX", + "ADCOX", + + "CLR", +}; + +static void +cpu_x86_dump_seg_cache(CPUX86State *env, FILE *f, + const char *name, struct SegmentCache *sc) +{ +#ifdef TARGET_X86_64 + if (env->hflags & HF_CS64_MASK) { + qemu_fprintf(f, "%-3s=3D%04x %016" PRIx64 " %08x %08x", name, + sc->selector, sc->base, sc->limit, + sc->flags & 0x00ffff00); + } else +#endif + { + qemu_fprintf(f, "%-3s=3D%04x %08x %08x %08x", name, sc->selector, + (uint32_t)sc->base, sc->limit, + sc->flags & 0x00ffff00); + } + + if (!(env->hflags & HF_PE_MASK) || !(sc->flags & DESC_P_MASK)) + goto done; + + qemu_fprintf(f, " DPL=3D%d ", + (sc->flags & DESC_DPL_MASK) >> DESC_DPL_SHIFT); + if (sc->flags & DESC_S_MASK) { + if (sc->flags & DESC_CS_MASK) { + qemu_fprintf(f, (sc->flags & DESC_L_MASK) ? "CS64" : + ((sc->flags & DESC_B_MASK) ? "CS32" : "CS16")); + qemu_fprintf(f, " [%c%c", (sc->flags & DESC_C_MASK) ? 'C' : '-= ', + (sc->flags & DESC_R_MASK) ? 'R' : '-'); + } else { + qemu_fprintf(f, (sc->flags & DESC_B_MASK + || env->hflags & HF_LMA_MASK) + ? "DS " : "DS16"); + qemu_fprintf(f, " [%c%c", (sc->flags & DESC_E_MASK) ? 'E' : '-= ', + (sc->flags & DESC_W_MASK) ? 'W' : '-'); + } + qemu_fprintf(f, "%c]", (sc->flags & DESC_A_MASK) ? 'A' : '-'); + } else { + static const char *sys_type_name[2][16] =3D { + { /* 32 bit mode */ + "Reserved", "TSS16-avl", "LDT", "TSS16-busy", + "CallGate16", "TaskGate", "IntGate16", "TrapGate16", + "Reserved", "TSS32-avl", "Reserved", "TSS32-busy", + "CallGate32", "Reserved", "IntGate32", "TrapGate32" + }, + { /* 64 bit mode */ + "", "Reserved", "LDT", "Reserved", "Reserved", + "Reserved", "Reserved", "Reserved", "Reserved", + "TSS64-avl", "Reserved", "TSS64-busy", "CallGate64", + "Reserved", "IntGate64", "TrapGate64" + } + }; + qemu_fprintf(f, "%s", + sys_type_name[(env->hflags & HF_LMA_MASK) ? 1 : 0] + [(sc->flags & DESC_TYPE_MASK) >> DESC_TYPE_SHIFT]); + } +done: + qemu_fprintf(f, "\n"); +} + +#ifndef CONFIG_USER_ONLY + +/* ARRAY_SIZE check is not required because + * DeliveryMode(dm) has a size of 3 bit. + */ +static inline const char *dm2str(uint32_t dm) +{ + static const char *str[] =3D { + "Fixed", + "...", + "SMI", + "...", + "NMI", + "INIT", + "...", + "ExtINT" + }; + return str[dm]; +} + +static void dump_apic_lvt(const char *name, uint32_t lvt, bool is_timer) +{ + uint32_t dm =3D (lvt & APIC_LVT_DELIV_MOD) >> APIC_LVT_DELIV_MOD_SHIFT; + qemu_printf("%s\t 0x%08x %s %-5s %-6s %-7s %-12s %-6s", + name, lvt, + lvt & APIC_LVT_INT_POLARITY ? "active-lo" : "active-hi", + lvt & APIC_LVT_LEVEL_TRIGGER ? "level" : "edge", + lvt & APIC_LVT_MASKED ? "masked" : "", + lvt & APIC_LVT_DELIV_STS ? "pending" : "", + !is_timer ? + "" : lvt & APIC_LVT_TIMER_PERIODIC ? + "periodic" : lvt & APIC_LVT_TIMER_TSCDEADLINE ? + "tsc-deadline" : "one-shot", + dm2str(dm)); + if (dm !=3D APIC_DM_NMI) { + qemu_printf(" (vec %u)\n", lvt & APIC_VECTOR_MASK); + } else { + qemu_printf("\n"); + } +} + +/* ARRAY_SIZE check is not required because + * destination shorthand has a size of 2 bit. + */ +static inline const char *shorthand2str(uint32_t shorthand) +{ + const char *str[] =3D { + "no-shorthand", "self", "all-self", "all" + }; + return str[shorthand]; +} + +static inline uint8_t divider_conf(uint32_t divide_conf) +{ + uint8_t divide_val =3D ((divide_conf & 0x8) >> 1) | (divide_conf & 0x3= ); + + return divide_val =3D=3D 7 ? 1 : 2 << divide_val; +} + +static inline void mask2str(char *str, uint32_t val, uint8_t size) +{ + while (size--) { + *str++ =3D (val >> size) & 1 ? '1' : '0'; + } + *str =3D 0; +} + +#define MAX_LOGICAL_APIC_ID_MASK_SIZE 16 + +static void dump_apic_icr(APICCommonState *s, CPUX86State *env) +{ + uint32_t icr =3D s->icr[0], icr2 =3D s->icr[1]; + uint8_t dest_shorthand =3D \ + (icr & APIC_ICR_DEST_SHORT) >> APIC_ICR_DEST_SHORT_SHIFT; + bool logical_mod =3D icr & APIC_ICR_DEST_MOD; + char apic_id_str[MAX_LOGICAL_APIC_ID_MASK_SIZE + 1]; + uint32_t dest_field; + bool x2apic; + + qemu_printf("ICR\t 0x%08x %s %s %s %s\n", + icr, + logical_mod ? "logical" : "physical", + icr & APIC_ICR_TRIGGER_MOD ? "level" : "edge", + icr & APIC_ICR_LEVEL ? "assert" : "de-assert", + shorthand2str(dest_shorthand)); + + qemu_printf("ICR2\t 0x%08x", icr2); + if (dest_shorthand !=3D 0) { + qemu_printf("\n"); + return; + } + x2apic =3D env->features[FEAT_1_ECX] & CPUID_EXT_X2APIC; + dest_field =3D x2apic ? icr2 : icr2 >> APIC_ICR_DEST_SHIFT; + + if (!logical_mod) { + if (x2apic) { + qemu_printf(" cpu %u (X2APIC ID)\n", dest_field); + } else { + qemu_printf(" cpu %u (APIC ID)\n", + dest_field & APIC_LOGDEST_XAPIC_ID); + } + return; + } + + if (s->dest_mode =3D=3D 0xf) { /* flat mode */ + mask2str(apic_id_str, icr2 >> APIC_ICR_DEST_SHIFT, 8); + qemu_printf(" mask %s (APIC ID)\n", apic_id_str); + } else if (s->dest_mode =3D=3D 0) { /* cluster mode */ + if (x2apic) { + mask2str(apic_id_str, dest_field & APIC_LOGDEST_X2APIC_ID, 16); + qemu_printf(" cluster %u mask %s (X2APIC ID)\n", + dest_field >> APIC_LOGDEST_X2APIC_SHIFT, apic_id_s= tr); + } else { + mask2str(apic_id_str, dest_field & APIC_LOGDEST_XAPIC_ID, 4); + qemu_printf(" cluster %u mask %s (APIC ID)\n", + dest_field >> APIC_LOGDEST_XAPIC_SHIFT, apic_id_st= r); + } + } +} + +static void dump_apic_interrupt(const char *name, uint32_t *ireg_tab, + uint32_t *tmr_tab) +{ + int i, empty =3D true; + + qemu_printf("%s\t ", name); + for (i =3D 0; i < 256; i++) { + if (apic_get_bit(ireg_tab, i)) { + qemu_printf("%u%s ", i, + apic_get_bit(tmr_tab, i) ? "(level)" : ""); + empty =3D false; + } + } + qemu_printf("%s\n", empty ? "(none)" : ""); +} + +void x86_cpu_dump_local_apic_state(CPUState *cs, int flags) +{ + X86CPU *cpu =3D X86_CPU(cs); + APICCommonState *s =3D APIC_COMMON(cpu->apic_state); + if (!s) { + qemu_printf("local apic state not available\n"); + return; + } + uint32_t *lvt =3D s->lvt; + + qemu_printf("dumping local APIC state for CPU %-2u\n\n", + CPU(cpu)->cpu_index); + dump_apic_lvt("LVT0", lvt[APIC_LVT_LINT0], false); + dump_apic_lvt("LVT1", lvt[APIC_LVT_LINT1], false); + dump_apic_lvt("LVTPC", lvt[APIC_LVT_PERFORM], false); + dump_apic_lvt("LVTERR", lvt[APIC_LVT_ERROR], false); + dump_apic_lvt("LVTTHMR", lvt[APIC_LVT_THERMAL], false); + dump_apic_lvt("LVTT", lvt[APIC_LVT_TIMER], true); + + qemu_printf("Timer\t DCR=3D0x%x (divide by %u) initial_count =3D %u" + " current_count =3D %u\n", + s->divide_conf & APIC_DCR_MASK, + divider_conf(s->divide_conf), + s->initial_count, apic_get_current_count(s)); + + qemu_printf("SPIV\t 0x%08x APIC %s, focus=3D%s, spurious vec %u\n", + s->spurious_vec, + s->spurious_vec & APIC_SPURIO_ENABLED ? "enabled" : "disab= led", + s->spurious_vec & APIC_SPURIO_FOCUS ? "on" : "off", + s->spurious_vec & APIC_VECTOR_MASK); + + dump_apic_icr(s, &cpu->env); + + qemu_printf("ESR\t 0x%08x\n", s->esr); + + dump_apic_interrupt("ISR", s->isr, s->tmr); + dump_apic_interrupt("IRR", s->irr, s->tmr); + + qemu_printf("\nAPR 0x%02x TPR 0x%02x DFR 0x%02x LDR 0x%02x", + s->arb_id, s->tpr, s->dest_mode, s->log_dest); + if (s->dest_mode =3D=3D 0) { + qemu_printf("(cluster %u: id %u)", + s->log_dest >> APIC_LOGDEST_XAPIC_SHIFT, + s->log_dest & APIC_LOGDEST_XAPIC_ID); + } + qemu_printf(" PPR 0x%02x\n", apic_get_ppr(s)); +} +#else +void x86_cpu_dump_local_apic_state(CPUState *cs, int flags) +{ +} +#endif /* !CONFIG_USER_ONLY */ + +#define DUMP_CODE_BYTES_TOTAL 50 +#define DUMP_CODE_BYTES_BACKWARD 20 + +void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + int eflags, i, nb; + char cc_op_name[32]; + static const char *seg_name[6] =3D { "ES", "CS", "SS", "DS", "FS", "GS= " }; + + eflags =3D cpu_compute_eflags(env); +#ifdef TARGET_X86_64 + if (env->hflags & HF_CS64_MASK) { + qemu_fprintf(f, "RAX=3D%016" PRIx64 " RBX=3D%016" PRIx64 " RCX=3D%= 016" PRIx64 " RDX=3D%016" PRIx64 "\n" + "RSI=3D%016" PRIx64 " RDI=3D%016" PRIx64 " RBP=3D%016= " PRIx64 " RSP=3D%016" PRIx64 "\n" + "R8 =3D%016" PRIx64 " R9 =3D%016" PRIx64 " R10=3D%016= " PRIx64 " R11=3D%016" PRIx64 "\n" + "R12=3D%016" PRIx64 " R13=3D%016" PRIx64 " R14=3D%016= " PRIx64 " R15=3D%016" PRIx64 "\n" + "RIP=3D%016" PRIx64 " RFL=3D%08x [%c%c%c%c%c%c%c] CPL= =3D%d II=3D%d A20=3D%d SMM=3D%d HLT=3D%d\n", + env->regs[R_EAX], + env->regs[R_EBX], + env->regs[R_ECX], + env->regs[R_EDX], + env->regs[R_ESI], + env->regs[R_EDI], + env->regs[R_EBP], + env->regs[R_ESP], + env->regs[8], + env->regs[9], + env->regs[10], + env->regs[11], + env->regs[12], + env->regs[13], + env->regs[14], + env->regs[15], + env->eip, eflags, + eflags & DF_MASK ? 'D' : '-', + eflags & CC_O ? 'O' : '-', + eflags & CC_S ? 'S' : '-', + eflags & CC_Z ? 'Z' : '-', + eflags & CC_A ? 'A' : '-', + eflags & CC_P ? 'P' : '-', + eflags & CC_C ? 'C' : '-', + env->hflags & HF_CPL_MASK, + (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1, + (env->a20_mask >> 20) & 1, + (env->hflags >> HF_SMM_SHIFT) & 1, + cs->halted); + } else +#endif + { + qemu_fprintf(f, "EAX=3D%08x EBX=3D%08x ECX=3D%08x EDX=3D%08x\n" + "ESI=3D%08x EDI=3D%08x EBP=3D%08x ESP=3D%08x\n" + "EIP=3D%08x EFL=3D%08x [%c%c%c%c%c%c%c] CPL=3D%d II= =3D%d A20=3D%d SMM=3D%d HLT=3D%d\n", + (uint32_t)env->regs[R_EAX], + (uint32_t)env->regs[R_EBX], + (uint32_t)env->regs[R_ECX], + (uint32_t)env->regs[R_EDX], + (uint32_t)env->regs[R_ESI], + (uint32_t)env->regs[R_EDI], + (uint32_t)env->regs[R_EBP], + (uint32_t)env->regs[R_ESP], + (uint32_t)env->eip, eflags, + eflags & DF_MASK ? 'D' : '-', + eflags & CC_O ? 'O' : '-', + eflags & CC_S ? 'S' : '-', + eflags & CC_Z ? 'Z' : '-', + eflags & CC_A ? 'A' : '-', + eflags & CC_P ? 'P' : '-', + eflags & CC_C ? 'C' : '-', + env->hflags & HF_CPL_MASK, + (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1, + (env->a20_mask >> 20) & 1, + (env->hflags >> HF_SMM_SHIFT) & 1, + cs->halted); + } + + for(i =3D 0; i < 6; i++) { + cpu_x86_dump_seg_cache(env, f, seg_name[i], &env->segs[i]); + } + cpu_x86_dump_seg_cache(env, f, "LDT", &env->ldt); + cpu_x86_dump_seg_cache(env, f, "TR", &env->tr); + +#ifdef TARGET_X86_64 + if (env->hflags & HF_LMA_MASK) { + qemu_fprintf(f, "GDT=3D %016" PRIx64 " %08x\n", + env->gdt.base, env->gdt.limit); + qemu_fprintf(f, "IDT=3D %016" PRIx64 " %08x\n", + env->idt.base, env->idt.limit); + qemu_fprintf(f, "CR0=3D%08x CR2=3D%016" PRIx64 " CR3=3D%016" PRIx6= 4 " CR4=3D%08x\n", + (uint32_t)env->cr[0], + env->cr[2], + env->cr[3], + (uint32_t)env->cr[4]); + for(i =3D 0; i < 4; i++) + qemu_fprintf(f, "DR%d=3D%016" PRIx64 " ", i, env->dr[i]); + qemu_fprintf(f, "\nDR6=3D%016" PRIx64 " DR7=3D%016" PRIx64 "\n", + env->dr[6], env->dr[7]); + } else +#endif + { + qemu_fprintf(f, "GDT=3D %08x %08x\n", + (uint32_t)env->gdt.base, env->gdt.limit); + qemu_fprintf(f, "IDT=3D %08x %08x\n", + (uint32_t)env->idt.base, env->idt.limit); + qemu_fprintf(f, "CR0=3D%08x CR2=3D%08x CR3=3D%08x CR4=3D%08x\n", + (uint32_t)env->cr[0], + (uint32_t)env->cr[2], + (uint32_t)env->cr[3], + (uint32_t)env->cr[4]); + for(i =3D 0; i < 4; i++) { + qemu_fprintf(f, "DR%d=3D" TARGET_FMT_lx " ", i, env->dr[i]); + } + qemu_fprintf(f, "\nDR6=3D" TARGET_FMT_lx " DR7=3D" TARGET_FMT_lx "= \n", + env->dr[6], env->dr[7]); + } + if (flags & CPU_DUMP_CCOP) { + if ((unsigned)env->cc_op < CC_OP_NB) + snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->= cc_op]); + else + snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op); +#ifdef TARGET_X86_64 + if (env->hflags & HF_CS64_MASK) { + qemu_fprintf(f, "CCS=3D%016" PRIx64 " CCD=3D%016" PRIx64 " CCO= =3D%-8s\n", + env->cc_src, env->cc_dst, + cc_op_name); + } else +#endif + { + qemu_fprintf(f, "CCS=3D%08x CCD=3D%08x CCO=3D%-8s\n", + (uint32_t)env->cc_src, (uint32_t)env->cc_dst, + cc_op_name); + } + } + qemu_fprintf(f, "EFER=3D%016" PRIx64 "\n", env->efer); + if (flags & CPU_DUMP_FPU) { + int fptag; + fptag =3D 0; + for(i =3D 0; i < 8; i++) { + fptag |=3D ((!env->fptags[i]) << i); + } + update_mxcsr_from_sse_status(env); + qemu_fprintf(f, "FCW=3D%04x FSW=3D%04x [ST=3D%d] FTW=3D%02x MXCSR= =3D%08x\n", + env->fpuc, + (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11, + env->fpstt, + fptag, + env->mxcsr); + for(i=3D0;i<8;i++) { + CPU_LDoubleU u; + u.d =3D env->fpregs[i].d; + qemu_fprintf(f, "FPR%d=3D%016" PRIx64 " %04x", + i, u.l.lower, u.l.upper); + if ((i & 1) =3D=3D 1) + qemu_fprintf(f, "\n"); + else + qemu_fprintf(f, " "); + } + if (env->hflags & HF_CS64_MASK) + nb =3D 16; + else + nb =3D 8; + for(i=3D0;ixmm_regs[i].ZMM_L(3), + env->xmm_regs[i].ZMM_L(2), + env->xmm_regs[i].ZMM_L(1), + env->xmm_regs[i].ZMM_L(0)); + if ((i & 1) =3D=3D 1) + qemu_fprintf(f, "\n"); + else + qemu_fprintf(f, " "); + } + } + if (flags & CPU_DUMP_CODE) { + target_ulong base =3D env->segs[R_CS].base + env->eip; + target_ulong offs =3D MIN(env->eip, DUMP_CODE_BYTES_BACKWARD); + uint8_t code; + char codestr[3]; + + qemu_fprintf(f, "Code=3D"); + for (i =3D 0; i < DUMP_CODE_BYTES_TOTAL; i++) { + if (cpu_memory_rw_debug(cs, base - offs + i, &code, 1, 0) =3D= =3D 0) { + snprintf(codestr, sizeof(codestr), "%02x", code); + } else { + snprintf(codestr, sizeof(codestr), "??"); + } + qemu_fprintf(f, "%s%s%s%s", i > 0 ? " " : "", + i =3D=3D offs ? "<" : "", codestr, i =3D=3D offs = ? ">" : ""); + } + qemu_fprintf(f, "\n"); + } +} diff --git a/target/i386/helper.c b/target/i386/helper.c index a1b3367ab2..6e7e0f507c 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -21,8 +21,6 @@ #include "qapi/qapi-events-run-state.h" #include "cpu.h" #include "exec/exec-all.h" -#include "qemu/qemu-print.h" -#include "sysemu/kvm.h" #include "sysemu/runstate.h" #include "kvm/kvm_i386.h" #ifndef CONFIG_USER_ONLY @@ -88,518 +86,6 @@ int cpu_x86_support_mca_broadcast(CPUX86State *env) return 0; } =20 -/***********************************************************/ -/* x86 debug */ - -static const char *cc_op_str[CC_OP_NB] =3D { - "DYNAMIC", - "EFLAGS", - - "MULB", - "MULW", - "MULL", - "MULQ", - - "ADDB", - "ADDW", - "ADDL", - "ADDQ", - - "ADCB", - "ADCW", - "ADCL", - "ADCQ", - - "SUBB", - "SUBW", - "SUBL", - "SUBQ", - - "SBBB", - "SBBW", - "SBBL", - "SBBQ", - - "LOGICB", - "LOGICW", - "LOGICL", - "LOGICQ", - - "INCB", - "INCW", - "INCL", - "INCQ", - - "DECB", - "DECW", - "DECL", - "DECQ", - - "SHLB", - "SHLW", - "SHLL", - "SHLQ", - - "SARB", - "SARW", - "SARL", - "SARQ", - - "BMILGB", - "BMILGW", - "BMILGL", - "BMILGQ", - - "ADCX", - "ADOX", - "ADCOX", - - "CLR", -}; - -static void -cpu_x86_dump_seg_cache(CPUX86State *env, FILE *f, - const char *name, struct SegmentCache *sc) -{ -#ifdef TARGET_X86_64 - if (env->hflags & HF_CS64_MASK) { - qemu_fprintf(f, "%-3s=3D%04x %016" PRIx64 " %08x %08x", name, - sc->selector, sc->base, sc->limit, - sc->flags & 0x00ffff00); - } else -#endif - { - qemu_fprintf(f, "%-3s=3D%04x %08x %08x %08x", name, sc->selector, - (uint32_t)sc->base, sc->limit, - sc->flags & 0x00ffff00); - } - - if (!(env->hflags & HF_PE_MASK) || !(sc->flags & DESC_P_MASK)) - goto done; - - qemu_fprintf(f, " DPL=3D%d ", - (sc->flags & DESC_DPL_MASK) >> DESC_DPL_SHIFT); - if (sc->flags & DESC_S_MASK) { - if (sc->flags & DESC_CS_MASK) { - qemu_fprintf(f, (sc->flags & DESC_L_MASK) ? "CS64" : - ((sc->flags & DESC_B_MASK) ? "CS32" : "CS16")); - qemu_fprintf(f, " [%c%c", (sc->flags & DESC_C_MASK) ? 'C' : '-= ', - (sc->flags & DESC_R_MASK) ? 'R' : '-'); - } else { - qemu_fprintf(f, (sc->flags & DESC_B_MASK - || env->hflags & HF_LMA_MASK) - ? "DS " : "DS16"); - qemu_fprintf(f, " [%c%c", (sc->flags & DESC_E_MASK) ? 'E' : '-= ', - (sc->flags & DESC_W_MASK) ? 'W' : '-'); - } - qemu_fprintf(f, "%c]", (sc->flags & DESC_A_MASK) ? 'A' : '-'); - } else { - static const char *sys_type_name[2][16] =3D { - { /* 32 bit mode */ - "Reserved", "TSS16-avl", "LDT", "TSS16-busy", - "CallGate16", "TaskGate", "IntGate16", "TrapGate16", - "Reserved", "TSS32-avl", "Reserved", "TSS32-busy", - "CallGate32", "Reserved", "IntGate32", "TrapGate32" - }, - { /* 64 bit mode */ - "", "Reserved", "LDT", "Reserved", "Reserved", - "Reserved", "Reserved", "Reserved", "Reserved", - "TSS64-avl", "Reserved", "TSS64-busy", "CallGate64", - "Reserved", "IntGate64", "TrapGate64" - } - }; - qemu_fprintf(f, "%s", - sys_type_name[(env->hflags & HF_LMA_MASK) ? 1 : 0] - [(sc->flags & DESC_TYPE_MASK) >> DESC_TYPE_SHIFT]); - } -done: - qemu_fprintf(f, "\n"); -} - -#ifndef CONFIG_USER_ONLY - -/* ARRAY_SIZE check is not required because - * DeliveryMode(dm) has a size of 3 bit. - */ -static inline const char *dm2str(uint32_t dm) -{ - static const char *str[] =3D { - "Fixed", - "...", - "SMI", - "...", - "NMI", - "INIT", - "...", - "ExtINT" - }; - return str[dm]; -} - -static void dump_apic_lvt(const char *name, uint32_t lvt, bool is_timer) -{ - uint32_t dm =3D (lvt & APIC_LVT_DELIV_MOD) >> APIC_LVT_DELIV_MOD_SHIFT; - qemu_printf("%s\t 0x%08x %s %-5s %-6s %-7s %-12s %-6s", - name, lvt, - lvt & APIC_LVT_INT_POLARITY ? "active-lo" : "active-hi", - lvt & APIC_LVT_LEVEL_TRIGGER ? "level" : "edge", - lvt & APIC_LVT_MASKED ? "masked" : "", - lvt & APIC_LVT_DELIV_STS ? "pending" : "", - !is_timer ? - "" : lvt & APIC_LVT_TIMER_PERIODIC ? - "periodic" : lvt & APIC_LVT_TIMER_TSCDEADLINE ? - "tsc-deadline" : "one-shot", - dm2str(dm)); - if (dm !=3D APIC_DM_NMI) { - qemu_printf(" (vec %u)\n", lvt & APIC_VECTOR_MASK); - } else { - qemu_printf("\n"); - } -} - -/* ARRAY_SIZE check is not required because - * destination shorthand has a size of 2 bit. - */ -static inline const char *shorthand2str(uint32_t shorthand) -{ - const char *str[] =3D { - "no-shorthand", "self", "all-self", "all" - }; - return str[shorthand]; -} - -static inline uint8_t divider_conf(uint32_t divide_conf) -{ - uint8_t divide_val =3D ((divide_conf & 0x8) >> 1) | (divide_conf & 0x3= ); - - return divide_val =3D=3D 7 ? 1 : 2 << divide_val; -} - -static inline void mask2str(char *str, uint32_t val, uint8_t size) -{ - while (size--) { - *str++ =3D (val >> size) & 1 ? '1' : '0'; - } - *str =3D 0; -} - -#define MAX_LOGICAL_APIC_ID_MASK_SIZE 16 - -static void dump_apic_icr(APICCommonState *s, CPUX86State *env) -{ - uint32_t icr =3D s->icr[0], icr2 =3D s->icr[1]; - uint8_t dest_shorthand =3D \ - (icr & APIC_ICR_DEST_SHORT) >> APIC_ICR_DEST_SHORT_SHIFT; - bool logical_mod =3D icr & APIC_ICR_DEST_MOD; - char apic_id_str[MAX_LOGICAL_APIC_ID_MASK_SIZE + 1]; - uint32_t dest_field; - bool x2apic; - - qemu_printf("ICR\t 0x%08x %s %s %s %s\n", - icr, - logical_mod ? "logical" : "physical", - icr & APIC_ICR_TRIGGER_MOD ? "level" : "edge", - icr & APIC_ICR_LEVEL ? "assert" : "de-assert", - shorthand2str(dest_shorthand)); - - qemu_printf("ICR2\t 0x%08x", icr2); - if (dest_shorthand !=3D 0) { - qemu_printf("\n"); - return; - } - x2apic =3D env->features[FEAT_1_ECX] & CPUID_EXT_X2APIC; - dest_field =3D x2apic ? icr2 : icr2 >> APIC_ICR_DEST_SHIFT; - - if (!logical_mod) { - if (x2apic) { - qemu_printf(" cpu %u (X2APIC ID)\n", dest_field); - } else { - qemu_printf(" cpu %u (APIC ID)\n", - dest_field & APIC_LOGDEST_XAPIC_ID); - } - return; - } - - if (s->dest_mode =3D=3D 0xf) { /* flat mode */ - mask2str(apic_id_str, icr2 >> APIC_ICR_DEST_SHIFT, 8); - qemu_printf(" mask %s (APIC ID)\n", apic_id_str); - } else if (s->dest_mode =3D=3D 0) { /* cluster mode */ - if (x2apic) { - mask2str(apic_id_str, dest_field & APIC_LOGDEST_X2APIC_ID, 16); - qemu_printf(" cluster %u mask %s (X2APIC ID)\n", - dest_field >> APIC_LOGDEST_X2APIC_SHIFT, apic_id_s= tr); - } else { - mask2str(apic_id_str, dest_field & APIC_LOGDEST_XAPIC_ID, 4); - qemu_printf(" cluster %u mask %s (APIC ID)\n", - dest_field >> APIC_LOGDEST_XAPIC_SHIFT, apic_id_st= r); - } - } -} - -static void dump_apic_interrupt(const char *name, uint32_t *ireg_tab, - uint32_t *tmr_tab) -{ - int i, empty =3D true; - - qemu_printf("%s\t ", name); - for (i =3D 0; i < 256; i++) { - if (apic_get_bit(ireg_tab, i)) { - qemu_printf("%u%s ", i, - apic_get_bit(tmr_tab, i) ? "(level)" : ""); - empty =3D false; - } - } - qemu_printf("%s\n", empty ? "(none)" : ""); -} - -void x86_cpu_dump_local_apic_state(CPUState *cs, int flags) -{ - X86CPU *cpu =3D X86_CPU(cs); - APICCommonState *s =3D APIC_COMMON(cpu->apic_state); - if (!s) { - qemu_printf("local apic state not available\n"); - return; - } - uint32_t *lvt =3D s->lvt; - - qemu_printf("dumping local APIC state for CPU %-2u\n\n", - CPU(cpu)->cpu_index); - dump_apic_lvt("LVT0", lvt[APIC_LVT_LINT0], false); - dump_apic_lvt("LVT1", lvt[APIC_LVT_LINT1], false); - dump_apic_lvt("LVTPC", lvt[APIC_LVT_PERFORM], false); - dump_apic_lvt("LVTERR", lvt[APIC_LVT_ERROR], false); - dump_apic_lvt("LVTTHMR", lvt[APIC_LVT_THERMAL], false); - dump_apic_lvt("LVTT", lvt[APIC_LVT_TIMER], true); - - qemu_printf("Timer\t DCR=3D0x%x (divide by %u) initial_count =3D %u" - " current_count =3D %u\n", - s->divide_conf & APIC_DCR_MASK, - divider_conf(s->divide_conf), - s->initial_count, apic_get_current_count(s)); - - qemu_printf("SPIV\t 0x%08x APIC %s, focus=3D%s, spurious vec %u\n", - s->spurious_vec, - s->spurious_vec & APIC_SPURIO_ENABLED ? "enabled" : "disab= led", - s->spurious_vec & APIC_SPURIO_FOCUS ? "on" : "off", - s->spurious_vec & APIC_VECTOR_MASK); - - dump_apic_icr(s, &cpu->env); - - qemu_printf("ESR\t 0x%08x\n", s->esr); - - dump_apic_interrupt("ISR", s->isr, s->tmr); - dump_apic_interrupt("IRR", s->irr, s->tmr); - - qemu_printf("\nAPR 0x%02x TPR 0x%02x DFR 0x%02x LDR 0x%02x", - s->arb_id, s->tpr, s->dest_mode, s->log_dest); - if (s->dest_mode =3D=3D 0) { - qemu_printf("(cluster %u: id %u)", - s->log_dest >> APIC_LOGDEST_XAPIC_SHIFT, - s->log_dest & APIC_LOGDEST_XAPIC_ID); - } - qemu_printf(" PPR 0x%02x\n", apic_get_ppr(s)); -} -#else -void x86_cpu_dump_local_apic_state(CPUState *cs, int flags) -{ -} -#endif /* !CONFIG_USER_ONLY */ - -#define DUMP_CODE_BYTES_TOTAL 50 -#define DUMP_CODE_BYTES_BACKWARD 20 - -void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags) -{ - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - int eflags, i, nb; - char cc_op_name[32]; - static const char *seg_name[6] =3D { "ES", "CS", "SS", "DS", "FS", "GS= " }; - - eflags =3D cpu_compute_eflags(env); -#ifdef TARGET_X86_64 - if (env->hflags & HF_CS64_MASK) { - qemu_fprintf(f, "RAX=3D%016" PRIx64 " RBX=3D%016" PRIx64 " RCX=3D%= 016" PRIx64 " RDX=3D%016" PRIx64 "\n" - "RSI=3D%016" PRIx64 " RDI=3D%016" PRIx64 " RBP=3D%016= " PRIx64 " RSP=3D%016" PRIx64 "\n" - "R8 =3D%016" PRIx64 " R9 =3D%016" PRIx64 " R10=3D%016= " PRIx64 " R11=3D%016" PRIx64 "\n" - "R12=3D%016" PRIx64 " R13=3D%016" PRIx64 " R14=3D%016= " PRIx64 " R15=3D%016" PRIx64 "\n" - "RIP=3D%016" PRIx64 " RFL=3D%08x [%c%c%c%c%c%c%c] CPL= =3D%d II=3D%d A20=3D%d SMM=3D%d HLT=3D%d\n", - env->regs[R_EAX], - env->regs[R_EBX], - env->regs[R_ECX], - env->regs[R_EDX], - env->regs[R_ESI], - env->regs[R_EDI], - env->regs[R_EBP], - env->regs[R_ESP], - env->regs[8], - env->regs[9], - env->regs[10], - env->regs[11], - env->regs[12], - env->regs[13], - env->regs[14], - env->regs[15], - env->eip, eflags, - eflags & DF_MASK ? 'D' : '-', - eflags & CC_O ? 'O' : '-', - eflags & CC_S ? 'S' : '-', - eflags & CC_Z ? 'Z' : '-', - eflags & CC_A ? 'A' : '-', - eflags & CC_P ? 'P' : '-', - eflags & CC_C ? 'C' : '-', - env->hflags & HF_CPL_MASK, - (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1, - (env->a20_mask >> 20) & 1, - (env->hflags >> HF_SMM_SHIFT) & 1, - cs->halted); - } else -#endif - { - qemu_fprintf(f, "EAX=3D%08x EBX=3D%08x ECX=3D%08x EDX=3D%08x\n" - "ESI=3D%08x EDI=3D%08x EBP=3D%08x ESP=3D%08x\n" - "EIP=3D%08x EFL=3D%08x [%c%c%c%c%c%c%c] CPL=3D%d II= =3D%d A20=3D%d SMM=3D%d HLT=3D%d\n", - (uint32_t)env->regs[R_EAX], - (uint32_t)env->regs[R_EBX], - (uint32_t)env->regs[R_ECX], - (uint32_t)env->regs[R_EDX], - (uint32_t)env->regs[R_ESI], - (uint32_t)env->regs[R_EDI], - (uint32_t)env->regs[R_EBP], - (uint32_t)env->regs[R_ESP], - (uint32_t)env->eip, eflags, - eflags & DF_MASK ? 'D' : '-', - eflags & CC_O ? 'O' : '-', - eflags & CC_S ? 'S' : '-', - eflags & CC_Z ? 'Z' : '-', - eflags & CC_A ? 'A' : '-', - eflags & CC_P ? 'P' : '-', - eflags & CC_C ? 'C' : '-', - env->hflags & HF_CPL_MASK, - (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1, - (env->a20_mask >> 20) & 1, - (env->hflags >> HF_SMM_SHIFT) & 1, - cs->halted); - } - - for(i =3D 0; i < 6; i++) { - cpu_x86_dump_seg_cache(env, f, seg_name[i], &env->segs[i]); - } - cpu_x86_dump_seg_cache(env, f, "LDT", &env->ldt); - cpu_x86_dump_seg_cache(env, f, "TR", &env->tr); - -#ifdef TARGET_X86_64 - if (env->hflags & HF_LMA_MASK) { - qemu_fprintf(f, "GDT=3D %016" PRIx64 " %08x\n", - env->gdt.base, env->gdt.limit); - qemu_fprintf(f, "IDT=3D %016" PRIx64 " %08x\n", - env->idt.base, env->idt.limit); - qemu_fprintf(f, "CR0=3D%08x CR2=3D%016" PRIx64 " CR3=3D%016" PRIx6= 4 " CR4=3D%08x\n", - (uint32_t)env->cr[0], - env->cr[2], - env->cr[3], - (uint32_t)env->cr[4]); - for(i =3D 0; i < 4; i++) - qemu_fprintf(f, "DR%d=3D%016" PRIx64 " ", i, env->dr[i]); - qemu_fprintf(f, "\nDR6=3D%016" PRIx64 " DR7=3D%016" PRIx64 "\n", - env->dr[6], env->dr[7]); - } else -#endif - { - qemu_fprintf(f, "GDT=3D %08x %08x\n", - (uint32_t)env->gdt.base, env->gdt.limit); - qemu_fprintf(f, "IDT=3D %08x %08x\n", - (uint32_t)env->idt.base, env->idt.limit); - qemu_fprintf(f, "CR0=3D%08x CR2=3D%08x CR3=3D%08x CR4=3D%08x\n", - (uint32_t)env->cr[0], - (uint32_t)env->cr[2], - (uint32_t)env->cr[3], - (uint32_t)env->cr[4]); - for(i =3D 0; i < 4; i++) { - qemu_fprintf(f, "DR%d=3D" TARGET_FMT_lx " ", i, env->dr[i]); - } - qemu_fprintf(f, "\nDR6=3D" TARGET_FMT_lx " DR7=3D" TARGET_FMT_lx "= \n", - env->dr[6], env->dr[7]); - } - if (flags & CPU_DUMP_CCOP) { - if ((unsigned)env->cc_op < CC_OP_NB) - snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->= cc_op]); - else - snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op); -#ifdef TARGET_X86_64 - if (env->hflags & HF_CS64_MASK) { - qemu_fprintf(f, "CCS=3D%016" PRIx64 " CCD=3D%016" PRIx64 " CCO= =3D%-8s\n", - env->cc_src, env->cc_dst, - cc_op_name); - } else -#endif - { - qemu_fprintf(f, "CCS=3D%08x CCD=3D%08x CCO=3D%-8s\n", - (uint32_t)env->cc_src, (uint32_t)env->cc_dst, - cc_op_name); - } - } - qemu_fprintf(f, "EFER=3D%016" PRIx64 "\n", env->efer); - if (flags & CPU_DUMP_FPU) { - int fptag; - fptag =3D 0; - for(i =3D 0; i < 8; i++) { - fptag |=3D ((!env->fptags[i]) << i); - } - update_mxcsr_from_sse_status(env); - qemu_fprintf(f, "FCW=3D%04x FSW=3D%04x [ST=3D%d] FTW=3D%02x MXCSR= =3D%08x\n", - env->fpuc, - (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11, - env->fpstt, - fptag, - env->mxcsr); - for(i=3D0;i<8;i++) { - CPU_LDoubleU u; - u.d =3D env->fpregs[i].d; - qemu_fprintf(f, "FPR%d=3D%016" PRIx64 " %04x", - i, u.l.lower, u.l.upper); - if ((i & 1) =3D=3D 1) - qemu_fprintf(f, "\n"); - else - qemu_fprintf(f, " "); - } - if (env->hflags & HF_CS64_MASK) - nb =3D 16; - else - nb =3D 8; - for(i=3D0;ixmm_regs[i].ZMM_L(3), - env->xmm_regs[i].ZMM_L(2), - env->xmm_regs[i].ZMM_L(1), - env->xmm_regs[i].ZMM_L(0)); - if ((i & 1) =3D=3D 1) - qemu_fprintf(f, "\n"); - else - qemu_fprintf(f, " "); - } - } - if (flags & CPU_DUMP_CODE) { - target_ulong base =3D env->segs[R_CS].base + env->eip; - target_ulong offs =3D MIN(env->eip, DUMP_CODE_BYTES_BACKWARD); - uint8_t code; - char codestr[3]; - - qemu_fprintf(f, "Code=3D"); - for (i =3D 0; i < DUMP_CODE_BYTES_TOTAL; i++) { - if (cpu_memory_rw_debug(cs, base - offs + i, &code, 1, 0) =3D= =3D 0) { - snprintf(codestr, sizeof(codestr), "%02x", code); - } else { - snprintf(codestr, sizeof(codestr), "??"); - } - qemu_fprintf(f, "%s%s%s%s", i > 0 ? " " : "", - i =3D=3D offs ? "<" : "", codestr, i =3D=3D offs = ? ">" : ""); - } - qemu_fprintf(f, "\n"); - } -} - /***********************************************************/ /* x86 mmu */ /* XXX: add PGE support */ diff --git a/target/i386/meson.build b/target/i386/meson.build index 750471c9f3..c4bf20b319 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -4,6 +4,7 @@ i386_ss.add(files( 'gdbstub.c', 'helper.c', 'xsave_helper.c', + 'cpu-dump.c', )) i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('= sev-stub.c')) =20 --=20 2.26.2 From nobody Mon May 20 22:41:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607676025; cv=none; d=zohomail.com; s=zohoarc; b=Op+/swlhbK46FoWJ6aQCxzYdYggONgMCNpG1+SbVP0CffznGjOi1T+mpOiaFeO0uEZkqhGetCU1cYISWTXS1jARkVFUI8148joXJ9PVZIaGPrbXjL8ksLirVVGsSnsusdABIeNsiDge4ijJvhfA/PJRLwDnLnk5dBrYrcFr6ito= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607676025; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dKkOSYuQjcweEMj1oYA3iRVIq7VlLJMvoi4Y/CZX9Ok=; b=QCwlbwQAY1B7FWzfTY6ikp+dllqQjsgrcOeKcG7hZ2FLK9+J3HtVKuh8zBYDi32RC6/hpSdVg+l9C86MiTA7PdaST337JWjhkwhamCIR6H4YGrMDg1JxfectWretvsCEdAkrXvJFA7TNdYyOGPleAN4UWCMQ67ul3lDp6tQLvJ8= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607676025976443.14198024148743; Fri, 11 Dec 2020 00:40:25 -0800 (PST) Received: from localhost ([::1]:53266 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kndyS-0001FU-Gd for importer@patchew.org; Fri, 11 Dec 2020 03:40:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42570) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqe-0008MA-2h for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:32:20 -0500 Received: from mx2.suse.de ([195.135.220.15]:34984) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqO-00028Y-CV for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:32:19 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 969F1B05C; Fri, 11 Dec 2020 08:31:52 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 10/25] i386: move TCG cpu class initialization out of helper.c Date: Fri, 11 Dec 2020 09:31:28 +0100 Message-Id: <20201211083143.14350-11-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211083143.14350-1-cfontana@suse.de> References: <20201211083143.14350-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: Claudio Fontana --- target/i386/cpu.h | 97 ++--------------------------- target/i386/tcg/helper-tcg.h | 112 ++++++++++++++++++++++++++++++++++ target/i386/tcg/tcg-cpu.h | 15 +++++ target/i386/cpu.c | 33 ++++------ target/i386/helper.c | 23 ------- target/i386/tcg/bpt_helper.c | 1 + target/i386/tcg/cc_helper.c | 1 + target/i386/tcg/excp_helper.c | 1 + target/i386/tcg/fpu_helper.c | 33 +++++----- target/i386/tcg/int_helper.c | 1 + target/i386/tcg/mem_helper.c | 1 + target/i386/tcg/misc_helper.c | 1 + target/i386/tcg/mpx_helper.c | 1 + target/i386/tcg/seg_helper.c | 1 + target/i386/tcg/smm_helper.c | 2 + target/i386/tcg/svm_helper.c | 1 + target/i386/tcg/tcg-cpu.c | 71 +++++++++++++++++++++ target/i386/tcg/translate.c | 1 + target/i386/tcg/meson.build | 1 + 19 files changed, 244 insertions(+), 153 deletions(-) create mode 100644 target/i386/tcg/helper-tcg.h create mode 100644 target/i386/tcg/tcg-cpu.h create mode 100644 target/i386/tcg/tcg-cpu.c diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d6ed45c5d7..a0d64613dc 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -31,9 +31,6 @@ =20 #define KVM_HAVE_MCE_INJECTION 1 =20 -/* Maximum instruction code size */ -#define TARGET_MAX_INSN_SIZE 16 - /* support for self modifying code even if the modified instruction is close to the modifying instruction */ #define TARGET_HAS_PRECISE_SMC @@ -1037,6 +1034,12 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; * using this information. Condition codes are not generated if they * are only needed for conditional branches. */ + +#define CC_DST (env->cc_dst) +#define CC_SRC (env->cc_src) +#define CC_SRC2 (env->cc_src2) +#define CC_OP (env->cc_op) + typedef enum { CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC =3D flags */ @@ -1765,12 +1768,6 @@ struct X86CPU { extern VMStateDescription vmstate_x86_cpu; #endif =20 -/** - * x86_cpu_do_interrupt: - * @cpu: vCPU the interrupt is to be handled by. - */ -void x86_cpu_do_interrupt(CPUState *cpu); -bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); =20 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, @@ -1793,9 +1790,6 @@ hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cp= u, vaddr addr, int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); =20 -void x86_cpu_exec_enter(CPUState *cpu); -void x86_cpu_exec_exit(CPUState *cpu); - void x86_cpu_list(void); int cpu_x86_support_mca_broadcast(CPUX86State *env); =20 @@ -1920,9 +1914,6 @@ void host_cpuid(uint32_t function, uint32_t count, void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); =20 /* helper.c */ -bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); void x86_cpu_set_a20(X86CPU *cpu, int a20_state); =20 #ifndef CONFIG_USER_ONLY @@ -1947,8 +1938,6 @@ void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t= val); void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); #endif =20 -void breakpoint_handler(CPUState *cs); - /* will be suppressed */ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); @@ -1958,16 +1947,6 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t n= ew_dr7); /* hw/pc.c */ uint64_t cpu_get_tsc(CPUX86State *env); =20 -/* XXX: This value should match the one returned by CPUID - * and in exec.c */ -# if defined(TARGET_X86_64) -# define TCG_PHYS_ADDR_BITS 40 -# else -# define TCG_PHYS_ADDR_BITS 36 -# endif - -#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS) - #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_X86_CPU @@ -1999,30 +1978,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *= env) ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; } =20 -#define CC_DST (env->cc_dst) -#define CC_SRC (env->cc_src) -#define CC_SRC2 (env->cc_src2) -#define CC_OP (env->cc_op) - -/* n must be a constant to be efficient */ -static inline target_long lshift(target_long x, int n) -{ - if (n >=3D 0) { - return x << n; - } else { - return x >> (-n); - } -} - -/* float macros */ -#define FT0 (env->ft0) -#define ST0 (env->fpregs[env->fpstt].d) -#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) -#define ST1 ST(1) - -/* translate.c */ -void tcg_x86_init(void); - typedef CPUX86State CPUArchState; typedef X86CPU ArchCPU; =20 @@ -2052,19 +2007,6 @@ void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, i= nt bank, uint64_t status, uint64_t mcg_status, uint64_t add= r, uint64_t misc, int flags); =20 -/* excp_helper.c */ -void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); -void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_inde= x, - uintptr_t retaddr); -void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_ind= ex, - int error_code); -void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_= index, - int error_code, uintptr_t retadd= r); -void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_in= t, - int error_code, int next_eip_addend); - -/* cc_helper.c */ -extern const uint8_t parity_table[256]; uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); =20 static inline uint32_t cpu_compute_eflags(CPUX86State *env) @@ -2076,18 +2018,6 @@ static inline uint32_t cpu_compute_eflags(CPUX86Stat= e *env) return eflags; } =20 -/* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS - * after generating a call to a helper that uses this. - */ -static inline void cpu_load_eflags(CPUX86State *env, int eflags, - int update_mask) -{ - CC_SRC =3D eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); - CC_OP =3D CC_OP_EFLAGS; - env->df =3D 1 - (2 * ((eflags >> 10) & 1)); - env->eflags =3D (env->eflags & ~update_mask) | - (eflags & update_mask) | 0x2; -} =20 /* load efer and update the corresponding hflags. XXX: do consistency checks with cpuid bits? */ @@ -2176,16 +2106,6 @@ void helper_lock_init(void); /* svm_helper.c */ void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, uint64_t param, uintptr_t retaddr); -void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, - uint64_t exit_info_1, uintptr_t retaddr); -void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1); - -/* seg_helper.c */ -void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); - -/* smm_helper.c */ -void do_smm_enter(X86CPU *cpu); - /* apic.c */ void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, @@ -2224,11 +2144,6 @@ typedef int X86CPUVersion; */ void x86_cpu_set_default_version(X86CPUVersion version); =20 -/* Return name of 32-bit register, from a R_* constant */ -const char *get_register_name_32(unsigned int reg); - -void enable_compat_apic_id_mode(void); - #define APIC_DEFAULT_ADDRESS 0xfee00000 #define APIC_SPACE_SIZE 0x100000 =20 diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h new file mode 100644 index 0000000000..57b4391a7d --- /dev/null +++ b/target/i386/tcg/helper-tcg.h @@ -0,0 +1,112 @@ +/* + * TCG specific prototypes for helpers + * + * Copyright (c) 2003 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef I386_HELPER_TCG_H +#define I386_HELPER_TCG_H + +#include "exec/exec-all.h" + +/* Maximum instruction code size */ +#define TARGET_MAX_INSN_SIZE 16 + +/* + * XXX: This value should match the one returned by CPUID + * and in exec.c + */ +# if defined(TARGET_X86_64) +# define TCG_PHYS_ADDR_BITS 40 +# else +# define TCG_PHYS_ADDR_BITS 36 +# endif + +#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS) + +/** + * x86_cpu_do_interrupt: + * @cpu: vCPU the interrupt is to be handled by. + */ +void x86_cpu_do_interrupt(CPUState *cpu); +bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); + +/* helper.c */ +bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + +void breakpoint_handler(CPUState *cs); + +/* n must be a constant to be efficient */ +static inline target_long lshift(target_long x, int n) +{ + if (n >=3D 0) { + return x << n; + } else { + return x >> (-n); + } +} + +/* float macros */ +#define FT0 (env->ft0) +#define ST0 (env->fpregs[env->fpstt].d) +#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) +#define ST1 ST(1) + +/* translate.c */ +void tcg_x86_init(void); + +/* excp_helper.c */ +void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); +void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_inde= x, + uintptr_t retaddr); +void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_ind= ex, + int error_code); +void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_= index, + int error_code, uintptr_t retadd= r); +void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_in= t, + int error_code, int next_eip_addend); + +/* cc_helper.c */ +extern const uint8_t parity_table[256]; + +/* + * NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS + * after generating a call to a helper that uses this. + */ +static inline void cpu_load_eflags(CPUX86State *env, int eflags, + int update_mask) +{ + CC_SRC =3D eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); + CC_OP =3D CC_OP_EFLAGS; + env->df =3D 1 - (2 * ((eflags >> 10) & 1)); + env->eflags =3D (env->eflags & ~update_mask) | + (eflags & update_mask) | 0x2; +} + +/* svm_helper.c */ +void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, + uint64_t exit_info_1, uintptr_t retaddr); +void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1); + +/* seg_helper.c */ +void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); + +/* smm_helper.c */ +void do_smm_enter(X86CPU *cpu); + +#endif /* I386_HELPER_TCG_H */ diff --git a/target/i386/tcg/tcg-cpu.h b/target/i386/tcg/tcg-cpu.h new file mode 100644 index 0000000000..81f02e562e --- /dev/null +++ b/target/i386/tcg/tcg-cpu.h @@ -0,0 +1,15 @@ +/* + * i386 TCG CPU class initialization + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef TCG_CPU_H +#define TCG_CPU_H + +void tcg_cpu_common_class_init(CPUClass *cc); + +#endif /* TCG_CPU_H */ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b9bd249c8f..f0aa6d1841 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -24,6 +24,8 @@ #include "qemu/qemu-print.h" =20 #include "cpu.h" +#include "tcg/tcg-cpu.h" +#include "tcg/helper-tcg.h" #include "exec/exec-all.h" #include "sysemu/kvm.h" #include "sysemu/reset.h" @@ -1495,7 +1497,8 @@ static inline uint64_t x86_cpu_xsave_components(X86CP= U *cpu) cpu->env.features[FEAT_XSAVE_COMP_LO]; } =20 -const char *get_register_name_32(unsigned int reg) +/* Return name of 32-bit register, from a R_* constant */ +static const char *get_register_name_32(unsigned int reg) { if (reg >=3D CPU_NB_REGS32) { return NULL; @@ -7012,13 +7015,6 @@ static void x86_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.eip =3D value; } =20 -static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) -{ - X86CPU *cpu =3D X86_CPU(cs); - - cpu->env.eip =3D tb->pc - tb->cs_base; -} - int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) { X86CPU *cpu =3D X86_CPU(cs); @@ -7252,17 +7248,18 @@ static void x86_cpu_common_class_init(ObjectClass *= oc, void *data) cc->class_by_name =3D x86_cpu_class_by_name; cc->parse_features =3D x86_cpu_parse_featurestr; cc->has_work =3D x86_cpu_has_work; + #ifdef CONFIG_TCG - cc->do_interrupt =3D x86_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D x86_cpu_exec_interrupt; -#endif + tcg_cpu_common_class_init(cc); +#endif /* CONFIG_TCG */ + cc->dump_state =3D x86_cpu_dump_state; cc->set_pc =3D x86_cpu_set_pc; - cc->synchronize_from_tb =3D x86_cpu_synchronize_from_tb; cc->gdb_read_register =3D x86_cpu_gdb_read_register; cc->gdb_write_register =3D x86_cpu_gdb_write_register; cc->get_arch_id =3D x86_cpu_get_arch_id; cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; + #ifndef CONFIG_USER_ONLY cc->asidx_from_attrs =3D x86_asidx_from_attrs; cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; @@ -7273,7 +7270,8 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->write_elf32_note =3D x86_cpu_write_elf32_note; cc->write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote; cc->vmsd =3D &vmstate_x86_cpu; -#endif +#endif /* !CONFIG_USER_ONLY */ + cc->gdb_arch_name =3D x86_gdb_arch_name; #ifdef TARGET_X86_64 cc->gdb_core_xml_file =3D "i386-64bit.xml"; @@ -7281,15 +7279,6 @@ static void x86_cpu_common_class_init(ObjectClass *o= c, void *data) #else cc->gdb_core_xml_file =3D "i386-32bit.xml"; cc->gdb_num_core_regs =3D 50; -#endif -#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) - cc->debug_excp_handler =3D breakpoint_handler; -#endif - cc->cpu_exec_enter =3D x86_cpu_exec_enter; - cc->cpu_exec_exit =3D x86_cpu_exec_exit; -#ifdef CONFIG_TCG - cc->tcg_initialize =3D tcg_x86_init; - cc->tlb_fill =3D x86_cpu_tlb_fill; #endif cc->disas_set_info =3D x86_disas_set_info; =20 diff --git a/target/i386/helper.c b/target/i386/helper.c index 6e7e0f507c..6bb0c53182 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -24,10 +24,8 @@ #include "sysemu/runstate.h" #include "kvm/kvm_i386.h" #ifndef CONFIG_USER_ONLY -#include "sysemu/tcg.h" #include "sysemu/hw_accel.h" #include "monitor/monitor.h" -#include "hw/i386/apic_internal.h" #endif =20 void cpu_sync_bndcs_hflags(CPUX86State *env) @@ -572,27 +570,6 @@ void do_cpu_sipi(X86CPU *cpu) } #endif =20 -/* Frob eflags into and out of the CPU temporary format. */ - -void x86_cpu_exec_enter(CPUState *cs) -{ - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - - CC_SRC =3D env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); - env->df =3D 1 - (2 * ((env->eflags >> 10) & 1)); - CC_OP =3D CC_OP_EFLAGS; - env->eflags &=3D ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); -} - -void x86_cpu_exec_exit(CPUState *cs) -{ - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - - env->eflags =3D cpu_compute_eflags(env); -} - #ifndef CONFIG_USER_ONLY uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr) { diff --git a/target/i386/tcg/bpt_helper.c b/target/i386/tcg/bpt_helper.c index e6cc2921e2..979230ac12 100644 --- a/target/i386/tcg/bpt_helper.c +++ b/target/i386/tcg/bpt_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" +#include "helper-tcg.h" =20 =20 #ifndef CONFIG_USER_ONLY diff --git a/target/i386/tcg/cc_helper.c b/target/i386/tcg/cc_helper.c index 924dd3cd57..cc7ea9e8b9 100644 --- a/target/i386/tcg/cc_helper.c +++ b/target/i386/tcg/cc_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" +#include "helper-tcg.h" =20 const uint8_t parity_table[256] =3D { CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, diff --git a/target/i386/tcg/excp_helper.c b/target/i386/tcg/excp_helper.c index 191471749f..a0f44431fe 100644 --- a/target/i386/tcg/excp_helper.c +++ b/target/i386/tcg/excp_helper.c @@ -23,6 +23,7 @@ #include "qemu/log.h" #include "sysemu/runstate.h" #include "exec/helper-proto.h" +#include "helper-tcg.h" =20 void helper_raise_interrupt(CPUX86State *env, int intno, int next_eip_adde= nd) { diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 03b35443a6..13f31b6ac7 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -26,6 +26,7 @@ #include "exec/cpu_ldst.h" #include "fpu/softfloat.h" #include "fpu/softfloat-macros.h" +#include "helper-tcg.h" =20 #ifdef CONFIG_SOFTMMU #include "hw/irq.h" @@ -2986,23 +2987,21 @@ void update_mxcsr_status(CPUX86State *env) =20 void update_mxcsr_from_sse_status(CPUX86State *env) { - if (tcg_enabled()) { - uint8_t flags =3D get_float_exception_flags(&env->sse_status); - /* - * The MXCSR denormal flag has opposite semantics to - * float_flag_input_denormal (the softfloat code sets that flag - * only when flushing input denormals to zero, but SSE sets it - * only when not flushing them to zero), so is not converted - * here. - */ - env->mxcsr |=3D ((flags & float_flag_invalid ? FPUS_IE : 0) | - (flags & float_flag_divbyzero ? FPUS_ZE : 0) | - (flags & float_flag_overflow ? FPUS_OE : 0) | - (flags & float_flag_underflow ? FPUS_UE : 0) | - (flags & float_flag_inexact ? FPUS_PE : 0) | - (flags & float_flag_output_denormal ? FPUS_UE | FPU= S_PE : - 0)); - } + uint8_t flags =3D get_float_exception_flags(&env->sse_status); + /* + * The MXCSR denormal flag has opposite semantics to + * float_flag_input_denormal (the softfloat code sets that flag + * only when flushing input denormals to zero, but SSE sets it + * only when not flushing them to zero), so is not converted + * here. + */ + env->mxcsr |=3D ((flags & float_flag_invalid ? FPUS_IE : 0) | + (flags & float_flag_divbyzero ? FPUS_ZE : 0) | + (flags & float_flag_overflow ? FPUS_OE : 0) | + (flags & float_flag_underflow ? FPUS_UE : 0) | + (flags & float_flag_inexact ? FPUS_PE : 0) | + (flags & float_flag_output_denormal ? FPUS_UE | FPUS_PE= : + 0)); } =20 void helper_update_mxcsr(CPUX86State *env) diff --git a/target/i386/tcg/int_helper.c b/target/i386/tcg/int_helper.c index 4f89436b53..87fa7280ee 100644 --- a/target/i386/tcg/int_helper.c +++ b/target/i386/tcg/int_helper.c @@ -24,6 +24,7 @@ #include "exec/helper-proto.h" #include "qapi/error.h" #include "qemu/guest-random.h" +#include "helper-tcg.h" =20 //#define DEBUG_MULDIV =20 diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c index 21ca3e3e88..e5cd2de1bf 100644 --- a/target/i386/tcg/mem_helper.c +++ b/target/i386/tcg/mem_helper.c @@ -25,6 +25,7 @@ #include "qemu/int128.h" #include "qemu/atomic128.h" #include "tcg/tcg.h" +#include "helper-tcg.h" =20 void helper_cmpxchg8b_unlocked(CPUX86State *env, target_ulong a0) { diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c index ae259d9145..c99370e5e3 100644 --- a/target/i386/tcg/misc_helper.c +++ b/target/i386/tcg/misc_helper.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "exec/address-spaces.h" +#include "helper-tcg.h" =20 void helper_outb(CPUX86State *env, uint32_t port, uint32_t data) { diff --git a/target/i386/tcg/mpx_helper.c b/target/i386/tcg/mpx_helper.c index fd966174b4..22423eedcd 100644 --- a/target/i386/tcg/mpx_helper.c +++ b/target/i386/tcg/mpx_helper.c @@ -22,6 +22,7 @@ #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "exec/exec-all.h" +#include "helper-tcg.h" =20 =20 void helper_bndck(CPUX86State *env, uint32_t fail) diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index 09b6554660..ed3e04a187 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -25,6 +25,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "exec/log.h" +#include "helper-tcg.h" =20 //#define DEBUG_PCALL =20 diff --git a/target/i386/tcg/smm_helper.c b/target/i386/tcg/smm_helper.c index d20e8edfdf..62d027abd3 100644 --- a/target/i386/tcg/smm_helper.c +++ b/target/i386/tcg/smm_helper.c @@ -22,6 +22,8 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/log.h" +#include "helper-tcg.h" + =20 /* SMM support */ =20 diff --git a/target/i386/tcg/svm_helper.c b/target/i386/tcg/svm_helper.c index 38931586e5..097bb9b83d 100644 --- a/target/i386/tcg/svm_helper.c +++ b/target/i386/tcg/svm_helper.c @@ -22,6 +22,7 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" +#include "helper-tcg.h" =20 /* Secure Virtual Machine helpers */ =20 diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c new file mode 100644 index 0000000000..628dd29fe7 --- /dev/null +++ b/target/i386/tcg/tcg-cpu.c @@ -0,0 +1,71 @@ +/* + * i386 TCG cpu class initialization + * + * Copyright (c) 2003 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "tcg-cpu.h" +#include "exec/exec-all.h" +#include "sysemu/runstate.h" +#include "helper-tcg.h" + +#if !defined(CONFIG_USER_ONLY) +#include "hw/i386/apic.h" +#endif + +/* Frob eflags into and out of the CPU temporary format. */ + +static void x86_cpu_exec_enter(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + + CC_SRC =3D env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); + env->df =3D 1 - (2 * ((env->eflags >> 10) & 1)); + CC_OP =3D CC_OP_EFLAGS; + env->eflags &=3D ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); +} + +static void x86_cpu_exec_exit(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + + env->eflags =3D cpu_compute_eflags(env); +} + +static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +{ + X86CPU *cpu =3D X86_CPU(cs); + + cpu->env.eip =3D tb->pc - tb->cs_base; +} + +void tcg_cpu_common_class_init(CPUClass *cc) +{ + cc->do_interrupt =3D x86_cpu_do_interrupt; + cc->cpu_exec_interrupt =3D x86_cpu_exec_interrupt; + cc->synchronize_from_tb =3D x86_cpu_synchronize_from_tb; + cc->cpu_exec_enter =3D x86_cpu_exec_enter; + cc->cpu_exec_exit =3D x86_cpu_exec_exit; + cc->tcg_initialize =3D tcg_x86_init; + cc->tlb_fill =3D x86_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY + cc->debug_excp_handler =3D breakpoint_handler; +#endif +} diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 4c57307e42..5988ea0289 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -28,6 +28,7 @@ =20 #include "exec/helper-proto.h" #include "exec/helper-gen.h" +#include "helper-tcg.h" =20 #include "trace-tcg.h" #include "exec/log.h" diff --git a/target/i386/tcg/meson.build b/target/i386/tcg/meson.build index 02794226c2..6a1a73cdbf 100644 --- a/target/i386/tcg/meson.build +++ b/target/i386/tcg/meson.build @@ -10,4 +10,5 @@ i386_ss.add(when: 'CONFIG_TCG', if_true: files( 'seg_helper.c', 'smm_helper.c', 'svm_helper.c', + 'tcg-cpu.c', 'translate.c'), if_false: files('tcg-stub.c')) --=20 2.26.2 From nobody Mon May 20 22:41:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 11 Dec 2020 00:36:29 -0800 (PST) Received: from localhost ([::1]:42354 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kndud-00051V-RF for importer@patchew.org; Fri, 11 Dec 2020 03:36:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42524) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqY-0008Gw-AM for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:32:14 -0500 Received: from mx2.suse.de ([195.135.220.15]:35026) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqO-00028i-IL for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:32:13 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 4BFECB04C; Fri, 11 Dec 2020 08:31:53 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 11/25] tcg: cpu_exec_{enter,exit} helpers Date: Fri, 11 Dec 2020 09:31:29 +0100 Message-Id: <20201211083143.14350-12-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211083143.14350-1-cfontana@suse.de> References: <20201211083143.14350-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; 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Cota" , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Eduardo Habkost Move invocation of CPUClass.cpu_exec_*() to separate helpers, to make it easier to refactor that code later. Signed-off-by: Eduardo Habkost Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- accel/tcg/cpu-exec.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 58aea605d8..8d31145ad2 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -236,9 +236,22 @@ static void cpu_exec_nocache(CPUState *cpu, int max_cy= cles, } #endif =20 +static void cpu_exec_enter(CPUState *cpu) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + cc->cpu_exec_enter(cpu); +} + +static void cpu_exec_exit(CPUState *cpu) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + cc->cpu_exec_exit(cpu); +} + void cpu_exec_step_atomic(CPUState *cpu) { - CPUClass *cc =3D CPU_GET_CLASS(cpu); TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; @@ -257,11 +270,11 @@ void cpu_exec_step_atomic(CPUState *cpu) =20 /* Since we got here, we know that parallel_cpus must be true. */ parallel_cpus =3D false; - cc->cpu_exec_enter(cpu); + cpu_exec_enter(cpu); /* execute the generated code */ trace_exec_tb(tb, pc); cpu_tb_exec(cpu, tb); - cc->cpu_exec_exit(cpu); + cpu_exec_exit(cpu); } else { /* * The mmap_lock is dropped by tb_gen_code if it runs out of @@ -713,7 +726,7 @@ int cpu_exec(CPUState *cpu) =20 rcu_read_lock(); =20 - cc->cpu_exec_enter(cpu); + cpu_exec_enter(cpu); =20 /* Calculate difference between guest clock and host clock. * This delay includes the delay of the last cycle, so @@ -775,7 +788,7 @@ int cpu_exec(CPUState *cpu) } } =20 - cc->cpu_exec_exit(cpu); + cpu_exec_exit(cpu); rcu_read_unlock(); =20 return ret; --=20 2.26.2 From nobody Mon May 20 22:41:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607676136; cv=none; d=zohomail.com; s=zohoarc; b=U/Wzo5Hz0HUEXFYkRW+GHOEvvWxVaMtDcaxacrJBj4O3qRbUrEh03q0v45zrfuN3zuylVhcvapqcWkxJFPqhUhg2ZvghFKC9v0445ANp3kr4CMLDhyqiGJ7f83JMPEqOlkHn5QKiiyb9uIUlD4UrfKrLXdGMnVHfGfc0RGGIw5s= ARC-Message-Signature: i=1; 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Fri, 11 Dec 2020 03:42:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42510) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqW-0008Et-Q2 for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:32:12 -0500 Received: from mx2.suse.de ([195.135.220.15]:35058) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqP-00029J-I1 for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:32:10 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 0A1D3AFF9; Fri, 11 Dec 2020 08:31:54 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 12/25] tcg: make CPUClass.cpu_exec_* optional Date: Fri, 11 Dec 2020 09:31:30 +0100 Message-Id: <20201211083143.14350-13-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211083143.14350-1-cfontana@suse.de> References: <20201211083143.14350-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Colin Xu , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Eduardo Habkost This will let us simplify the code that initializes CPU class methods, when we move cpu_exec_*() to a separate struct. Signed-off-by: Eduardo Habkost Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e --- accel/tcg/cpu-exec.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 8d31145ad2..890b88861a 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -240,14 +240,18 @@ static void cpu_exec_enter(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - cc->cpu_exec_enter(cpu); + if (cc->cpu_exec_enter) { + cc->cpu_exec_enter(cpu); + } } =20 static void cpu_exec_exit(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - cc->cpu_exec_exit(cpu); + if (cc->cpu_exec_exit) { + cc->cpu_exec_exit(cpu); + } } =20 void cpu_exec_step_atomic(CPUState *cpu) @@ -619,7 +623,8 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, True when it is, and we should restart on a new TB, and via longjmp via cpu_loop_exit. */ else { - if (cc->cpu_exec_interrupt(cpu, interrupt_request)) { + if (cc->cpu_exec_interrupt && + cc->cpu_exec_interrupt(cpu, interrupt_request)) { if (need_replay_interrupt(interrupt_request)) { replay_interrupt(); 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Fri, 11 Dec 2020 08:31:54 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 13/25] tcg: Make CPUClass.debug_excp_handler optional Date: Fri, 11 Dec 2020 09:31:31 +0100 Message-Id: <20201211083143.14350-14-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211083143.14350-1-cfontana@suse.de> References: <20201211083143.14350-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Colin Xu , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Eduardo Habkost Signed-off-by: Eduardo Habkost Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e --- accel/tcg/cpu-exec.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 890b88861a..64cba89356 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -482,7 +482,9 @@ static inline void cpu_handle_debug_exception(CPUState = *cpu) } } =20 - cc->debug_excp_handler(cpu); + if (cc->debug_excp_handler) { + cc->debug_excp_handler(cpu); + } } =20 static inline bool cpu_handle_exception(CPUState *cpu, int *ret) --=20 2.26.2 From nobody Mon May 20 22:41:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607676440; cv=none; d=zohomail.com; s=zohoarc; b=UC9QrOAUG52PyCJXT+XMW07Rq3wKuXwjcIiWvl0mhApds4OcDmRuwu+kUhulMmK3eGLymDpeuLayk6Jeh8C+FE8BMKZ/0DsbaHLYUHr35elaUvE4xSrhKEV9lpSdDf0Mu3N2gGzO7AZnEp3NuNOisMod1AnCuIoRdm3b1V0y/2o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607676440; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5Ia0mdn1ZKmDii1SSGmj3tauOKXHXE8csPa34Yp4b9U=; b=YcTcA+tVhLrxhx/GISWX5Nch/PeMNGkeWa4WAT1IvzRjAHGBXtQ77pDhqtMW7THZKw/TV4JT/yr9OG3Jq9mP+D0gMVClGLdupr4SSp6olKBcaB1VEzuwmBLqMVsFibPZ/TgOpNg5NYW4ZYt1lhdBGzzWeHiUt+qkuYhh3qENw70= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607676440692157.53920671646893; Fri, 11 Dec 2020 00:47:20 -0800 (PST) Received: from localhost ([::1]:44794 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kne59-0001P5-Br for importer@patchew.org; Fri, 11 Dec 2020 03:47:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42568) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqe-0008Lt-0p for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:32:20 -0500 Received: from mx2.suse.de ([195.135.220.15]:35142) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqR-00029c-JJ for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:32:19 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 797D3B173; Fri, 11 Dec 2020 08:31:55 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 14/25] cpu: Remove unnecessary noop methods Date: Fri, 11 Dec 2020 09:31:32 +0100 Message-Id: <20201211083143.14350-15-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211083143.14350-1-cfontana@suse.de> References: <20201211083143.14350-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Colin Xu , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Eduardo Habkost Signed-off-by: Eduardo Habkost Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/core/cpu.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 576fa1d7ba..994a12cb35 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -199,15 +199,6 @@ static bool cpu_common_virtio_is_big_endian(CPUState *= cpu) return target_words_bigendian(); } =20 -static void cpu_common_noop(CPUState *cpu) -{ -} - -static bool cpu_common_exec_interrupt(CPUState *cpu, int int_req) -{ - return false; -} - #if !defined(CONFIG_USER_ONLY) GuestPanicInformation *cpu_get_crash_info(CPUState *cpu) { @@ -410,11 +401,7 @@ static void cpu_class_init(ObjectClass *klass, void *d= ata) k->gdb_read_register =3D cpu_common_gdb_read_register; k->gdb_write_register =3D cpu_common_gdb_write_register; k->virtio_is_big_endian =3D cpu_common_virtio_is_big_endian; - k->debug_excp_handler =3D cpu_common_noop; k->debug_check_watchpoint =3D cpu_common_debug_check_watchpoint; - k->cpu_exec_enter =3D cpu_common_noop; - k->cpu_exec_exit =3D cpu_common_noop; - k->cpu_exec_interrupt =3D cpu_common_exec_interrupt; k->adjust_watchpoint_address =3D cpu_adjust_watchpoint_address; set_bit(DEVICE_CATEGORY_CPU, dc->categories); dc->realize =3D cpu_common_realizefn; --=20 2.26.2 From nobody Mon May 20 22:41:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607676268; cv=none; d=zohomail.com; s=zohoarc; b=EhIRHtdZz3ern7ygxxPrRrzmuSc6xA/jVOOVdTYuX+jjoQCyPnCREHQoDmdpXQwAGLIem88nqvtZT07JBDn/LXDzo/cgY3UYAlo0oZ1Y/Mdarb/9YHvNC6iV5zlkdldONoMS1bdkJd9LXZNm6KEzQYiTN7+mehmuKOg/dhqg+dU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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Fri, 11 Dec 2020 03:32:17 -0500 Received: from mx2.suse.de ([195.135.220.15]:35174) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqR-00029g-JL for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:32:15 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 35E7BB13A; Fri, 11 Dec 2020 08:31:56 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 15/25] cpu: Introduce TCGCpuOperations struct Date: Fri, 11 Dec 2020 09:31:33 +0100 Message-Id: <20201211083143.14350-16-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211083143.14350-1-cfontana@suse.de> References: <20201211083143.14350-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Colin Xu , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Eduardo Habkost The TCG-specific CPU methods will be moved to a separate struct, to make it easier to move accel-specific code outside generic CPU code in the future. Start by moving tcg_initialize(). The new CPUClass.tcg_opts field may eventually become a pointer, but keep it an embedded struct for now, to make code conversion easier. Signed-off-by: Eduardo Habkost [claudio: make the tcg code build for CONFIG_TCG only] Signed-off-by: Claudio Fontana Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 9 ++++++++- include/hw/core/tcg-cpu-ops.h | 25 +++++++++++++++++++++++++ cpu.c | 6 +++++- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/avr/cpu.c | 2 +- target/cris/cpu.c | 12 ++++++------ target/hppa/cpu.c | 2 +- target/i386/tcg/tcg-cpu.c | 2 +- target/lm32/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/moxie/cpu.c | 2 +- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tilegx/cpu.c | 2 +- target/tricore/cpu.c | 2 +- target/unicore32/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- MAINTAINERS | 1 + target/ppc/translate_init.c.inc | 2 +- 27 files changed, 67 insertions(+), 30 deletions(-) create mode 100644 include/hw/core/tcg-cpu-ops.h diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 3d92c967ff..c93b08a0fb 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -76,6 +76,10 @@ typedef struct CPUWatchpoint CPUWatchpoint; =20 struct TranslationBlock; =20 +#ifdef CONFIG_TCG +#include "tcg-cpu-ops.h" +#endif /* CONFIG_TCG */ + /** * CPUClass: * @class_by_name: Callback to map -cpu command line model name to an @@ -221,12 +225,15 @@ struct CPUClass { =20 void (*disas_set_info)(CPUState *cpu, disassemble_info *info); vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len); - void (*tcg_initialize)(void); =20 const char *deprecation_note; /* Keep non-pointer data at the end to minimize holes. */ int gdb_num_core_regs; bool gdb_stop_before_watchpoint; + +#ifdef CONFIG_TCG + TcgCpuOperations tcg_ops; +#endif /* CONFIG_TCG */ }; =20 /* diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h new file mode 100644 index 0000000000..4475ef0996 --- /dev/null +++ b/include/hw/core/tcg-cpu-ops.h @@ -0,0 +1,25 @@ +/* + * TCG-Specific operations that are not meaningful for hardware accelerato= rs + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef TCG_CPU_OPS_H +#define TCG_CPU_OPS_H + +/** + * struct TcgCpuOperations: TCG operations specific to a CPU class + */ +typedef struct TcgCpuOperations { + /** + * @initialize: Initalize TCG state + * + * Called when the first CPU is realized. + */ + void (*initialize)(void); +} TcgCpuOperations; + +#endif /* TCG_CPU_OPS_H */ diff --git a/cpu.c b/cpu.c index 0be5dcb6f3..27ad096cc4 100644 --- a/cpu.c +++ b/cpu.c @@ -174,14 +174,18 @@ void cpu_exec_initfn(CPUState *cpu) void cpu_exec_realizefn(CPUState *cpu, Error **errp) { CPUClass *cc =3D CPU_GET_CLASS(cpu); +#ifdef CONFIG_TCG static bool tcg_target_initialized; +#endif /* CONFIG_TCG */ =20 cpu_list_add(cpu); =20 +#ifdef CONFIG_TCG if (tcg_enabled() && !tcg_target_initialized) { tcg_target_initialized =3D true; - cc->tcg_initialize(); + cc->tcg_ops.initialize(); } +#endif /* CONFIG_TCG */ tlb_init(cpu); =20 qemu_plugin_vcpu_init_hook(cpu); diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index b3fd6643e8..d66f0351a9 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -231,7 +231,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) dc->vmsd =3D &vmstate_alpha_cpu; #endif cc->disas_set_info =3D alpha_cpu_disas_set_info; - cc->tcg_initialize =3D alpha_translate_init; + cc->tcg_ops.initialize =3D alpha_translate_init; =20 cc->gdb_num_core_regs =3D 67; } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 07492e9f9a..1fa9382a7c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2261,7 +2261,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_stop_before_watchpoint =3D true; cc->disas_set_info =3D arm_disas_set_info; #ifdef CONFIG_TCG - cc->tcg_initialize =3D arm_translate_init; + cc->tcg_ops.initialize =3D arm_translate_init; cc->tlb_fill =3D arm_cpu_tlb_fill; cc->debug_excp_handler =3D arm_debug_excp_handler; cc->debug_check_watchpoint =3D arm_debug_check_watchpoint; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 5d9c4ad5bf..94306a2aa0 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -206,7 +206,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->tlb_fill =3D avr_cpu_tlb_fill; cc->vmsd =3D &vms_avr_cpu; cc->disas_set_info =3D avr_cpu_disas_set_info; - cc->tcg_initialize =3D avr_cpu_tcg_init; + cc->tcg_ops.initialize =3D avr_cpu_tcg_init; cc->synchronize_from_tb =3D avr_cpu_synchronize_from_tb; cc->gdb_read_register =3D avr_cpu_gdb_read_register; cc->gdb_write_register =3D avr_cpu_gdb_write_register; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index cff6b9eabf..4328f8e6c9 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -201,7 +201,7 @@ static void crisv8_cpu_class_init(ObjectClass *oc, void= *data) ccc->vr =3D 8; cc->do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; - cc->tcg_initialize =3D cris_initialize_crisv10_tcg; + cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; } =20 static void crisv9_cpu_class_init(ObjectClass *oc, void *data) @@ -212,7 +212,7 @@ static void crisv9_cpu_class_init(ObjectClass *oc, void= *data) ccc->vr =3D 9; cc->do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; - cc->tcg_initialize =3D cris_initialize_crisv10_tcg; + cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; } =20 static void crisv10_cpu_class_init(ObjectClass *oc, void *data) @@ -223,7 +223,7 @@ static void crisv10_cpu_class_init(ObjectClass *oc, voi= d *data) ccc->vr =3D 10; cc->do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; - cc->tcg_initialize =3D cris_initialize_crisv10_tcg; + cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; } =20 static void crisv11_cpu_class_init(ObjectClass *oc, void *data) @@ -234,7 +234,7 @@ static void crisv11_cpu_class_init(ObjectClass *oc, voi= d *data) ccc->vr =3D 11; cc->do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; - cc->tcg_initialize =3D cris_initialize_crisv10_tcg; + cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; } =20 static void crisv17_cpu_class_init(ObjectClass *oc, void *data) @@ -245,7 +245,7 @@ static void crisv17_cpu_class_init(ObjectClass *oc, voi= d *data) ccc->vr =3D 17; cc->do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; - cc->tcg_initialize =3D cris_initialize_crisv10_tcg; + cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; } =20 static void crisv32_cpu_class_init(ObjectClass *oc, void *data) @@ -284,7 +284,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_stop_before_watchpoint =3D true; =20 cc->disas_set_info =3D cris_disas_set_info; - cc->tcg_initialize =3D cris_initialize_tcg; + cc->tcg_ops.initialize =3D cris_initialize_tcg; } =20 #define DEFINE_CRIS_CPU_TYPE(cpu_model, initfn) \ diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 71b6aca45d..4c778966c2 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -153,7 +153,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) #endif cc->do_unaligned_access =3D hppa_cpu_do_unaligned_access; cc->disas_set_info =3D hppa_cpu_disas_set_info; - cc->tcg_initialize =3D hppa_translate_init; + cc->tcg_ops.initialize =3D hppa_translate_init; =20 cc->gdb_num_core_regs =3D 128; } diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 628dd29fe7..1f2a3e881a 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -63,7 +63,7 @@ void tcg_cpu_common_class_init(CPUClass *cc) cc->synchronize_from_tb =3D x86_cpu_synchronize_from_tb; cc->cpu_exec_enter =3D x86_cpu_exec_enter; cc->cpu_exec_exit =3D x86_cpu_exec_exit; - cc->tcg_initialize =3D tcg_x86_init; + cc->tcg_ops.initialize =3D tcg_x86_init; cc->tlb_fill =3D x86_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->debug_excp_handler =3D breakpoint_handler; diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index c50ad5fa15..ef795b81a4 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -237,7 +237,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_stop_before_watchpoint =3D true; cc->debug_excp_handler =3D lm32_debug_excp_handler; cc->disas_set_info =3D lm32_cpu_disas_set_info; - cc->tcg_initialize =3D lm32_translate_init; + cc->tcg_ops.initialize =3D lm32_translate_init; } =20 #define DEFINE_LM32_CPU_TYPE(cpu_model, initfn) \ diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 72c545149e..b66d86c353 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -289,7 +289,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D m68k_cpu_disas_set_info; - cc->tcg_initialize =3D m68k_tcg_init; + cc->tcg_ops.initialize =3D m68k_tcg_init; =20 cc->gdb_num_core_regs =3D 18; =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 9b2482159d..bc10518fa3 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -335,7 +335,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->gdb_num_core_regs =3D 32 + 27; =20 cc->disas_set_info =3D mb_disas_set_info; - cc->tcg_initialize =3D mb_tcg_init; + cc->tcg_ops.initialize =3D mb_tcg_init; } =20 static const TypeInfo mb_cpu_type_info =3D { diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 76d50b00b4..bc48573763 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -249,7 +249,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) #endif cc->disas_set_info =3D mips_cpu_disas_set_info; #ifdef CONFIG_TCG - cc->tcg_initialize =3D mips_tcg_init; + cc->tcg_ops.initialize =3D mips_tcg_init; cc->tlb_fill =3D mips_cpu_tlb_fill; #endif =20 diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 6e0443ccb7..224cfc8361 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -116,7 +116,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) cc->vmsd =3D &vmstate_moxie_cpu; #endif cc->disas_set_info =3D moxie_cpu_disas_set_info; - cc->tcg_initialize =3D moxie_translate_init; + cc->tcg_ops.initialize =3D moxie_translate_init; } =20 static void moxielite_initfn(Object *obj) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 8f7011fcb9..29c9c6f634 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -205,7 +205,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D nios2_cpu_gdb_read_register; cc->gdb_write_register =3D nios2_cpu_gdb_write_register; cc->gdb_num_core_regs =3D 49; - cc->tcg_initialize =3D nios2_tcg_init; + cc->tcg_ops.initialize =3D nios2_tcg_init; } =20 static const TypeInfo nios2_cpu_type_info =3D { diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 5528c0918f..e442f4f97c 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -166,7 +166,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) dc->vmsd =3D &vmstate_openrisc_cpu; #endif cc->gdb_num_core_regs =3D 32 + 3; - cc->tcg_initialize =3D openrisc_translate_init; + cc->tcg_ops.initialize =3D openrisc_translate_init; cc->disas_set_info =3D openrisc_disas_set_info; } =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6a0264fc6b..a52e0ce466 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -562,7 +562,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->vmsd =3D &vmstate_riscv_cpu; #endif #ifdef CONFIG_TCG - cc->tcg_initialize =3D riscv_translate_init; + cc->tcg_ops.initialize =3D riscv_translate_init; cc->tlb_fill =3D riscv_cpu_tlb_fill; #endif device_class_set_props(dc, riscv_cpu_properties); diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 23ee17a701..a701a09b11 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -194,7 +194,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) cc->gdb_write_register =3D rx_cpu_gdb_write_register; cc->get_phys_page_debug =3D rx_cpu_get_phys_page_debug; cc->disas_set_info =3D rx_cpu_disas_set_info; - cc->tcg_initialize =3D rx_translate_init; + cc->tcg_ops.initialize =3D rx_translate_init; cc->tlb_fill =3D rx_cpu_tlb_fill; =20 cc->gdb_num_core_regs =3D 26; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 7b66718c44..697b94ff7b 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -512,7 +512,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) #endif cc->disas_set_info =3D s390_cpu_disas_set_info; #ifdef CONFIG_TCG - cc->tcg_initialize =3D s390x_translate_init; + cc->tcg_ops.initialize =3D s390x_translate_init; cc->tlb_fill =3D s390_cpu_tlb_fill; #endif =20 diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 3c68021c56..bdc5c9d90b 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -231,7 +231,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->get_phys_page_debug =3D superh_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D superh_cpu_disas_set_info; - cc->tcg_initialize =3D sh4_translate_init; + cc->tcg_ops.initialize =3D sh4_translate_init; =20 cc->gdb_num_core_regs =3D 59; =20 diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 701e794eac..07e48b86d1 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -879,7 +879,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->vmsd =3D &vmstate_sparc_cpu; #endif cc->disas_set_info =3D cpu_sparc_disas_set_info; - cc->tcg_initialize =3D sparc_tcg_init; + cc->tcg_ops.initialize =3D sparc_tcg_init; =20 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) cc->gdb_num_core_regs =3D 86; diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index 1fee87c094..cd24d0eb9d 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -153,7 +153,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void= *data) cc->set_pc =3D tilegx_cpu_set_pc; cc->tlb_fill =3D tilegx_cpu_tlb_fill; cc->gdb_num_core_regs =3D 0; - cc->tcg_initialize =3D tilegx_tcg_init; + cc->tcg_ops.initialize =3D tilegx_tcg_init; } =20 static const TypeInfo tilegx_cpu_type_info =3D { diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 2f2e5b029f..78b2925955 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -164,7 +164,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) cc->set_pc =3D tricore_cpu_set_pc; cc->synchronize_from_tb =3D tricore_cpu_synchronize_from_tb; cc->get_phys_page_debug =3D tricore_cpu_get_phys_page_debug; - cc->tcg_initialize =3D tricore_tcg_init; + cc->tcg_ops.initialize =3D tricore_tcg_init; cc->tlb_fill =3D tricore_cpu_tlb_fill; } =20 diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index b27fb9689f..226bf4226e 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -137,7 +137,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) cc->set_pc =3D uc32_cpu_set_pc; cc->tlb_fill =3D uc32_cpu_tlb_fill; cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; - cc->tcg_initialize =3D uc32_translate_init; + cc->tcg_ops.initialize =3D uc32_translate_init; dc->vmsd =3D &vmstate_uc32_cpu; } =20 diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 88a32268a1..5a6f5bf88b 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -209,7 +209,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) #endif cc->debug_excp_handler =3D xtensa_breakpoint_handler; cc->disas_set_info =3D xtensa_cpu_disas_set_info; - cc->tcg_initialize =3D xtensa_translate_init; + cc->tcg_ops.initialize =3D xtensa_translate_init; dc->vmsd =3D &vmstate_xtensa_cpu; } =20 diff --git a/MAINTAINERS b/MAINTAINERS index f53f2678d8..d876f504a6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1535,6 +1535,7 @@ F: qapi/machine.json F: qapi/machine-target.json F: include/hw/boards.h F: include/hw/core/cpu.h +F: include/hw/core/tcg-cpu-ops.h F: include/hw/cpu/cluster.h F: include/sysemu/numa.h T: git https://github.com/ehabkost/qemu.git machine-next diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 78cc8f043b..9a6932b774 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10945,7 +10945,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->virtio_is_big_endian =3D ppc_cpu_is_big_endian; #endif #ifdef CONFIG_TCG - cc->tcg_initialize =3D ppc_translate_init; + cc->tcg_ops.initialize =3D ppc_translate_init; cc->tlb_fill =3D ppc_cpu_tlb_fill; #endif #ifndef CONFIG_USER_ONLY --=20 2.26.2 From nobody Mon May 20 22:41:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607676449; cv=none; d=zohomail.com; s=zohoarc; b=LDnAVGnNGPAGMSotgatUTTC2zuWxHY/QxbcgeWnRiUoPnOf+GeEpSj6j7JNA8eHqTNGF/uYOLesR4sEJFqkw7sNVF7NX6PaTdDxQScnsyHzOorOyHwJ7OHS06nnHefAvLOnKJCnRtqF/SDXmXaHvkF68iBRzjfxnc9vUb1G1MAU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607676449; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=TN6e/mHm0WxDiwdct7Z80VYxPiflAtn65VWL50VZdWY=; b=kCqJwc8T0zZh686ego4P+44NsJswhFSClORnCf13Gj7nlp4ksNoqHgjlz7QXxuacPuyESUixhYW90LpCBjJyOe+ENj/EOI/b4XqWR67Nnh3hyc/ZnKrhZHvjz1hm2b+Qvnu21ZtuzahQ6Zl3Q8Bj49+/qF5tAdwGqDpZelCUl3U= ARC-Authentication-Results: i=1; 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Fri, 11 Dec 2020 08:31:57 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 16/25] target/riscv: remove CONFIG_TCG, as it is always TCG Date: Fri, 11 Dec 2020 09:31:34 +0100 Message-Id: <20201211083143.14350-17-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211083143.14350-1-cfontana@suse.de> References: <20201211083143.14350-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Alistair Francis , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" for now only TCG is allowed as an accelerator for riscv, so remove the CONFIG_TCG use. Signed-off-by: Claudio Fontana Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a52e0ce466..27dd1645c9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -561,10 +561,9 @@ static void riscv_cpu_class_init(ObjectClass *c, void = *data) /* For now, mark unmigratable: */ cc->vmsd =3D &vmstate_riscv_cpu; #endif -#ifdef CONFIG_TCG cc->tcg_ops.initialize =3D riscv_translate_init; cc->tlb_fill =3D riscv_cpu_tlb_fill; -#endif + device_class_set_props(dc, riscv_cpu_properties); } =20 --=20 2.26.2 From nobody Mon May 20 22:41:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607676029; cv=none; d=zohomail.com; s=zohoarc; b=H8O0FWzjJBK5T+w4c1L9IELGyMJfO5Wr5p+Xcs2vg0Jspj9SX5YSIGuuERWjjGoq5GP5f/vXARhWHfUkJvQFzmhggxEssVdIUvI+ZPER1bG26HjftWVRXlGxOhx6FPQKehtUVS6mGMxOtzPMQZwek/cRNtLdSI1C4acmoa7YqdY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607676029; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YjPMvCRQHPhX5Y1gLxT9itYUd60yVxwF7orGpgsBiC4=; b=agdoQbe7aPgIqFgAJ0p0RhnlZXgXZBfbVzxyST0SujsQSe9kl5HDZ1LQWxlCM7YIfaSkJBW7ZojdRlyns9BBJ4jEk1MWQ2zLAud5Svqp+9At6vJixqIrtf/Kk/AflnkmFN9BEX/jbguGxrH8wK45EiPndb/I6yGmYCXgsJ3bU+4= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607676029027853.3801918270208; Fri, 11 Dec 2020 00:40:29 -0800 (PST) Received: from localhost ([::1]:53722 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kndyV-0001RN-QM for importer@patchew.org; Fri, 11 Dec 2020 03:40:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42590) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqf-0008NP-Ec for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:32:21 -0500 Received: from mx2.suse.de ([195.135.220.15]:35252) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqT-00029q-7k for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:32:21 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 9F021B1A1; Fri, 11 Dec 2020 08:31:57 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 17/25] accel/tcg: split TCG-only code from cpu_exec_realizefn Date: Fri, 11 Dec 2020 09:31:35 +0100 Message-Id: <20201211083143.14350-18-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211083143.14350-1-cfontana@suse.de> References: <20201211083143.14350-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" move away TCG-only code, make it compile only on TCG. Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 8 +++++ accel/tcg/cpu-exec.c | 28 +++++++++++++++++ cpu.c | 70 ++++++++++++++++++++----------------------- hw/core/cpu.c | 6 +++- 4 files changed, 74 insertions(+), 38 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index c93b08a0fb..ea648d52ad 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1119,10 +1119,18 @@ AddressSpace *cpu_get_address_space(CPUState *cpu, = int asidx); void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...) GCC_FMT_ATTR(2, 3); extern Property cpu_common_props[]; + +/* $(top_srcdir)/cpu.c */ void cpu_exec_initfn(CPUState *cpu); void cpu_exec_realizefn(CPUState *cpu, Error **errp); void cpu_exec_unrealizefn(CPUState *cpu); =20 +#ifdef CONFIG_TCG +/* accel/tcg/cpu-exec.c */ +void tcg_exec_realizefn(CPUState *cpu, Error **errp); +void tcg_exec_unrealizefn(CPUState *cpu); +#endif /* CONFIG_TCG */ + /** * target_words_bigendian: * Returns true if the (default) endianness of the target is big endian, diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 64cba89356..50eb92d217 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -801,6 +801,34 @@ int cpu_exec(CPUState *cpu) return ret; } =20 +void tcg_exec_realizefn(CPUState *cpu, Error **errp) +{ + static bool tcg_target_initialized; + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + if (!tcg_target_initialized) { + cc->tcg_ops.initialize(); + tcg_target_initialized =3D true; + } + tlb_init(cpu); + qemu_plugin_vcpu_init_hook(cpu); + +#ifndef CONFIG_USER_ONLY + tcg_iommu_init_notifier_list(cpu); +#endif /* !CONFIG_USER_ONLY */ +} + +/* undo the initializations in reverse order */ +void tcg_exec_unrealizefn(CPUState *cpu) +{ +#ifndef CONFIG_USER_ONLY + tcg_iommu_free_notifier_list(cpu); +#endif /* !CONFIG_USER_ONLY */ + + qemu_plugin_vcpu_exit_hook(cpu); + tlb_destroy(cpu); +} + #ifndef CONFIG_USER_ONLY =20 void dump_drift_info(void) diff --git a/cpu.c b/cpu.c index 27ad096cc4..5cc8f181be 100644 --- a/cpu.c +++ b/cpu.c @@ -124,13 +124,35 @@ const VMStateDescription vmstate_cpu_common =3D { }; #endif =20 +void cpu_exec_realizefn(CPUState *cpu, Error **errp) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + cpu_list_add(cpu); + +#ifdef CONFIG_TCG + /* NB: errp parameter is unused currently */ + if (tcg_enabled()) { + tcg_exec_realizefn(cpu, errp); + } +#endif /* CONFIG_TCG */ + +#ifdef CONFIG_USER_ONLY + assert(cc->vmsd =3D=3D NULL); +#else + if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { + vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); + } + if (cc->vmsd !=3D NULL) { + vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu); + } +#endif /* CONFIG_USER_ONLY */ +} + void cpu_exec_unrealizefn(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - tlb_destroy(cpu); - cpu_list_remove(cpu); - #ifdef CONFIG_USER_ONLY assert(cc->vmsd =3D=3D NULL); #else @@ -140,8 +162,15 @@ void cpu_exec_unrealizefn(CPUState *cpu) if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { vmstate_unregister(NULL, &vmstate_cpu_common, cpu); } - tcg_iommu_free_notifier_list(cpu); #endif +#ifdef CONFIG_TCG + /* NB: errp parameter is unused currently */ + if (tcg_enabled()) { + tcg_exec_unrealizefn(cpu); + } +#endif /* CONFIG_TCG */ + + cpu_list_remove(cpu); } =20 Property cpu_common_props[] =3D { @@ -171,39 +200,6 @@ void cpu_exec_initfn(CPUState *cpu) #endif } =20 -void cpu_exec_realizefn(CPUState *cpu, Error **errp) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); -#ifdef CONFIG_TCG - static bool tcg_target_initialized; -#endif /* CONFIG_TCG */ - - cpu_list_add(cpu); - -#ifdef CONFIG_TCG - if (tcg_enabled() && !tcg_target_initialized) { - tcg_target_initialized =3D true; - cc->tcg_ops.initialize(); - } -#endif /* CONFIG_TCG */ - tlb_init(cpu); - - qemu_plugin_vcpu_init_hook(cpu); - -#ifdef CONFIG_USER_ONLY - assert(cc->vmsd =3D=3D NULL); -#else /* !CONFIG_USER_ONLY */ - if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { - vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); - } - if (cc->vmsd !=3D NULL) { - vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu); - } - - tcg_iommu_init_notifier_list(cpu); -#endif -} - const char *parse_cpu_option(const char *cpu_option) { ObjectClass *oc; diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 994a12cb35..1f04aab16b 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -199,6 +199,10 @@ static bool cpu_common_virtio_is_big_endian(CPUState *= cpu) return target_words_bigendian(); } =20 +/* + * XXX the following #if is always true because this is a common_ss + * module, so target CONFIG_* is never defined. + */ #if !defined(CONFIG_USER_ONLY) GuestPanicInformation *cpu_get_crash_info(CPUState *cpu) { @@ -340,9 +344,9 @@ static void cpu_common_realizefn(DeviceState *dev, Erro= r **errp) static void cpu_common_unrealizefn(DeviceState *dev) { CPUState *cpu =3D CPU(dev); + /* NOTE: latest generic point before the cpu is fully unrealized */ trace_fini_vcpu(cpu); - qemu_plugin_vcpu_exit_hook(cpu); cpu_exec_unrealizefn(cpu); } =20 --=20 2.26.2 From nobody Mon May 20 22:41:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607676308; cv=none; d=zohomail.com; s=zohoarc; b=nckHpFrByUjPK4uCBOHd3VOdR+8UBhMd/LpXVPtZM7em/lyaH20Q4Lyskkaeb7kQDGE8nF10TjaV0kreO0b/LZKVo/Nm96GeUKM1yCj4u0nCoK8NrqrEf7FmMeJaPaJI1de13TmoK1lNhW9sI5w6lBfoR+0DTmSSfq651SjdLD4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607676308; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PuKJDydihECT1bDP9cHWy8MhrXnPklpxpDLCsua3JWY=; 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Fri, 11 Dec 2020 03:32:23 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 6047FB1A3; Fri, 11 Dec 2020 08:31:58 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 18/25] cpu: Move synchronize_from_tb() to tcg_ops Date: Fri, 11 Dec 2020 09:31:36 +0100 Message-Id: <20201211083143.14350-19-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211083143.14350-1-cfontana@suse.de> References: <20201211083143.14350-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Colin Xu , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Eduardo Habkost Signed-off-by: Eduardo Habkost [claudio: wrapped in CONFIG_TCG] Signed-off-by: Claudio Fontana Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e --- include/hw/core/cpu.h | 8 -------- include/hw/core/tcg-cpu-ops.h | 12 ++++++++++++ accel/tcg/cpu-exec.c | 4 ++-- target/arm/cpu.c | 4 +++- target/avr/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/tcg/tcg-cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 4 +++- target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 2 +- 14 files changed, 29 insertions(+), 21 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index ea648d52ad..83007d262c 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -110,13 +110,6 @@ struct TranslationBlock; * If the target behaviour here is anything other than "set * the PC register to the value passed in" then the target must * also implement the synchronize_from_tb hook. - * @synchronize_from_tb: Callback for synchronizing state from a TCG - * #TranslationBlock. This is called when we abandon execution - * of a TB before starting it, and must set all parts of the CPU - * state which the previous TB in the chain may not have updated. - * This always includes at least the program counter; some targets - * will need to do more. If this hook is not implemented then the - * default is to call @set_pc(tb->pc). * @tlb_fill: Callback for handling a softmmu tlb miss or user-only * address fault. For system mode, if the access is valid, call * tlb_set_page and return true; if the access is invalid, and @@ -193,7 +186,6 @@ struct CPUClass { void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); - void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb= ); bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 4475ef0996..e1d50b3c8b 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -10,6 +10,8 @@ #ifndef TCG_CPU_OPS_H #define TCG_CPU_OPS_H =20 +#include "hw/core/cpu.h" + /** * struct TcgCpuOperations: TCG operations specific to a CPU class */ @@ -20,6 +22,16 @@ typedef struct TcgCpuOperations { * Called when the first CPU is realized. */ void (*initialize)(void); + /** + * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock + * + * This is called when we abandon execution of a TB before + * starting it, and must set all parts of the CPU state which + * the previous TB in the chain may not have updated. This + * will need to do more. If this hook is not implemented then + * the default is to call @set_pc(tb->pc). + */ + void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb= ); } TcgCpuOperations; =20 #endif /* TCG_CPU_OPS_H */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 50eb92d217..05dba7f2cc 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -192,8 +192,8 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cp= u, TranslationBlock *itb) TARGET_FMT_lx "] %s\n", last_tb->tc.ptr, last_tb->pc, lookup_symbol(last_tb->pc)); - if (cc->synchronize_from_tb) { - cc->synchronize_from_tb(cpu, last_tb); + if (cc->tcg_ops.synchronize_from_tb) { + cc->tcg_ops.synchronize_from_tb(cpu, last_tb); } else { assert(cc->set_pc); cc->set_pc(cpu, last_tb->pc); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1fa9382a7c..ac1757d49f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -54,6 +54,7 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) } } =20 +#ifdef CONFIG_TCG static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) { ARMCPU *cpu =3D ARM_CPU(cs); @@ -69,6 +70,7 @@ static void arm_cpu_synchronize_from_tb(CPUState *cs, Tra= nslationBlock *tb) env->regs[15] =3D tb->pc; } } +#endif /* CONFIG_TCG */ =20 static bool arm_cpu_has_work(CPUState *cs) { @@ -2242,7 +2244,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->cpu_exec_interrupt =3D arm_cpu_exec_interrupt; cc->dump_state =3D arm_cpu_dump_state; cc->set_pc =3D arm_cpu_set_pc; - cc->synchronize_from_tb =3D arm_cpu_synchronize_from_tb; cc->gdb_read_register =3D arm_cpu_gdb_read_register; cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY @@ -2262,6 +2263,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->disas_set_info =3D arm_disas_set_info; #ifdef CONFIG_TCG cc->tcg_ops.initialize =3D arm_translate_init; + cc->tcg_ops.synchronize_from_tb =3D arm_cpu_synchronize_from_tb; cc->tlb_fill =3D arm_cpu_tlb_fill; cc->debug_excp_handler =3D arm_debug_excp_handler; cc->debug_check_watchpoint =3D arm_debug_check_watchpoint; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 94306a2aa0..f753c15768 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -207,7 +207,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->vmsd =3D &vms_avr_cpu; cc->disas_set_info =3D avr_cpu_disas_set_info; cc->tcg_ops.initialize =3D avr_cpu_tcg_init; - cc->synchronize_from_tb =3D avr_cpu_synchronize_from_tb; + cc->tcg_ops.synchronize_from_tb =3D avr_cpu_synchronize_from_tb; cc->gdb_read_register =3D avr_cpu_gdb_read_register; cc->gdb_write_register =3D avr_cpu_gdb_write_register; cc->gdb_num_core_regs =3D 35; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 4c778966c2..12a09e93ae 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -143,7 +143,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->cpu_exec_interrupt =3D hppa_cpu_exec_interrupt; cc->dump_state =3D hppa_cpu_dump_state; cc->set_pc =3D hppa_cpu_set_pc; - cc->synchronize_from_tb =3D hppa_cpu_synchronize_from_tb; + cc->tcg_ops.synchronize_from_tb =3D hppa_cpu_synchronize_from_tb; cc->gdb_read_register =3D hppa_cpu_gdb_read_register; cc->gdb_write_register =3D hppa_cpu_gdb_write_register; cc->tlb_fill =3D hppa_cpu_tlb_fill; diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 1f2a3e881a..d1414e2970 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -60,7 +60,7 @@ void tcg_cpu_common_class_init(CPUClass *cc) { cc->do_interrupt =3D x86_cpu_do_interrupt; cc->cpu_exec_interrupt =3D x86_cpu_exec_interrupt; - cc->synchronize_from_tb =3D x86_cpu_synchronize_from_tb; + cc->tcg_ops.synchronize_from_tb =3D x86_cpu_synchronize_from_tb; cc->cpu_exec_enter =3D x86_cpu_exec_enter; cc->cpu_exec_exit =3D x86_cpu_exec_exit; cc->tcg_ops.initialize =3D tcg_x86_init; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index bc10518fa3..97d94d9c27 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -322,7 +322,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->cpu_exec_interrupt =3D mb_cpu_exec_interrupt; cc->dump_state =3D mb_cpu_dump_state; cc->set_pc =3D mb_cpu_set_pc; - cc->synchronize_from_tb =3D mb_cpu_synchronize_from_tb; + cc->tcg_ops.synchronize_from_tb =3D mb_cpu_synchronize_from_tb; cc->gdb_read_register =3D mb_cpu_gdb_read_register; cc->gdb_write_register =3D mb_cpu_gdb_write_register; cc->tlb_fill =3D mb_cpu_tlb_fill; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index bc48573763..4a539349a9 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -44,6 +44,7 @@ static void mips_cpu_set_pc(CPUState *cs, vaddr value) } } =20 +#ifdef CONFIG_TCG static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *t= b) { MIPSCPU *cpu =3D MIPS_CPU(cs); @@ -53,6 +54,7 @@ static void mips_cpu_synchronize_from_tb(CPUState *cs, Tr= anslationBlock *tb) env->hflags &=3D ~MIPS_HFLAG_BMASK; env->hflags |=3D tb->flags & MIPS_HFLAG_BMASK; } +#endif /* CONFIG_TCG */ =20 static bool mips_cpu_has_work(CPUState *cs) { @@ -238,7 +240,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->cpu_exec_interrupt =3D mips_cpu_exec_interrupt; cc->dump_state =3D mips_cpu_dump_state; cc->set_pc =3D mips_cpu_set_pc; - cc->synchronize_from_tb =3D mips_cpu_synchronize_from_tb; cc->gdb_read_register =3D mips_cpu_gdb_read_register; cc->gdb_write_register =3D mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY @@ -250,6 +251,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->disas_set_info =3D mips_cpu_disas_set_info; #ifdef CONFIG_TCG cc->tcg_ops.initialize =3D mips_tcg_init; + cc->tcg_ops.synchronize_from_tb =3D mips_cpu_synchronize_from_tb; cc->tlb_fill =3D mips_cpu_tlb_fill; #endif =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 27dd1645c9..a9c30879d3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -543,7 +543,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->cpu_exec_interrupt =3D riscv_cpu_exec_interrupt; cc->dump_state =3D riscv_cpu_dump_state; cc->set_pc =3D riscv_cpu_set_pc; - cc->synchronize_from_tb =3D riscv_cpu_synchronize_from_tb; + cc->tcg_ops.synchronize_from_tb =3D riscv_cpu_synchronize_from_tb; cc->gdb_read_register =3D riscv_cpu_gdb_read_register; cc->gdb_write_register =3D riscv_cpu_gdb_write_register; cc->gdb_num_core_regs =3D 33; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index a701a09b11..d03c4e0b05 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -189,7 +189,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) cc->cpu_exec_interrupt =3D rx_cpu_exec_interrupt; cc->dump_state =3D rx_cpu_dump_state; cc->set_pc =3D rx_cpu_set_pc; - cc->synchronize_from_tb =3D rx_cpu_synchronize_from_tb; + cc->tcg_ops.synchronize_from_tb =3D rx_cpu_synchronize_from_tb; cc->gdb_read_register =3D rx_cpu_gdb_read_register; cc->gdb_write_register =3D rx_cpu_gdb_write_register; cc->get_phys_page_debug =3D rx_cpu_get_phys_page_debug; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index bdc5c9d90b..a33025b5c8 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -222,7 +222,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->cpu_exec_interrupt =3D superh_cpu_exec_interrupt; cc->dump_state =3D superh_cpu_dump_state; cc->set_pc =3D superh_cpu_set_pc; - cc->synchronize_from_tb =3D superh_cpu_synchronize_from_tb; + cc->tcg_ops.synchronize_from_tb =3D superh_cpu_synchronize_from_tb; cc->gdb_read_register =3D superh_cpu_gdb_read_register; cc->gdb_write_register =3D superh_cpu_gdb_write_register; cc->tlb_fill =3D superh_cpu_tlb_fill; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 07e48b86d1..baf6c5b587 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -868,7 +868,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->memory_rw_debug =3D sparc_cpu_memory_rw_debug; #endif cc->set_pc =3D sparc_cpu_set_pc; - cc->synchronize_from_tb =3D sparc_cpu_synchronize_from_tb; + cc->tcg_ops.synchronize_from_tb =3D sparc_cpu_synchronize_from_tb; cc->gdb_read_register =3D sparc_cpu_gdb_read_register; cc->gdb_write_register =3D sparc_cpu_gdb_write_register; cc->tlb_fill =3D sparc_cpu_tlb_fill; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 78b2925955..5edf96c600 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -162,7 +162,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) =20 cc->dump_state =3D tricore_cpu_dump_state; cc->set_pc =3D tricore_cpu_set_pc; - cc->synchronize_from_tb =3D tricore_cpu_synchronize_from_tb; + cc->tcg_ops.synchronize_from_tb =3D tricore_cpu_synchronize_from_tb; cc->get_phys_page_debug =3D tricore_cpu_get_phys_page_debug; cc->tcg_ops.initialize =3D tricore_tcg_init; cc->tlb_fill =3D tricore_cpu_tlb_fill; --=20 2.26.2 From nobody Mon May 20 22:41:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607676478; cv=none; d=zohomail.com; s=zohoarc; b=IuNQj5dktIF4BkCZM0xzg4JkfXe8ViiQlZoZGYb90vt0qzAoqKZormtXF8goWxhGCBsBmcmFug2pIe++NAxevo7j8QhZieuAhD5L10LHpq0S2X68hVfARnZ9FyXsF+fZkcwMJ7kGcdaqJ8aHvyrPJWLdIp2njNM6FPEQE3W6tdk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607676478; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Fri, 11 Dec 2020 03:32:25 -0500 Received: from mx2.suse.de ([195.135.220.15]:35344) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqU-0002Ad-HV for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:32:25 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 1CB8BB066; Fri, 11 Dec 2020 08:31:59 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 19/25] cpu: Move cpu_exec_* to tcg_ops Date: Fri, 11 Dec 2020 09:31:37 +0100 Message-Id: <20201211083143.14350-20-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211083143.14350-1-cfontana@suse.de> References: <20201211083143.14350-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Cota" , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Eduardo Habkost Signed-off-by: Eduardo Habkost [claudio: wrapped in CONFIG_TCG] Signed-off-by: Claudio Fontana Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 6 ------ include/hw/core/tcg-cpu-ops.h | 6 ++++++ accel/tcg/cpu-exec.c | 12 ++++++------ target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/arm/cpu64.c | 5 ++++- target/arm/cpu_tcg.c | 7 ++++++- target/avr/cpu.c | 2 +- target/cris/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/tcg/tcg-cpu.c | 6 +++--- target/lm32/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tilegx/cpu.c | 2 +- target/unicore32/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- target/ppc/translate_init.c.inc | 16 ++++++++++------ 26 files changed, 54 insertions(+), 42 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 83007d262c..52142e9094 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -146,9 +146,6 @@ struct TranslationBlock; * @gdb_get_dynamic_xml: Callback to return dynamically generated XML for = the * gdb stub. Returns a pointer to the XML contents for the specified XML= file * or NULL if the CPU doesn't have a dynamically generated content for i= t. - * @cpu_exec_enter: Callback for cpu_exec preparation. - * @cpu_exec_exit: Callback for cpu_exec cleanup. - * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec. * @disas_set_info: Setup architecture specific components of disassembly = info * @adjust_watchpoint_address: Perform a target-specific adjustment to an * address before attempting to match it against watchpoints. @@ -211,9 +208,6 @@ struct CPUClass { const char *gdb_core_xml_file; gchar * (*gdb_arch_name)(CPUState *cpu); const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname= ); - void (*cpu_exec_enter)(CPUState *cpu); - void (*cpu_exec_exit)(CPUState *cpu); - bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); =20 void (*disas_set_info)(CPUState *cpu, disassemble_info *info); vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len); diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index e1d50b3c8b..fbd579c2a6 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -32,6 +32,12 @@ typedef struct TcgCpuOperations { * the default is to call @set_pc(tb->pc). */ void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb= ); + /** @cpu_exec_enter: Callback for cpu_exec preparation */ + void (*cpu_exec_enter)(CPUState *cpu); + /** @cpu_exec_exit: Callback for cpu_exec cleanup */ + void (*cpu_exec_exit)(CPUState *cpu); + /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exe= c */ + bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); } TcgCpuOperations; =20 #endif /* TCG_CPU_OPS_H */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 05dba7f2cc..502f6a53ae 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -240,8 +240,8 @@ static void cpu_exec_enter(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->cpu_exec_enter) { - cc->cpu_exec_enter(cpu); + if (cc->tcg_ops.cpu_exec_enter) { + cc->tcg_ops.cpu_exec_enter(cpu); } } =20 @@ -249,8 +249,8 @@ static void cpu_exec_exit(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->cpu_exec_exit) { - cc->cpu_exec_exit(cpu); + if (cc->tcg_ops.cpu_exec_exit) { + cc->tcg_ops.cpu_exec_exit(cpu); } } =20 @@ -625,8 +625,8 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, True when it is, and we should restart on a new TB, and via longjmp via cpu_loop_exit. */ else { - if (cc->cpu_exec_interrupt && - cc->cpu_exec_interrupt(cpu, interrupt_request)) { + if (cc->tcg_ops.cpu_exec_interrupt && + cc->tcg_ops.cpu_exec_interrupt(cpu, interrupt_request)) { if (need_replay_interrupt(interrupt_request)) { replay_interrupt(); } diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index d66f0351a9..d9ced1635a 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -218,7 +218,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->class_by_name =3D alpha_cpu_class_by_name; cc->has_work =3D alpha_cpu_has_work; cc->do_interrupt =3D alpha_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D alpha_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D alpha_cpu_exec_interrupt; cc->dump_state =3D alpha_cpu_dump_state; cc->set_pc =3D alpha_cpu_set_pc; cc->gdb_read_register =3D alpha_cpu_gdb_read_register; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ac1757d49f..897db4335a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2241,7 +2241,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) =20 cc->class_by_name =3D arm_cpu_class_by_name; cc->has_work =3D arm_cpu_has_work; - cc->cpu_exec_interrupt =3D arm_cpu_exec_interrupt; cc->dump_state =3D arm_cpu_dump_state; cc->set_pc =3D arm_cpu_set_pc; cc->gdb_read_register =3D arm_cpu_gdb_read_register; @@ -2263,6 +2262,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->disas_set_info =3D arm_disas_set_info; #ifdef CONFIG_TCG cc->tcg_ops.initialize =3D arm_translate_init; + cc->tcg_ops.cpu_exec_interrupt =3D arm_cpu_exec_interrupt; cc->tcg_ops.synchronize_from_tb =3D arm_cpu_synchronize_from_tb; cc->tlb_fill =3D arm_cpu_tlb_fill; cc->debug_excp_handler =3D arm_debug_excp_handler; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 649213082f..ebc53c8bdc 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -784,7 +784,10 @@ static void aarch64_cpu_class_init(ObjectClass *oc, vo= id *data) { CPUClass *cc =3D CPU_CLASS(oc); =20 - cc->cpu_exec_interrupt =3D arm_cpu_exec_interrupt; +#ifdef CONFIG_TCG + cc->tcg_ops.cpu_exec_interrupt =3D arm_cpu_exec_interrupt; +#endif /* CONFIG_TCG */ + cc->gdb_read_register =3D aarch64_cpu_gdb_read_register; cc->gdb_write_register =3D aarch64_cpu_gdb_write_register; cc->gdb_num_core_regs =3D 34; diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 0013e25412..e261839d08 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -15,6 +15,7 @@ /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) =20 +#ifdef CONFIG_TCG static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc =3D CPU_GET_CLASS(cs); @@ -38,6 +39,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int = interrupt_request) } return ret; } +#endif /* CONFIG_TCG */ =20 static void arm926_initfn(Object *obj) { @@ -628,7 +630,10 @@ static void arm_v7m_class_init(ObjectClass *oc, void *= data) cc->do_interrupt =3D arm_v7m_cpu_do_interrupt; #endif =20 - cc->cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt; +#ifdef CONFIG_TCG + cc->tcg_ops.cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt; +#endif /* CONFIG_TCG */ + cc->gdb_core_xml_file =3D "arm-m-profile.xml"; } =20 diff --git a/target/avr/cpu.c b/target/avr/cpu.c index f753c15768..277b00dbfc 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -198,7 +198,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) =20 cc->has_work =3D avr_cpu_has_work; cc->do_interrupt =3D avr_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D avr_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D avr_cpu_exec_interrupt; cc->dump_state =3D avr_cpu_dump_state; cc->set_pc =3D avr_cpu_set_pc; cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 4328f8e6c9..7489fc20c8 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -269,7 +269,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->class_by_name =3D cris_cpu_class_by_name; cc->has_work =3D cris_cpu_has_work; cc->do_interrupt =3D cris_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D cris_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D cris_cpu_exec_interrupt; cc->dump_state =3D cris_cpu_dump_state; cc->set_pc =3D cris_cpu_set_pc; cc->gdb_read_register =3D cris_cpu_gdb_read_register; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 12a09e93ae..61444753f2 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -140,7 +140,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->class_by_name =3D hppa_cpu_class_by_name; cc->has_work =3D hppa_cpu_has_work; cc->do_interrupt =3D hppa_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D hppa_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D hppa_cpu_exec_interrupt; cc->dump_state =3D hppa_cpu_dump_state; cc->set_pc =3D hppa_cpu_set_pc; cc->tcg_ops.synchronize_from_tb =3D hppa_cpu_synchronize_from_tb; diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index d1414e2970..5e0f2a2fae 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -59,10 +59,10 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, T= ranslationBlock *tb) void tcg_cpu_common_class_init(CPUClass *cc) { cc->do_interrupt =3D x86_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D x86_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D x86_cpu_exec_interrupt; cc->tcg_ops.synchronize_from_tb =3D x86_cpu_synchronize_from_tb; - cc->cpu_exec_enter =3D x86_cpu_exec_enter; - cc->cpu_exec_exit =3D x86_cpu_exec_exit; + cc->tcg_ops.cpu_exec_enter =3D x86_cpu_exec_enter; + cc->tcg_ops.cpu_exec_exit =3D x86_cpu_exec_exit; cc->tcg_ops.initialize =3D tcg_x86_init; cc->tlb_fill =3D x86_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index ef795b81a4..eea2d3e515 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -223,7 +223,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) cc->class_by_name =3D lm32_cpu_class_by_name; cc->has_work =3D lm32_cpu_has_work; cc->do_interrupt =3D lm32_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D lm32_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D lm32_cpu_exec_interrupt; cc->dump_state =3D lm32_cpu_dump_state; cc->set_pc =3D lm32_cpu_set_pc; cc->gdb_read_register =3D lm32_cpu_gdb_read_register; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index b66d86c353..c0fa517fc3 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -278,7 +278,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->class_by_name =3D m68k_cpu_class_by_name; cc->has_work =3D m68k_cpu_has_work; cc->do_interrupt =3D m68k_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D m68k_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D m68k_cpu_exec_interrupt; cc->dump_state =3D m68k_cpu_dump_state; cc->set_pc =3D m68k_cpu_set_pc; cc->gdb_read_register =3D m68k_cpu_gdb_read_register; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 97d94d9c27..833d7f2d59 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -319,7 +319,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->has_work =3D mb_cpu_has_work; cc->do_interrupt =3D mb_cpu_do_interrupt; cc->do_unaligned_access =3D mb_cpu_do_unaligned_access; - cc->cpu_exec_interrupt =3D mb_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D mb_cpu_exec_interrupt; cc->dump_state =3D mb_cpu_dump_state; cc->set_pc =3D mb_cpu_set_pc; cc->tcg_ops.synchronize_from_tb =3D mb_cpu_synchronize_from_tb; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 4a539349a9..6c525a6af1 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -237,7 +237,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->class_by_name =3D mips_cpu_class_by_name; cc->has_work =3D mips_cpu_has_work; cc->do_interrupt =3D mips_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D mips_cpu_exec_interrupt; cc->dump_state =3D mips_cpu_dump_state; cc->set_pc =3D mips_cpu_set_pc; cc->gdb_read_register =3D mips_cpu_gdb_read_register; @@ -251,6 +250,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->disas_set_info =3D mips_cpu_disas_set_info; #ifdef CONFIG_TCG cc->tcg_ops.initialize =3D mips_tcg_init; + cc->tcg_ops.cpu_exec_interrupt =3D mips_cpu_exec_interrupt; cc->tcg_ops.synchronize_from_tb =3D mips_cpu_synchronize_from_tb; cc->tlb_fill =3D mips_cpu_tlb_fill; #endif diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 29c9c6f634..9eeb01fb5b 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -193,7 +193,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) cc->class_by_name =3D nios2_cpu_class_by_name; cc->has_work =3D nios2_cpu_has_work; cc->do_interrupt =3D nios2_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D nios2_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D nios2_cpu_exec_interrupt; cc->dump_state =3D nios2_cpu_dump_state; cc->set_pc =3D nios2_cpu_set_pc; cc->disas_set_info =3D nios2_cpu_disas_set_info; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index e442f4f97c..df8a41f956 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -155,7 +155,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->class_by_name =3D openrisc_cpu_class_by_name; cc->has_work =3D openrisc_cpu_has_work; cc->do_interrupt =3D openrisc_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt; cc->dump_state =3D openrisc_cpu_dump_state; cc->set_pc =3D openrisc_cpu_set_pc; cc->gdb_read_register =3D openrisc_cpu_gdb_read_register; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a9c30879d3..15d58698a6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -540,7 +540,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->class_by_name =3D riscv_cpu_class_by_name; cc->has_work =3D riscv_cpu_has_work; cc->do_interrupt =3D riscv_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D riscv_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D riscv_cpu_exec_interrupt; cc->dump_state =3D riscv_cpu_dump_state; cc->set_pc =3D riscv_cpu_set_pc; cc->tcg_ops.synchronize_from_tb =3D riscv_cpu_synchronize_from_tb; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index d03c4e0b05..3ba93590d2 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -186,7 +186,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) cc->class_by_name =3D rx_cpu_class_by_name; cc->has_work =3D rx_cpu_has_work; cc->do_interrupt =3D rx_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D rx_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D rx_cpu_exec_interrupt; cc->dump_state =3D rx_cpu_dump_state; cc->set_pc =3D rx_cpu_set_pc; cc->tcg_ops.synchronize_from_tb =3D rx_cpu_synchronize_from_tb; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 697b94ff7b..add2f4b21f 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -505,7 +505,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->get_crash_info =3D s390_cpu_get_crash_info; cc->write_elf64_note =3D s390_cpu_write_elf64_note; #ifdef CONFIG_TCG - cc->cpu_exec_interrupt =3D s390_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D s390_cpu_exec_interrupt; cc->debug_excp_handler =3D s390x_cpu_debug_excp_handler; cc->do_unaligned_access =3D s390x_cpu_do_unaligned_access; #endif diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index a33025b5c8..0574194cd0 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -219,7 +219,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->class_by_name =3D superh_cpu_class_by_name; cc->has_work =3D superh_cpu_has_work; cc->do_interrupt =3D superh_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D superh_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D superh_cpu_exec_interrupt; cc->dump_state =3D superh_cpu_dump_state; cc->set_pc =3D superh_cpu_set_pc; cc->tcg_ops.synchronize_from_tb =3D superh_cpu_synchronize_from_tb; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index baf6c5b587..c559f15e14 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -862,7 +862,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->parse_features =3D sparc_cpu_parse_features; cc->has_work =3D sparc_cpu_has_work; cc->do_interrupt =3D sparc_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D sparc_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D sparc_cpu_exec_interrupt; cc->dump_state =3D sparc_cpu_dump_state; #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) cc->memory_rw_debug =3D sparc_cpu_memory_rw_debug; diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index cd24d0eb9d..4c6176d26e 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -148,7 +148,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void= *data) cc->class_by_name =3D tilegx_cpu_class_by_name; cc->has_work =3D tilegx_cpu_has_work; cc->do_interrupt =3D tilegx_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D tilegx_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D tilegx_cpu_exec_interrupt; cc->dump_state =3D tilegx_cpu_dump_state; cc->set_pc =3D tilegx_cpu_set_pc; cc->tlb_fill =3D tilegx_cpu_tlb_fill; diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 226bf4226e..84c3419989 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -132,7 +132,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) cc->class_by_name =3D uc32_cpu_class_by_name; cc->has_work =3D uc32_cpu_has_work; cc->do_interrupt =3D uc32_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D uc32_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D uc32_cpu_exec_interrupt; cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; cc->tlb_fill =3D uc32_cpu_tlb_fill; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 5a6f5bf88b..42a5e4ebe8 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -195,7 +195,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->class_by_name =3D xtensa_cpu_class_by_name; cc->has_work =3D xtensa_cpu_has_work; cc->do_interrupt =3D xtensa_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D xtensa_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D xtensa_cpu_exec_interrupt; cc->dump_state =3D xtensa_cpu_dump_state; cc->set_pc =3D xtensa_cpu_set_pc; cc->gdb_read_register =3D xtensa_cpu_gdb_read_register; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 9a6932b774..e82c92bcf8 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10765,6 +10765,7 @@ static void ppc_cpu_reset(DeviceState *dev) } =20 #ifndef CONFIG_USER_ONLY + static bool ppc_cpu_is_big_endian(CPUState *cs) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); @@ -10775,6 +10776,7 @@ static bool ppc_cpu_is_big_endian(CPUState *cs) return !msr_le; } =20 +#ifdef CONFIG_TCG static void ppc_cpu_exec_enter(CPUState *cs) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); @@ -10796,7 +10798,9 @@ static void ppc_cpu_exec_exit(CPUState *cs) vhc->cpu_exec_exit(cpu->vhyp, cpu); } } -#endif +#endif /* CONFIG_TCG */ + +#endif /* !CONFIG_USER_ONLY */ =20 static void ppc_cpu_instance_init(Object *obj) { @@ -10909,7 +10913,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->parse_features =3D ppc_cpu_parse_featurestr; cc->has_work =3D ppc_cpu_has_work; cc->do_interrupt =3D ppc_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D ppc_cpu_exec_interrupt; cc->dump_state =3D ppc_cpu_dump_state; cc->dump_statistics =3D ppc_cpu_dump_statistics; cc->set_pc =3D ppc_cpu_set_pc; @@ -10946,12 +10949,13 @@ static void ppc_cpu_class_init(ObjectClass *oc, v= oid *data) #endif #ifdef CONFIG_TCG cc->tcg_ops.initialize =3D ppc_translate_init; + cc->tcg_ops.cpu_exec_interrupt =3D ppc_cpu_exec_interrupt; cc->tlb_fill =3D ppc_cpu_tlb_fill; -#endif #ifndef CONFIG_USER_ONLY - cc->cpu_exec_enter =3D ppc_cpu_exec_enter; - cc->cpu_exec_exit =3D ppc_cpu_exec_exit; -#endif + cc->tcg_ops.cpu_exec_enter =3D ppc_cpu_exec_enter; + cc->tcg_ops.cpu_exec_exit =3D ppc_cpu_exec_exit; +#endif /* !CONFIG_USER_ONLY */ +#endif /* CONFIG_TCG */ =20 cc->disas_set_info =3D ppc_disas_set_info; =20 --=20 2.26.2 From nobody Mon May 20 22:41:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607676177; cv=none; d=zohomail.com; s=zohoarc; b=CqdbuKzY9v4+MuCd1hqkSwIKBZV91kDzqGKsuEpXAi3C82qDXvBeTWuahIy6tzP0KMMcPAG64BaLvkP+k+cqSgFsOMgmSNxTaOubt0sbaSZwoi0oPJiR/LHg9KdxW2tUJJgPoOuCIry+UUJFXVt4KvQg7WNJkdMhTwwFpQ1dO14= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607676177; 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Fri, 11 Dec 2020 03:32:23 -0500 Received: from mx2.suse.de ([195.135.220.15]:35364) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqV-0002Ah-2J for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:32:22 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id D7D09B13D; Fri, 11 Dec 2020 08:31:59 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 20/25] cpu: Move tlb_fill to tcg_ops Date: Fri, 11 Dec 2020 09:31:38 +0100 Message-Id: <20201211083143.14350-21-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211083143.14350-1-cfontana@suse.de> References: <20201211083143.14350-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Cota" , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Eduardo Habkost Signed-off-by: Eduardo Habkost [claudio: wrapped in CONFIG_TCG] Signed-off-by: Claudio Fontana Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 9 --------- include/hw/core/tcg-cpu-ops.h | 12 ++++++++++++ accel/tcg/cputlb.c | 6 +++--- accel/tcg/user-exec.c | 6 +++--- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/avr/cpu.c | 2 +- target/cris/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/tcg/tcg-cpu.c | 2 +- target/lm32/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/moxie/cpu.c | 2 +- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tilegx/cpu.c | 2 +- target/tricore/cpu.c | 2 +- target/unicore32/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- target/ppc/translate_init.c.inc | 2 +- 27 files changed, 41 insertions(+), 38 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 52142e9094..c82ef261c6 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -110,12 +110,6 @@ struct TranslationBlock; * If the target behaviour here is anything other than "set * the PC register to the value passed in" then the target must * also implement the synchronize_from_tb hook. - * @tlb_fill: Callback for handling a softmmu tlb miss or user-only - * address fault. For system mode, if the access is valid, call - * tlb_set_page and return true; if the access is invalid, and - * probe is true, return false; otherwise raise an exception and - * do not return. For user-only mode, always raise an exception - * and do not return. * @get_phys_page_debug: Callback for obtaining a physical address. * @get_phys_page_attrs_debug: Callback for obtaining a physical address a= nd the * associated memory transaction attributes to use for the access. @@ -183,9 +177,6 @@ struct CPUClass { void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); - bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index fbd579c2a6..deeabbcf33 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -38,6 +38,18 @@ typedef struct TcgCpuOperations { void (*cpu_exec_exit)(CPUState *cpu); /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exe= c */ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); + /** + * @tlb_fill: Handle a softmmu tlb miss or user-only address fault + * + * For system mode, if the access is valid, call tlb_set_page + * and return true; if the access is invalid, and probe is + * true, return false; otherwise raise an exception and do + * not return. For user-only mode, always raise an exception + * and do not return. + */ + bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); } TcgCpuOperations; =20 #endif /* TCG_CPU_OPS_H */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 42ab79c1a5..2dc71b5528 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1286,7 +1286,7 @@ static void tlb_fill(CPUState *cpu, target_ulong addr= , int size, * This is not a probe, so only valid return is success; failure * should result in exception + longjmp to the cpu loop. */ - ok =3D cc->tlb_fill(cpu, addr, size, access_type, mmu_idx, false, reta= ddr); + ok =3D cc->tcg_ops.tlb_fill(cpu, addr, size, access_type, mmu_idx, fal= se, retaddr); assert(ok); } =20 @@ -1557,8 +1557,8 @@ static int probe_access_internal(CPUArchState *env, t= arget_ulong addr, CPUState *cs =3D env_cpu(env); CPUClass *cc =3D CPU_GET_CLASS(cs); =20 - if (!cc->tlb_fill(cs, addr, fault_size, access_type, - mmu_idx, nonfault, retaddr)) { + if (!cc->tcg_ops.tlb_fill(cs, addr, fault_size, access_type, + mmu_idx, nonfault, retaddr)) { /* Non-faulting page table read failed. */ *phost =3D NULL; return TLB_INVALID_MASK; diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 4ebe25461a..7f53992251 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -186,7 +186,7 @@ static inline int handle_cpu_signal(uintptr_t pc, sigin= fo_t *info, clear_helper_retaddr(); =20 cc =3D CPU_GET_CLASS(cpu); - cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc); + cc->tcg_ops.tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false= , pc); g_assert_not_reached(); } =20 @@ -216,8 +216,8 @@ static int probe_access_internal(CPUArchState *env, tar= get_ulong addr, } else { CPUState *cpu =3D env_cpu(env); CPUClass *cc =3D CPU_GET_CLASS(cpu); - cc->tlb_fill(cpu, addr, fault_size, access_type, - MMU_USER_IDX, false, ra); + cc->tcg_ops.tlb_fill(cpu, addr, fault_size, access_type, + MMU_USER_IDX, false, ra); g_assert_not_reached(); } } diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index d9ced1635a..9f36f824fd 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -223,7 +223,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->set_pc =3D alpha_cpu_set_pc; cc->gdb_read_register =3D alpha_cpu_gdb_read_register; cc->gdb_write_register =3D alpha_cpu_gdb_write_register; - cc->tlb_fill =3D alpha_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D alpha_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->do_transaction_failed =3D alpha_cpu_do_transaction_failed; cc->do_unaligned_access =3D alpha_cpu_do_unaligned_access; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 897db4335a..c9aee4d566 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2264,7 +2264,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->tcg_ops.initialize =3D arm_translate_init; cc->tcg_ops.cpu_exec_interrupt =3D arm_cpu_exec_interrupt; cc->tcg_ops.synchronize_from_tb =3D arm_cpu_synchronize_from_tb; - cc->tlb_fill =3D arm_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D arm_cpu_tlb_fill; cc->debug_excp_handler =3D arm_debug_excp_handler; cc->debug_check_watchpoint =3D arm_debug_check_watchpoint; cc->do_unaligned_access =3D arm_cpu_do_unaligned_access; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 277b00dbfc..699055de7c 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -203,7 +203,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->set_pc =3D avr_cpu_set_pc; cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; cc->get_phys_page_debug =3D avr_cpu_get_phys_page_debug; - cc->tlb_fill =3D avr_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D avr_cpu_tlb_fill; cc->vmsd =3D &vms_avr_cpu; cc->disas_set_info =3D avr_cpu_disas_set_info; cc->tcg_ops.initialize =3D avr_cpu_tcg_init; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 7489fc20c8..9222717f3e 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -274,7 +274,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->set_pc =3D cris_cpu_set_pc; cc->gdb_read_register =3D cris_cpu_gdb_read_register; cc->gdb_write_register =3D cris_cpu_gdb_write_register; - cc->tlb_fill =3D cris_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D cris_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D cris_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_cris_cpu; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 61444753f2..e2d79f954e 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -146,7 +146,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->tcg_ops.synchronize_from_tb =3D hppa_cpu_synchronize_from_tb; cc->gdb_read_register =3D hppa_cpu_gdb_read_register; cc->gdb_write_register =3D hppa_cpu_gdb_write_register; - cc->tlb_fill =3D hppa_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D hppa_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_hppa_cpu; diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 5e0f2a2fae..8606dd6a3e 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -64,7 +64,7 @@ void tcg_cpu_common_class_init(CPUClass *cc) cc->tcg_ops.cpu_exec_enter =3D x86_cpu_exec_enter; cc->tcg_ops.cpu_exec_exit =3D x86_cpu_exec_exit; cc->tcg_ops.initialize =3D tcg_x86_init; - cc->tlb_fill =3D x86_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D x86_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->debug_excp_handler =3D breakpoint_handler; #endif diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index eea2d3e515..76dc728858 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -228,7 +228,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) cc->set_pc =3D lm32_cpu_set_pc; cc->gdb_read_register =3D lm32_cpu_gdb_read_register; cc->gdb_write_register =3D lm32_cpu_gdb_write_register; - cc->tlb_fill =3D lm32_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D lm32_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D lm32_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_lm32_cpu; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index c0fa517fc3..bc109faa21 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -283,7 +283,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->set_pc =3D m68k_cpu_set_pc; cc->gdb_read_register =3D m68k_cpu_gdb_read_register; cc->gdb_write_register =3D m68k_cpu_gdb_write_register; - cc->tlb_fill =3D m68k_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D m68k_cpu_tlb_fill; #if defined(CONFIG_SOFTMMU) cc->do_transaction_failed =3D m68k_cpu_transaction_failed; cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 833d7f2d59..6e660a27b8 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -325,7 +325,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->tcg_ops.synchronize_from_tb =3D mb_cpu_synchronize_from_tb; cc->gdb_read_register =3D mb_cpu_gdb_read_register; cc->gdb_write_register =3D mb_cpu_gdb_write_register; - cc->tlb_fill =3D mb_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D mb_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->do_transaction_failed =3D mb_cpu_transaction_failed; cc->get_phys_page_debug =3D mb_cpu_get_phys_page_debug; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 6c525a6af1..b258560da9 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -252,7 +252,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->tcg_ops.initialize =3D mips_tcg_init; cc->tcg_ops.cpu_exec_interrupt =3D mips_cpu_exec_interrupt; cc->tcg_ops.synchronize_from_tb =3D mips_cpu_synchronize_from_tb; - cc->tlb_fill =3D mips_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D mips_cpu_tlb_fill; #endif =20 cc->gdb_num_core_regs =3D 73; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 224cfc8361..1177d092c1 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -110,7 +110,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) cc->do_interrupt =3D moxie_cpu_do_interrupt; cc->dump_state =3D moxie_cpu_dump_state; cc->set_pc =3D moxie_cpu_set_pc; - cc->tlb_fill =3D moxie_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D moxie_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D moxie_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_moxie_cpu; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 9eeb01fb5b..a96b74b00c 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -197,7 +197,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) cc->dump_state =3D nios2_cpu_dump_state; cc->set_pc =3D nios2_cpu_set_pc; cc->disas_set_info =3D nios2_cpu_disas_set_info; - cc->tlb_fill =3D nios2_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D nios2_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->do_unaligned_access =3D nios2_cpu_do_unaligned_access; cc->get_phys_page_debug =3D nios2_cpu_get_phys_page_debug; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index df8a41f956..e6d1c9764b 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -160,7 +160,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->set_pc =3D openrisc_cpu_set_pc; cc->gdb_read_register =3D openrisc_cpu_gdb_read_register; cc->gdb_write_register =3D openrisc_cpu_gdb_write_register; - cc->tlb_fill =3D openrisc_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D openrisc_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_openrisc_cpu; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 15d58698a6..31a43f7bfb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -562,7 +562,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->vmsd =3D &vmstate_riscv_cpu; #endif cc->tcg_ops.initialize =3D riscv_translate_init; - cc->tlb_fill =3D riscv_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D riscv_cpu_tlb_fill; =20 device_class_set_props(dc, riscv_cpu_properties); } diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 3ba93590d2..c815533223 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -195,7 +195,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) cc->get_phys_page_debug =3D rx_cpu_get_phys_page_debug; cc->disas_set_info =3D rx_cpu_disas_set_info; cc->tcg_ops.initialize =3D rx_translate_init; - cc->tlb_fill =3D rx_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D rx_cpu_tlb_fill; =20 cc->gdb_num_core_regs =3D 26; cc->gdb_core_xml_file =3D "rx-core.xml"; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index add2f4b21f..6cd2b30192 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -513,7 +513,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->disas_set_info =3D s390_cpu_disas_set_info; #ifdef CONFIG_TCG cc->tcg_ops.initialize =3D s390x_translate_init; - cc->tlb_fill =3D s390_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D s390_cpu_tlb_fill; #endif =20 cc->gdb_num_core_regs =3D S390_NUM_CORE_REGS; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 0574194cd0..7a9019edec 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -225,7 +225,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->tcg_ops.synchronize_from_tb =3D superh_cpu_synchronize_from_tb; cc->gdb_read_register =3D superh_cpu_gdb_read_register; cc->gdb_write_register =3D superh_cpu_gdb_write_register; - cc->tlb_fill =3D superh_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D superh_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->do_unaligned_access =3D superh_cpu_do_unaligned_access; cc->get_phys_page_debug =3D superh_cpu_get_phys_page_debug; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index c559f15e14..760e0ea92c 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -871,7 +871,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->tcg_ops.synchronize_from_tb =3D sparc_cpu_synchronize_from_tb; cc->gdb_read_register =3D sparc_cpu_gdb_read_register; cc->gdb_write_register =3D sparc_cpu_gdb_write_register; - cc->tlb_fill =3D sparc_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D sparc_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->do_transaction_failed =3D sparc_cpu_do_transaction_failed; cc->do_unaligned_access =3D sparc_cpu_do_unaligned_access; diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index 4c6176d26e..75b3a4bae3 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -151,7 +151,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void= *data) cc->tcg_ops.cpu_exec_interrupt =3D tilegx_cpu_exec_interrupt; cc->dump_state =3D tilegx_cpu_dump_state; cc->set_pc =3D tilegx_cpu_set_pc; - cc->tlb_fill =3D tilegx_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D tilegx_cpu_tlb_fill; cc->gdb_num_core_regs =3D 0; cc->tcg_ops.initialize =3D tilegx_tcg_init; } diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 5edf96c600..89a14f81d7 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -165,7 +165,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) cc->tcg_ops.synchronize_from_tb =3D tricore_cpu_synchronize_from_tb; cc->get_phys_page_debug =3D tricore_cpu_get_phys_page_debug; cc->tcg_ops.initialize =3D tricore_tcg_init; - cc->tlb_fill =3D tricore_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D tricore_cpu_tlb_fill; } =20 #define DEFINE_TRICORE_CPU_TYPE(cpu_model, initfn) \ diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 84c3419989..a57d315d2f 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -135,7 +135,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) cc->tcg_ops.cpu_exec_interrupt =3D uc32_cpu_exec_interrupt; cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; - cc->tlb_fill =3D uc32_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D uc32_cpu_tlb_fill; cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; cc->tcg_ops.initialize =3D uc32_translate_init; dc->vmsd =3D &vmstate_uc32_cpu; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 42a5e4ebe8..e764dbeb73 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -201,7 +201,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_read_register =3D xtensa_cpu_gdb_read_register; cc->gdb_write_register =3D xtensa_cpu_gdb_write_register; cc->gdb_stop_before_watchpoint =3D true; - cc->tlb_fill =3D xtensa_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D xtensa_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->do_unaligned_access =3D xtensa_cpu_do_unaligned_access; cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index e82c92bcf8..16d92f0a49 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10950,7 +10950,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) #ifdef CONFIG_TCG cc->tcg_ops.initialize =3D ppc_translate_init; cc->tcg_ops.cpu_exec_interrupt =3D ppc_cpu_exec_interrupt; - cc->tlb_fill =3D ppc_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D ppc_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->tcg_ops.cpu_exec_enter =3D ppc_cpu_exec_enter; cc->tcg_ops.cpu_exec_exit =3D ppc_cpu_exec_exit; --=20 2.26.2 From nobody Mon May 20 22:41:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607676183; cv=none; d=zohomail.com; s=zohoarc; b=aXtVfDbCN3wZWdXYNcGFjzAwcbelb0dFGWWqtPR0y7yOcP8Ez6ul9qJsh+WM3WLON7Gs35yCzM6bwCvOKD+VeP3CAuyW0TuUejPXQcXgpwDXOOcqihIFnbMQG+gbqaNfp7I47GkxtHfLYoekSrBL26zAxUSN8czMURHBsk56QAc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607676183; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Fri, 11 Dec 2020 03:32:22 -0500 Received: from mx2.suse.de ([195.135.220.15]:35426) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqW-0002Aq-L5 for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:32:21 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 8DDBBB1C1; Fri, 11 Dec 2020 08:32:00 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 21/25] cpu: Move debug_excp_handler to tcg_ops Date: Fri, 11 Dec 2020 09:31:39 +0100 Message-Id: <20201211083143.14350-22-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211083143.14350-1-cfontana@suse.de> References: <20201211083143.14350-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Colin Xu , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Eduardo Habkost Signed-off-by: Eduardo Habkost Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 2 -- include/hw/core/tcg-cpu-ops.h | 2 ++ accel/tcg/cpu-exec.c | 4 ++-- target/arm/cpu.c | 2 +- target/i386/tcg/tcg-cpu.c | 2 +- target/lm32/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- 8 files changed, 9 insertions(+), 9 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index c82ef261c6..f438abb785 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -121,7 +121,6 @@ struct TranslationBlock; * @gdb_write_register: Callback for letting GDB write a register. * @debug_check_watchpoint: Callback: return true if the architectural * watchpoint whose address has matched should really fire. - * @debug_excp_handler: Callback for handling debug exceptions. * @write_elf64_note: Callback for writing a CPU-specific ELF note to a * 64-bit VM coredump. * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF @@ -184,7 +183,6 @@ struct CPUClass { int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); - void (*debug_excp_handler)(CPUState *cpu); =20 int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, int cpuid, void *opaque); diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index deeabbcf33..322204c441 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -50,6 +50,8 @@ typedef struct TcgCpuOperations { bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); + /** @debug_excp_handler: Callback for handling debug exceptions */ + void (*debug_excp_handler)(CPUState *cpu); } TcgCpuOperations; =20 #endif /* TCG_CPU_OPS_H */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 502f6a53ae..17dc86af50 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -482,8 +482,8 @@ static inline void cpu_handle_debug_exception(CPUState = *cpu) } } =20 - if (cc->debug_excp_handler) { - cc->debug_excp_handler(cpu); + if (cc->tcg_ops.debug_excp_handler) { + cc->tcg_ops.debug_excp_handler(cpu); } } =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c9aee4d566..d27bc5ef0a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2265,7 +2265,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->tcg_ops.cpu_exec_interrupt =3D arm_cpu_exec_interrupt; cc->tcg_ops.synchronize_from_tb =3D arm_cpu_synchronize_from_tb; cc->tcg_ops.tlb_fill =3D arm_cpu_tlb_fill; - cc->debug_excp_handler =3D arm_debug_excp_handler; + cc->tcg_ops.debug_excp_handler =3D arm_debug_excp_handler; cc->debug_check_watchpoint =3D arm_debug_check_watchpoint; cc->do_unaligned_access =3D arm_cpu_do_unaligned_access; #if !defined(CONFIG_USER_ONLY) diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 8606dd6a3e..38ed8bf6d3 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -66,6 +66,6 @@ void tcg_cpu_common_class_init(CPUClass *cc) cc->tcg_ops.initialize =3D tcg_x86_init; cc->tcg_ops.tlb_fill =3D x86_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY - cc->debug_excp_handler =3D breakpoint_handler; + cc->tcg_ops.debug_excp_handler =3D breakpoint_handler; #endif } diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index 76dc728858..bbe1405e32 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -235,7 +235,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) #endif cc->gdb_num_core_regs =3D 32 + 7; cc->gdb_stop_before_watchpoint =3D true; - cc->debug_excp_handler =3D lm32_debug_excp_handler; + cc->tcg_ops.debug_excp_handler =3D lm32_debug_excp_handler; cc->disas_set_info =3D lm32_cpu_disas_set_info; cc->tcg_ops.initialize =3D lm32_translate_init; } diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 6cd2b30192..04856076b3 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -506,7 +506,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->write_elf64_note =3D s390_cpu_write_elf64_note; #ifdef CONFIG_TCG cc->tcg_ops.cpu_exec_interrupt =3D s390_cpu_exec_interrupt; - cc->debug_excp_handler =3D s390x_cpu_debug_excp_handler; + cc->tcg_ops.debug_excp_handler =3D s390x_cpu_debug_excp_handler; cc->do_unaligned_access =3D s390x_cpu_do_unaligned_access; #endif #endif diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index e764dbeb73..b6f13ceb32 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -207,7 +207,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; cc->do_transaction_failed =3D xtensa_cpu_do_transaction_failed; #endif - cc->debug_excp_handler =3D xtensa_breakpoint_handler; + cc->tcg_ops.debug_excp_handler =3D xtensa_breakpoint_handler; cc->disas_set_info =3D xtensa_cpu_disas_set_info; cc->tcg_ops.initialize =3D xtensa_translate_init; dc->vmsd =3D &vmstate_xtensa_cpu; --=20 2.26.2 From nobody Mon May 20 22:41:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Fri, 11 Dec 2020 00:53:30 -0800 (PST) Received: from localhost ([::1]:60382 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kneB7-00084u-Lz for importer@patchew.org; Fri, 11 Dec 2020 03:53:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42656) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqk-0008Ur-Me for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:32:26 -0500 Received: from mx2.suse.de ([195.135.220.15]:35444) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqX-0002At-8B for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:32:25 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 42818B16A; Fri, 11 Dec 2020 08:32:01 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 22/25] target/arm: do not use cc->do_interrupt for KVM directly Date: Fri, 11 Dec 2020 09:31:40 +0100 Message-Id: <20201211083143.14350-23-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211083143.14350-1-cfontana@suse.de> References: <20201211083143.14350-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" cc->do_interrupt is in theory a TCG callback used in accel/tcg only, to prepare the emulated architecture to take an interrupt as defined in the hardware specifications, but in reality the _do_interrupt style of functions in targets are also occasionally reused by KVM to prepare the architecture state in a similar way where userspace code has identified that it needs to deliver an exception to the guest. In the case of ARM, that includes: 1) the vcpu thread got a SIGBUS indicating a memory error, and we need to deliver a Synchronous External Abort to the guest to let it know about the error. 2) the kernel told us about a debug exception (breakpoint, watchpoint) but it is not for one of QEMU's own gdbstub breakpoints/watchpoints so it must be a breakpoint the guest itself has set up, therefore we need to deliver it to the guest. So in order to reuse code, the same arm_do_interrupt function is used. This is all fine, but we need to avoid calling it using the callback registered in CPUClass, since that one is now TCG-only. Fortunately this is easily solved by replacing calls to CPUClass::do_interrupt() with explicit calls to arm_do_interrupt(). Signed-off-by: Claudio Fontana Cc: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/helper.c | 4 ++++ target/arm/kvm64.c | 6 ++---- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 38cd35c049..bebaabf525 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9895,6 +9895,10 @@ static void handle_semihosting(CPUState *cs) * Do any appropriate logging, handle PSCI calls, and then hand off * to the AArch64-entry or AArch32-entry function depending on the * target exception level's register width. + * + * Note: this is used for both TCG (as the do_interrupt tcg op), + * and KVM to re-inject guest debug exceptions, and to + * inject a Synchronous-External-Abort. */ void arm_cpu_do_interrupt(CPUState *cs) { diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index f74bac2457..3728b3a336 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -944,7 +944,6 @@ static void kvm_inject_arm_sea(CPUState *c) { ARMCPU *cpu =3D ARM_CPU(c); CPUARMState *env =3D &cpu->env; - CPUClass *cc =3D CPU_GET_CLASS(c); uint32_t esr; bool same_el; =20 @@ -960,7 +959,7 @@ static void kvm_inject_arm_sea(CPUState *c) =20 env->exception.syndrome =3D esr; =20 - cc->do_interrupt(c); + arm_cpu_do_interrupt(c); } =20 #define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ @@ -1491,7 +1490,6 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_de= bug_exit_arch *debug_exit) { int hsr_ec =3D syn_get_ec(debug_exit->hsr); ARMCPU *cpu =3D ARM_CPU(cs); - CPUClass *cc =3D CPU_GET_CLASS(cs); CPUARMState *env =3D &cpu->env; =20 /* Ensure PC is synchronised */ @@ -1545,7 +1543,7 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_de= bug_exit_arch *debug_exit) env->exception.vaddress =3D debug_exit->far; env->exception.target_el =3D 1; qemu_mutex_lock_iothread(); - cc->do_interrupt(cs); + arm_cpu_do_interrupt(cs); qemu_mutex_unlock_iothread(); =20 return false; --=20 2.26.2 From nobody Mon May 20 22:41:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 2 -- include/hw/core/tcg-cpu-ops.h | 3 +++ accel/tcg/cpu-exec.c | 4 ++-- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 4 ++-- target/arm/cpu_tcg.c | 9 ++++----- target/avr/cpu.c | 2 +- target/avr/helper.c | 4 ++-- target/cris/cpu.c | 12 ++++++------ target/cris/helper.c | 4 ++-- target/hppa/cpu.c | 2 +- target/i386/tcg/tcg-cpu.c | 2 +- target/lm32/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 4 ++-- target/moxie/cpu.c | 2 +- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tilegx/cpu.c | 2 +- target/unicore32/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- target/ppc/translate_init.c.inc | 2 +- 28 files changed, 42 insertions(+), 42 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index f438abb785..b178549d48 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -87,7 +87,6 @@ struct TranslationBlock; * @parse_features: Callback to parse command line arguments. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. * @has_work: Callback for checking if there is work to do. - * @do_interrupt: Callback for interrupt handling. * @do_unaligned_access: Callback for unaligned access handling, if * the target defines #TARGET_ALIGNED_ONLY. * @do_transaction_failed: Callback for handling failed memory transactions @@ -157,7 +156,6 @@ struct CPUClass { =20 int reset_dump_flags; bool (*has_work)(CPUState *cpu); - void (*do_interrupt)(CPUState *cpu); void (*do_unaligned_access)(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 322204c441..a7387b5c39 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -38,6 +38,9 @@ typedef struct TcgCpuOperations { void (*cpu_exec_exit)(CPUState *cpu); /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exe= c */ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); + /** @do_interrupt: Callback for interrupt handling. */ + void (*do_interrupt)(CPUState *cpu); + /** * @tlb_fill: Handle a softmmu tlb miss or user-only address fault * diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 17dc86af50..eafd600085 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -517,7 +517,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, = int *ret) loop */ #if defined(TARGET_I386) CPUClass *cc =3D CPU_GET_CLASS(cpu); - cc->do_interrupt(cpu); + cc->tcg_ops.do_interrupt(cpu); #endif *ret =3D cpu->exception_index; cpu->exception_index =3D -1; @@ -526,7 +526,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, = int *ret) if (replay_exception()) { CPUClass *cc =3D CPU_GET_CLASS(cpu); qemu_mutex_lock_iothread(); - cc->do_interrupt(cpu); + cc->tcg_ops.do_interrupt(cpu); qemu_mutex_unlock_iothread(); cpu->exception_index =3D -1; =20 diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 9f36f824fd..66f1166672 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -217,7 +217,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) =20 cc->class_by_name =3D alpha_cpu_class_by_name; cc->has_work =3D alpha_cpu_has_work; - cc->do_interrupt =3D alpha_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D alpha_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D alpha_cpu_exec_interrupt; cc->dump_state =3D alpha_cpu_dump_state; cc->set_pc =3D alpha_cpu_set_pc; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d27bc5ef0a..1d0fe58771 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -586,7 +586,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt= _request) found: cs->exception_index =3D excp_idx; env->exception.target_el =3D target_el; - cc->do_interrupt(cs); + cc->tcg_ops.do_interrupt(cs); return true; } =20 @@ -2246,7 +2246,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D arm_cpu_gdb_read_register; cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->do_interrupt =3D arm_cpu_do_interrupt; cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs =3D arm_asidx_from_attrs; cc->vmsd =3D &vmstate_arm_cpu; @@ -2271,6 +2270,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) #if !defined(CONFIG_USER_ONLY) cc->do_transaction_failed =3D arm_cpu_do_transaction_failed; cc->adjust_watchpoint_address =3D arm_adjust_watchpoint_address; + cc->tcg_ops.do_interrupt =3D arm_cpu_do_interrupt; #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ #endif } diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index e261839d08..451a6a5a40 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -34,7 +34,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int = interrupt_request) if (interrupt_request & CPU_INTERRUPT_HARD && (armv7m_nvic_can_take_pending_exception(env->nvic))) { cs->exception_index =3D EXCP_IRQ; - cc->do_interrupt(cs); + cc->tcg_ops.do_interrupt(cs); ret =3D true; } return ret; @@ -626,12 +626,11 @@ static void arm_v7m_class_init(ObjectClass *oc, void = *data) CPUClass *cc =3D CPU_CLASS(oc); =20 acc->info =3D data; +#ifdef CONFIG_TCG + cc->tcg_ops.cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt; #ifndef CONFIG_USER_ONLY - cc->do_interrupt =3D arm_v7m_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D arm_v7m_cpu_do_interrupt; #endif - -#ifdef CONFIG_TCG - cc->tcg_ops.cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt; #endif /* CONFIG_TCG */ =20 cc->gdb_core_xml_file =3D "arm-m-profile.xml"; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 699055de7c..5a5ae68444 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -197,7 +197,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->class_by_name =3D avr_cpu_class_by_name; =20 cc->has_work =3D avr_cpu_has_work; - cc->do_interrupt =3D avr_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D avr_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D avr_cpu_exec_interrupt; cc->dump_state =3D avr_cpu_dump_state; cc->set_pc =3D avr_cpu_set_pc; diff --git a/target/avr/helper.c b/target/avr/helper.c index d96d14372b..69d3b6181f 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -34,7 +34,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_r= equest) if (interrupt_request & CPU_INTERRUPT_RESET) { if (cpu_interrupts_enabled(env)) { cs->exception_index =3D EXCP_RESET; - cc->do_interrupt(cs); + cc->tcg_ops.do_interrupt(cs); =20 cs->interrupt_request &=3D ~CPU_INTERRUPT_RESET; =20 @@ -45,7 +45,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_r= equest) if (cpu_interrupts_enabled(env) && env->intsrc !=3D 0) { int index =3D ctz32(env->intsrc); cs->exception_index =3D EXCP_INT(index); - cc->do_interrupt(cs); + cc->tcg_ops.do_interrupt(cs); =20 env->intsrc &=3D env->intsrc - 1; /* clear the interrupt */ cs->interrupt_request &=3D ~CPU_INTERRUPT_HARD; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 9222717f3e..b65743e8ca 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -199,7 +199,7 @@ static void crisv8_cpu_class_init(ObjectClass *oc, void= *data) CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); =20 ccc->vr =3D 8; - cc->do_interrupt =3D crisv10_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; } @@ -210,7 +210,7 @@ static void crisv9_cpu_class_init(ObjectClass *oc, void= *data) CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); =20 ccc->vr =3D 9; - cc->do_interrupt =3D crisv10_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; } @@ -221,7 +221,7 @@ static void crisv10_cpu_class_init(ObjectClass *oc, voi= d *data) CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); =20 ccc->vr =3D 10; - cc->do_interrupt =3D crisv10_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; } @@ -232,7 +232,7 @@ static void crisv11_cpu_class_init(ObjectClass *oc, voi= d *data) CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); =20 ccc->vr =3D 11; - cc->do_interrupt =3D crisv10_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; } @@ -243,7 +243,7 @@ static void crisv17_cpu_class_init(ObjectClass *oc, voi= d *data) CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); =20 ccc->vr =3D 17; - cc->do_interrupt =3D crisv10_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; } @@ -268,7 +268,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) =20 cc->class_by_name =3D cris_cpu_class_by_name; cc->has_work =3D cris_cpu_has_work; - cc->do_interrupt =3D cris_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D cris_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D cris_cpu_exec_interrupt; cc->dump_state =3D cris_cpu_dump_state; cc->set_pc =3D cris_cpu_set_pc; diff --git a/target/cris/helper.c b/target/cris/helper.c index ed45c3d9b7..1f4d6f7d45 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -299,7 +299,7 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) && (env->pregs[PR_CCS] & I_FLAG) && !env->locked_irq) { cs->exception_index =3D EXCP_IRQ; - cc->do_interrupt(cs); + cc->tcg_ops.do_interrupt(cs); ret =3D true; } if (interrupt_request & CPU_INTERRUPT_NMI) { @@ -311,7 +311,7 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) } if ((env->pregs[PR_CCS] & m_flag_archval)) { cs->exception_index =3D EXCP_NMI; - cc->do_interrupt(cs); + cc->tcg_ops.do_interrupt(cs); ret =3D true; } } diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index e2d79f954e..cce6ae6213 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -139,7 +139,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) =20 cc->class_by_name =3D hppa_cpu_class_by_name; cc->has_work =3D hppa_cpu_has_work; - cc->do_interrupt =3D hppa_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D hppa_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D hppa_cpu_exec_interrupt; cc->dump_state =3D hppa_cpu_dump_state; cc->set_pc =3D hppa_cpu_set_pc; diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 38ed8bf6d3..d2dd521612 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -58,7 +58,7 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, Tra= nslationBlock *tb) =20 void tcg_cpu_common_class_init(CPUClass *cc) { - cc->do_interrupt =3D x86_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D x86_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D x86_cpu_exec_interrupt; cc->tcg_ops.synchronize_from_tb =3D x86_cpu_synchronize_from_tb; cc->tcg_ops.cpu_exec_enter =3D x86_cpu_exec_enter; diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index bbe1405e32..fb3761b749 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -222,7 +222,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) =20 cc->class_by_name =3D lm32_cpu_class_by_name; cc->has_work =3D lm32_cpu_has_work; - cc->do_interrupt =3D lm32_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D lm32_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D lm32_cpu_exec_interrupt; cc->dump_state =3D lm32_cpu_dump_state; cc->set_pc =3D lm32_cpu_set_pc; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index bc109faa21..3e84de772c 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -277,7 +277,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) =20 cc->class_by_name =3D m68k_cpu_class_by_name; cc->has_work =3D m68k_cpu_has_work; - cc->do_interrupt =3D m68k_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D m68k_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D m68k_cpu_exec_interrupt; cc->dump_state =3D m68k_cpu_dump_state; cc->set_pc =3D m68k_cpu_set_pc; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 6e660a27b8..4f95248b2e 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -317,7 +317,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) =20 cc->class_by_name =3D mb_cpu_class_by_name; cc->has_work =3D mb_cpu_has_work; - cc->do_interrupt =3D mb_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D mb_cpu_do_interrupt; cc->do_unaligned_access =3D mb_cpu_do_unaligned_access; cc->tcg_ops.cpu_exec_interrupt =3D mb_cpu_exec_interrupt; cc->dump_state =3D mb_cpu_dump_state; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index b258560da9..25c4a55a6a 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -236,7 +236,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) =20 cc->class_by_name =3D mips_cpu_class_by_name; cc->has_work =3D mips_cpu_has_work; - cc->do_interrupt =3D mips_cpu_do_interrupt; cc->dump_state =3D mips_cpu_dump_state; cc->set_pc =3D mips_cpu_set_pc; cc->gdb_read_register =3D mips_cpu_gdb_read_register; @@ -250,10 +249,11 @@ static void mips_cpu_class_init(ObjectClass *c, void = *data) cc->disas_set_info =3D mips_cpu_disas_set_info; #ifdef CONFIG_TCG cc->tcg_ops.initialize =3D mips_tcg_init; + cc->tcg_ops.do_interrupt =3D mips_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D mips_cpu_exec_interrupt; cc->tcg_ops.synchronize_from_tb =3D mips_cpu_synchronize_from_tb; cc->tcg_ops.tlb_fill =3D mips_cpu_tlb_fill; -#endif +#endif /* CONFIG_TCG */ =20 cc->gdb_num_core_regs =3D 73; cc->gdb_stop_before_watchpoint =3D true; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 1177d092c1..36bef4d357 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -107,7 +107,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) cc->class_by_name =3D moxie_cpu_class_by_name; =20 cc->has_work =3D moxie_cpu_has_work; - cc->do_interrupt =3D moxie_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D moxie_cpu_do_interrupt; cc->dump_state =3D moxie_cpu_dump_state; cc->set_pc =3D moxie_cpu_set_pc; cc->tcg_ops.tlb_fill =3D moxie_cpu_tlb_fill; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index a96b74b00c..2b959f0e49 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -192,7 +192,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) =20 cc->class_by_name =3D nios2_cpu_class_by_name; cc->has_work =3D nios2_cpu_has_work; - cc->do_interrupt =3D nios2_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D nios2_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D nios2_cpu_exec_interrupt; cc->dump_state =3D nios2_cpu_dump_state; cc->set_pc =3D nios2_cpu_set_pc; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index e6d1c9764b..27105c5c09 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -154,7 +154,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) =20 cc->class_by_name =3D openrisc_cpu_class_by_name; cc->has_work =3D openrisc_cpu_has_work; - cc->do_interrupt =3D openrisc_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D openrisc_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt; cc->dump_state =3D openrisc_cpu_dump_state; cc->set_pc =3D openrisc_cpu_set_pc; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 31a43f7bfb..6a815569cc 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -539,7 +539,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) =20 cc->class_by_name =3D riscv_cpu_class_by_name; cc->has_work =3D riscv_cpu_has_work; - cc->do_interrupt =3D riscv_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D riscv_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D riscv_cpu_exec_interrupt; cc->dump_state =3D riscv_cpu_dump_state; cc->set_pc =3D riscv_cpu_set_pc; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index c815533223..dc7d1c3c57 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -185,7 +185,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) =20 cc->class_by_name =3D rx_cpu_class_by_name; cc->has_work =3D rx_cpu_has_work; - cc->do_interrupt =3D rx_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D rx_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D rx_cpu_exec_interrupt; cc->dump_state =3D rx_cpu_dump_state; cc->set_pc =3D rx_cpu_set_pc; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 04856076b3..b838bd61a4 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -493,7 +493,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->class_by_name =3D s390_cpu_class_by_name, cc->has_work =3D s390_cpu_has_work; #ifdef CONFIG_TCG - cc->do_interrupt =3D s390_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D s390_cpu_do_interrupt; #endif cc->dump_state =3D s390_cpu_dump_state; cc->set_pc =3D s390_cpu_set_pc; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 7a9019edec..ff835d4bc1 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -218,7 +218,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->class_by_name =3D superh_cpu_class_by_name; cc->has_work =3D superh_cpu_has_work; - cc->do_interrupt =3D superh_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D superh_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D superh_cpu_exec_interrupt; cc->dump_state =3D superh_cpu_dump_state; cc->set_pc =3D superh_cpu_set_pc; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 760e0ea92c..3f23aa5962 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -861,7 +861,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->class_by_name =3D sparc_cpu_class_by_name; cc->parse_features =3D sparc_cpu_parse_features; cc->has_work =3D sparc_cpu_has_work; - cc->do_interrupt =3D sparc_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D sparc_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D sparc_cpu_exec_interrupt; cc->dump_state =3D sparc_cpu_dump_state; #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index 75b3a4bae3..7d4ead4ef1 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -147,7 +147,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->class_by_name =3D tilegx_cpu_class_by_name; cc->has_work =3D tilegx_cpu_has_work; - cc->do_interrupt =3D tilegx_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D tilegx_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D tilegx_cpu_exec_interrupt; cc->dump_state =3D tilegx_cpu_dump_state; cc->set_pc =3D tilegx_cpu_set_pc; diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index a57d315d2f..e27ffc571a 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -131,7 +131,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) =20 cc->class_by_name =3D uc32_cpu_class_by_name; cc->has_work =3D uc32_cpu_has_work; - cc->do_interrupt =3D uc32_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D uc32_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D uc32_cpu_exec_interrupt; cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index b6f13ceb32..3ff025f0fe 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -194,7 +194,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->class_by_name =3D xtensa_cpu_class_by_name; cc->has_work =3D xtensa_cpu_has_work; - cc->do_interrupt =3D xtensa_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D xtensa_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D xtensa_cpu_exec_interrupt; cc->dump_state =3D xtensa_cpu_dump_state; cc->set_pc =3D xtensa_cpu_set_pc; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 16d92f0a49..dc13ff2cf8 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10912,7 +10912,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) pcc->parent_parse_features =3D cc->parse_features; cc->parse_features =3D ppc_cpu_parse_featurestr; cc->has_work =3D ppc_cpu_has_work; - cc->do_interrupt =3D ppc_cpu_do_interrupt; cc->dump_state =3D ppc_cpu_dump_state; cc->dump_statistics =3D ppc_cpu_dump_statistics; cc->set_pc =3D ppc_cpu_set_pc; @@ -10950,6 +10949,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) #ifdef CONFIG_TCG cc->tcg_ops.initialize =3D ppc_translate_init; cc->tcg_ops.cpu_exec_interrupt =3D ppc_cpu_exec_interrupt; + cc->tcg_ops.do_interrupt =3D ppc_cpu_do_interrupt; cc->tcg_ops.tlb_fill =3D ppc_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->tcg_ops.cpu_exec_enter =3D ppc_cpu_exec_enter; --=20 2.26.2 From nobody Mon May 20 22:41:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607676543; cv=none; d=zohomail.com; s=zohoarc; b=I74PK0S3/bf7UitusP59KpPVLj9g/cALXh1t6CiqZUW/QNGlm+nbkiX5A3JfFM9rJGL8y5K3JWBJm+YijIvUuEvjJbwMmWGCqsYPxAQTp0WLTSBSx7ase7eBiVf0ce9zobwH7NEnF2D+F2oeEuRNaDi4xpIL5JuKIZteg8f8tpk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607676543; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Fri, 11 Dec 2020 03:32:25 -0500 Received: from mx2.suse.de ([195.135.220.15]:35558) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqZ-0002B6-2H for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:32:24 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id AB74CB1C9; Fri, 11 Dec 2020 08:32:02 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 24/25] cpu: move cc->transaction_failed to tcg_ops Date: Fri, 11 Dec 2020 09:31:42 +0100 Message-Id: <20201211083143.14350-25-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211083143.14350-1-cfontana@suse.de> References: <20201211083143.14350-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 18 +++++++----------- include/hw/core/tcg-cpu-ops.h | 14 ++++++++++++++ hw/mips/jazz.c | 9 +++++++-- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 4 ++-- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 4 +++- target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 2 +- target/sparc/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- target/xtensa/helper.c | 4 ++-- 13 files changed, 42 insertions(+), 25 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index b178549d48..0c6c17fb48 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -89,8 +89,6 @@ struct TranslationBlock; * @has_work: Callback for checking if there is work to do. * @do_unaligned_access: Callback for unaligned access handling, if * the target defines #TARGET_ALIGNED_ONLY. - * @do_transaction_failed: Callback for handling failed memory transactions - * (ie bus faults or external aborts; not MMU faults) * @virtio_is_big_endian: Callback to return %true if a CPU which supports * runtime configurable endianness is currently big-endian. Non-configurab= le * CPUs can use the default implementation of this method. This method sho= uld @@ -159,10 +157,6 @@ struct CPUClass { void (*do_unaligned_access)(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); - void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr ad= dr, - unsigned size, MMUAccessType access_type, - int mmu_idx, MemTxAttrs attrs, - MemTxResult response, uintptr_t retaddr); bool (*virtio_is_big_endian)(CPUState *cpu); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); @@ -848,7 +842,7 @@ static inline void cpu_unaligned_access(CPUState *cpu, = vaddr addr, =20 cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr); } - +#ifdef CONFIG_TCG static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, @@ -858,12 +852,14 @@ static inline void cpu_transaction_failed(CPUState *c= pu, hwaddr physaddr, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (!cpu->ignore_memory_transaction_failures && cc->do_transaction_fai= led) { - cc->do_transaction_failed(cpu, physaddr, addr, size, access_type, - mmu_idx, attrs, response, retaddr); + if (!cpu->ignore_memory_transaction_failures && + cc->tcg_ops.do_transaction_failed) { + cc->tcg_ops.do_transaction_failed(cpu, physaddr, addr, size, acces= s_type, + mmu_idx, attrs, response, retadd= r); } } -#endif +#endif /* CONFIG_TCG */ +#endif /* CONFIG_SOFTMMU */ =20 #endif /* NEED_CPU_H */ =20 diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index a7387b5c39..dbf17c4f96 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -11,6 +11,7 @@ #define TCG_CPU_OPS_H =20 #include "hw/core/cpu.h" +#include "exec/memattrs.h" =20 /** * struct TcgCpuOperations: TCG operations specific to a CPU class @@ -55,6 +56,19 @@ typedef struct TcgCpuOperations { bool probe, uintptr_t retaddr); /** @debug_excp_handler: Callback for handling debug exceptions */ void (*debug_excp_handler)(CPUState *cpu); + +#ifndef CONFIG_USER_ONLY + /** + * @do_transaction_failed: Callback for handling failed memory transac= tions + * (ie bus faults or external aborts; not MMU faults) + */ + void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr ad= dr, + unsigned size, MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr); + +#endif /* !CONFIG_USER_ONLY */ + } TcgCpuOperations; =20 #endif /* TCG_CPU_OPS_H */ diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c index 71448f72ac..753256d377 100644 --- a/hw/mips/jazz.c +++ b/hw/mips/jazz.c @@ -115,6 +115,8 @@ static const MemoryRegionOps dma_dummy_ops =3D { #define MAGNUM_BIOS_SIZE_MAX 0x7e000 #define MAGNUM_BIOS_SIZE = \ (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_M= AX) + +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static void (*real_do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, @@ -136,6 +138,7 @@ static void mips_jazz_do_transaction_failed(CPUState *c= s, hwaddr physaddr, (*real_do_transaction_failed)(cs, physaddr, addr, size, access_type, mmu_idx, attrs, response, retaddr); } +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ =20 static void mips_jazz_init(MachineState *machine, enum jazz_model_e jazz_model) @@ -204,8 +207,10 @@ static void mips_jazz_init(MachineState *machine, * memory region that catches all memory accesses, as we do on Malta. */ cc =3D CPU_GET_CLASS(cpu); - real_do_transaction_failed =3D cc->do_transaction_failed; - cc->do_transaction_failed =3D mips_jazz_do_transaction_failed; +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) + real_do_transaction_failed =3D cc->tcg_ops.do_transaction_failed; + cc->tcg_ops.do_transaction_failed =3D mips_jazz_do_transaction_failed; +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ =20 /* allocate RAM */ memory_region_add_subregion(address_space, 0, machine->ram); diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 66f1166672..a1696bebeb 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -225,7 +225,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D alpha_cpu_gdb_write_register; cc->tcg_ops.tlb_fill =3D alpha_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY - cc->do_transaction_failed =3D alpha_cpu_do_transaction_failed; + cc->tcg_ops.do_transaction_failed =3D alpha_cpu_do_transaction_failed; cc->do_unaligned_access =3D alpha_cpu_do_unaligned_access; cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_alpha_cpu; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1d0fe58771..39663d2861 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2268,11 +2268,11 @@ static void arm_cpu_class_init(ObjectClass *oc, voi= d *data) cc->debug_check_watchpoint =3D arm_debug_check_watchpoint; cc->do_unaligned_access =3D arm_cpu_do_unaligned_access; #if !defined(CONFIG_USER_ONLY) - cc->do_transaction_failed =3D arm_cpu_do_transaction_failed; + cc->tcg_ops.do_transaction_failed =3D arm_cpu_do_transaction_failed; cc->adjust_watchpoint_address =3D arm_adjust_watchpoint_address; cc->tcg_ops.do_interrupt =3D arm_cpu_do_interrupt; #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ -#endif +#endif /* CONFIG_TCG */ } =20 #ifdef CONFIG_KVM diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 3e84de772c..3f60c99865 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -285,7 +285,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_write_register =3D m68k_cpu_gdb_write_register; cc->tcg_ops.tlb_fill =3D m68k_cpu_tlb_fill; #if defined(CONFIG_SOFTMMU) - cc->do_transaction_failed =3D m68k_cpu_transaction_failed; + cc->tcg_ops.do_transaction_failed =3D m68k_cpu_transaction_failed; cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D m68k_cpu_disas_set_info; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 4f95248b2e..fa57a324dc 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -327,7 +327,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->gdb_write_register =3D mb_cpu_gdb_write_register; cc->tcg_ops.tlb_fill =3D mb_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY - cc->do_transaction_failed =3D mb_cpu_transaction_failed; + cc->tcg_ops.do_transaction_failed =3D mb_cpu_transaction_failed; cc->get_phys_page_debug =3D mb_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_mb_cpu; #endif diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 25c4a55a6a..fe8bca41b7 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -241,7 +241,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_read_register =3D mips_cpu_gdb_read_register; cc->gdb_write_register =3D mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->do_transaction_failed =3D mips_cpu_do_transaction_failed; cc->do_unaligned_access =3D mips_cpu_do_unaligned_access; cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_mips_cpu; @@ -253,6 +252,9 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->tcg_ops.cpu_exec_interrupt =3D mips_cpu_exec_interrupt; cc->tcg_ops.synchronize_from_tb =3D mips_cpu_synchronize_from_tb; cc->tcg_ops.tlb_fill =3D mips_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY + cc->tcg_ops.do_transaction_failed =3D mips_cpu_do_transaction_failed; +#endif /* CONFIG_USER_ONLY */ #endif /* CONFIG_TCG */ =20 cc->gdb_num_core_regs =3D 73; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6a815569cc..7dfd8d7339 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -555,7 +555,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->gdb_stop_before_watchpoint =3D true; cc->disas_set_info =3D riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY - cc->do_transaction_failed =3D riscv_cpu_do_transaction_failed; + cc->tcg_ops.do_transaction_failed =3D riscv_cpu_do_transaction_failed; cc->do_unaligned_access =3D riscv_cpu_do_unaligned_access; cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; /* For now, mark unmigratable: */ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index a2787b1d48..4c3e0382ce 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -667,7 +667,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr = addr, env->badaddr =3D addr; riscv_raise_exception(env, cs->exception_index, retaddr); } -#endif +#endif /* !CONFIG_USER_ONLY */ =20 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 3f23aa5962..009d0f07c3 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -873,7 +873,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D sparc_cpu_gdb_write_register; cc->tcg_ops.tlb_fill =3D sparc_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY - cc->do_transaction_failed =3D sparc_cpu_do_transaction_failed; + cc->tcg_ops.do_transaction_failed =3D sparc_cpu_do_transaction_failed; cc->do_unaligned_access =3D sparc_cpu_do_unaligned_access; cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_sparc_cpu; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 3ff025f0fe..fc52fde696 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -205,7 +205,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) #ifndef CONFIG_USER_ONLY cc->do_unaligned_access =3D xtensa_cpu_do_unaligned_access; cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; - cc->do_transaction_failed =3D xtensa_cpu_do_transaction_failed; + cc->tcg_ops.do_transaction_failed =3D xtensa_cpu_do_transaction_failed; #endif cc->tcg_ops.debug_excp_handler =3D xtensa_breakpoint_handler; cc->disas_set_info =3D xtensa_cpu_disas_set_info; diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 05e2b7f70a..eeffee297d 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -261,7 +261,7 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, cpu_loop_exit_restore(cs, retaddr); } =20 -#else +#else /* !CONFIG_USER_ONLY */ =20 void xtensa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, @@ -337,4 +337,4 @@ void xtensa_runstall(CPUXtensaState *env, bool runstall) qemu_cpu_kick(cpu); } } -#endif +#endif /* !CONFIG_USER_ONLY */ --=20 2.26.2 From nobody Mon May 20 22:41:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607676562; cv=none; d=zohomail.com; s=zohoarc; b=NMtR7/HBbCpJl8mqC4VC3ub0WRrCSbWTV/tP6RbxfXyS/y3WdsX3Wqzwx2DMmF0v8FFMAlpq8/UTUhzErKm206L7hqgGZPteIxhCy1bbPUFrpHcr9RsKcg6aRUXFqTBX6OwvUW9ljYX07KK+vO2xu3ftV7wUdMCVDLg8B8vhOXI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607676562; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Fri, 11 Dec 2020 03:32:32 -0500 Received: from mx2.suse.de ([195.135.220.15]:35644) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kndqi-0002DH-3V for qemu-devel@nongnu.org; Fri, 11 Dec 2020 03:32:32 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 6A36BAFFA; Fri, 11 Dec 2020 08:32:03 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v11 25/25] cpu: move do_unaligned_access to tcg_ops Date: Fri, 11 Dec 2020 09:31:43 +0100 Message-Id: <20201211083143.14350-26-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211083143.14350-1-cfontana@suse.de> References: <20201211083143.14350-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" make it consistently SOFTMMU-only. Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 17 +++-------------- include/hw/core/tcg-cpu-ops.h | 7 +++++++ target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/hppa/cpu.c | 4 +++- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 3 ++- target/nios2/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/s390x/excp_helper.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- target/ppc/translate_init.c.inc | 2 +- 15 files changed, 26 insertions(+), 27 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 0c6c17fb48..db54223983 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -87,8 +87,6 @@ struct TranslationBlock; * @parse_features: Callback to parse command line arguments. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. * @has_work: Callback for checking if there is work to do. - * @do_unaligned_access: Callback for unaligned access handling, if - * the target defines #TARGET_ALIGNED_ONLY. * @virtio_is_big_endian: Callback to return %true if a CPU which supports * runtime configurable endianness is currently big-endian. Non-configurab= le * CPUs can use the default implementation of this method. This method sho= uld @@ -154,9 +152,6 @@ struct CPUClass { =20 int reset_dump_flags; bool (*has_work)(CPUState *cpu); - void (*do_unaligned_access)(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); bool (*virtio_is_big_endian)(CPUState *cpu); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); @@ -831,18 +826,15 @@ CPUState *cpu_by_arch_id(int64_t id); =20 void cpu_interrupt(CPUState *cpu, int mask); =20 -#ifdef NEED_CPU_H - -#ifdef CONFIG_SOFTMMU +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr); + cc->tcg_ops.do_unaligned_access(cpu, addr, access_type, mmu_idx, retad= dr); } -#ifdef CONFIG_TCG static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, @@ -858,10 +850,7 @@ static inline void cpu_transaction_failed(CPUState *cp= u, hwaddr physaddr, mmu_idx, attrs, response, retadd= r); } } -#endif /* CONFIG_TCG */ -#endif /* CONFIG_SOFTMMU */ - -#endif /* NEED_CPU_H */ +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ =20 /** * cpu_set_pc: diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index dbf17c4f96..e92e0ea536 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -66,6 +66,13 @@ typedef struct TcgCpuOperations { unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr); + /** + * @do_unaligned_access: Callback for unaligned access handling, if + * the target defines #TARGET_ALIGNED_ONLY. + */ + void (*do_unaligned_access)(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); =20 #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index a1696bebeb..0710298e5a 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -226,7 +226,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->tcg_ops.tlb_fill =3D alpha_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->tcg_ops.do_transaction_failed =3D alpha_cpu_do_transaction_failed; - cc->do_unaligned_access =3D alpha_cpu_do_unaligned_access; + cc->tcg_ops.do_unaligned_access =3D alpha_cpu_do_unaligned_access; cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_alpha_cpu; #endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 39663d2861..1ba11698eb 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2266,9 +2266,9 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->tcg_ops.tlb_fill =3D arm_cpu_tlb_fill; cc->tcg_ops.debug_excp_handler =3D arm_debug_excp_handler; cc->debug_check_watchpoint =3D arm_debug_check_watchpoint; - cc->do_unaligned_access =3D arm_cpu_do_unaligned_access; #if !defined(CONFIG_USER_ONLY) cc->tcg_ops.do_transaction_failed =3D arm_cpu_do_transaction_failed; + cc->tcg_ops.do_unaligned_access =3D arm_cpu_do_unaligned_access; cc->adjust_watchpoint_address =3D arm_adjust_watchpoint_address; cc->tcg_ops.do_interrupt =3D arm_cpu_do_interrupt; #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index cce6ae6213..0985b3661f 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -70,6 +70,7 @@ static void hppa_cpu_disas_set_info(CPUState *cs, disasse= mble_info *info) info->print_insn =3D print_insn_hppa; } =20 +#ifndef CONFIG_USER_ONLY static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) @@ -86,6 +87,7 @@ static void hppa_cpu_do_unaligned_access(CPUState *cs, va= ddr addr, =20 cpu_loop_exit_restore(cs, retaddr); } +#endif /* CONFIG_USER_ONLY */ =20 static void hppa_cpu_realizefn(DeviceState *dev, Error **errp) { @@ -149,9 +151,9 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->tcg_ops.tlb_fill =3D hppa_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; + cc->tcg_ops.do_unaligned_access =3D hppa_cpu_do_unaligned_access; dc->vmsd =3D &vmstate_hppa_cpu; #endif - cc->do_unaligned_access =3D hppa_cpu_do_unaligned_access; cc->disas_set_info =3D hppa_cpu_disas_set_info; cc->tcg_ops.initialize =3D hppa_translate_init; =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index fa57a324dc..395f4a300f 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -318,7 +318,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->class_by_name =3D mb_cpu_class_by_name; cc->has_work =3D mb_cpu_has_work; cc->tcg_ops.do_interrupt =3D mb_cpu_do_interrupt; - cc->do_unaligned_access =3D mb_cpu_do_unaligned_access; cc->tcg_ops.cpu_exec_interrupt =3D mb_cpu_exec_interrupt; cc->dump_state =3D mb_cpu_dump_state; cc->set_pc =3D mb_cpu_set_pc; @@ -328,6 +327,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->tcg_ops.tlb_fill =3D mb_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->tcg_ops.do_transaction_failed =3D mb_cpu_transaction_failed; + cc->tcg_ops.do_unaligned_access =3D mb_cpu_do_unaligned_access; cc->get_phys_page_debug =3D mb_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_mb_cpu; #endif diff --git a/target/mips/cpu.c b/target/mips/cpu.c index fe8bca41b7..e99c692e2d 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -241,7 +241,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_read_register =3D mips_cpu_gdb_read_register; cc->gdb_write_register =3D mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->do_unaligned_access =3D mips_cpu_do_unaligned_access; cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_mips_cpu; #endif @@ -254,6 +253,8 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->tcg_ops.tlb_fill =3D mips_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->tcg_ops.do_transaction_failed =3D mips_cpu_do_transaction_failed; + cc->tcg_ops.do_unaligned_access =3D mips_cpu_do_unaligned_access; + #endif /* CONFIG_USER_ONLY */ #endif /* CONFIG_TCG */ =20 diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 2b959f0e49..059eea8c94 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -199,7 +199,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) cc->disas_set_info =3D nios2_cpu_disas_set_info; cc->tcg_ops.tlb_fill =3D nios2_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY - cc->do_unaligned_access =3D nios2_cpu_do_unaligned_access; + cc->tcg_ops.do_unaligned_access =3D nios2_cpu_do_unaligned_access; cc->get_phys_page_debug =3D nios2_cpu_get_phys_page_debug; #endif cc->gdb_read_register =3D nios2_cpu_gdb_read_register; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7dfd8d7339..e5626862c2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -556,7 +556,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->disas_set_info =3D riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY cc->tcg_ops.do_transaction_failed =3D riscv_cpu_do_transaction_failed; - cc->do_unaligned_access =3D riscv_cpu_do_unaligned_access; + cc->tcg_ops.do_unaligned_access =3D riscv_cpu_do_unaligned_access; cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; /* For now, mark unmigratable: */ cc->vmsd =3D &vmstate_riscv_cpu; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index b838bd61a4..86f654fd6b 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -507,7 +507,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) #ifdef CONFIG_TCG cc->tcg_ops.cpu_exec_interrupt =3D s390_cpu_exec_interrupt; cc->tcg_ops.debug_excp_handler =3D s390x_cpu_debug_excp_handler; - cc->do_unaligned_access =3D s390x_cpu_do_unaligned_access; + cc->tcg_ops.do_unaligned_access =3D s390x_cpu_do_unaligned_access; #endif #endif cc->disas_set_info =3D s390_cpu_disas_set_info; diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index 0adfbbda27..abe5e3c62a 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -633,4 +633,4 @@ void HELPER(monitor_call)(CPUS390XState *env, uint64_t = monitor_code, } } =20 -#endif /* CONFIG_USER_ONLY */ +#endif /* !CONFIG_USER_ONLY */ diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index ff835d4bc1..fbd5f42675 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -227,7 +227,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_write_register =3D superh_cpu_gdb_write_register; cc->tcg_ops.tlb_fill =3D superh_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY - cc->do_unaligned_access =3D superh_cpu_do_unaligned_access; + cc->tcg_ops.do_unaligned_access =3D superh_cpu_do_unaligned_access; cc->get_phys_page_debug =3D superh_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D superh_cpu_disas_set_info; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 009d0f07c3..3b53ef2390 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -874,7 +874,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->tcg_ops.tlb_fill =3D sparc_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->tcg_ops.do_transaction_failed =3D sparc_cpu_do_transaction_failed; - cc->do_unaligned_access =3D sparc_cpu_do_unaligned_access; + cc->tcg_ops.do_unaligned_access =3D sparc_cpu_do_unaligned_access; cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_sparc_cpu; #endif diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index fc52fde696..4b6381569f 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -203,7 +203,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_stop_before_watchpoint =3D true; cc->tcg_ops.tlb_fill =3D xtensa_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY - cc->do_unaligned_access =3D xtensa_cpu_do_unaligned_access; + cc->tcg_ops.do_unaligned_access =3D xtensa_cpu_do_unaligned_access; cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; cc->tcg_ops.do_transaction_failed =3D xtensa_cpu_do_transaction_failed; #endif diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index dc13ff2cf8..3fbec30a65 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10917,7 +10917,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->set_pc =3D ppc_cpu_set_pc; cc->gdb_read_register =3D ppc_cpu_gdb_read_register; cc->gdb_write_register =3D ppc_cpu_gdb_write_register; - cc->do_unaligned_access =3D ppc_cpu_do_unaligned_access; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D ppc_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_ppc_cpu; @@ -10954,6 +10953,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) #ifndef CONFIG_USER_ONLY cc->tcg_ops.cpu_exec_enter =3D ppc_cpu_exec_enter; cc->tcg_ops.cpu_exec_exit =3D ppc_cpu_exec_exit; + cc->tcg_ops.do_unaligned_access =3D ppc_cpu_do_unaligned_access; #endif /* !CONFIG_USER_ONLY */ #endif /* CONFIG_TCG */ =20 --=20 2.26.2