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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id h8sm8293554pfk.71.2020.12.10.21.14.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 21:14:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yk+UkyZ3zZHaivDH6FffLRUoNUblBlLI7PyiOu0Mpgc=; b=SAbVM5tsQS1VvNG/xnPmksqWiO3QKd5IkDxIS2ij5mSWQ7CAXQBiTOQfEB0xlVeMZv Q6DvU8OS8hcukD4Fau24coGUoJtSFzBYm952EaVKndww5VD14D8gEm0HQbE7tPHKajfm KV6BSU3iBQrVqReOG/GxR9DimY1TreMxuUSKL4gPeQqdwcwqePvT9f5mlyXBU7Nr6CMy JQigDpWUnkoGoJwg65HeCFsw+9v/uVU06/y6K0s+XnCF4NMuI4WRTdHWf1yBlB+QMhWb VK/r5Qacvgllw7wPn8LvO8gl75gwxaBQ6Qe7HsOQWYh/9lqN4M1qQ9eVk/j0HhFKfyOP PNqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yk+UkyZ3zZHaivDH6FffLRUoNUblBlLI7PyiOu0Mpgc=; b=PB1k7R8cb6AGIZcxdkZ0wyf0wXmcxUdMwZ8tLiAwFVFp5MxI+W2dwGkTEHqsat7kvY bRuVOyXhhlOHcYV1Wt1pXVr5CtV5WaiagVozaHkF1z4OsKXlFAN4C4yUO/4AoGT17mT7 sv9iGotZMTc3LPACJguqeVmrGOVbMVpBOeaiL3BSdh+4R1YLktCyWFFfBLMhmbtZlXb6 5B++r7jdkgjtStAE6Aq7tdawp4YwtLcTMWkcgwp2EFfjoM+CVVroM0/GNgUVAK51IXpo TSZFp3aDQpPeyPg6/QIdz8aJaS8xRbc7ccb2miWUeHgQJ+k7Aa5MHTEr7+8+7Zm/DfDz wshw== X-Gm-Message-State: AOAM532pj7Gwp4MfGjrs6JBgSetD1rYUY5KuIFC7fW3OB5vnI/3xOjZH DGtzxnvS4lmD5/IL7O4gO4s+b9FydzfO6or6rvHLrqa9xrRdZ7YSZzgLxsUXoREwH3dhfnf59pk nFlpSqfCJgslgYdMG/Wjcxqhm8pJv/64LIjVmkgWebllVnnLvg6PP26u99FnBvdreM1u1tIg77g == X-Google-Smtp-Source: ABdhPJxlalB0j7pFcqdIL2QsCRRP6OPCQMjOPYvHp1Su2JdVAl18YM2eE7K7Io3gjDl3mLu6qsvipw== X-Received: by 2002:a62:844b:0:b029:19e:62a0:ca18 with SMTP id k72-20020a62844b0000b029019e62a0ca18mr9990456pfd.46.1607663660601; Thu, 10 Dec 2020 21:14:20 -0800 (PST) From: Rebecca Cran To: qemu-devel@nongnu.org Subject: [PATCH 1/2] target/arm: add support for FEAT_DIT, Data Independent Timing Date: Thu, 10 Dec 2020 22:13:58 -0700 Message-Id: <20201211051359.3231-2-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211051359.3231-1-rebecca@nuviainc.com> References: <20201211051359.3231-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=rebecca@nuviainc.com; helo=mail-pg1-x52a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Rebecca Cran Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add support for FEAT_DIT. DIT (Data Independent Timing) is a required feature for ARMv8.4. Since virtual machine execution is largely nondeterministic, it's implemented as a NOP. Signed-off-by: Rebecca Cran --- target/arm/cpu.h | 20 +++++++++++++- target/arm/helper.c | 28 +++++++++++++++++++- target/arm/internals.h | 6 +++++ target/arm/translate-a64.c | 14 ++++++++++ 4 files changed, 66 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4c9cbfbd9975..862be662cef7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -269,6 +269,7 @@ typedef struct CPUARMState { uint32_t NF; /* N is bit 31. All other bits are undefined. */ uint32_t ZF; /* Z set if zero. */ uint32_t QF; /* 0 or 1 */ + uint32_t DIT; /* 0 or 1 */ uint32_t GE; /* cpsr[19:16] */ uint32_t thumb; /* cpsr[5]. 0 =3D arm mode, 1 =3D thumb mode. */ uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ @@ -1233,6 +1234,7 @@ void pmu_init(ARMCPU *cpu); #define CPSR_IT_2_7 (0xfc00U) #define CPSR_GE (0xfU << 16) #define CPSR_IL (1U << 20) +#define CPSR_DIT (1U << 21) #define CPSR_PAN (1U << 22) #define CPSR_J (1U << 24) #define CPSR_IT_0_1 (3U << 25) @@ -1266,6 +1268,7 @@ void pmu_init(ARMCPU *cpu); #define XPSR_Z CPSR_Z #define XPSR_N CPSR_N #define XPSR_NZCV CPSR_NZCV +#define XPSR_DIT CPSR_DIT #define XPSR_IT CPSR_IT =20 #define TTBCR_N (7U << 0) /* TTBCR.EAE=3D=3D0 */ @@ -1300,6 +1303,7 @@ void pmu_init(ARMCPU *cpu); #define PSTATE_SS (1U << 21) #define PSTATE_PAN (1U << 22) #define PSTATE_UAO (1U << 23) +#define PSTATE_DIT (1U << 24) #define PSTATE_TCO (1U << 25) #define PSTATE_V (1U << 28) #define PSTATE_C (1U << 29) @@ -1374,7 +1378,8 @@ static inline uint32_t xpsr_read(CPUARMState *env) ZF =3D (env->ZF =3D=3D 0); return (env->NF & 0x80000000) | (ZF << 30) | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) - | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) + | (env->thumb << 24) | (env->DIT << 21) + | ((env->condexec_bits & 3) << 25) | ((env->condexec_bits & 0xfc) << 8) | (env->GE << 16) | env->v7m.exception; @@ -1389,6 +1394,9 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) env->CF =3D (val >> 29) & 1; env->VF =3D (val << 3) & 0x80000000; } + if (mask & XPSR_DIT) { + env->DIT =3D ((val & XPSR_DIT) !=3D 0); + } if (mask & XPSR_Q) { env->QF =3D ((val & XPSR_Q) !=3D 0); } @@ -3823,6 +3831,11 @@ static inline bool isar_feature_aa32_tts2uxn(const A= RMISARegisters *id) return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) !=3D 0; } =20 +static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) !=3D 0; +} + /* * 64-bit feature tests via id registers. */ @@ -4050,6 +4063,11 @@ static inline bool isar_feature_aa64_tts2uxn(const A= RMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) !=3D 0; } =20 +static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) !=3D 0; +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 7b8bcd69030f..eb4979baceff 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4390,6 +4390,24 @@ static const ARMCPRegInfo uao_reginfo =3D { .readfn =3D aa64_uao_read, .writefn =3D aa64_uao_write }; =20 +static uint64_t aa64_dit_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_DIT; +} + +static void aa64_dit_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->pstate =3D (env->pstate & ~PSTATE_DIT) | (value & PSTATE_DIT); +} + +static const ARMCPRegInfo dit_reginfo =3D { + .name =3D "DIT", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 4, .crm =3D 2, .opc2 =3D 5, + .type =3D ARM_CP_NO_RAW, .access =3D PL0_RW, + .readfn =3D aa64_dit_read, .writefn =3D aa64_dit_write +}; + static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -8133,6 +8151,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &uao_reginfo); } =20 + if (cpu_isar_feature(aa64_dit, cpu)) { + define_one_arm_cp_reg(cpu, &dit_reginfo); + } + if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { define_arm_cp_regs(cpu, vhe_reginfo); } @@ -8740,7 +8762,8 @@ uint32_t cpsr_read(CPUARMState *env) ZF =3D (env->ZF =3D=3D 0); return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) - | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) + | (env->DIT << 21) | (env->thumb << 5) + | ((env->condexec_bits & 3) << 25) | ((env->condexec_bits & 0xfc) << 8) | (env->GE << 16) | (env->daif & CPSR_AIF); } @@ -8756,6 +8779,9 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint3= 2_t mask, env->CF =3D (val >> 29) & 1; env->VF =3D (val << 3) & 0x80000000; } + if (mask & CPSR_DIT) { + env->DIT =3D ((val & CPSR_DIT) !=3D 0); + } if (mask & CPSR_Q) env->QF =3D ((val & CPSR_Q) !=3D 0); if (mask & CPSR_T) diff --git a/target/arm/internals.h b/target/arm/internals.h index 5460678756d3..00ecfc174c80 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1186,6 +1186,9 @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64= _t features, if (isar_feature_aa32_pan(id)) { valid |=3D CPSR_PAN; } + if (isar_feature_aa32_dit(id)) { + valid |=3D CPSR_DIT; + } =20 return valid; } @@ -1204,6 +1207,9 @@ static inline uint32_t aarch64_pstate_valid_mask(cons= t ARMISARegisters *id) if (isar_feature_aa64_uao(id)) { valid |=3D PSTATE_UAO; } + if (isar_feature_aa64_dit(id)) { + valid |=3D PSTATE_DIT; + } if (isar_feature_aa64_mte(id)) { valid |=3D PSTATE_TCO; } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2e3fdfdf6ba8..0cafba6188c6 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1696,6 +1696,20 @@ static void handle_msr_i(DisasContext *s, uint32_t i= nsn, tcg_temp_free_i32(t1); break; =20 + case 0x1a: /* DIT */ + if (!dc_isar_feature(aa64_dit, s)) { + goto do_unallocated; + } + if (crm & 1) { + set_pstate_bits(PSTATE_DIT); + } else { + clear_pstate_bits(PSTATE_DIT); + } + t1 =3D tcg_const_i32(s->current_el); + gen_helper_rebuild_hflags_a64(cpu_env, t1); + tcg_temp_free_i32(t1); + break; + case 0x1e: /* DAIFSet */ t1 =3D tcg_const_i32(crm); gen_helper_msr_i_daifset(cpu_env, t1); --=20 2.26.2 From nobody Fri May 17 07:56:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607663753; cv=none; d=zohomail.com; s=zohoarc; b=jeKgmNRv76u/XOYGu3uXuhEsNzRJL34GPLSp48Bl1sXh4LNADyk/aRoSGcglAye4MH5HR0WX3G8i3NPqPGdKzlhPZmgwCeNY7LWBS+IR5TkcnFIhjdSR6npYDoz9QWuDM05CL24CST5ImuCx35YPyg0L4cdBbIDP0oRBLaJq+ew= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id h8sm8293554pfk.71.2020.12.10.21.14.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 21:14:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v0JHzy0Ta5fehdYhfT6YCukRceZeuP8yRCzh8zxFvO0=; b=wMXZIt8YK6pTBLpXZFUgHWXh5ox3P0rOJOtEW+10QpSdqEgiG8cmgCQgrGOSUYgvOh O9gchJzc46MioG6xGgSKoqsoG+K6/GLeB1lKhy/+X/IPHx+L00DiY+R0wqw/XEm+6Ifr oygiCNU36AK1ZenaDaM2Zbs9plZxp3/6h6PR8eBlwKHQjrppjG6OZyfH/+D4C9WCN4lH KjebeAz6ERMsm2qeF8F9Dmkwc5fg/zro53PudoAnE/fQzCnNyyBzzEti27XAdOdZRN8a Uqmp8F/IPb+42pLMM7a65M6K69TxrGTRITMVfthVwlo4CrLh2hzAAw98hOR0lPLpxe7H SdpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v0JHzy0Ta5fehdYhfT6YCukRceZeuP8yRCzh8zxFvO0=; b=F03FWkhDG9KSfczdGwjuyZKBa7pJzZ6xvO744jhWVj4lBtHRd3gOLVzOuGIEarUHLP JUyLI8ByRJ8HdP1XGHZLts1lAkBcnAxpRJV8TeSeztg/1cczafM9rloLtOLVeF5ZeTdp osP9YsPup/Qb/c0/b9bNiK7JzkTzGVDXAsX4xaITu2nAUWSraLsSuTW9e8PJTV3l4WlV WNzGsxlr8u+/gDIkPEm0s7MCYz0BOpKmaSejKtXelLy52HsrF6SL0xPNylIKbJdHOriF Y1lqN/555hj3xo7nz7RznkA305s9R3IeKOdWLDh7rUC83dXkI4uoJzOl8Cd+Siv7WjyW b1Hg== X-Gm-Message-State: AOAM532lGNy4eae2mqYbzPPpMK9ScH4fKInU2fx31EqxwzHQHqNO+hnD c9dcZSCt4WTZzZpTD5wEXZ2qF8zzagrjz4n+zgldJZLgeEnToE/04mB1cYw05/baGiY+huAVo3v IOmHZHrAMCNHsRIENdtpVpmC33qAR5BJvTFa8SjUPNPV2yNtMdAKtDll0q89+m4+04JnG9rtBbw == X-Google-Smtp-Source: ABdhPJzp+sfzEBLV1YEKqFViz+bbm/PignwlIJEJeccStdDRgccyv2Gbxm3+A+3Bs38zkW4Zwnme2A== X-Received: by 2002:a63:3e84:: with SMTP id l126mr10045952pga.39.1607663663020; Thu, 10 Dec 2020 21:14:23 -0800 (PST) From: Rebecca Cran To: qemu-devel@nongnu.org Subject: [PATCH 2/2] target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU Date: Thu, 10 Dec 2020 22:13:59 -0700 Message-Id: <20201211051359.3231-3-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201211051359.3231-1-rebecca@nuviainc.com> References: <20201211051359.3231-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::544; envelope-from=rebecca@nuviainc.com; helo=mail-pg1-x544.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Rebecca Cran Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Enable FEAT_DIT for the "max" AARCH64 CPU. Signed-off-by: Rebecca Cran Reviewed-by: Richard Henderson --- target/arm/cpu64.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 649213082ff9..223e0bfd22c2 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -641,6 +641,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); + t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); cpu->isar.id_aa64pfr0 =3D t; =20 t =3D cpu->isar.id_aa64pfr1; @@ -689,6 +690,10 @@ static void aarch64_max_initfn(Object *obj) u =3D FIELD_DP32(u, ID_ISAR6, SPECRES, 1); cpu->isar.id_isar6 =3D u; =20 + u =3D cpu->isar.id_pfr0; + u =3D FIELD_DP32(u, ID_PFR0, DIT, 1); + cpu->isar.id_pfr0 =3D u; + u =3D cpu->isar.id_mmfr3; u =3D FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ cpu->isar.id_mmfr3 =3D u; --=20 2.26.2