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bh=YcznJt9lG+IXOdzL3mHkf2pUsDtQK+WVN/Kh97Dp0uw=; b=IcrLXjqbMEOtjT/AAT2TwoWtIKXvssAcAfcHyp+GPkdvG+WobjTGiNdBgIIdiOSFUH1W0F 9shZY3TBmBs7rZMtBIj65LR7MLxZ72fQ6+2EfvccixEIbgf6fz5CnxRtUUQLP5b5XPqb9L 066M6lZ6yR9Wz7apa3HFeuA3P3K1z6g= X-MC-Unique: At9h46GbPGSjdLeCN0FQSQ-1 From: Eduardo Habkost To: Peter Maydell , qemu-devel@nongnu.org Subject: [PULL 3/3] i386/cpu: Make the Intel PT LIP feature configurable Date: Thu, 10 Dec 2020 17:42:12 -0500 Message-Id: <20201210224212.2052368-4-ehabkost@redhat.com> In-Reply-To: <20201210224212.2052368-1-ehabkost@redhat.com> References: <20201210224212.2052368-1-ehabkost@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=ehabkost@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=63.128.21.124; envelope-from=ehabkost@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , Luwei Kang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Luwei Kang The current implementation will disable the guest Intel PT feature if the Intel PT LIP feature is supported on the host, but the LIP feature is comming soon(e.g. SnowRidge and later). This patch will make the guest LIP feature configurable and Intel PT feature can be enabled in guest when the guest LIP status same with the host. Signed-off-by: Luwei Kang Message-Id: <20201202101042.11967-1-luwei.kang@intel.com> Signed-off-by: Eduardo Habkost --- target/i386/cpu.h | 4 ++++ target/i386/cpu.c | 31 ++++++++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 88e8586f8f..c4a49c06a8 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -541,6 +541,7 @@ typedef enum FeatureWord { FEAT_VMX_EPT_VPID_CAPS, FEAT_VMX_BASIC, FEAT_VMX_VMFUNC, + FEAT_14_0_ECX, FEATURE_WORDS, } FeatureWord; =20 @@ -797,6 +798,9 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; /* AVX512 BFloat16 Instruction */ #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) =20 +/* Packets which contain IP payload have LIP values */ +#define CPUID_14_0_ECX_LIP (1U << 31) + /* CLZERO instruction */ #define CPUID_8000_0008_EBX_CLZERO (1U << 0) /* Always save/restore FP error pointers */ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5a8c96072e..900ea08283 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -672,6 +672,7 @@ static void x86_cpu_vendor_words2str(char *dst, uint32_= t vendor1, #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) /* missing: CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ +#define TCG_14_0_ECX_FEATURES 0 =20 typedef enum FeatureWordType { CPUID_FEATURE_WORD, @@ -1301,6 +1302,26 @@ static FeatureWordInfo feature_word_info[FEATURE_WOR= DS] =3D { } }, =20 + [FEAT_14_0_ECX] =3D { + .type =3D CPUID_FEATURE_WORD, + .feat_names =3D { + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, "intel-pt-lip", + }, + .cpuid =3D { + .eax =3D 0x14, + .needs_ecx =3D true, .ecx =3D 0, + .reg =3D R_ECX, + }, + .tcg_features =3D TCG_14_0_ECX_FEATURES, + }, + }; =20 typedef struct FeatureMask { @@ -1373,6 +1394,10 @@ static FeatureDep feature_dependencies[] =3D { .from =3D { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, .to =3D { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EX= ITING }, }, + { + .from =3D { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, + .to =3D { FEAT_14_0_ECX, ~0ull }, + }, { .from =3D { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, .to =3D { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, @@ -5752,6 +5777,9 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, *eax =3D INTEL_PT_MAX_SUBLEAF; *ebx =3D INTEL_PT_MINIMAL_EBX; *ecx =3D INTEL_PT_MINIMAL_ECX; + if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { + *ecx |=3D CPUID_14_0_ECX_LIP; + } } else if (count =3D=3D 1) { *eax =3D INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; *ebx =3D INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; @@ -6498,7 +6526,8 @@ static void x86_cpu_filter_features(X86CPU *cpu, bool= verbose) INTEL_PT_ADDR_RANGES_NUM) || ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=3D (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || - (ecx_0 & INTEL_PT_IP_LIP)) { + ((ecx_0 & CPUID_14_0_ECX_LIP) !=3D + (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { /* * Processor Trace capabilities aren't configurable, so if the * host can't emulate the capabilities we report on --=20 2.28.0