From nobody Mon Feb 9 07:23:16 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607633874; cv=none; d=zohomail.com; s=zohoarc; b=Bc8Rotcs7lqCJMSA8K1rb3uAIXEnQbA1DdUaJt3qLvJLH+FWq0nfJGxJDbkl+gxEkjruKkTLnboCrLqdwTMsg/sPIToEQbKZ35lPTgQTqKJXcMjvYfX8JCg2g12572d3JcdZsToVbYvklIM8MHXTF3prSkYm0omB5EX/NpvrmLU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607633874; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VW73SL2e03HTZn5SraqkB3la7LiS2Li1U2Ibx4vs/D8=; b=PB6R61GLkexBYKfNYFFnEF9JhDGXmvY80TKgf3uYqTXb6QIu5NAXKuLl2DW4s5TLCUkP/BJ1SZXJfl5c+cNE+ZlAhynq4cqDIGajDOvO6ucpL95G8HTNWibGKHtRb6wkN6ujYr7DpU3zTBECDloRIBy0y6LI6LVs8b85KE2KxOc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607633874552840.5318533867087; Thu, 10 Dec 2020 12:57:54 -0800 (PST) Received: from localhost ([::1]:56418 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knSNE-0000X7-7E for importer@patchew.org; Thu, 10 Dec 2020 15:17:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39954) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knSKp-0007YK-B7 for qemu-devel@nongnu.org; Thu, 10 Dec 2020 15:14:43 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:52565) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knSKn-00012d-D1 for qemu-devel@nongnu.org; Thu, 10 Dec 2020 15:14:43 -0500 Received: by mail-wm1-x329.google.com with SMTP id a6so5752324wmc.2 for ; Thu, 10 Dec 2020 12:14:40 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y130sm11879591wmc.22.2020.12.10.12.14.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 12:14:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=VW73SL2e03HTZn5SraqkB3la7LiS2Li1U2Ibx4vs/D8=; b=opQuOfDRjs14oB2GM83bdzsk0jmJ4Mgl8BxrlydHs0SNGyxh5bUZPV4fgGuUIDoie4 OCDnN3hbG6Wio12Hqrdgl74APgfNZztvIoQ1gQhxf9WjTSRu41maXGxCcAKUIzWhnV4B n53b/D1ujM8SpLHZFIlVvaIulxJ/xD++DD1LJQEgs6pX18zQ8msoNntVEB6kQ9sIQ1R1 9TbxE6bWWc2OU6V7vQspZkt7oZSwYmhMCiv4mo1xTG5aXqmQ6jtp1MEzBM3GwAbrH5oC eWy6fr3QT+s4Hr4uTg5shhgVv0U9OWzz1qlSLlcyOEaQDLmJ7fyG/JqSfrH5g8BFKfLi fJKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VW73SL2e03HTZn5SraqkB3la7LiS2Li1U2Ibx4vs/D8=; b=h7nlDeHNpt4nhn+HtsO35Vh8EQUwpZhYjLt4ECbiv1IQouhPJgrsBmde05C+oWacq/ eq28iyTZAgs2wkI9mwOpi8/yjKLszvK3EPwWBgbfjMkpLupTnHCC1mhWaHu+1KCkyGDQ tS9wOSWRWOxYYRcrdpuoNUXrw7k6axHRZVPcQlYTinYTn7WRqtLCp7GSUd9g/gmDn4xa +VdZlbIG0tF2ufsteRSIILIxb/xTInF78G1pmj+sBJIgXfyPckPgvy3ER1jzOC4ZcLeZ 0RbAnTrqfPeRHDF0XpWsM/l6pGE9TwxtmWOAi5ZiA4b5hsm9HrSGneMQy+fEZzmmfCGY 8ydA== X-Gm-Message-State: AOAM531m6+LcWBDvP5/DLU2ZivlElvJmWgIBmf8PkQ+OprFVj9/2v6n3 MPQxyc42iLBowS3rZ9b/+TbnbqQIGRTzRg== X-Google-Smtp-Source: ABdhPJy0Y3CQvaLJc/6aG4eJ7oc8RFBpwobvTSqdPJjcpg4UJMguHJSSPNXjfWzscs0ATQITwLSm8Q== X-Received: by 2002:a7b:c773:: with SMTP id x19mr9761941wmk.127.1607631279694; Thu, 10 Dec 2020 12:14:39 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH v3 3/4] target/arm: Implement FPCXT_NS fp system register Date: Thu, 10 Dec 2020 20:14:32 +0000 Message-Id: <20201210201433.26262-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210201433.26262-1-peter.maydell@linaro.org> References: <20201210201433.26262-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the v8.1M FPCXT_NS floating-point system register. This is a little more complicated than FPCXT_S, because it has specific handling for "current FP state is inactive", and it only wants to do PreserveFPState(), not the full set of actions done by ExecuteFPCheck() which vfp_access_check() implements. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- Changes since v2: refactored along lines suggested by RTH --- target/arm/translate-vfp.c.inc | 102 ++++++++++++++++++++++++++++++++- 1 file changed, 99 insertions(+), 3 deletions(-) diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 8b4cfd68cad..10766f210c1 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -663,6 +663,7 @@ static FPSysRegCheckResult fp_sysreg_checks(DisasContex= t *s, int regno) } break; case ARM_VFP_FPCXT_S: + case ARM_VFP_FPCXT_NS: if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { return false; } @@ -674,13 +675,48 @@ static FPSysRegCheckResult fp_sysreg_checks(DisasCont= ext *s, int regno) return FPSysRegCheckFailed; } =20 - if (!vfp_access_check(s)) { + /* + * FPCXT_NS is a special case: it has specific handling for + * "current FP state is inactive", and must do the PreserveFPState() + * but not the usual full set of actions done by ExecuteFPCheck(). + * So we don't call vfp_access_check() and the callers must handle thi= s. + */ + if (regno !=3D ARM_VFP_FPCXT_NS && !vfp_access_check(s)) { return FPSysRegCheckDone; } - return FPSysRegCheckContinue; } =20 +static void gen_branch_fpInactive(DisasContext *s, TCGCond cond, + TCGLabel *label) +{ + /* + * FPCXT_NS is a special case: it has specific handling for + * "current FP state is inactive", and must do the PreserveFPState() + * but not the usual full set of actions done by ExecuteFPCheck(). + * We don't have a TB flag that matches the fpInactive check, so we + * do it at runtime as we don't expect FPCXT_NS accesses to be frequen= t. + * + * Emit code that checks fpInactive and does a conditional + * branch to label based on it: + * if cond is TCG_COND_NE then branch if fpInactive !=3D 0 (ie if ina= ctive) + * if cond is TCG_COND_EQ then branch if fpInactive =3D=3D 0 (ie if a= ctive) + */ + assert(cond =3D=3D TCG_COND_EQ || cond =3D=3D TCG_COND_NE); + + /* fpInactive =3D FPCCR_NS.ASPEN =3D=3D 1 && CONTROL.FPCA =3D=3D 0 */ + TCGv_i32 aspen, fpca; + aspen =3D load_cpu_field(v7m.fpccr[M_REG_NS]); + fpca =3D load_cpu_field(v7m.control[M_REG_S]); + tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); + tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); + tcg_gen_andi_i32(fpca, fpca, R_V7M_CONTROL_FPCA_MASK); + tcg_gen_or_i32(fpca, fpca, aspen); + tcg_gen_brcondi_i32(tcg_invert_cond(cond), fpca, 0, label); + tcg_temp_free_i32(aspen); + tcg_temp_free_i32(fpca); +} + static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, =20 fp_sysreg_loadfn *loadfn, @@ -688,6 +724,7 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int = regno, { /* Do a write to an M-profile floating point system register */ TCGv_i32 tmp; + TCGLabel *lab_end =3D NULL; =20 switch (fp_sysreg_checks(s, regno)) { case FPSysRegCheckFailed: @@ -721,6 +758,13 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int= regno, tcg_temp_free_i32(tmp); break; } + case ARM_VFP_FPCXT_NS: + lab_end =3D gen_new_label(); + /* fpInactive case: write is a NOP, so branch to end */ + gen_branch_fpInactive(s, TCG_COND_NE, lab_end); + /* !fpInactive: PreserveFPState(), and reads same as FPCXT_S */ + gen_preserve_fp_state(s); + /* fall through */ case ARM_VFP_FPCXT_S: { TCGv_i32 sfpa, control; @@ -744,6 +788,9 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int = regno, default: g_assert_not_reached(); } + if (lab_end) { + gen_set_label(lab_end); + } return true; } =20 @@ -753,6 +800,8 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int r= egno, { /* Do a read from an M-profile floating point system register */ TCGv_i32 tmp; + TCGLabel *lab_end =3D NULL; + bool lookup_tb =3D false; =20 switch (fp_sysreg_checks(s, regno)) { case FPSysRegCheckFailed: @@ -811,12 +860,59 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int= regno, fpscr =3D load_cpu_field(v7m.fpdscr[M_REG_NS]); gen_helper_vfp_set_fpscr(cpu_env, fpscr); tcg_temp_free_i32(fpscr); - gen_lookup_tb(s); + lookup_tb =3D true; + break; + } + case ARM_VFP_FPCXT_NS: + { + TCGv_i32 control, sfpa, fpscr, fpdscr, zero; + TCGLabel *lab_active =3D gen_new_label(); + + lookup_tb =3D true; + + gen_branch_fpInactive(s, TCG_COND_EQ, lab_active); + /* fpInactive case: reads as FPDSCR_NS */ + TCGv_i32 tmp =3D load_cpu_field(v7m.fpdscr[M_REG_NS]); + storefn(s, opaque, tmp); + lab_end =3D gen_new_label(); + tcg_gen_br(lab_end); + + gen_set_label(lab_active); + /* !fpInactive: Reads the same as FPCXT_S, but side effects differ= */ + gen_preserve_fp_state(s); + tmp =3D tcg_temp_new_i32(); + sfpa =3D tcg_temp_new_i32(); + fpscr =3D tcg_temp_new_i32(); + gen_helper_vfp_get_fpscr(fpscr, cpu_env); + tcg_gen_andi_i32(tmp, fpscr, ~FPCR_NZCV_MASK); + control =3D load_cpu_field(v7m.control[M_REG_S]); + tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK); + tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT); + tcg_gen_or_i32(tmp, tmp, sfpa); + tcg_temp_free_i32(control); + /* Store result before updating FPSCR, in case it faults */ + storefn(s, opaque, tmp); + /* If SFPA is zero then set FPSCR from FPDSCR_NS */ + fpdscr =3D load_cpu_field(v7m.fpdscr[M_REG_NS]); + zero =3D tcg_const_i32(0); + tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, zero, fpdscr, fpscr); + gen_helper_vfp_set_fpscr(cpu_env, fpscr); + tcg_temp_free_i32(zero); + tcg_temp_free_i32(sfpa); + tcg_temp_free_i32(fpdscr); + tcg_temp_free_i32(fpscr); break; } default: g_assert_not_reached(); } + + if (lab_end) { + gen_set_label(lab_end); + } + if (lookup_tb) { + gen_lookup_tb(s); + } return true; } =20 --=20 2.20.1