From nobody Sun Feb 8 11:40:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607632244; cv=none; d=zohomail.com; s=zohoarc; b=lfXl1X9bCMFYcN1UQFQAocBJahtO5zP97ItfBQYJ+aShfP5t84gLdmclWTO4P1rfEsrAojKOV1PpoNg+HocdFATmhurO7XK36mikQcEysBTBesjSUkZ0fFYmfbviR31hFarKFHGSoP4rherGX7jVQGW+l7vQP8AHwALYkazpZEI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607632244; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DcYO717g+h48zX5CfwBJY1EuyVi+kJp3S/Ky2vihqM0=; b=PVGpdtCPYe07Raud+4h1TLkUvL2DnLH4H3DPq5X2NIuXmubI7cJ0pQUdh0q0F8TINpMus2FRa4aNeB9jSY1ceigLfPc8ltdF6a7lXm+cwfJXCF0zer6jGt/M/jK6DO9yHEnA1mWgnjQFf1lEgJcJEdGktzqfvLvu86gyfLqOJ3E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607632244051805.6704236687549; Thu, 10 Dec 2020 12:30:44 -0800 (PST) Received: from localhost ([::1]:56460 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knSNF-0000Y2-9s for importer@patchew.org; Thu, 10 Dec 2020 15:17:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39930) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knSKn-0007Vg-8d for qemu-devel@nongnu.org; Thu, 10 Dec 2020 15:14:41 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:39346) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knSKl-00010y-12 for qemu-devel@nongnu.org; Thu, 10 Dec 2020 15:14:41 -0500 Received: by mail-wm1-x341.google.com with SMTP id 3so6585931wmg.4 for ; Thu, 10 Dec 2020 12:14:38 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y130sm11879591wmc.22.2020.12.10.12.14.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 12:14:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=DcYO717g+h48zX5CfwBJY1EuyVi+kJp3S/Ky2vihqM0=; b=Y3q9nK8ffYQ/yKv53wM3p3wtKw32Lsx62o76ypYd0HVTw0nqvZi9dabU0vDI9E2BDp rN6FWmtixGvOnzBVW4Sx1dOeHCH7tzDuFugqpkZ/qJw3yy8SKzWTn6kDgUPEKt+a//jq eQSWtZaZh9Xn8/8R83qLRfZMDFUAfY6kzVgbD1IfgIC1nk55u7ch5M4TYXaTJE3t7mxQ 7jaGVHsqzxcu9VRevhGnbLpfVPWoKY3zcaPYs7X7ZQYkB2WVvY1GEiuREWAbMDSevBk+ 3NRZLY+DR6Y+jvKmjWM9Ya86lqv62lm3P0wQJb2agBQJg4D3XGeihklVdOnTDKfbLbRf fbVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DcYO717g+h48zX5CfwBJY1EuyVi+kJp3S/Ky2vihqM0=; b=ZqfILSoQ+mLAVDI0zw9grogzLgEJjIUSuV1OLbuc77UXkKSn0b3Z0k56Ndare3Ozvp wckwhDVZN6LPO3FbfSwh0cBTRVEBqluCne9UQh7Ze7fpQdcUn/WeJuM3zUt6V3KygBnf g21eY8yIPiJ2cZhtaBI6SBBeN700cKGi3B3KvzwZIyOfdkkK+ZvaozqDij9lFToJWbhn p4DBViXz8FZV5l1yVJ8GwRsl+wZUUvwOnN9p0HQ3hetCnIKLujivdVwrCJBrUMZWF/vH 6lxnNcX5CK8UyBX8WB+DauZ0S/QfvGBM8CWtF9taztjt4kuZG6NRq6+I7aTe8kkeZXQG VIOg== X-Gm-Message-State: AOAM530ZpsnxD/7RGZBwB5/kGcMxJhr0Qd8Vv5q9ahj+AOy4S2vPCiHG nmt4g14lqDSVQy00PhTAzOujJO5HfGXNHA== X-Google-Smtp-Source: ABdhPJw283ybtzLmmV2oURlUcoF6AVpkRLZHoBYFRKqeAsDyycEJ2shczsws5XLrbTLstSpQ2R0dmg== X-Received: by 2002:a05:600c:224b:: with SMTP id a11mr9957899wmm.97.1607631277294; Thu, 10 Dec 2020 12:14:37 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH v3 1/4] hw/intc/armv7m_nvic: Correct handling of CCR.BFHFNMIGN Date: Thu, 10 Dec 2020 20:14:30 +0000 Message-Id: <20201210201433.26262-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210201433.26262-1-peter.maydell@linaro.org> References: <20201210201433.26262-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x341.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The CCR is a register most of whose bits are banked between security states but where BFHFNMIGN is not, and we keep it in the non-secure entry of the v7m.ccr[] array. The logic which tries to handle this bit fails to implement the "RAZ/WI from Nonsecure if AIRCR.BFHFNMINS is zero" requirement; correct the omission. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- Changes since v2: get the "WI" bit right --- hw/intc/armv7m_nvic.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index f63aa2d8713..0d8426dafc9 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1106,6 +1106,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t of= fset, MemTxAttrs attrs) */ val =3D cpu->env.v7m.ccr[attrs.secure]; val |=3D cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK; + /* BFHFNMIGN is RAZ/WI from NS if AIRCR.BFHFNMINS is 0 */ + if (!attrs.secure) { + if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { + val &=3D ~R_V7M_CCR_BFHFNMIGN_MASK; + } + } return val; case 0xd24: /* System Handler Control and State (SHCSR) */ if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) { @@ -1683,6 +1689,15 @@ static void nvic_writel(NVICState *s, uint32_t offse= t, uint32_t value, (cpu->env.v7m.ccr[M_REG_NS] & ~R_V7M_CCR_BFHFNMIGN_MASK) | (value & R_V7M_CCR_BFHFNMIGN_MASK); value &=3D ~R_V7M_CCR_BFHFNMIGN_MASK; + } else { + /* + * BFHFNMIGN is RAZ/WI from NS if AIRCR.BFHFNMINS is 0, so + * preserve the state currently in the NS element of the array + */ + if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { + value &=3D ~R_V7M_CCR_BFHFNMIGN_MASK; + value |=3D cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIG= N_MASK; + } } =20 cpu->env.v7m.ccr[attrs.secure] =3D value; --=20 2.20.1 From nobody Sun Feb 8 11:40:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607633460; cv=none; d=zohomail.com; s=zohoarc; b=W57Kvr+QhUKj/JFfZM10n2o9q6MiXwLUhzdpsiR7Cj4hO+E67Lq1iw57fYyu6XSbVvnOhoyu5uPiTfHwoApU3kw7RE4JkrtFgKTX66alGN6ClKhFXRMv+piX5AWFPG7M+HoMtq2qRPjSpsSvb0/t1A8A9/XXjm2O7lmn22+7Cg4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607633460; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4JszHbEHPGhqf66CxwuYFej6f7p+30mZ+/vaBICvo3g=; b=LGSPJopLoagOF9hs3Idnep1lffwRqdYczfVzmjDH5thwrNyM4I2zHhe9icffEyIo3pagP8tX+2KUV5p7CiwAJH5Fpfip/xAbpWODo4vUF1fgrK3sxuYpXyVqv/PdFRRY6onZNNdtX03WzfIvSi9TRFXyBEo8qXe/wOBGTfgk5GI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607633460958596.0906953453054; Thu, 10 Dec 2020 12:51:00 -0800 (PST) Received: from localhost ([::1]:34672 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knSRV-0003NI-Fm for importer@patchew.org; Thu, 10 Dec 2020 15:21:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39936) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knSKn-0007WX-Uf for qemu-devel@nongnu.org; Thu, 10 Dec 2020 15:14:41 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:51836) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knSKl-000113-Qs for qemu-devel@nongnu.org; Thu, 10 Dec 2020 15:14:41 -0500 Received: by mail-wm1-x343.google.com with SMTP id v14so5755069wml.1 for ; Thu, 10 Dec 2020 12:14:39 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y130sm11879591wmc.22.2020.12.10.12.14.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 12:14:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=4JszHbEHPGhqf66CxwuYFej6f7p+30mZ+/vaBICvo3g=; b=m5NsZuccYFf8exaynJ+yABK0pfeETDKhzKSpS5DPcxtiHSf26B4PPTZg7tmG2NbV/L nW6AiEM5WXsrHOTKRc9+qb9Vcbhh9+RSJ7f9OOKly4lVycDlU/0Ch/Og/FAjTM492KvT /tPTWplWfjdg/CsP8NX5+GAAs5yuq7xQ7+XuAkJ1wmJwpE8a7Q2wAeM0S43H35INvDYa TLB+qDvyOiEG7UmuqEom0LeyPL0M/+P5FdomZYnAwpE8TioVr2/Kf0f89YTcX4WZft9B iYh6iiuYydhajfusrC+jwrVQabeRga+P/r9OOzhmgzcF2xifARWUCWIWOATDgZF7h/T1 rnLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4JszHbEHPGhqf66CxwuYFej6f7p+30mZ+/vaBICvo3g=; b=cwx8IbrAn7CC4vSXw8aXDW9PlBE0ZGpn4C/rqyQdr4ND7UcZL8mgan4jNPMsCkL3Jy 8XegqCq6QEeKC82/EQbsIj14I3DrdHVNksK1bohm37wuFtKIdzeCey3qrxWbUUxWFsTA KL91Z7pEh6UUFsjZ7Aka/qhuouM5KtjnquOR5XTFLJbq7c0ub38p975CGfxylU7bxWEK 9OqgmvlsT8JRXa9g9FpEMATw5O8pEv7OnDc6Bp4AN+n3c6ovvbiaCoKD80+yq0S8kSUb c4vWsmnIRBGmtu7fSUq1fDjYOkAk+VaLu/XdxB+wuosuSR1uVIjlFVGJu9pEWuLWDWQO 0efA== X-Gm-Message-State: AOAM5311idBjzboYbWgjk7FISImfazuPv07X0XNW5NT9EuQUHaM74T0Z RsV0P9pCO/Y1NO6BAh1SIcPuLXGhbAPKAA== X-Google-Smtp-Source: ABdhPJxiS0Yuxg0z5HMfstOJGCor3x61aS8Z8lAK38dr268sto7Pejl7hQc9IO2nM6i7ZuEBPVPn6g== X-Received: by 2002:a1c:4156:: with SMTP id o83mr9938467wma.178.1607631278283; Thu, 10 Dec 2020 12:14:38 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH v3 2/4] target/arm: Correct store of FPSCR value via FPCXT_S Date: Thu, 10 Dec 2020 20:14:31 +0000 Message-Id: <20201210201433.26262-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210201433.26262-1-peter.maydell@linaro.org> References: <20201210201433.26262-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x343.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In commit 64f863baeedc8659 we implemented the v8.1M FPCXT_S register, but we got the write behaviour wrong. On read, this register reads bits [27:0] of FPSCR plus the CONTROL.SFPA bit. On write, it doesn't just write back those bits -- it writes a value to the whole FPSCR, whose upper 4 bits are zeroes. We also incorrectly implemented the write-to-FPSCR as a simple store to vfp.xregs; this skips the "update the softfloat flags" part of the vfp_set_fpscr helper so the value would read back correctly but not actually take effect. Fix both of these things by doing a complete write to the FPSCR using the helper function. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.c.inc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 0db936084bd..8b4cfd68cad 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -723,8 +723,11 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int= regno, } case ARM_VFP_FPCXT_S: { - TCGv_i32 sfpa, control, fpscr; - /* Set FPSCR[27:0] and CONTROL.SFPA from value */ + TCGv_i32 sfpa, control; + /* + * Set FPSCR and CONTROL.SFPA from value; the new FPSCR takes + * bits [27:0] from value and zeroes bits [31:28]. + */ tmp =3D loadfn(s, opaque); sfpa =3D tcg_temp_new_i32(); tcg_gen_shri_i32(sfpa, tmp, 31); @@ -732,11 +735,8 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int= regno, tcg_gen_deposit_i32(control, control, sfpa, R_V7M_CONTROL_SFPA_SHIFT, 1); store_cpu_field(control, v7m.control[M_REG_S]); - fpscr =3D load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); - tcg_gen_andi_i32(fpscr, fpscr, FPCR_NZCV_MASK); tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK); - tcg_gen_or_i32(fpscr, fpscr, tmp); - store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]); + gen_helper_vfp_set_fpscr(cpu_env, tmp); tcg_temp_free_i32(tmp); tcg_temp_free_i32(sfpa); break; --=20 2.20.1 From nobody Sun Feb 8 11:40:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607633874; cv=none; d=zohomail.com; s=zohoarc; b=Bc8Rotcs7lqCJMSA8K1rb3uAIXEnQbA1DdUaJt3qLvJLH+FWq0nfJGxJDbkl+gxEkjruKkTLnboCrLqdwTMsg/sPIToEQbKZ35lPTgQTqKJXcMjvYfX8JCg2g12572d3JcdZsToVbYvklIM8MHXTF3prSkYm0omB5EX/NpvrmLU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607633874; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VW73SL2e03HTZn5SraqkB3la7LiS2Li1U2Ibx4vs/D8=; b=PB6R61GLkexBYKfNYFFnEF9JhDGXmvY80TKgf3uYqTXb6QIu5NAXKuLl2DW4s5TLCUkP/BJ1SZXJfl5c+cNE+ZlAhynq4cqDIGajDOvO6ucpL95G8HTNWibGKHtRb6wkN6ujYr7DpU3zTBECDloRIBy0y6LI6LVs8b85KE2KxOc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607633874552840.5318533867087; Thu, 10 Dec 2020 12:57:54 -0800 (PST) Received: from localhost ([::1]:56418 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knSNE-0000X7-7E for importer@patchew.org; Thu, 10 Dec 2020 15:17:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39954) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knSKp-0007YK-B7 for qemu-devel@nongnu.org; Thu, 10 Dec 2020 15:14:43 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:52565) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knSKn-00012d-D1 for qemu-devel@nongnu.org; Thu, 10 Dec 2020 15:14:43 -0500 Received: by mail-wm1-x329.google.com with SMTP id a6so5752324wmc.2 for ; Thu, 10 Dec 2020 12:14:40 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id y130sm11879591wmc.22.2020.12.10.12.14.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 12:14:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=VW73SL2e03HTZn5SraqkB3la7LiS2Li1U2Ibx4vs/D8=; b=opQuOfDRjs14oB2GM83bdzsk0jmJ4Mgl8BxrlydHs0SNGyxh5bUZPV4fgGuUIDoie4 OCDnN3hbG6Wio12Hqrdgl74APgfNZztvIoQ1gQhxf9WjTSRu41maXGxCcAKUIzWhnV4B n53b/D1ujM8SpLHZFIlVvaIulxJ/xD++DD1LJQEgs6pX18zQ8msoNntVEB6kQ9sIQ1R1 9TbxE6bWWc2OU6V7vQspZkt7oZSwYmhMCiv4mo1xTG5aXqmQ6jtp1MEzBM3GwAbrH5oC eWy6fr3QT+s4Hr4uTg5shhgVv0U9OWzz1qlSLlcyOEaQDLmJ7fyG/JqSfrH5g8BFKfLi fJKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VW73SL2e03HTZn5SraqkB3la7LiS2Li1U2Ibx4vs/D8=; b=h7nlDeHNpt4nhn+HtsO35Vh8EQUwpZhYjLt4ECbiv1IQouhPJgrsBmde05C+oWacq/ eq28iyTZAgs2wkI9mwOpi8/yjKLszvK3EPwWBgbfjMkpLupTnHCC1mhWaHu+1KCkyGDQ tS9wOSWRWOxYYRcrdpuoNUXrw7k6axHRZVPcQlYTinYTn7WRqtLCp7GSUd9g/gmDn4xa +VdZlbIG0tF2ufsteRSIILIxb/xTInF78G1pmj+sBJIgXfyPckPgvy3ER1jzOC4ZcLeZ 0RbAnTrqfPeRHDF0XpWsM/l6pGE9TwxtmWOAi5ZiA4b5hsm9HrSGneMQy+fEZzmmfCGY 8ydA== X-Gm-Message-State: AOAM531m6+LcWBDvP5/DLU2ZivlElvJmWgIBmf8PkQ+OprFVj9/2v6n3 MPQxyc42iLBowS3rZ9b/+TbnbqQIGRTzRg== X-Google-Smtp-Source: ABdhPJy0Y3CQvaLJc/6aG4eJ7oc8RFBpwobvTSqdPJjcpg4UJMguHJSSPNXjfWzscs0ATQITwLSm8Q== X-Received: by 2002:a7b:c773:: with SMTP id x19mr9761941wmk.127.1607631279694; Thu, 10 Dec 2020 12:14:39 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH v3 3/4] target/arm: Implement FPCXT_NS fp system register Date: Thu, 10 Dec 2020 20:14:32 +0000 Message-Id: <20201210201433.26262-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210201433.26262-1-peter.maydell@linaro.org> References: <20201210201433.26262-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the v8.1M FPCXT_NS floating-point system register. This is a little more complicated than FPCXT_S, because it has specific handling for "current FP state is inactive", and it only wants to do PreserveFPState(), not the full set of actions done by ExecuteFPCheck() which vfp_access_check() implements. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- Changes since v2: refactored along lines suggested by RTH --- target/arm/translate-vfp.c.inc | 102 ++++++++++++++++++++++++++++++++- 1 file changed, 99 insertions(+), 3 deletions(-) diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 8b4cfd68cad..10766f210c1 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -663,6 +663,7 @@ static FPSysRegCheckResult fp_sysreg_checks(DisasContex= t *s, int regno) } break; case ARM_VFP_FPCXT_S: + case ARM_VFP_FPCXT_NS: if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { return false; } @@ -674,13 +675,48 @@ static FPSysRegCheckResult fp_sysreg_checks(DisasCont= ext *s, int regno) return FPSysRegCheckFailed; } =20 - if (!vfp_access_check(s)) { + /* + * FPCXT_NS is a special case: it has specific handling for + * "current FP state is inactive", and must do the PreserveFPState() + * but not the usual full set of actions done by ExecuteFPCheck(). + * So we don't call vfp_access_check() and the callers must handle thi= s. + */ + if (regno !=3D ARM_VFP_FPCXT_NS && !vfp_access_check(s)) { return FPSysRegCheckDone; } - return FPSysRegCheckContinue; } =20 +static void gen_branch_fpInactive(DisasContext *s, TCGCond cond, + TCGLabel *label) +{ + /* + * FPCXT_NS is a special case: it has specific handling for + * "current FP state is inactive", and must do the PreserveFPState() + * but not the usual full set of actions done by ExecuteFPCheck(). + * We don't have a TB flag that matches the fpInactive check, so we + * do it at runtime as we don't expect FPCXT_NS accesses to be frequen= t. + * + * Emit code that checks fpInactive and does a conditional + * branch to label based on it: + * if cond is TCG_COND_NE then branch if fpInactive !=3D 0 (ie if ina= ctive) + * if cond is TCG_COND_EQ then branch if fpInactive =3D=3D 0 (ie if a= ctive) + */ + assert(cond =3D=3D TCG_COND_EQ || cond =3D=3D TCG_COND_NE); + + /* fpInactive =3D FPCCR_NS.ASPEN =3D=3D 1 && CONTROL.FPCA =3D=3D 0 */ + TCGv_i32 aspen, fpca; + aspen =3D load_cpu_field(v7m.fpccr[M_REG_NS]); + fpca =3D load_cpu_field(v7m.control[M_REG_S]); + tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); + tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); + tcg_gen_andi_i32(fpca, fpca, R_V7M_CONTROL_FPCA_MASK); + tcg_gen_or_i32(fpca, fpca, aspen); + tcg_gen_brcondi_i32(tcg_invert_cond(cond), fpca, 0, label); + tcg_temp_free_i32(aspen); + tcg_temp_free_i32(fpca); +} + static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, =20 fp_sysreg_loadfn *loadfn, @@ -688,6 +724,7 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int = regno, { /* Do a write to an M-profile floating point system register */ TCGv_i32 tmp; + TCGLabel *lab_end =3D NULL; =20 switch (fp_sysreg_checks(s, regno)) { case FPSysRegCheckFailed: @@ -721,6 +758,13 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int= regno, tcg_temp_free_i32(tmp); break; } + case ARM_VFP_FPCXT_NS: + lab_end =3D gen_new_label(); + /* fpInactive case: write is a NOP, so branch to end */ + gen_branch_fpInactive(s, TCG_COND_NE, lab_end); + /* !fpInactive: PreserveFPState(), and reads same as FPCXT_S */ + gen_preserve_fp_state(s); + /* fall through */ case ARM_VFP_FPCXT_S: { TCGv_i32 sfpa, control; @@ -744,6 +788,9 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int = regno, default: g_assert_not_reached(); } + if (lab_end) { + gen_set_label(lab_end); + } return true; } =20 @@ -753,6 +800,8 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int r= egno, { /* Do a read from an M-profile floating point system register */ TCGv_i32 tmp; + TCGLabel *lab_end =3D NULL; + bool lookup_tb =3D false; =20 switch (fp_sysreg_checks(s, regno)) { case FPSysRegCheckFailed: @@ -811,12 +860,59 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int= regno, fpscr =3D load_cpu_field(v7m.fpdscr[M_REG_NS]); gen_helper_vfp_set_fpscr(cpu_env, fpscr); tcg_temp_free_i32(fpscr); - gen_lookup_tb(s); + lookup_tb =3D true; + break; + } + case ARM_VFP_FPCXT_NS: + { + TCGv_i32 control, sfpa, fpscr, fpdscr, zero; + TCGLabel *lab_active =3D gen_new_label(); + + lookup_tb =3D true; + + gen_branch_fpInactive(s, TCG_COND_EQ, lab_active); + /* fpInactive case: reads as FPDSCR_NS */ + TCGv_i32 tmp =3D load_cpu_field(v7m.fpdscr[M_REG_NS]); + storefn(s, opaque, tmp); + lab_end =3D gen_new_label(); + tcg_gen_br(lab_end); + + gen_set_label(lab_active); + /* !fpInactive: Reads the same as FPCXT_S, but side effects differ= */ + gen_preserve_fp_state(s); + tmp =3D tcg_temp_new_i32(); + sfpa =3D tcg_temp_new_i32(); + fpscr =3D tcg_temp_new_i32(); + gen_helper_vfp_get_fpscr(fpscr, cpu_env); + tcg_gen_andi_i32(tmp, fpscr, ~FPCR_NZCV_MASK); + control =3D load_cpu_field(v7m.control[M_REG_S]); + tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK); + tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT); + tcg_gen_or_i32(tmp, tmp, sfpa); + tcg_temp_free_i32(control); + /* Store result before updating FPSCR, in case it faults */ + storefn(s, opaque, tmp); + /* If SFPA is zero then set FPSCR from FPDSCR_NS */ + fpdscr =3D load_cpu_field(v7m.fpdscr[M_REG_NS]); + zero =3D tcg_const_i32(0); + tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, zero, fpdscr, fpscr); + gen_helper_vfp_set_fpscr(cpu_env, fpscr); + tcg_temp_free_i32(zero); + tcg_temp_free_i32(sfpa); + tcg_temp_free_i32(fpdscr); + tcg_temp_free_i32(fpscr); break; } default: g_assert_not_reached(); } + + if (lab_end) { + gen_set_label(lab_end); + } + if (lookup_tb) { + gen_lookup_tb(s); + } return true; } =20 --=20 2.20.1 From nobody Sun Feb 8 11:40:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607633851; cv=none; d=zohomail.com; s=zohoarc; b=SygZ6+x8LqKwM8iK7+2eQnxBLGnHt60JNiz88weFGTn4yVs+nFDOkRuTrDxlC5DwQd/pOkelQvJfeRzF5UZ+q9jQKthKzAXfO7kus4TK8XkSPI29KPgvAGY1V3kuQ1scjfUuGFpO1YA5bCSBURO8pwG4eqZfh5H8RDR8OUz4DA8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607633851; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y130sm11879591wmc.22.2020.12.10.12.14.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 12:14:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=aUi6vcMH4o0CYad/653lpbXGwZgjtkuhUa4zld0PALo=; b=w+BS881wXyEJlIKegHwmhD1uj1IrL/mXlXoc+eOME4KbzWEpgZ4nrFPvKLYZDhwyhD WRyxv8wPH+1LFjx73bJPG/cOWVz9SqvGDkZXsvcJoFXGNsWbbUrkjjuKmyfwXmdoi0iZ juNRPU9pmOB6XxZR7AHaKyErAJX2tvi7RttdorGiTbt6a3+gqXrfVvGxybSEwil7FjiE l9Av3qEUqAFunOK68qazkWwsnoRweIYD8rPRYz6zsGdIUBO5eLSgFG2kY/MToQ64GFsn 1SARu6R5mzgopuq6qWuCz3GyY85PMHUJw/pupYBakboQoyLKLLOwBb9aeeyPKcs/twcM EwEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aUi6vcMH4o0CYad/653lpbXGwZgjtkuhUa4zld0PALo=; b=jAAgEopPkGzY8Gc9lJcG1Yyi3ShHeDdgrT7Gj8VWavSXrDrFBQRyjf15NI15EHZZa6 7FLDKUiXmUR5yd03RAOEOPcAOYOXuV/8ZUwhX4lQxr9GsEwmZpq2FCiyIZWkBJNLbXH9 DwC+czxAfcldnR0owxYNYYcuVq7BgqXyl12cUz7f7ZfBo1UQPC1DeXF2iCgpZFI7nflz KRPoPLyy9K/arfoLhh1boioZ90013Jqe/C3EVQGGVAT/0PlVlc8ztgPjTHAKVtt6SbV7 tkJb4f0pXHua7/2yXaEkQ7jeaQkJgPEajQeTnyhR7MCP2cmqwZcsBD82/IXE80FTVOPD 9IkQ== X-Gm-Message-State: AOAM531UdfZjcDiecdawTH9ZCAZehhSu8uiG8ROJ4PqA6J6UkGshmo0J 6XzJZVEXrOjNtLcQTgXkDY4gXAuInYulxw== X-Google-Smtp-Source: ABdhPJwNDE6XgkdBLyjbgT+woL3dcoshKqW6e0n5hm+4CYI/GMNYOAYrwZxbTqx1NGl/fPhpujGJ/Q== X-Received: by 2002:a5d:5385:: with SMTP id d5mr6260008wrv.384.1607631280697; Thu, 10 Dec 2020 12:14:40 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH v3 4/4] target/arm: Implement Cortex-M55 model Date: Thu, 10 Dec 2020 20:14:33 +0000 Message-Id: <20201210201433.26262-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210201433.26262-1-peter.maydell@linaro.org> References: <20201210201433.26262-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::443; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x443.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Now that we have implemented all the features needed by the v8.1M architecture, we can add the model of the Cortex-M55. This is the configuration without MVE support; we'll add MVE later. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu_tcg.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 0013e25412f..98544db2df3 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -401,6 +401,46 @@ static void cortex_m33_initfn(Object *obj) cpu->ctr =3D 0x8000c000; } =20 +static void cortex_m55_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_V8_1M); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + cpu->midr =3D 0x410fd221; /* r0p1 */ + cpu->revidr =3D 0; + cpu->pmsav7_dregion =3D 16; + cpu->sau_sregion =3D 8; + /* + * These are the MVFR* values for the FPU, no MVE configuration; + * we will update them later when we implement MVE + */ + cpu->isar.mvfr0 =3D 0x10110221; + cpu->isar.mvfr1 =3D 0x12100011; + cpu->isar.mvfr2 =3D 0x00000040; + cpu->isar.id_pfr0 =3D 0x20000030; + cpu->isar.id_pfr1 =3D 0x00000230; + cpu->isar.id_dfr0 =3D 0x10200000; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x00111040; + cpu->isar.id_mmfr1 =3D 0x00000000; + cpu->isar.id_mmfr2 =3D 0x01000000; + cpu->isar.id_mmfr3 =3D 0x00000011; + cpu->isar.id_isar0 =3D 0x01103110; + cpu->isar.id_isar1 =3D 0x02212000; + cpu->isar.id_isar2 =3D 0x20232232; + cpu->isar.id_isar3 =3D 0x01111131; + cpu->isar.id_isar4 =3D 0x01310132; + cpu->isar.id_isar5 =3D 0x00000000; + cpu->isar.id_isar6 =3D 0x00000000; + cpu->clidr =3D 0x00000000; /* caches not implemented */ + cpu->ctr =3D 0x8303c003; +} + static const ARMCPRegInfo cortexr5_cp_reginfo[] =3D { /* Dummy the TCM region regs for the moment */ { .name =3D "ATCM", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .= opc2 =3D 0, @@ -655,6 +695,8 @@ static const ARMCPUInfo arm_tcg_cpus[] =3D { .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-m33", .initfn =3D cortex_m33_initfn, .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-m55", .initfn =3D cortex_m55_initfn, + .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-r5", .initfn =3D cortex_r5_initfn }, { .name =3D "cortex-r5f", .initfn =3D cortex_r5f_initfn }, { .name =3D "ti925t", .initfn =3D ti925t_initfn }, --=20 2.20.1