From nobody Mon Feb 9 20:31:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607603877; cv=none; d=zohomail.com; s=zohoarc; b=ifr3VoMcKbcg/BFKatqouna1qs2hmLGPgTVLeVX2/DVAGO7iGniW82JJeQdVluK77f5ZJAidS3x9MOsY0BTUCnEsiz7bRhWu7IUuD1C03HH2FZ2GCL+Zqe4rt5pLWJZe//b8hJY6RCdd0uqtmK91muzVvxzXoP6u4YOhu4A6FZk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607603877; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6eetIb6SqFeNaiwDJqaDOP7O/FXRJZ3thSmOeU+DzJc=; b=AMYNj1zjsgSEPoisIBCY4Juf96Zx4t786XBuBYHTBfUHZBCU9zLOERmUqErc/L0ik/7emmqQcWmtbQW22DcYun4pLGzT89QYsG5/qkJ0Iua75CiwlbzPaqWdwrztMBC4V6PxaGoby+GP5lJzflr7rhRB45JeyzEw16+esHAej7M= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607603877054270.3654655566328; Thu, 10 Dec 2020 04:37:57 -0800 (PST) Received: from localhost ([::1]:51080 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knLCl-0005Ki-Lx for importer@patchew.org; Thu, 10 Dec 2020 07:37:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56606) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKog-0002U6-CO for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:13:02 -0500 Received: from mx2.suse.de ([195.135.220.15]:47630) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKod-0006VY-2u for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:13:02 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id CADA4AD75; Thu, 10 Dec 2020 12:12:47 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 18/32] cpu: Move synchronize_from_tb() to tcg_ops Date: Thu, 10 Dec 2020 13:12:12 +0100 Message-Id: <20201210121226.19822-19-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Colin Xu , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Eduardo Habkost Signed-off-by: Eduardo Habkost [claudio: wrapped in CONFIG_TCG] Signed-off-by: Claudio Fontana Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e --- include/hw/core/cpu.h | 8 -------- include/hw/core/tcg-cpu-ops.h | 12 ++++++++++++ accel/tcg/cpu-exec.c | 4 ++-- target/arm/cpu.c | 2 +- target/avr/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/tcg/tcg-cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 2 +- 14 files changed, 25 insertions(+), 21 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index ea648d52ad..83007d262c 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -110,13 +110,6 @@ struct TranslationBlock; * If the target behaviour here is anything other than "set * the PC register to the value passed in" then the target must * also implement the synchronize_from_tb hook. - * @synchronize_from_tb: Callback for synchronizing state from a TCG - * #TranslationBlock. This is called when we abandon execution - * of a TB before starting it, and must set all parts of the CPU - * state which the previous TB in the chain may not have updated. - * This always includes at least the program counter; some targets - * will need to do more. If this hook is not implemented then the - * default is to call @set_pc(tb->pc). * @tlb_fill: Callback for handling a softmmu tlb miss or user-only * address fault. For system mode, if the access is valid, call * tlb_set_page and return true; if the access is invalid, and @@ -193,7 +186,6 @@ struct CPUClass { void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); - void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb= ); bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 4475ef0996..e1d50b3c8b 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -10,6 +10,8 @@ #ifndef TCG_CPU_OPS_H #define TCG_CPU_OPS_H =20 +#include "hw/core/cpu.h" + /** * struct TcgCpuOperations: TCG operations specific to a CPU class */ @@ -20,6 +22,16 @@ typedef struct TcgCpuOperations { * Called when the first CPU is realized. */ void (*initialize)(void); + /** + * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock + * + * This is called when we abandon execution of a TB before + * starting it, and must set all parts of the CPU state which + * the previous TB in the chain may not have updated. This + * will need to do more. If this hook is not implemented then + * the default is to call @set_pc(tb->pc). + */ + void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb= ); } TcgCpuOperations; =20 #endif /* TCG_CPU_OPS_H */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 50eb92d217..05dba7f2cc 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -192,8 +192,8 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cp= u, TranslationBlock *itb) TARGET_FMT_lx "] %s\n", last_tb->tc.ptr, last_tb->pc, lookup_symbol(last_tb->pc)); - if (cc->synchronize_from_tb) { - cc->synchronize_from_tb(cpu, last_tb); + if (cc->tcg_ops.synchronize_from_tb) { + cc->tcg_ops.synchronize_from_tb(cpu, last_tb); } else { assert(cc->set_pc); cc->set_pc(cpu, last_tb->pc); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1fa9382a7c..2f9e27c248 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2242,7 +2242,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->cpu_exec_interrupt =3D arm_cpu_exec_interrupt; cc->dump_state =3D arm_cpu_dump_state; cc->set_pc =3D arm_cpu_set_pc; - cc->synchronize_from_tb =3D arm_cpu_synchronize_from_tb; cc->gdb_read_register =3D arm_cpu_gdb_read_register; cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY @@ -2262,6 +2261,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->disas_set_info =3D arm_disas_set_info; #ifdef CONFIG_TCG cc->tcg_ops.initialize =3D arm_translate_init; + cc->tcg_ops.synchronize_from_tb =3D arm_cpu_synchronize_from_tb; cc->tlb_fill =3D arm_cpu_tlb_fill; cc->debug_excp_handler =3D arm_debug_excp_handler; cc->debug_check_watchpoint =3D arm_debug_check_watchpoint; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 94306a2aa0..f753c15768 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -207,7 +207,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->vmsd =3D &vms_avr_cpu; cc->disas_set_info =3D avr_cpu_disas_set_info; cc->tcg_ops.initialize =3D avr_cpu_tcg_init; - cc->synchronize_from_tb =3D avr_cpu_synchronize_from_tb; + cc->tcg_ops.synchronize_from_tb =3D avr_cpu_synchronize_from_tb; cc->gdb_read_register =3D avr_cpu_gdb_read_register; cc->gdb_write_register =3D avr_cpu_gdb_write_register; cc->gdb_num_core_regs =3D 35; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 4c778966c2..12a09e93ae 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -143,7 +143,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->cpu_exec_interrupt =3D hppa_cpu_exec_interrupt; cc->dump_state =3D hppa_cpu_dump_state; cc->set_pc =3D hppa_cpu_set_pc; - cc->synchronize_from_tb =3D hppa_cpu_synchronize_from_tb; + cc->tcg_ops.synchronize_from_tb =3D hppa_cpu_synchronize_from_tb; cc->gdb_read_register =3D hppa_cpu_gdb_read_register; cc->gdb_write_register =3D hppa_cpu_gdb_write_register; cc->tlb_fill =3D hppa_cpu_tlb_fill; diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 1f2a3e881a..d1414e2970 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -60,7 +60,7 @@ void tcg_cpu_common_class_init(CPUClass *cc) { cc->do_interrupt =3D x86_cpu_do_interrupt; cc->cpu_exec_interrupt =3D x86_cpu_exec_interrupt; - cc->synchronize_from_tb =3D x86_cpu_synchronize_from_tb; + cc->tcg_ops.synchronize_from_tb =3D x86_cpu_synchronize_from_tb; cc->cpu_exec_enter =3D x86_cpu_exec_enter; cc->cpu_exec_exit =3D x86_cpu_exec_exit; cc->tcg_ops.initialize =3D tcg_x86_init; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index bc10518fa3..97d94d9c27 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -322,7 +322,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->cpu_exec_interrupt =3D mb_cpu_exec_interrupt; cc->dump_state =3D mb_cpu_dump_state; cc->set_pc =3D mb_cpu_set_pc; - cc->synchronize_from_tb =3D mb_cpu_synchronize_from_tb; + cc->tcg_ops.synchronize_from_tb =3D mb_cpu_synchronize_from_tb; cc->gdb_read_register =3D mb_cpu_gdb_read_register; cc->gdb_write_register =3D mb_cpu_gdb_write_register; cc->tlb_fill =3D mb_cpu_tlb_fill; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index bc48573763..71c488f3dd 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -238,7 +238,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->cpu_exec_interrupt =3D mips_cpu_exec_interrupt; cc->dump_state =3D mips_cpu_dump_state; cc->set_pc =3D mips_cpu_set_pc; - cc->synchronize_from_tb =3D mips_cpu_synchronize_from_tb; cc->gdb_read_register =3D mips_cpu_gdb_read_register; cc->gdb_write_register =3D mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY @@ -250,6 +249,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->disas_set_info =3D mips_cpu_disas_set_info; #ifdef CONFIG_TCG cc->tcg_ops.initialize =3D mips_tcg_init; + cc->tcg_ops.synchronize_from_tb =3D mips_cpu_synchronize_from_tb; cc->tlb_fill =3D mips_cpu_tlb_fill; #endif =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 27dd1645c9..a9c30879d3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -543,7 +543,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->cpu_exec_interrupt =3D riscv_cpu_exec_interrupt; cc->dump_state =3D riscv_cpu_dump_state; cc->set_pc =3D riscv_cpu_set_pc; - cc->synchronize_from_tb =3D riscv_cpu_synchronize_from_tb; + cc->tcg_ops.synchronize_from_tb =3D riscv_cpu_synchronize_from_tb; cc->gdb_read_register =3D riscv_cpu_gdb_read_register; cc->gdb_write_register =3D riscv_cpu_gdb_write_register; cc->gdb_num_core_regs =3D 33; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index a701a09b11..d03c4e0b05 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -189,7 +189,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) cc->cpu_exec_interrupt =3D rx_cpu_exec_interrupt; cc->dump_state =3D rx_cpu_dump_state; cc->set_pc =3D rx_cpu_set_pc; - cc->synchronize_from_tb =3D rx_cpu_synchronize_from_tb; + cc->tcg_ops.synchronize_from_tb =3D rx_cpu_synchronize_from_tb; cc->gdb_read_register =3D rx_cpu_gdb_read_register; cc->gdb_write_register =3D rx_cpu_gdb_write_register; cc->get_phys_page_debug =3D rx_cpu_get_phys_page_debug; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index bdc5c9d90b..a33025b5c8 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -222,7 +222,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->cpu_exec_interrupt =3D superh_cpu_exec_interrupt; cc->dump_state =3D superh_cpu_dump_state; cc->set_pc =3D superh_cpu_set_pc; - cc->synchronize_from_tb =3D superh_cpu_synchronize_from_tb; + cc->tcg_ops.synchronize_from_tb =3D superh_cpu_synchronize_from_tb; cc->gdb_read_register =3D superh_cpu_gdb_read_register; cc->gdb_write_register =3D superh_cpu_gdb_write_register; cc->tlb_fill =3D superh_cpu_tlb_fill; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 07e48b86d1..baf6c5b587 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -868,7 +868,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->memory_rw_debug =3D sparc_cpu_memory_rw_debug; #endif cc->set_pc =3D sparc_cpu_set_pc; - cc->synchronize_from_tb =3D sparc_cpu_synchronize_from_tb; + cc->tcg_ops.synchronize_from_tb =3D sparc_cpu_synchronize_from_tb; cc->gdb_read_register =3D sparc_cpu_gdb_read_register; cc->gdb_write_register =3D sparc_cpu_gdb_write_register; cc->tlb_fill =3D sparc_cpu_tlb_fill; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 78b2925955..5edf96c600 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -162,7 +162,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) =20 cc->dump_state =3D tricore_cpu_dump_state; cc->set_pc =3D tricore_cpu_set_pc; - cc->synchronize_from_tb =3D tricore_cpu_synchronize_from_tb; + cc->tcg_ops.synchronize_from_tb =3D tricore_cpu_synchronize_from_tb; cc->get_phys_page_debug =3D tricore_cpu_get_phys_page_debug; cc->tcg_ops.initialize =3D tricore_tcg_init; cc->tlb_fill =3D tricore_cpu_tlb_fill; --=20 2.26.2