From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607604570; cv=none; d=zohomail.com; s=zohoarc; b=jufxWR13Cck7Yc1Zaf4z4Fw0zvnLp9gmWD/mYjI7HyvOXTiX55/gem+pN+p/KI/UBUamYIJ4l7RJWSyEhb9tf+u7e1VvA2y6Yqx0rwLltAH5SrzkykIpwJg14UnIRtV9FxI7Y0B+1rIaAmZ6N0vhtwmhGh1v4F7DTcIY13x94cU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607604570; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cx6M4ge5TCAcIivCr+EWQRpDLKAVTq/s3OYCEqfskXY=; b=fwFcRNsawqg+VwXVobSjBIqdLsN/S7KFaf7mkAcVPyRnq7zUwWrj2Yw6OvsJ7cq12j0u2c1gEuZ9JZERlSksdLgPr83FwRMRcUPd75uM++OFKqwmMWs3uZ/Jc2FeOqqZy5A+ZMG+0tIko7h1fTcvg0A0YtEMCPyTySbfWyI49QI= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607604570290786.7425629890726; Thu, 10 Dec 2020 04:49:30 -0800 (PST) Received: from localhost ([::1]:45936 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knLNw-0006ZW-Um for importer@patchew.org; Thu, 10 Dec 2020 07:49:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56366) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoI-0001x6-6o for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:12:38 -0500 Received: from mx2.suse.de ([195.135.220.15]:46942) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoC-0006PI-Ba for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:12:37 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 0A181AD29; Thu, 10 Dec 2020 12:12:30 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 01/32] accel/tcg: split CpusAccel into three TCG variants Date: Thu, 10 Dec 2020 13:11:55 +0100 Message-Id: <20201210121226.19822-2-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" split up the CpusAccel tcg_cpus into three TCG variants: tcg_cpus_rr (single threaded, round robin cpus) tcg_cpus_icount (same as rr, but with instruction counting enabled) tcg_cpus_mttcg (multi-threaded cpus) Suggested-by: Richard Henderson Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/tcg-cpus-icount.h | 17 ++ accel/tcg/tcg-cpus-mttcg.h | 21 ++ accel/tcg/tcg-cpus-rr.h | 20 ++ accel/tcg/tcg-cpus.h | 13 +- accel/tcg/tcg-all.c | 8 +- accel/tcg/tcg-cpus-icount.c | 147 +++++++++++ accel/tcg/tcg-cpus-mttcg.c | 117 +++++++++ accel/tcg/tcg-cpus-rr.c | 270 ++++++++++++++++++++ accel/tcg/tcg-cpus.c | 484 ++---------------------------------- softmmu/icount.c | 2 +- accel/tcg/meson.build | 9 +- 11 files changed, 646 insertions(+), 462 deletions(-) create mode 100644 accel/tcg/tcg-cpus-icount.h create mode 100644 accel/tcg/tcg-cpus-mttcg.h create mode 100644 accel/tcg/tcg-cpus-rr.h create mode 100644 accel/tcg/tcg-cpus-icount.c create mode 100644 accel/tcg/tcg-cpus-mttcg.c create mode 100644 accel/tcg/tcg-cpus-rr.c diff --git a/accel/tcg/tcg-cpus-icount.h b/accel/tcg/tcg-cpus-icount.h new file mode 100644 index 0000000000..cbcf76b413 --- /dev/null +++ b/accel/tcg/tcg-cpus-icount.h @@ -0,0 +1,17 @@ +/* + * QEMU TCG Single Threaded vCPUs implementation using instruction counting + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef TCG_CPUS_ICOUNT_H +#define TCG_CPUS_ICOUNT_H + +void handle_icount_deadline(void); +void prepare_icount_for_run(CPUState *cpu); +void process_icount_data(CPUState *cpu); + +#endif /* TCG_CPUS_ICOUNT_H */ diff --git a/accel/tcg/tcg-cpus-mttcg.h b/accel/tcg/tcg-cpus-mttcg.h new file mode 100644 index 0000000000..d1bd771f49 --- /dev/null +++ b/accel/tcg/tcg-cpus-mttcg.h @@ -0,0 +1,21 @@ +/* + * QEMU TCG Multi Threaded vCPUs implementation + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef TCG_CPUS_MTTCG_H +#define TCG_CPUS_MTTCG_H + +/* + * In the multi-threaded case each vCPU has its own thread. The TLS + * variable current_cpu can be used deep in the code to find the + * current CPUState for a given thread. + */ + +void *tcg_cpu_thread_fn(void *arg); + +#endif /* TCG_CPUS_MTTCG_H */ diff --git a/accel/tcg/tcg-cpus-rr.h b/accel/tcg/tcg-cpus-rr.h new file mode 100644 index 0000000000..1936fd16ab --- /dev/null +++ b/accel/tcg/tcg-cpus-rr.h @@ -0,0 +1,20 @@ +/* + * QEMU TCG Single Threaded vCPUs implementation + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef TCG_CPUS_RR_H +#define TCG_CPUS_RR_H + +#define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10) + +/* Kick all RR vCPUs. */ +void qemu_cpu_kick_rr_cpus(CPUState *unused); + +void *tcg_rr_cpu_thread_fn(void *arg); + +#endif /* TCG_CPUS_RR_H */ diff --git a/accel/tcg/tcg-cpus.h b/accel/tcg/tcg-cpus.h index 8b1d9d2abc..279ba72e1f 100644 --- a/accel/tcg/tcg-cpus.h +++ b/accel/tcg/tcg-cpus.h @@ -1,5 +1,7 @@ /* - * Accelerator CPUS Interface + * QEMU TCG vCPU common functionality + * + * Functionality common to all TCG vcpu variants: mttcg, rr and icount. * * Copyright 2020 SUSE LLC * @@ -12,6 +14,13 @@ =20 #include "sysemu/cpus.h" =20 -extern const CpusAccel tcg_cpus; +extern const CpusAccel tcg_cpus_mttcg; +extern const CpusAccel tcg_cpus_icount; +extern const CpusAccel tcg_cpus_rr; + +void tcg_start_vcpu_thread(CPUState *cpu); +void qemu_tcg_destroy_vcpu(CPUState *cpu); +int tcg_cpu_exec(CPUState *cpu); +void tcg_handle_interrupt(CPUState *cpu, int mask); =20 #endif /* TCG_CPUS_H */ diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index fa1208158f..e42a028043 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -104,8 +104,14 @@ static int tcg_init(MachineState *ms) =20 tcg_exec_init(s->tb_size * 1024 * 1024); mttcg_enabled =3D s->mttcg_enabled; - cpus_register_accel(&tcg_cpus); =20 + if (mttcg_enabled) { + cpus_register_accel(&tcg_cpus_mttcg); + } else if (icount_enabled()) { + cpus_register_accel(&tcg_cpus_icount); + } else { + cpus_register_accel(&tcg_cpus_rr); + } return 0; } =20 diff --git a/accel/tcg/tcg-cpus-icount.c b/accel/tcg/tcg-cpus-icount.c new file mode 100644 index 0000000000..d3af3afb6d --- /dev/null +++ b/accel/tcg/tcg-cpus-icount.c @@ -0,0 +1,147 @@ +/* + * QEMU TCG Single Threaded vCPUs implementation using instruction counting + * + * Copyright (c) 2003-2008 Fabrice Bellard + * Copyright (c) 2014 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "sysemu/tcg.h" +#include "sysemu/replay.h" +#include "qemu/main-loop.h" +#include "qemu/guest-random.h" +#include "exec/exec-all.h" +#include "hw/boards.h" + +#include "tcg-cpus.h" +#include "tcg-cpus-icount.h" +#include "tcg-cpus-rr.h" + +static int64_t tcg_get_icount_limit(void) +{ + int64_t deadline; + + if (replay_mode !=3D REPLAY_MODE_PLAY) { + /* + * Include all the timers, because they may need an attention. + * Too long CPU execution may create unnecessary delay in UI. + */ + deadline =3D qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL, + QEMU_TIMER_ATTR_ALL); + /* Check realtime timers, because they help with input processing = */ + deadline =3D qemu_soonest_timeout(deadline, + qemu_clock_deadline_ns_all(QEMU_CLOCK_REALTIME, + QEMU_TIMER_ATTR_ALL)); + + /* + * Maintain prior (possibly buggy) behaviour where if no deadline + * was set (as there is no QEMU_CLOCK_VIRTUAL timer) or it is more= than + * INT32_MAX nanoseconds ahead, we still use INT32_MAX + * nanoseconds. + */ + if ((deadline < 0) || (deadline > INT32_MAX)) { + deadline =3D INT32_MAX; + } + + return icount_round(deadline); + } else { + return replay_get_instructions(); + } +} + +static void notify_aio_contexts(void) +{ + /* Wake up other AioContexts. */ + qemu_clock_notify(QEMU_CLOCK_VIRTUAL); + qemu_clock_run_timers(QEMU_CLOCK_VIRTUAL); +} + +void handle_icount_deadline(void) +{ + assert(qemu_in_vcpu_thread()); + int64_t deadline =3D qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL, + QEMU_TIMER_ATTR_ALL); + + if (deadline =3D=3D 0) { + notify_aio_contexts(); + } +} + +void prepare_icount_for_run(CPUState *cpu) +{ + int insns_left; + + /* + * These should always be cleared by process_icount_data after + * each vCPU execution. However u16.high can be raised + * asynchronously by cpu_exit/cpu_interrupt/tcg_handle_interrupt + */ + g_assert(cpu_neg(cpu)->icount_decr.u16.low =3D=3D 0); + g_assert(cpu->icount_extra =3D=3D 0); + + cpu->icount_budget =3D tcg_get_icount_limit(); + insns_left =3D MIN(0xffff, cpu->icount_budget); + cpu_neg(cpu)->icount_decr.u16.low =3D insns_left; + cpu->icount_extra =3D cpu->icount_budget - insns_left; + + replay_mutex_lock(); + + if (cpu->icount_budget =3D=3D 0 && replay_has_checkpoint()) { + notify_aio_contexts(); + } +} + +void process_icount_data(CPUState *cpu) +{ + /* Account for executed instructions */ + icount_update(cpu); + + /* Reset the counters */ + cpu_neg(cpu)->icount_decr.u16.low =3D 0; + cpu->icount_extra =3D 0; + cpu->icount_budget =3D 0; + + replay_account_executed_instructions(); + + replay_mutex_unlock(); +} + +static void icount_handle_interrupt(CPUState *cpu, int mask) +{ + int old_mask =3D cpu->interrupt_request; + + tcg_handle_interrupt(cpu, mask); + if (qemu_cpu_is_self(cpu) && + !cpu->can_do_io + && (mask & ~old_mask) !=3D 0) { + cpu_abort(cpu, "Raised interrupt while not in I/O function"); + } +} + +const CpusAccel tcg_cpus_icount =3D { + .create_vcpu_thread =3D tcg_start_vcpu_thread, + .kick_vcpu_thread =3D qemu_cpu_kick_rr_cpus, + + .handle_interrupt =3D icount_handle_interrupt, + .get_virtual_clock =3D icount_get, + .get_elapsed_ticks =3D icount_get, +}; diff --git a/accel/tcg/tcg-cpus-mttcg.c b/accel/tcg/tcg-cpus-mttcg.c new file mode 100644 index 0000000000..dac724fc85 --- /dev/null +++ b/accel/tcg/tcg-cpus-mttcg.c @@ -0,0 +1,117 @@ +/* + * QEMU TCG Multi Threaded vCPUs implementation + * + * Copyright (c) 2003-2008 Fabrice Bellard + * Copyright (c) 2014 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "sysemu/tcg.h" +#include "sysemu/replay.h" +#include "qemu/main-loop.h" +#include "qemu/guest-random.h" +#include "exec/exec-all.h" +#include "hw/boards.h" + +#include "tcg-cpus.h" +#include "tcg-cpus-mttcg.h" + +/* + * In the multi-threaded case each vCPU has its own thread. The TLS + * variable current_cpu can be used deep in the code to find the + * current CPUState for a given thread. + */ + +void *tcg_cpu_thread_fn(void *arg) +{ + CPUState *cpu =3D arg; + + assert(tcg_enabled()); + g_assert(!icount_enabled()); + + rcu_register_thread(); + tcg_register_thread(); + + qemu_mutex_lock_iothread(); + qemu_thread_get_self(cpu->thread); + + cpu->thread_id =3D qemu_get_thread_id(); + cpu->can_do_io =3D 1; + current_cpu =3D cpu; + cpu_thread_signal_created(cpu); + qemu_guest_random_seed_thread_part2(cpu->random_seed); + + /* process any pending work */ + cpu->exit_request =3D 1; + + do { + if (cpu_can_run(cpu)) { + int r; + qemu_mutex_unlock_iothread(); + r =3D tcg_cpu_exec(cpu); + qemu_mutex_lock_iothread(); + switch (r) { + case EXCP_DEBUG: + cpu_handle_guest_debug(cpu); + break; + case EXCP_HALTED: + /* + * during start-up the vCPU is reset and the thread is + * kicked several times. If we don't ensure we go back + * to sleep in the halted state we won't cleanly + * start-up when the vCPU is enabled. + * + * cpu->halted should ensure we sleep in wait_io_event + */ + g_assert(cpu->halted); + break; + case EXCP_ATOMIC: + qemu_mutex_unlock_iothread(); + cpu_exec_step_atomic(cpu); + qemu_mutex_lock_iothread(); + default: + /* Ignore everything else? */ + break; + } + } + + qatomic_mb_set(&cpu->exit_request, 0); + qemu_wait_io_event(cpu); + } while (!cpu->unplug || cpu_can_run(cpu)); + + qemu_tcg_destroy_vcpu(cpu); + qemu_mutex_unlock_iothread(); + rcu_unregister_thread(); + return NULL; +} + +static void mttcg_kick_vcpu_thread(CPUState *cpu) +{ + cpu_exit(cpu); +} + +const CpusAccel tcg_cpus_mttcg =3D { + .create_vcpu_thread =3D tcg_start_vcpu_thread, + .kick_vcpu_thread =3D mttcg_kick_vcpu_thread, + + .handle_interrupt =3D tcg_handle_interrupt, +}; diff --git a/accel/tcg/tcg-cpus-rr.c b/accel/tcg/tcg-cpus-rr.c new file mode 100644 index 0000000000..ad50a3765f --- /dev/null +++ b/accel/tcg/tcg-cpus-rr.c @@ -0,0 +1,270 @@ +/* + * QEMU TCG Single Threaded vCPUs implementation + * + * Copyright (c) 2003-2008 Fabrice Bellard + * Copyright (c) 2014 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "sysemu/tcg.h" +#include "sysemu/replay.h" +#include "qemu/main-loop.h" +#include "qemu/guest-random.h" +#include "exec/exec-all.h" +#include "hw/boards.h" + +#include "tcg-cpus.h" +#include "tcg-cpus-rr.h" +#include "tcg-cpus-icount.h" + +/* Kick all RR vCPUs */ +void qemu_cpu_kick_rr_cpus(CPUState *unused) +{ + CPUState *cpu; + + CPU_FOREACH(cpu) { + cpu_exit(cpu); + }; +} + +/* + * TCG vCPU kick timer + * + * The kick timer is responsible for moving single threaded vCPU + * emulation on to the next vCPU. If more than one vCPU is running a + * timer event with force a cpu->exit so the next vCPU can get + * scheduled. + * + * The timer is removed if all vCPUs are idle and restarted again once + * idleness is complete. + */ + +static QEMUTimer *tcg_kick_vcpu_timer; +static CPUState *tcg_current_rr_cpu; + +#define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10) + +static inline int64_t qemu_tcg_next_kick(void) +{ + return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + TCG_KICK_PERIOD; +} + +/* Kick the currently round-robin scheduled vCPU to next */ +static void qemu_cpu_kick_rr_next_cpu(void) +{ + CPUState *cpu; + do { + cpu =3D qatomic_mb_read(&tcg_current_rr_cpu); + if (cpu) { + cpu_exit(cpu); + } + } while (cpu !=3D qatomic_mb_read(&tcg_current_rr_cpu)); +} + +static void kick_tcg_thread(void *opaque) +{ + timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick()); + qemu_cpu_kick_rr_next_cpu(); +} + +static void start_tcg_kick_timer(void) +{ + if (!tcg_kick_vcpu_timer && CPU_NEXT(first_cpu)) { + tcg_kick_vcpu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + kick_tcg_thread, NULL); + } + if (tcg_kick_vcpu_timer && !timer_pending(tcg_kick_vcpu_timer)) { + timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick()); + } +} + +static void stop_tcg_kick_timer(void) +{ + if (tcg_kick_vcpu_timer && timer_pending(tcg_kick_vcpu_timer)) { + timer_del(tcg_kick_vcpu_timer); + } +} + +static void qemu_tcg_rr_wait_io_event(void) +{ + CPUState *cpu; + + while (all_cpu_threads_idle()) { + stop_tcg_kick_timer(); + qemu_cond_wait_iothread(first_cpu->halt_cond); + } + + start_tcg_kick_timer(); + + CPU_FOREACH(cpu) { + qemu_wait_io_event_common(cpu); + } +} + +/* + * Destroy any remaining vCPUs which have been unplugged and have + * finished running + */ +static void deal_with_unplugged_cpus(void) +{ + CPUState *cpu; + + CPU_FOREACH(cpu) { + if (cpu->unplug && !cpu_can_run(cpu)) { + qemu_tcg_destroy_vcpu(cpu); + break; + } + } +} + +/* + * In the single-threaded case each vCPU is simulated in turn. If + * there is more than a single vCPU we create a simple timer to kick + * the vCPU and ensure we don't get stuck in a tight loop in one vCPU. + * This is done explicitly rather than relying on side-effects + * elsewhere. + */ + +void *tcg_rr_cpu_thread_fn(void *arg) +{ + CPUState *cpu =3D arg; + + assert(tcg_enabled()); + rcu_register_thread(); + tcg_register_thread(); + + qemu_mutex_lock_iothread(); + qemu_thread_get_self(cpu->thread); + + cpu->thread_id =3D qemu_get_thread_id(); + cpu->can_do_io =3D 1; + cpu_thread_signal_created(cpu); + qemu_guest_random_seed_thread_part2(cpu->random_seed); + + /* wait for initial kick-off after machine start */ + while (first_cpu->stopped) { + qemu_cond_wait_iothread(first_cpu->halt_cond); + + /* process any pending work */ + CPU_FOREACH(cpu) { + current_cpu =3D cpu; + qemu_wait_io_event_common(cpu); + } + } + + start_tcg_kick_timer(); + + cpu =3D first_cpu; + + /* process any pending work */ + cpu->exit_request =3D 1; + + while (1) { + qemu_mutex_unlock_iothread(); + replay_mutex_lock(); + qemu_mutex_lock_iothread(); + + if (icount_enabled()) { + /* Account partial waits to QEMU_CLOCK_VIRTUAL. */ + icount_account_warp_timer(); + /* + * Run the timers here. This is much more efficient than + * waking up the I/O thread and waiting for completion. + */ + handle_icount_deadline(); + } + + replay_mutex_unlock(); + + if (!cpu) { + cpu =3D first_cpu; + } + + while (cpu && cpu_work_list_empty(cpu) && !cpu->exit_request) { + + qatomic_mb_set(&tcg_current_rr_cpu, cpu); + current_cpu =3D cpu; + + qemu_clock_enable(QEMU_CLOCK_VIRTUAL, + (cpu->singlestep_enabled & SSTEP_NOTIMER) = =3D=3D 0); + + if (cpu_can_run(cpu)) { + int r; + + qemu_mutex_unlock_iothread(); + if (icount_enabled()) { + prepare_icount_for_run(cpu); + } + r =3D tcg_cpu_exec(cpu); + if (icount_enabled()) { + process_icount_data(cpu); + } + qemu_mutex_lock_iothread(); + + if (r =3D=3D EXCP_DEBUG) { + cpu_handle_guest_debug(cpu); + break; + } else if (r =3D=3D EXCP_ATOMIC) { + qemu_mutex_unlock_iothread(); + cpu_exec_step_atomic(cpu); + qemu_mutex_lock_iothread(); + break; + } + } else if (cpu->stop) { + if (cpu->unplug) { + cpu =3D CPU_NEXT(cpu); + } + break; + } + + cpu =3D CPU_NEXT(cpu); + } /* while (cpu && !cpu->exit_request).. */ + + /* Does not need qatomic_mb_set because a spurious wakeup is okay.= */ + qatomic_set(&tcg_current_rr_cpu, NULL); + + if (cpu && cpu->exit_request) { + qatomic_mb_set(&cpu->exit_request, 0); + } + + if (icount_enabled() && all_cpu_threads_idle()) { + /* + * When all cpus are sleeping (e.g in WFI), to avoid a deadlock + * in the main_loop, wake it up in order to start the warp tim= er. + */ + qemu_notify_event(); + } + + qemu_tcg_rr_wait_io_event(); + deal_with_unplugged_cpus(); + } + + rcu_unregister_thread(); + return NULL; +} + +const CpusAccel tcg_cpus_rr =3D { + .create_vcpu_thread =3D tcg_start_vcpu_thread, + .kick_vcpu_thread =3D qemu_cpu_kick_rr_cpus, + + .handle_interrupt =3D tcg_handle_interrupt, +}; diff --git a/accel/tcg/tcg-cpus.c b/accel/tcg/tcg-cpus.c index da1c63d8f6..f2b9bbf99e 100644 --- a/accel/tcg/tcg-cpus.c +++ b/accel/tcg/tcg-cpus.c @@ -1,5 +1,7 @@ /* - * QEMU System Emulator + * QEMU TCG vCPU common functionality + * + * Functionality common to all TCG vCPU variants: mttcg, rr and icount. * * Copyright (c) 2003-2008 Fabrice Bellard * Copyright (c) 2014 Red Hat Inc. @@ -33,436 +35,12 @@ #include "hw/boards.h" =20 #include "tcg-cpus.h" +#include "tcg-cpus-mttcg.h" +#include "tcg-cpus-rr.h" =20 -/* Kick all RR vCPUs */ -static void qemu_cpu_kick_rr_cpus(void) -{ - CPUState *cpu; +/* common functionality among all TCG variants */ =20 - CPU_FOREACH(cpu) { - cpu_exit(cpu); - }; -} - -static void tcg_kick_vcpu_thread(CPUState *cpu) -{ - if (qemu_tcg_mttcg_enabled()) { - cpu_exit(cpu); - } else { - qemu_cpu_kick_rr_cpus(); - } -} - -/* - * TCG vCPU kick timer - * - * The kick timer is responsible for moving single threaded vCPU - * emulation on to the next vCPU. If more than one vCPU is running a - * timer event with force a cpu->exit so the next vCPU can get - * scheduled. - * - * The timer is removed if all vCPUs are idle and restarted again once - * idleness is complete. - */ - -static QEMUTimer *tcg_kick_vcpu_timer; -static CPUState *tcg_current_rr_cpu; - -#define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10) - -static inline int64_t qemu_tcg_next_kick(void) -{ - return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + TCG_KICK_PERIOD; -} - -/* Kick the currently round-robin scheduled vCPU to next */ -static void qemu_cpu_kick_rr_next_cpu(void) -{ - CPUState *cpu; - do { - cpu =3D qatomic_mb_read(&tcg_current_rr_cpu); - if (cpu) { - cpu_exit(cpu); - } - } while (cpu !=3D qatomic_mb_read(&tcg_current_rr_cpu)); -} - -static void kick_tcg_thread(void *opaque) -{ - timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick()); - qemu_cpu_kick_rr_next_cpu(); -} - -static void start_tcg_kick_timer(void) -{ - assert(!mttcg_enabled); - if (!tcg_kick_vcpu_timer && CPU_NEXT(first_cpu)) { - tcg_kick_vcpu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, - kick_tcg_thread, NULL); - } - if (tcg_kick_vcpu_timer && !timer_pending(tcg_kick_vcpu_timer)) { - timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick()); - } -} - -static void stop_tcg_kick_timer(void) -{ - assert(!mttcg_enabled); - if (tcg_kick_vcpu_timer && timer_pending(tcg_kick_vcpu_timer)) { - timer_del(tcg_kick_vcpu_timer); - } -} - -static void qemu_tcg_destroy_vcpu(CPUState *cpu) -{ -} - -static void qemu_tcg_rr_wait_io_event(void) -{ - CPUState *cpu; - - while (all_cpu_threads_idle()) { - stop_tcg_kick_timer(); - qemu_cond_wait_iothread(first_cpu->halt_cond); - } - - start_tcg_kick_timer(); - - CPU_FOREACH(cpu) { - qemu_wait_io_event_common(cpu); - } -} - -static int64_t tcg_get_icount_limit(void) -{ - int64_t deadline; - - if (replay_mode !=3D REPLAY_MODE_PLAY) { - /* - * Include all the timers, because they may need an attention. - * Too long CPU execution may create unnecessary delay in UI. - */ - deadline =3D qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL, - QEMU_TIMER_ATTR_ALL); - /* Check realtime timers, because they help with input processing = */ - deadline =3D qemu_soonest_timeout(deadline, - qemu_clock_deadline_ns_all(QEMU_CLOCK_REALTIME, - QEMU_TIMER_ATTR_ALL)); - - /* - * Maintain prior (possibly buggy) behaviour where if no deadline - * was set (as there is no QEMU_CLOCK_VIRTUAL timer) or it is more= than - * INT32_MAX nanoseconds ahead, we still use INT32_MAX - * nanoseconds. - */ - if ((deadline < 0) || (deadline > INT32_MAX)) { - deadline =3D INT32_MAX; - } - - return icount_round(deadline); - } else { - return replay_get_instructions(); - } -} - -static void notify_aio_contexts(void) -{ - /* Wake up other AioContexts. */ - qemu_clock_notify(QEMU_CLOCK_VIRTUAL); - qemu_clock_run_timers(QEMU_CLOCK_VIRTUAL); -} - -static void handle_icount_deadline(void) -{ - assert(qemu_in_vcpu_thread()); - if (icount_enabled()) { - int64_t deadline =3D qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL, - QEMU_TIMER_ATTR_ALL); - - if (deadline =3D=3D 0) { - notify_aio_contexts(); - } - } -} - -static void prepare_icount_for_run(CPUState *cpu) -{ - if (icount_enabled()) { - int insns_left; - - /* - * These should always be cleared by process_icount_data after - * each vCPU execution. However u16.high can be raised - * asynchronously by cpu_exit/cpu_interrupt/tcg_handle_interrupt - */ - g_assert(cpu_neg(cpu)->icount_decr.u16.low =3D=3D 0); - g_assert(cpu->icount_extra =3D=3D 0); - - cpu->icount_budget =3D tcg_get_icount_limit(); - insns_left =3D MIN(0xffff, cpu->icount_budget); - cpu_neg(cpu)->icount_decr.u16.low =3D insns_left; - cpu->icount_extra =3D cpu->icount_budget - insns_left; - - replay_mutex_lock(); - - if (cpu->icount_budget =3D=3D 0 && replay_has_checkpoint()) { - notify_aio_contexts(); - } - } -} - -static void process_icount_data(CPUState *cpu) -{ - if (icount_enabled()) { - /* Account for executed instructions */ - icount_update(cpu); - - /* Reset the counters */ - cpu_neg(cpu)->icount_decr.u16.low =3D 0; - cpu->icount_extra =3D 0; - cpu->icount_budget =3D 0; - - replay_account_executed_instructions(); - - replay_mutex_unlock(); - } -} - -static int tcg_cpu_exec(CPUState *cpu) -{ - int ret; -#ifdef CONFIG_PROFILER - int64_t ti; -#endif - - assert(tcg_enabled()); -#ifdef CONFIG_PROFILER - ti =3D profile_getclock(); -#endif - cpu_exec_start(cpu); - ret =3D cpu_exec(cpu); - cpu_exec_end(cpu); -#ifdef CONFIG_PROFILER - qatomic_set(&tcg_ctx->prof.cpu_exec_time, - tcg_ctx->prof.cpu_exec_time + profile_getclock() - ti); -#endif - return ret; -} - -/* - * Destroy any remaining vCPUs which have been unplugged and have - * finished running - */ -static void deal_with_unplugged_cpus(void) -{ - CPUState *cpu; - - CPU_FOREACH(cpu) { - if (cpu->unplug && !cpu_can_run(cpu)) { - qemu_tcg_destroy_vcpu(cpu); - cpu_thread_signal_destroyed(cpu); - break; - } - } -} - -/* - * Single-threaded TCG - * - * In the single-threaded case each vCPU is simulated in turn. If - * there is more than a single vCPU we create a simple timer to kick - * the vCPU and ensure we don't get stuck in a tight loop in one vCPU. - * This is done explicitly rather than relying on side-effects - * elsewhere. - */ - -static void *tcg_rr_cpu_thread_fn(void *arg) -{ - CPUState *cpu =3D arg; - - assert(tcg_enabled()); - rcu_register_thread(); - tcg_register_thread(); - - qemu_mutex_lock_iothread(); - qemu_thread_get_self(cpu->thread); - - cpu->thread_id =3D qemu_get_thread_id(); - cpu->can_do_io =3D 1; - cpu_thread_signal_created(cpu); - qemu_guest_random_seed_thread_part2(cpu->random_seed); - - /* wait for initial kick-off after machine start */ - while (first_cpu->stopped) { - qemu_cond_wait_iothread(first_cpu->halt_cond); - - /* process any pending work */ - CPU_FOREACH(cpu) { - current_cpu =3D cpu; - qemu_wait_io_event_common(cpu); - } - } - - start_tcg_kick_timer(); - - cpu =3D first_cpu; - - /* process any pending work */ - cpu->exit_request =3D 1; - - while (1) { - qemu_mutex_unlock_iothread(); - replay_mutex_lock(); - qemu_mutex_lock_iothread(); - /* Account partial waits to QEMU_CLOCK_VIRTUAL. */ - icount_account_warp_timer(); - - /* - * Run the timers here. This is much more efficient than - * waking up the I/O thread and waiting for completion. - */ - handle_icount_deadline(); - - replay_mutex_unlock(); - - if (!cpu) { - cpu =3D first_cpu; - } - - while (cpu && cpu_work_list_empty(cpu) && !cpu->exit_request) { - - qatomic_mb_set(&tcg_current_rr_cpu, cpu); - current_cpu =3D cpu; - - qemu_clock_enable(QEMU_CLOCK_VIRTUAL, - (cpu->singlestep_enabled & SSTEP_NOTIMER) = =3D=3D 0); - - if (cpu_can_run(cpu)) { - int r; - - qemu_mutex_unlock_iothread(); - prepare_icount_for_run(cpu); - - r =3D tcg_cpu_exec(cpu); - - process_icount_data(cpu); - qemu_mutex_lock_iothread(); - - if (r =3D=3D EXCP_DEBUG) { - cpu_handle_guest_debug(cpu); - break; - } else if (r =3D=3D EXCP_ATOMIC) { - qemu_mutex_unlock_iothread(); - cpu_exec_step_atomic(cpu); - qemu_mutex_lock_iothread(); - break; - } - } else if (cpu->stop) { - if (cpu->unplug) { - cpu =3D CPU_NEXT(cpu); - } - break; - } - - cpu =3D CPU_NEXT(cpu); - } /* while (cpu && !cpu->exit_request).. */ - - /* Does not need qatomic_mb_set because a spurious wakeup is okay.= */ - qatomic_set(&tcg_current_rr_cpu, NULL); - - if (cpu && cpu->exit_request) { - qatomic_mb_set(&cpu->exit_request, 0); - } - - if (icount_enabled() && all_cpu_threads_idle()) { - /* - * When all cpus are sleeping (e.g in WFI), to avoid a deadlock - * in the main_loop, wake it up in order to start the warp tim= er. - */ - qemu_notify_event(); - } - - qemu_tcg_rr_wait_io_event(); - deal_with_unplugged_cpus(); - } - - rcu_unregister_thread(); - return NULL; -} - -/* - * Multi-threaded TCG - * - * In the multi-threaded case each vCPU has its own thread. The TLS - * variable current_cpu can be used deep in the code to find the - * current CPUState for a given thread. - */ - -static void *tcg_cpu_thread_fn(void *arg) -{ - CPUState *cpu =3D arg; - - assert(tcg_enabled()); - g_assert(!icount_enabled()); - - rcu_register_thread(); - tcg_register_thread(); - - qemu_mutex_lock_iothread(); - qemu_thread_get_self(cpu->thread); - - cpu->thread_id =3D qemu_get_thread_id(); - cpu->can_do_io =3D 1; - current_cpu =3D cpu; - cpu_thread_signal_created(cpu); - qemu_guest_random_seed_thread_part2(cpu->random_seed); - - /* process any pending work */ - cpu->exit_request =3D 1; - - do { - if (cpu_can_run(cpu)) { - int r; - qemu_mutex_unlock_iothread(); - r =3D tcg_cpu_exec(cpu); - qemu_mutex_lock_iothread(); - switch (r) { - case EXCP_DEBUG: - cpu_handle_guest_debug(cpu); - break; - case EXCP_HALTED: - /* - * during start-up the vCPU is reset and the thread is - * kicked several times. If we don't ensure we go back - * to sleep in the halted state we won't cleanly - * start-up when the vCPU is enabled. - * - * cpu->halted should ensure we sleep in wait_io_event - */ - g_assert(cpu->halted); - break; - case EXCP_ATOMIC: - qemu_mutex_unlock_iothread(); - cpu_exec_step_atomic(cpu); - qemu_mutex_lock_iothread(); - default: - /* Ignore everything else? */ - break; - } - } - - qatomic_mb_set(&cpu->exit_request, 0); - qemu_wait_io_event(cpu); - } while (!cpu->unplug || cpu_can_run(cpu)); - - qemu_tcg_destroy_vcpu(cpu); - cpu_thread_signal_destroyed(cpu); - qemu_mutex_unlock_iothread(); - rcu_unregister_thread(); - return NULL; -} - -static void tcg_start_vcpu_thread(CPUState *cpu) +void tcg_start_vcpu_thread(CPUState *cpu) { char thread_name[VCPU_THREAD_NAME_SIZE]; static QemuCond *single_tcg_halt_cond; @@ -518,29 +96,36 @@ static void tcg_start_vcpu_thread(CPUState *cpu) } } =20 -static int64_t tcg_get_virtual_clock(void) +void qemu_tcg_destroy_vcpu(CPUState *cpu) { - if (icount_enabled()) { - return icount_get(); - } - return cpu_get_clock(); + cpu_thread_signal_destroyed(cpu); } =20 -static int64_t tcg_get_elapsed_ticks(void) +int tcg_cpu_exec(CPUState *cpu) { - if (icount_enabled()) { - return icount_get(); - } - return cpu_get_ticks(); + int ret; +#ifdef CONFIG_PROFILER + int64_t ti; +#endif + assert(tcg_enabled()); +#ifdef CONFIG_PROFILER + ti =3D profile_getclock(); +#endif + cpu_exec_start(cpu); + ret =3D cpu_exec(cpu); + cpu_exec_end(cpu); +#ifdef CONFIG_PROFILER + qatomic_set(&tcg_ctx->prof.cpu_exec_time, + tcg_ctx->prof.cpu_exec_time + profile_getclock() - ti); +#endif + return ret; } =20 /* mask must never be zero, except for A20 change call */ -static void tcg_handle_interrupt(CPUState *cpu, int mask) +void tcg_handle_interrupt(CPUState *cpu, int mask) { - int old_mask; g_assert(qemu_mutex_iothread_locked()); =20 - old_mask =3D cpu->interrupt_request; cpu->interrupt_request |=3D mask; =20 /* @@ -551,20 +136,5 @@ static void tcg_handle_interrupt(CPUState *cpu, int ma= sk) qemu_cpu_kick(cpu); } else { qatomic_set(&cpu_neg(cpu)->icount_decr.u16.high, -1); - if (icount_enabled() && - !cpu->can_do_io - && (mask & ~old_mask) !=3D 0) { - cpu_abort(cpu, "Raised interrupt while not in I/O function"); - } } } - -const CpusAccel tcg_cpus =3D { - .create_vcpu_thread =3D tcg_start_vcpu_thread, - .kick_vcpu_thread =3D tcg_kick_vcpu_thread, - - .handle_interrupt =3D tcg_handle_interrupt, - - .get_virtual_clock =3D tcg_get_virtual_clock, - .get_elapsed_ticks =3D tcg_get_elapsed_ticks, -}; diff --git a/softmmu/icount.c b/softmmu/icount.c index 020a201a01..dbcd8c3594 100644 --- a/softmmu/icount.c +++ b/softmmu/icount.c @@ -396,7 +396,7 @@ void icount_start_warp_timer(void) =20 void icount_account_warp_timer(void) { - if (!icount_enabled() || !icount_sleep) { + if (!icount_sleep) { return; } =20 diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 19b9343d5b..f39aab0a0c 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -12,4 +12,11 @@ tcg_ss.add(when: 'CONFIG_SOFTMMU', if_false: files('user= -exec-stub.c')) tcg_ss.add(when: 'CONFIG_PLUGIN', if_true: [files('plugin-gen.c'), libdl]) specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss) =20 -specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files('tc= g-all.c', 'cputlb.c', 'tcg-cpus.c')) +specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files( + 'tcg-all.c', + 'cputlb.c', + 'tcg-cpus.c', + 'tcg-cpus-mttcg.c', + 'tcg-cpus-icount.c', + 'tcg-cpus-rr.c' +)) --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 10 Dec 2020 04:24:20 -0800 (PST) Received: from localhost ([::1]:39498 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKza-0005vm-Ue for importer@patchew.org; Thu, 10 Dec 2020 07:24:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56320) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoF-0001qr-JL for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:12:35 -0500 Received: from mx2.suse.de ([195.135.220.15]:46988) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoC-0006PP-B2 for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:12:35 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 060E7AD4D; Thu, 10 Dec 2020 12:12:31 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 02/32] accel/tcg: split tcg_start_vcpu_thread Date: Thu, 10 Dec 2020 13:11:56 +0100 Message-Id: <20201210121226.19822-3-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" after the initial split into 3 tcg variants, we proceed to also split tcg_start_vcpu_thread. We actually split it in 2 this time, since the icount variant just uses the round robin function. Suggested-by: Richard Henderson Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson --- accel/tcg/tcg-cpus-mttcg.h | 21 -------------- accel/tcg/tcg-cpus-rr.h | 3 +- accel/tcg/tcg-cpus.h | 1 - accel/tcg/tcg-all.c | 5 ++++ accel/tcg/tcg-cpus-icount.c | 2 +- accel/tcg/tcg-cpus-mttcg.c | 29 +++++++++++++++++-- accel/tcg/tcg-cpus-rr.c | 39 +++++++++++++++++++++++-- accel/tcg/tcg-cpus.c | 58 ------------------------------------- 8 files changed, 71 insertions(+), 87 deletions(-) delete mode 100644 accel/tcg/tcg-cpus-mttcg.h diff --git a/accel/tcg/tcg-cpus-mttcg.h b/accel/tcg/tcg-cpus-mttcg.h deleted file mode 100644 index d1bd771f49..0000000000 --- a/accel/tcg/tcg-cpus-mttcg.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * QEMU TCG Multi Threaded vCPUs implementation - * - * Copyright 2020 SUSE LLC - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - */ - -#ifndef TCG_CPUS_MTTCG_H -#define TCG_CPUS_MTTCG_H - -/* - * In the multi-threaded case each vCPU has its own thread. The TLS - * variable current_cpu can be used deep in the code to find the - * current CPUState for a given thread. - */ - -void *tcg_cpu_thread_fn(void *arg); - -#endif /* TCG_CPUS_MTTCG_H */ diff --git a/accel/tcg/tcg-cpus-rr.h b/accel/tcg/tcg-cpus-rr.h index 1936fd16ab..2e5943eda9 100644 --- a/accel/tcg/tcg-cpus-rr.h +++ b/accel/tcg/tcg-cpus-rr.h @@ -15,6 +15,7 @@ /* Kick all RR vCPUs. */ void qemu_cpu_kick_rr_cpus(CPUState *unused); =20 -void *tcg_rr_cpu_thread_fn(void *arg); +/* start the round robin vcpu thread */ +void rr_start_vcpu_thread(CPUState *cpu); =20 #endif /* TCG_CPUS_RR_H */ diff --git a/accel/tcg/tcg-cpus.h b/accel/tcg/tcg-cpus.h index 279ba72e1f..b7ca954e13 100644 --- a/accel/tcg/tcg-cpus.h +++ b/accel/tcg/tcg-cpus.h @@ -18,7 +18,6 @@ extern const CpusAccel tcg_cpus_mttcg; extern const CpusAccel tcg_cpus_icount; extern const CpusAccel tcg_cpus_rr; =20 -void tcg_start_vcpu_thread(CPUState *cpu); void qemu_tcg_destroy_vcpu(CPUState *cpu); int tcg_cpu_exec(CPUState *cpu); void tcg_handle_interrupt(CPUState *cpu, int mask); diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index e42a028043..1ac0b76515 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -105,6 +105,11 @@ static int tcg_init(MachineState *ms) tcg_exec_init(s->tb_size * 1024 * 1024); mttcg_enabled =3D s->mttcg_enabled; =20 + /* + * Initialize TCG regions + */ + tcg_region_init(); + if (mttcg_enabled) { cpus_register_accel(&tcg_cpus_mttcg); } else if (icount_enabled()) { diff --git a/accel/tcg/tcg-cpus-icount.c b/accel/tcg/tcg-cpus-icount.c index d3af3afb6d..82dbe2cacf 100644 --- a/accel/tcg/tcg-cpus-icount.c +++ b/accel/tcg/tcg-cpus-icount.c @@ -138,7 +138,7 @@ static void icount_handle_interrupt(CPUState *cpu, int = mask) } =20 const CpusAccel tcg_cpus_icount =3D { - .create_vcpu_thread =3D tcg_start_vcpu_thread, + .create_vcpu_thread =3D rr_start_vcpu_thread, .kick_vcpu_thread =3D qemu_cpu_kick_rr_cpus, =20 .handle_interrupt =3D icount_handle_interrupt, diff --git a/accel/tcg/tcg-cpus-mttcg.c b/accel/tcg/tcg-cpus-mttcg.c index dac724fc85..f2b892a380 100644 --- a/accel/tcg/tcg-cpus-mttcg.c +++ b/accel/tcg/tcg-cpus-mttcg.c @@ -33,7 +33,6 @@ #include "hw/boards.h" =20 #include "tcg-cpus.h" -#include "tcg-cpus-mttcg.h" =20 /* * In the multi-threaded case each vCPU has its own thread. The TLS @@ -41,7 +40,7 @@ * current CPUState for a given thread. */ =20 -void *tcg_cpu_thread_fn(void *arg) +static void *tcg_cpu_thread_fn(void *arg) { CPUState *cpu =3D arg; =20 @@ -109,8 +108,32 @@ static void mttcg_kick_vcpu_thread(CPUState *cpu) cpu_exit(cpu); } =20 +static void mttcg_start_vcpu_thread(CPUState *cpu) +{ + char thread_name[VCPU_THREAD_NAME_SIZE]; + + g_assert(tcg_enabled()); + + parallel_cpus =3D (current_machine->smp.max_cpus > 1); + + cpu->thread =3D g_malloc0(sizeof(QemuThread)); + cpu->halt_cond =3D g_malloc0(sizeof(QemuCond)); + qemu_cond_init(cpu->halt_cond); + + /* create a thread per vCPU with TCG (MTTCG) */ + snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "CPU %d/TCG", + cpu->cpu_index); + + qemu_thread_create(cpu->thread, thread_name, tcg_cpu_thread_fn, + cpu, QEMU_THREAD_JOINABLE); + +#ifdef _WIN32 + cpu->hThread =3D qemu_thread_get_handle(cpu->thread); +#endif +} + const CpusAccel tcg_cpus_mttcg =3D { - .create_vcpu_thread =3D tcg_start_vcpu_thread, + .create_vcpu_thread =3D mttcg_start_vcpu_thread, .kick_vcpu_thread =3D mttcg_kick_vcpu_thread, =20 .handle_interrupt =3D tcg_handle_interrupt, diff --git a/accel/tcg/tcg-cpus-rr.c b/accel/tcg/tcg-cpus-rr.c index ad50a3765f..f3b262bec7 100644 --- a/accel/tcg/tcg-cpus-rr.c +++ b/accel/tcg/tcg-cpus-rr.c @@ -144,7 +144,7 @@ static void deal_with_unplugged_cpus(void) * elsewhere. */ =20 -void *tcg_rr_cpu_thread_fn(void *arg) +static void *tcg_rr_cpu_thread_fn(void *arg) { CPUState *cpu =3D arg; =20 @@ -262,8 +262,43 @@ void *tcg_rr_cpu_thread_fn(void *arg) return NULL; } =20 +void rr_start_vcpu_thread(CPUState *cpu) +{ + char thread_name[VCPU_THREAD_NAME_SIZE]; + static QemuCond *single_tcg_halt_cond; + static QemuThread *single_tcg_cpu_thread; + + g_assert(tcg_enabled()); + parallel_cpus =3D false; + + if (!single_tcg_cpu_thread) { + cpu->thread =3D g_malloc0(sizeof(QemuThread)); + cpu->halt_cond =3D g_malloc0(sizeof(QemuCond)); + qemu_cond_init(cpu->halt_cond); + + /* share a single thread for all cpus with TCG */ + snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "ALL CPUs/TCG"); + qemu_thread_create(cpu->thread, thread_name, + tcg_rr_cpu_thread_fn, + cpu, QEMU_THREAD_JOINABLE); + + single_tcg_halt_cond =3D cpu->halt_cond; + single_tcg_cpu_thread =3D cpu->thread; +#ifdef _WIN32 + cpu->hThread =3D qemu_thread_get_handle(cpu->thread); +#endif + } else { + /* we share the thread */ + cpu->thread =3D single_tcg_cpu_thread; + cpu->halt_cond =3D single_tcg_halt_cond; + cpu->thread_id =3D first_cpu->thread_id; + cpu->can_do_io =3D 1; + cpu->created =3D true; + } +} + const CpusAccel tcg_cpus_rr =3D { - .create_vcpu_thread =3D tcg_start_vcpu_thread, + .create_vcpu_thread =3D rr_start_vcpu_thread, .kick_vcpu_thread =3D qemu_cpu_kick_rr_cpus, =20 .handle_interrupt =3D tcg_handle_interrupt, diff --git a/accel/tcg/tcg-cpus.c b/accel/tcg/tcg-cpus.c index f2b9bbf99e..86fd09545a 100644 --- a/accel/tcg/tcg-cpus.c +++ b/accel/tcg/tcg-cpus.c @@ -35,67 +35,9 @@ #include "hw/boards.h" =20 #include "tcg-cpus.h" -#include "tcg-cpus-mttcg.h" -#include "tcg-cpus-rr.h" =20 /* common functionality among all TCG variants */ =20 -void tcg_start_vcpu_thread(CPUState *cpu) -{ - char thread_name[VCPU_THREAD_NAME_SIZE]; - static QemuCond *single_tcg_halt_cond; - static QemuThread *single_tcg_cpu_thread; - static int tcg_region_inited; - - assert(tcg_enabled()); - /* - * Initialize TCG regions--once. Now is a good time, because: - * (1) TCG's init context, prologue and target globals have been set u= p. - * (2) qemu_tcg_mttcg_enabled() works now (TCG init code runs before t= he - * -accel flag is processed, so the check doesn't work then). - */ - if (!tcg_region_inited) { - tcg_region_inited =3D 1; - tcg_region_init(); - parallel_cpus =3D qemu_tcg_mttcg_enabled() && current_machine->smp= .max_cpus > 1; - } - - if (qemu_tcg_mttcg_enabled() || !single_tcg_cpu_thread) { - cpu->thread =3D g_malloc0(sizeof(QemuThread)); - cpu->halt_cond =3D g_malloc0(sizeof(QemuCond)); - qemu_cond_init(cpu->halt_cond); - - if (qemu_tcg_mttcg_enabled()) { - /* create a thread per vCPU with TCG (MTTCG) */ - snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "CPU %d/TCG", - cpu->cpu_index); - - qemu_thread_create(cpu->thread, thread_name, tcg_cpu_thread_fn, - cpu, QEMU_THREAD_JOINABLE); - - } else { - /* share a single thread for all cpus with TCG */ - snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "ALL CPUs/TCG"); - qemu_thread_create(cpu->thread, thread_name, - tcg_rr_cpu_thread_fn, - cpu, QEMU_THREAD_JOINABLE); - - single_tcg_halt_cond =3D cpu->halt_cond; - single_tcg_cpu_thread =3D cpu->thread; - } -#ifdef _WIN32 - cpu->hThread =3D qemu_thread_get_handle(cpu->thread); -#endif - } else { - /* For non-MTTCG cases we share the thread */ - cpu->thread =3D single_tcg_cpu_thread; - cpu->halt_cond =3D single_tcg_halt_cond; - cpu->thread_id =3D first_cpu->thread_id; - cpu->can_do_io =3D 1; - cpu->created =3D true; - } -} - void qemu_tcg_destroy_vcpu(CPUState *cpu) { cpu_thread_signal_destroyed(cpu); --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607603212; cv=none; d=zohomail.com; s=zohoarc; b=dKKaou4WFyQV+emEL0FUTBgRHcBjF3Zbho9eHgidb4lEgZ1flGcB51giV/A7E4f3SnRcrS3JOKfE62GbvCmkya6xQlE/Qawz8lgugJMJv4rdiR2nnSo0xMEsJWn3oiJP6oLKyCIgOgbPT6TiMa9f7Yzzjm+/tHpr/BTsizGv0FA= ARC-Message-Signature: i=1; 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Thu, 10 Dec 2020 07:26:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56342) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoG-0001tN-N6 for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:12:36 -0500 Received: from mx2.suse.de ([195.135.220.15]:47044) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoD-0006Pb-IP for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:12:36 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 2865CAD45; Thu, 10 Dec 2020 12:12:32 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 03/32] accel/tcg: rename tcg-cpus functions to match module name Date: Thu, 10 Dec 2020 13:11:57 +0100 Message-Id: <20201210121226.19822-4-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; 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Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Claudio Fontana Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- accel/tcg/tcg-cpus-icount.h | 6 +-- accel/tcg/tcg-cpus-rr.h | 2 +- accel/tcg/tcg-cpus.h | 6 +-- accel/tcg/tcg-cpus-icount.c | 24 ++++++------ accel/tcg/tcg-cpus-mttcg.c | 10 ++--- accel/tcg/tcg-cpus-rr.c | 74 ++++++++++++++++++------------------- accel/tcg/tcg-cpus.c | 6 +-- 7 files changed, 64 insertions(+), 64 deletions(-) diff --git a/accel/tcg/tcg-cpus-icount.h b/accel/tcg/tcg-cpus-icount.h index cbcf76b413..b695939dfa 100644 --- a/accel/tcg/tcg-cpus-icount.h +++ b/accel/tcg/tcg-cpus-icount.h @@ -10,8 +10,8 @@ #ifndef TCG_CPUS_ICOUNT_H #define TCG_CPUS_ICOUNT_H =20 -void handle_icount_deadline(void); -void prepare_icount_for_run(CPUState *cpu); -void process_icount_data(CPUState *cpu); +void icount_handle_deadline(void); +void icount_prepare_for_run(CPUState *cpu); +void icount_process_data(CPUState *cpu); =20 #endif /* TCG_CPUS_ICOUNT_H */ diff --git a/accel/tcg/tcg-cpus-rr.h b/accel/tcg/tcg-cpus-rr.h index 2e5943eda9..54f6ae6e86 100644 --- a/accel/tcg/tcg-cpus-rr.h +++ b/accel/tcg/tcg-cpus-rr.h @@ -13,7 +13,7 @@ #define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10) =20 /* Kick all RR vCPUs. */ -void qemu_cpu_kick_rr_cpus(CPUState *unused); +void rr_kick_vcpu_thread(CPUState *unused); =20 /* start the round robin vcpu thread */ void rr_start_vcpu_thread(CPUState *cpu); diff --git a/accel/tcg/tcg-cpus.h b/accel/tcg/tcg-cpus.h index b7ca954e13..d6893a32f8 100644 --- a/accel/tcg/tcg-cpus.h +++ b/accel/tcg/tcg-cpus.h @@ -18,8 +18,8 @@ extern const CpusAccel tcg_cpus_mttcg; extern const CpusAccel tcg_cpus_icount; extern const CpusAccel tcg_cpus_rr; =20 -void qemu_tcg_destroy_vcpu(CPUState *cpu); -int tcg_cpu_exec(CPUState *cpu); -void tcg_handle_interrupt(CPUState *cpu, int mask); +void tcg_cpus_destroy(CPUState *cpu); +int tcg_cpus_exec(CPUState *cpu); +void tcg_cpus_handle_interrupt(CPUState *cpu, int mask); =20 #endif /* TCG_CPUS_H */ diff --git a/accel/tcg/tcg-cpus-icount.c b/accel/tcg/tcg-cpus-icount.c index 82dbe2cacf..9f45432275 100644 --- a/accel/tcg/tcg-cpus-icount.c +++ b/accel/tcg/tcg-cpus-icount.c @@ -36,7 +36,7 @@ #include "tcg-cpus-icount.h" #include "tcg-cpus-rr.h" =20 -static int64_t tcg_get_icount_limit(void) +static int64_t icount_get_limit(void) { int64_t deadline; =20 @@ -68,37 +68,37 @@ static int64_t tcg_get_icount_limit(void) } } =20 -static void notify_aio_contexts(void) +static void icount_notify_aio_contexts(void) { /* Wake up other AioContexts. */ qemu_clock_notify(QEMU_CLOCK_VIRTUAL); qemu_clock_run_timers(QEMU_CLOCK_VIRTUAL); } =20 -void handle_icount_deadline(void) +void icount_handle_deadline(void) { assert(qemu_in_vcpu_thread()); int64_t deadline =3D qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL, QEMU_TIMER_ATTR_ALL); =20 if (deadline =3D=3D 0) { - notify_aio_contexts(); + icount_notify_aio_contexts(); } } =20 -void prepare_icount_for_run(CPUState *cpu) +void icount_prepare_for_run(CPUState *cpu) { int insns_left; =20 /* - * These should always be cleared by process_icount_data after + * These should always be cleared by icount_process_data after * each vCPU execution. However u16.high can be raised - * asynchronously by cpu_exit/cpu_interrupt/tcg_handle_interrupt + * asynchronously by cpu_exit/cpu_interrupt/tcg_cpus_handle_interrupt */ g_assert(cpu_neg(cpu)->icount_decr.u16.low =3D=3D 0); g_assert(cpu->icount_extra =3D=3D 0); =20 - cpu->icount_budget =3D tcg_get_icount_limit(); + cpu->icount_budget =3D icount_get_limit(); insns_left =3D MIN(0xffff, cpu->icount_budget); cpu_neg(cpu)->icount_decr.u16.low =3D insns_left; cpu->icount_extra =3D cpu->icount_budget - insns_left; @@ -106,11 +106,11 @@ void prepare_icount_for_run(CPUState *cpu) replay_mutex_lock(); =20 if (cpu->icount_budget =3D=3D 0 && replay_has_checkpoint()) { - notify_aio_contexts(); + icount_notify_aio_contexts(); } } =20 -void process_icount_data(CPUState *cpu) +void icount_process_data(CPUState *cpu) { /* Account for executed instructions */ icount_update(cpu); @@ -129,7 +129,7 @@ static void icount_handle_interrupt(CPUState *cpu, int = mask) { int old_mask =3D cpu->interrupt_request; =20 - tcg_handle_interrupt(cpu, mask); + tcg_cpus_handle_interrupt(cpu, mask); if (qemu_cpu_is_self(cpu) && !cpu->can_do_io && (mask & ~old_mask) !=3D 0) { @@ -139,7 +139,7 @@ static void icount_handle_interrupt(CPUState *cpu, int = mask) =20 const CpusAccel tcg_cpus_icount =3D { .create_vcpu_thread =3D rr_start_vcpu_thread, - .kick_vcpu_thread =3D qemu_cpu_kick_rr_cpus, + .kick_vcpu_thread =3D rr_kick_vcpu_thread, =20 .handle_interrupt =3D icount_handle_interrupt, .get_virtual_clock =3D icount_get, diff --git a/accel/tcg/tcg-cpus-mttcg.c b/accel/tcg/tcg-cpus-mttcg.c index f2b892a380..9c3767d260 100644 --- a/accel/tcg/tcg-cpus-mttcg.c +++ b/accel/tcg/tcg-cpus-mttcg.c @@ -40,7 +40,7 @@ * current CPUState for a given thread. */ =20 -static void *tcg_cpu_thread_fn(void *arg) +static void *mttcg_cpu_thread_fn(void *arg) { CPUState *cpu =3D arg; =20 @@ -66,7 +66,7 @@ static void *tcg_cpu_thread_fn(void *arg) if (cpu_can_run(cpu)) { int r; qemu_mutex_unlock_iothread(); - r =3D tcg_cpu_exec(cpu); + r =3D tcg_cpus_exec(cpu); qemu_mutex_lock_iothread(); switch (r) { case EXCP_DEBUG: @@ -97,7 +97,7 @@ static void *tcg_cpu_thread_fn(void *arg) qemu_wait_io_event(cpu); } while (!cpu->unplug || cpu_can_run(cpu)); =20 - qemu_tcg_destroy_vcpu(cpu); + tcg_cpus_destroy(cpu); qemu_mutex_unlock_iothread(); rcu_unregister_thread(); return NULL; @@ -124,7 +124,7 @@ static void mttcg_start_vcpu_thread(CPUState *cpu) snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "CPU %d/TCG", cpu->cpu_index); =20 - qemu_thread_create(cpu->thread, thread_name, tcg_cpu_thread_fn, + qemu_thread_create(cpu->thread, thread_name, mttcg_cpu_thread_fn, cpu, QEMU_THREAD_JOINABLE); =20 #ifdef _WIN32 @@ -136,5 +136,5 @@ const CpusAccel tcg_cpus_mttcg =3D { .create_vcpu_thread =3D mttcg_start_vcpu_thread, .kick_vcpu_thread =3D mttcg_kick_vcpu_thread, =20 - .handle_interrupt =3D tcg_handle_interrupt, + .handle_interrupt =3D tcg_cpus_handle_interrupt, }; diff --git a/accel/tcg/tcg-cpus-rr.c b/accel/tcg/tcg-cpus-rr.c index f3b262bec7..0181d2e4eb 100644 --- a/accel/tcg/tcg-cpus-rr.c +++ b/accel/tcg/tcg-cpus-rr.c @@ -37,7 +37,7 @@ #include "tcg-cpus-icount.h" =20 /* Kick all RR vCPUs */ -void qemu_cpu_kick_rr_cpus(CPUState *unused) +void rr_kick_vcpu_thread(CPUState *unused) { CPUState *cpu; =20 @@ -58,62 +58,62 @@ void qemu_cpu_kick_rr_cpus(CPUState *unused) * idleness is complete. */ =20 -static QEMUTimer *tcg_kick_vcpu_timer; -static CPUState *tcg_current_rr_cpu; +static QEMUTimer *rr_kick_vcpu_timer; +static CPUState *rr_current_cpu; =20 #define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10) =20 -static inline int64_t qemu_tcg_next_kick(void) +static inline int64_t rr_next_kick_time(void) { return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + TCG_KICK_PERIOD; } =20 /* Kick the currently round-robin scheduled vCPU to next */ -static void qemu_cpu_kick_rr_next_cpu(void) +static void rr_kick_next_cpu(void) { CPUState *cpu; do { - cpu =3D qatomic_mb_read(&tcg_current_rr_cpu); + cpu =3D qatomic_mb_read(&rr_current_cpu); if (cpu) { cpu_exit(cpu); } - } while (cpu !=3D qatomic_mb_read(&tcg_current_rr_cpu)); + } while (cpu !=3D qatomic_mb_read(&rr_current_cpu)); } =20 -static void kick_tcg_thread(void *opaque) +static void rr_kick_thread(void *opaque) { - timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick()); - qemu_cpu_kick_rr_next_cpu(); + timer_mod(rr_kick_vcpu_timer, rr_next_kick_time()); + rr_kick_next_cpu(); } =20 -static void start_tcg_kick_timer(void) +static void rr_start_kick_timer(void) { - if (!tcg_kick_vcpu_timer && CPU_NEXT(first_cpu)) { - tcg_kick_vcpu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, - kick_tcg_thread, NULL); + if (!rr_kick_vcpu_timer && CPU_NEXT(first_cpu)) { + rr_kick_vcpu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + rr_kick_thread, NULL); } - if (tcg_kick_vcpu_timer && !timer_pending(tcg_kick_vcpu_timer)) { - timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick()); + if (rr_kick_vcpu_timer && !timer_pending(rr_kick_vcpu_timer)) { + timer_mod(rr_kick_vcpu_timer, rr_next_kick_time()); } } =20 -static void stop_tcg_kick_timer(void) +static void rr_stop_kick_timer(void) { - if (tcg_kick_vcpu_timer && timer_pending(tcg_kick_vcpu_timer)) { - timer_del(tcg_kick_vcpu_timer); + if (rr_kick_vcpu_timer && timer_pending(rr_kick_vcpu_timer)) { + timer_del(rr_kick_vcpu_timer); } } =20 -static void qemu_tcg_rr_wait_io_event(void) +static void rr_wait_io_event(void) { CPUState *cpu; =20 while (all_cpu_threads_idle()) { - stop_tcg_kick_timer(); + rr_stop_kick_timer(); qemu_cond_wait_iothread(first_cpu->halt_cond); } =20 - start_tcg_kick_timer(); + rr_start_kick_timer(); =20 CPU_FOREACH(cpu) { qemu_wait_io_event_common(cpu); @@ -124,13 +124,13 @@ static void qemu_tcg_rr_wait_io_event(void) * Destroy any remaining vCPUs which have been unplugged and have * finished running */ -static void deal_with_unplugged_cpus(void) +static void rr_deal_with_unplugged_cpus(void) { CPUState *cpu; =20 CPU_FOREACH(cpu) { if (cpu->unplug && !cpu_can_run(cpu)) { - qemu_tcg_destroy_vcpu(cpu); + tcg_cpus_destroy(cpu); break; } } @@ -144,7 +144,7 @@ static void deal_with_unplugged_cpus(void) * elsewhere. */ =20 -static void *tcg_rr_cpu_thread_fn(void *arg) +static void *rr_cpu_thread_fn(void *arg) { CPUState *cpu =3D arg; =20 @@ -171,7 +171,7 @@ static void *tcg_rr_cpu_thread_fn(void *arg) } } =20 - start_tcg_kick_timer(); + rr_start_kick_timer(); =20 cpu =3D first_cpu; =20 @@ -190,7 +190,7 @@ static void *tcg_rr_cpu_thread_fn(void *arg) * Run the timers here. This is much more efficient than * waking up the I/O thread and waiting for completion. */ - handle_icount_deadline(); + icount_handle_deadline(); } =20 replay_mutex_unlock(); @@ -201,7 +201,7 @@ static void *tcg_rr_cpu_thread_fn(void *arg) =20 while (cpu && cpu_work_list_empty(cpu) && !cpu->exit_request) { =20 - qatomic_mb_set(&tcg_current_rr_cpu, cpu); + qatomic_mb_set(&rr_current_cpu, cpu); current_cpu =3D cpu; =20 qemu_clock_enable(QEMU_CLOCK_VIRTUAL, @@ -212,11 +212,11 @@ static void *tcg_rr_cpu_thread_fn(void *arg) =20 qemu_mutex_unlock_iothread(); if (icount_enabled()) { - prepare_icount_for_run(cpu); + icount_prepare_for_run(cpu); } - r =3D tcg_cpu_exec(cpu); + r =3D tcg_cpus_exec(cpu); if (icount_enabled()) { - process_icount_data(cpu); + icount_process_data(cpu); } qemu_mutex_lock_iothread(); =20 @@ -240,7 +240,7 @@ static void *tcg_rr_cpu_thread_fn(void *arg) } /* while (cpu && !cpu->exit_request).. */ =20 /* Does not need qatomic_mb_set because a spurious wakeup is okay.= */ - qatomic_set(&tcg_current_rr_cpu, NULL); + qatomic_set(&rr_current_cpu, NULL); =20 if (cpu && cpu->exit_request) { qatomic_mb_set(&cpu->exit_request, 0); @@ -254,8 +254,8 @@ static void *tcg_rr_cpu_thread_fn(void *arg) qemu_notify_event(); } =20 - qemu_tcg_rr_wait_io_event(); - deal_with_unplugged_cpus(); + rr_wait_io_event(); + rr_deal_with_unplugged_cpus(); } =20 rcu_unregister_thread(); @@ -279,7 +279,7 @@ void rr_start_vcpu_thread(CPUState *cpu) /* share a single thread for all cpus with TCG */ snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "ALL CPUs/TCG"); qemu_thread_create(cpu->thread, thread_name, - tcg_rr_cpu_thread_fn, + rr_cpu_thread_fn, cpu, QEMU_THREAD_JOINABLE); =20 single_tcg_halt_cond =3D cpu->halt_cond; @@ -299,7 +299,7 @@ void rr_start_vcpu_thread(CPUState *cpu) =20 const CpusAccel tcg_cpus_rr =3D { .create_vcpu_thread =3D rr_start_vcpu_thread, - .kick_vcpu_thread =3D qemu_cpu_kick_rr_cpus, + .kick_vcpu_thread =3D rr_kick_vcpu_thread, =20 - .handle_interrupt =3D tcg_handle_interrupt, + .handle_interrupt =3D tcg_cpus_handle_interrupt, }; diff --git a/accel/tcg/tcg-cpus.c b/accel/tcg/tcg-cpus.c index 86fd09545a..e335f9f155 100644 --- a/accel/tcg/tcg-cpus.c +++ b/accel/tcg/tcg-cpus.c @@ -38,12 +38,12 @@ =20 /* common functionality among all TCG variants */ =20 -void qemu_tcg_destroy_vcpu(CPUState *cpu) +void tcg_cpus_destroy(CPUState *cpu) { cpu_thread_signal_destroyed(cpu); } =20 -int tcg_cpu_exec(CPUState *cpu) +int tcg_cpus_exec(CPUState *cpu) { int ret; #ifdef CONFIG_PROFILER @@ -64,7 +64,7 @@ int tcg_cpu_exec(CPUState *cpu) } =20 /* mask must never be zero, except for A20 change call */ -void tcg_handle_interrupt(CPUState *cpu, int mask) +void tcg_cpus_handle_interrupt(CPUState *cpu, int mask) { g_assert(qemu_mutex_iothread_locked()); =20 --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Thu, 10 Dec 2020 04:29:24 -0800 (PST) Received: from localhost ([::1]:53946 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knL4V-0003O9-1M for importer@patchew.org; Thu, 10 Dec 2020 07:29:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56398) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoJ-0001zX-CW for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:12:39 -0500 Received: from mx2.suse.de ([195.135.220.15]:47076) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoE-0006QR-DC for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:12:39 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 2093EAD5C; Thu, 10 Dec 2020 12:12:33 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 04/32] i386: move kvm accel files into kvm/ Date: Thu, 10 Dec 2020 13:11:58 +0100 Message-Id: <20201210121226.19822-5-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; 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Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e --- meson.build | 1 + target/i386/cpu.h | 2 +- target/i386/{ =3D> kvm}/hyperv-proto.h | 0 target/i386/{ =3D> kvm}/hyperv.h | 0 target/i386/{ =3D> kvm}/kvm_i386.h | 0 target/i386/kvm/trace.h | 1 + hw/i386/fw_cfg.c | 2 +- hw/i386/intel_iommu.c | 2 +- hw/i386/kvm/apic.c | 2 +- hw/i386/kvm/clock.c | 2 +- hw/i386/microvm.c | 2 +- hw/i386/pc.c | 2 +- hw/i386/x86.c | 2 +- target/i386/cpu.c | 2 +- target/i386/helper.c | 2 +- target/i386/{ =3D> kvm}/hyperv-stub.c | 0 target/i386/{ =3D> kvm}/hyperv.c | 0 target/i386/{ =3D> kvm}/kvm-stub.c | 0 target/i386/{ =3D> kvm}/kvm.c | 0 target/i386/machine.c | 4 ++-- MAINTAINERS | 2 +- target/i386/kvm/meson.build | 3 +++ target/i386/kvm/trace-events | 7 +++++++ target/i386/meson.build | 4 +--- target/i386/trace-events | 6 ------ 25 files changed, 26 insertions(+), 22 deletions(-) rename target/i386/{ =3D> kvm}/hyperv-proto.h (100%) rename target/i386/{ =3D> kvm}/hyperv.h (100%) rename target/i386/{ =3D> kvm}/kvm_i386.h (100%) create mode 100644 target/i386/kvm/trace.h rename target/i386/{ =3D> kvm}/hyperv-stub.c (100%) rename target/i386/{ =3D> kvm}/hyperv.c (100%) rename target/i386/{ =3D> kvm}/kvm-stub.c (100%) rename target/i386/{ =3D> kvm}/kvm.c (100%) create mode 100644 target/i386/kvm/meson.build create mode 100644 target/i386/kvm/trace-events diff --git a/meson.build b/meson.build index 732b29a1f3..d3f4aeeb32 100644 --- a/meson.build +++ b/meson.build @@ -1467,6 +1467,7 @@ trace_events_subdirs +=3D [ 'target/arm', 'target/hppa', 'target/i386', + 'target/i386/kvm', 'target/mips', 'target/ppc', 'target/riscv', diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 88e8586f8f..9ecda75aec 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -22,7 +22,7 @@ =20 #include "sysemu/tcg.h" #include "cpu-qom.h" -#include "hyperv-proto.h" +#include "kvm/hyperv-proto.h" #include "exec/cpu-defs.h" #include "qapi/qapi-types-common.h" =20 diff --git a/target/i386/hyperv-proto.h b/target/i386/kvm/hyperv-proto.h similarity index 100% rename from target/i386/hyperv-proto.h rename to target/i386/kvm/hyperv-proto.h diff --git a/target/i386/hyperv.h b/target/i386/kvm/hyperv.h similarity index 100% rename from target/i386/hyperv.h rename to target/i386/kvm/hyperv.h diff --git a/target/i386/kvm_i386.h b/target/i386/kvm/kvm_i386.h similarity index 100% rename from target/i386/kvm_i386.h rename to target/i386/kvm/kvm_i386.h diff --git a/target/i386/kvm/trace.h b/target/i386/kvm/trace.h new file mode 100644 index 0000000000..46b75c6942 --- /dev/null +++ b/target/i386/kvm/trace.h @@ -0,0 +1 @@ +#include "trace/trace-target_i386_kvm.h" diff --git a/hw/i386/fw_cfg.c b/hw/i386/fw_cfg.c index e06579490c..fae1bb380f 100644 --- a/hw/i386/fw_cfg.c +++ b/hw/i386/fw_cfg.c @@ -21,7 +21,7 @@ #include "hw/timer/hpet.h" #include "hw/nvram/fw_cfg.h" #include "e820_memory_layout.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include CONFIG_DEVICES =20 struct hpet_fw_config hpet_cfg =3D {.count =3D UINT8_MAX}; diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 0cc71e4057..b4f5094259 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -37,7 +37,7 @@ #include "sysemu/kvm.h" #include "sysemu/sysemu.h" #include "hw/i386/apic_internal.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include "migration/vmstate.h" #include "trace.h" =20 diff --git a/hw/i386/kvm/apic.c b/hw/i386/kvm/apic.c index dd29906061..07bebc1282 100644 --- a/hw/i386/kvm/apic.c +++ b/hw/i386/kvm/apic.c @@ -17,7 +17,7 @@ #include "hw/pci/msi.h" #include "sysemu/hw_accel.h" #include "sysemu/kvm.h" -#include "target/i386/kvm_i386.h" +#include "kvm/kvm_i386.h" =20 static inline void kvm_apic_set_reg(struct kvm_lapic_state *kapic, int reg_id, uint32_t val) diff --git a/hw/i386/kvm/clock.c b/hw/i386/kvm/clock.c index 24fe5091b6..2d8a366369 100644 --- a/hw/i386/kvm/clock.c +++ b/hw/i386/kvm/clock.c @@ -20,7 +20,7 @@ #include "sysemu/kvm.h" #include "sysemu/runstate.h" #include "sysemu/hw_accel.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include "migration/vmstate.h" #include "hw/sysbus.h" #include "hw/kvm/clock.h" diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index 5428448b70..3ed6adff83 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -51,7 +51,7 @@ =20 #include "cpu.h" #include "elf.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include "hw/xen/start_info.h" =20 #define MICROVM_QBOOT_FILENAME "qboot.rom" diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 9e29f3792b..e562f5e190 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -61,7 +61,7 @@ #include "sysemu/qtest.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include "hw/xen/xen.h" #include "hw/xen/start_info.h" #include "ui/qemu-spice.h" diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 5944fc44ed..88d0c70e12 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -52,7 +52,7 @@ #include "elf.h" #include "standard-headers/asm-x86/bootparam.h" #include CONFIG_DEVICES -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" =20 #define BIOS_FILENAME "bios.bin" =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5a8c96072e..b9bd249c8f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -30,7 +30,7 @@ #include "sysemu/hvf.h" #include "sysemu/cpus.h" #include "sysemu/xen.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include "sev_i386.h" =20 #include "qemu/error-report.h" diff --git a/target/i386/helper.c b/target/i386/helper.c index 034f46bcc2..a1b3367ab2 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -24,7 +24,7 @@ #include "qemu/qemu-print.h" #include "sysemu/kvm.h" #include "sysemu/runstate.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #ifndef CONFIG_USER_ONLY #include "sysemu/tcg.h" #include "sysemu/hw_accel.h" diff --git a/target/i386/hyperv-stub.c b/target/i386/kvm/hyperv-stub.c similarity index 100% rename from target/i386/hyperv-stub.c rename to target/i386/kvm/hyperv-stub.c diff --git a/target/i386/hyperv.c b/target/i386/kvm/hyperv.c similarity index 100% rename from target/i386/hyperv.c rename to target/i386/kvm/hyperv.c diff --git a/target/i386/kvm-stub.c b/target/i386/kvm/kvm-stub.c similarity index 100% rename from target/i386/kvm-stub.c rename to target/i386/kvm/kvm-stub.c diff --git a/target/i386/kvm.c b/target/i386/kvm/kvm.c similarity index 100% rename from target/i386/kvm.c rename to target/i386/kvm/kvm.c diff --git a/target/i386/machine.c b/target/i386/machine.c index 233e46bb70..1614e8c2f8 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -3,9 +3,9 @@ #include "exec/exec-all.h" #include "hw/isa/isa.h" #include "migration/cpu.h" -#include "hyperv.h" +#include "kvm/hyperv.h" #include "hw/i386/x86.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" =20 #include "sysemu/kvm.h" #include "sysemu/tcg.h" diff --git a/MAINTAINERS b/MAINTAINERS index 68bc160f41..5b3eced829 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -425,7 +425,7 @@ M: Paolo Bonzini M: Marcelo Tosatti L: kvm@vger.kernel.org S: Supported -F: target/i386/kvm.c +F: target/i386/kvm/ F: scripts/kvm/vmxcap =20 Guest CPU Cores (other accelerators) diff --git a/target/i386/kvm/meson.build b/target/i386/kvm/meson.build new file mode 100644 index 0000000000..1d66559187 --- /dev/null +++ b/target/i386/kvm/meson.build @@ -0,0 +1,3 @@ +i386_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) +i386_softmmu_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) +i386_softmmu_ss.add(when: 'CONFIG_HYPERV', if_true: files('hyperv.c'), if_= false: files('hyperv-stub.c')) diff --git a/target/i386/kvm/trace-events b/target/i386/kvm/trace-events new file mode 100644 index 0000000000..b4e2d9e4ea --- /dev/null +++ b/target/i386/kvm/trace-events @@ -0,0 +1,7 @@ +# See docs/devel/tracing.txt for syntax documentation. + +# kvm.c +kvm_x86_fixup_msi_error(uint32_t gsi) "VT-d failed to remap interrupt for = GSI %" PRIu32 +kvm_x86_add_msi_route(int virq) "Adding route entry for virq %d" +kvm_x86_remove_msi_route(int virq) "Removing route entry for virq %d" +kvm_x86_update_msi_routes(int num) "Updated %d MSI routes" diff --git a/target/i386/meson.build b/target/i386/meson.build index a1a02f3e99..0209542a8a 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -18,7 +18,6 @@ i386_ss.add(when: 'CONFIG_TCG', if_true: files( 'smm_helper.c', 'svm_helper.c', 'translate.c'), if_false: files('tcg-stub.c')) -i386_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('= sev-stub.c')) =20 i386_softmmu_ss =3D ss.source_set() @@ -28,8 +27,6 @@ i386_softmmu_ss.add(files( 'machine.c', 'monitor.c', )) -i386_softmmu_ss.add(when: 'CONFIG_HYPERV', if_true: files('hyperv.c'), if_= false: files('hyperv-stub.c')) -i386_softmmu_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) i386_softmmu_ss.add(when: 'CONFIG_WHPX', if_true: files( 'whpx-all.c', 'whpx-cpus.c', @@ -42,6 +39,7 @@ i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files( i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('= hax-posix.c')) i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('= hax-windows.c')) =20 +subdir('kvm') subdir('hvf') =20 target_arch +=3D {'i386': i386_ss} diff --git a/target/i386/trace-events b/target/i386/trace-events index 789c700d4a..d166f9d5e0 100644 --- a/target/i386/trace-events +++ b/target/i386/trace-events @@ -1,11 +1,5 @@ # See docs/devel/tracing.txt for syntax documentation. =20 -# kvm.c -kvm_x86_fixup_msi_error(uint32_t gsi) "VT-d failed to remap interrupt for = GSI %" PRIu32 -kvm_x86_add_msi_route(int virq) "Adding route entry for virq %d" -kvm_x86_remove_msi_route(int virq) "Removing route entry for virq %d" -kvm_x86_update_msi_routes(int num) "Updated %d MSI routes" - # sev.c kvm_sev_init(void) "" kvm_memcrypt_register_region(void *addr, size_t len) "addr %p len 0x%zu" --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607604735; cv=none; d=zohomail.com; s=zohoarc; b=aSre/q8vlbITli/elh+nHQr5QIu1w2pzAjSDHdEeWuYFTcHnU8+v8rz8124cQCR4e5IWf7yHFcRDylXQrgUX3buYK51lztrEZQpO6zQzBJ6jC63HB6+Xcabjo68dg3V3ZDdwOwsjWXypzbSErd/3VkuIfq1xtf8eH95nUPc7B0g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607604735; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e --- target/i386/{ =3D> whpx}/whp-dispatch.h | 0 target/i386/{ =3D> whpx}/whpx-cpus.h | 0 target/i386/{ =3D> whpx}/whpx-all.c | 0 target/i386/{ =3D> whpx}/whpx-cpus.c | 0 MAINTAINERS | 5 +---- target/i386/meson.build | 5 +---- target/i386/whpx/meson.build | 4 ++++ 7 files changed, 6 insertions(+), 8 deletions(-) rename target/i386/{ =3D> whpx}/whp-dispatch.h (100%) rename target/i386/{ =3D> whpx}/whpx-cpus.h (100%) rename target/i386/{ =3D> whpx}/whpx-all.c (100%) rename target/i386/{ =3D> whpx}/whpx-cpus.c (100%) create mode 100644 target/i386/whpx/meson.build diff --git a/target/i386/whp-dispatch.h b/target/i386/whpx/whp-dispatch.h similarity index 100% rename from target/i386/whp-dispatch.h rename to target/i386/whpx/whp-dispatch.h diff --git a/target/i386/whpx-cpus.h b/target/i386/whpx/whpx-cpus.h similarity index 100% rename from target/i386/whpx-cpus.h rename to target/i386/whpx/whpx-cpus.h diff --git a/target/i386/whpx-all.c b/target/i386/whpx/whpx-all.c similarity index 100% rename from target/i386/whpx-all.c rename to target/i386/whpx/whpx-all.c diff --git a/target/i386/whpx-cpus.c b/target/i386/whpx/whpx-cpus.c similarity index 100% rename from target/i386/whpx-cpus.c rename to target/i386/whpx/whpx-cpus.c diff --git a/MAINTAINERS b/MAINTAINERS index 5b3eced829..20e079f40c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -451,10 +451,7 @@ F: include/sysemu/hvf.h WHPX CPUs M: Sunil Muthuswamy S: Supported -F: target/i386/whpx-all.c -F: target/i386/whpx-cpus.c -F: target/i386/whp-dispatch.h -F: accel/stubs/whpx-stub.c +F: target/i386/whpx/ F: include/sysemu/whpx.h =20 Guest CPU Cores (Xen) diff --git a/target/i386/meson.build b/target/i386/meson.build index 0209542a8a..62cd042915 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -27,10 +27,6 @@ i386_softmmu_ss.add(files( 'machine.c', 'monitor.c', )) -i386_softmmu_ss.add(when: 'CONFIG_WHPX', if_true: files( - 'whpx-all.c', - 'whpx-cpus.c', -)) i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files( 'hax-all.c', 'hax-mem.c', @@ -40,6 +36,7 @@ i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'],= if_true: files('hax-po i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('= hax-windows.c')) =20 subdir('kvm') +subdir('whpx') subdir('hvf') =20 target_arch +=3D {'i386': i386_ss} diff --git a/target/i386/whpx/meson.build b/target/i386/whpx/meson.build new file mode 100644 index 0000000000..94a72c8efc --- /dev/null +++ b/target/i386/whpx/meson.build @@ -0,0 +1,4 @@ +i386_softmmu_ss.add(when: 'CONFIG_WHPX', if_true: files( + 'whpx-all.c', + 'whpx-cpus.c', +)) --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 10 Dec 2020 04:28:22 -0800 (PST) Received: from localhost ([::1]:51198 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knL3V-0002H2-GC for importer@patchew.org; Thu, 10 Dec 2020 07:28:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56402) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoJ-000201-JE for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:12:39 -0500 Received: from mx2.suse.de ([195.135.220.15]:47162) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoG-0006Qp-HS for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:12:39 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 37887AD6B; Thu, 10 Dec 2020 12:12:35 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 06/32] i386: move hax accel files into hax/ Date: Thu, 10 Dec 2020 13:12:00 +0100 Message-Id: <20201210121226.19822-7-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e --- target/i386/{ =3D> hax}/hax-cpus.h | 0 target/i386/{ =3D> hax}/hax-i386.h | 6 +++--- target/i386/{ =3D> hax}/hax-interface.h | 0 target/i386/{ =3D> hax}/hax-posix.h | 0 target/i386/{ =3D> hax}/hax-windows.h | 0 target/i386/{ =3D> hax}/hax-all.c | 0 target/i386/{ =3D> hax}/hax-cpus.c | 0 target/i386/{ =3D> hax}/hax-mem.c | 0 target/i386/{ =3D> hax}/hax-posix.c | 0 target/i386/{ =3D> hax}/hax-windows.c | 0 MAINTAINERS | 2 +- target/i386/hax/meson.build | 7 +++++++ target/i386/meson.build | 8 +------- 13 files changed, 12 insertions(+), 11 deletions(-) rename target/i386/{ =3D> hax}/hax-cpus.h (100%) rename target/i386/{ =3D> hax}/hax-i386.h (95%) rename target/i386/{ =3D> hax}/hax-interface.h (100%) rename target/i386/{ =3D> hax}/hax-posix.h (100%) rename target/i386/{ =3D> hax}/hax-windows.h (100%) rename target/i386/{ =3D> hax}/hax-all.c (100%) rename target/i386/{ =3D> hax}/hax-cpus.c (100%) rename target/i386/{ =3D> hax}/hax-mem.c (100%) rename target/i386/{ =3D> hax}/hax-posix.c (100%) rename target/i386/{ =3D> hax}/hax-windows.c (100%) create mode 100644 target/i386/hax/meson.build diff --git a/target/i386/hax-cpus.h b/target/i386/hax/hax-cpus.h similarity index 100% rename from target/i386/hax-cpus.h rename to target/i386/hax/hax-cpus.h diff --git a/target/i386/hax-i386.h b/target/i386/hax/hax-i386.h similarity index 95% rename from target/i386/hax-i386.h rename to target/i386/hax/hax-i386.h index 48c4abe14e..efbb346238 100644 --- a/target/i386/hax-i386.h +++ b/target/i386/hax/hax-i386.h @@ -84,13 +84,13 @@ void hax_memory_init(void); =20 =20 #ifdef CONFIG_POSIX -#include "target/i386/hax-posix.h" +#include "hax-posix.h" #endif =20 #ifdef CONFIG_WIN32 -#include "target/i386/hax-windows.h" +#include "hax-windows.h" #endif =20 -#include "target/i386/hax-interface.h" +#include "hax-interface.h" =20 #endif diff --git a/target/i386/hax-interface.h b/target/i386/hax/hax-interface.h similarity index 100% rename from target/i386/hax-interface.h rename to target/i386/hax/hax-interface.h diff --git a/target/i386/hax-posix.h b/target/i386/hax/hax-posix.h similarity index 100% rename from target/i386/hax-posix.h rename to target/i386/hax/hax-posix.h diff --git a/target/i386/hax-windows.h b/target/i386/hax/hax-windows.h similarity index 100% rename from target/i386/hax-windows.h rename to target/i386/hax/hax-windows.h diff --git a/target/i386/hax-all.c b/target/i386/hax/hax-all.c similarity index 100% rename from target/i386/hax-all.c rename to target/i386/hax/hax-all.c diff --git a/target/i386/hax-cpus.c b/target/i386/hax/hax-cpus.c similarity index 100% rename from target/i386/hax-cpus.c rename to target/i386/hax/hax-cpus.c diff --git a/target/i386/hax-mem.c b/target/i386/hax/hax-mem.c similarity index 100% rename from target/i386/hax-mem.c rename to target/i386/hax/hax-mem.c diff --git a/target/i386/hax-posix.c b/target/i386/hax/hax-posix.c similarity index 100% rename from target/i386/hax-posix.c rename to target/i386/hax/hax-posix.c diff --git a/target/i386/hax-windows.c b/target/i386/hax/hax-windows.c similarity index 100% rename from target/i386/hax-windows.c rename to target/i386/hax/hax-windows.c diff --git a/MAINTAINERS b/MAINTAINERS index 20e079f40c..448593c904 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -491,7 +491,7 @@ W: https://github.com/intel/haxm/issues S: Maintained F: accel/stubs/hax-stub.c F: include/sysemu/hax.h -F: target/i386/hax-* +F: target/i386/hax/ =20 Hosts ----- diff --git a/target/i386/hax/meson.build b/target/i386/hax/meson.build new file mode 100644 index 0000000000..77ea431b30 --- /dev/null +++ b/target/i386/hax/meson.build @@ -0,0 +1,7 @@ +i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files( + 'hax-all.c', + 'hax-mem.c', + 'hax-cpus.c', +)) +i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('= hax-posix.c')) +i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('= hax-windows.c')) diff --git a/target/i386/meson.build b/target/i386/meson.build index 62cd042915..284d52ab81 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -27,15 +27,9 @@ i386_softmmu_ss.add(files( 'machine.c', 'monitor.c', )) -i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files( - 'hax-all.c', - 'hax-mem.c', - 'hax-cpus.c', -)) -i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('= hax-posix.c')) -i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('= hax-windows.c')) =20 subdir('kvm') +subdir('hax') subdir('whpx') subdir('hvf') =20 --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 10 Dec 2020 04:24:04 -0800 (PST) Received: from localhost ([::1]:38600 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKzL-0005Yc-Qj for importer@patchew.org; Thu, 10 Dec 2020 07:24:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56416) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoK-00022E-I5 for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:12:40 -0500 Received: from mx2.suse.de ([195.135.220.15]:47202) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoH-0006R7-IW for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:12:40 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 40BD2AD3F; Thu, 10 Dec 2020 12:12:36 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 07/32] i386: hvf: remove stale MAINTAINERS entry for old hvf stubs Date: Thu, 10 Dec 2020 13:12:01 +0100 Message-Id: <20201210121226.19822-8-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; 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Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Claudio Fontana Reviewed-by: Roman Bolshakov Reviewed-by: Alex Benn=C3=A9e --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 448593c904..f53f2678d8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -444,7 +444,6 @@ M: Cameron Esfahani M: Roman Bolshakov W: https://wiki.qemu.org/Features/HVF S: Maintained -F: accel/stubs/hvf-stub.c F: target/i386/hvf/ F: include/sysemu/hvf.h =20 --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607604909; cv=none; d=zohomail.com; s=zohoarc; b=fMXYECPFatsvDf9jGCTO7vlh8yxWAHk2llTgEYLwsxnKc/68zgvtQwVDYnmWcPCsAj5NOBp+N15d4jXFJHY1U4zlG/HzR3pUEZbVCeIlhQ+aurrtO0Y9P9IJXTAgocTTUlGx6HvLMkC3kr9puWpYzKhYjGGU+HpQLOQTOBBGRJo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607604909; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2SzwDrTszu7JxM9GP+uEaQ22m9Wgvz4VCHDyCkqGo/I=; b=Q3xeW1fez7SylYjMmykd2AoXyNYuJF65dWPEuXTSVAAjNKKAyAm5GFzVFgPmKd14fmQG9i6J5G1FvCReWgdkJ43YbFLNPnFbmq2SXqWdp76WBAL2kBJQ97k9YKqXUywM3RMt3xhE/UGYJGjzi6g/PH1BgrelBzjN/MrRTI/e9Cg= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607604909440253.71658976260164; Thu, 10 Dec 2020 04:55:09 -0800 (PST) Received: from localhost ([::1]:34044 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knLTP-00052W-SI for importer@patchew.org; Thu, 10 Dec 2020 07:55:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56418) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoL-00023O-1m for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:12:41 -0500 Received: from mx2.suse.de ([195.135.220.15]:47248) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoI-0006Rx-KN for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:12:40 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 4D3DAAD4D; Thu, 10 Dec 2020 12:12:37 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 08/32] i386: move TCG accel files into tcg/ Date: Thu, 10 Dec 2020 13:12:02 +0100 Message-Id: <20201210121226.19822-9-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e --- target/i386/{ =3D> tcg}/bpt_helper.c | 0 target/i386/{ =3D> tcg}/cc_helper.c | 0 target/i386/{ =3D> tcg}/excp_helper.c | 0 target/i386/{ =3D> tcg}/fpu_helper.c | 0 target/i386/{ =3D> tcg}/int_helper.c | 0 target/i386/{ =3D> tcg}/mem_helper.c | 0 target/i386/{ =3D> tcg}/misc_helper.c | 0 target/i386/{ =3D> tcg}/mpx_helper.c | 0 target/i386/{ =3D> tcg}/seg_helper.c | 0 target/i386/{ =3D> tcg}/smm_helper.c | 0 target/i386/{ =3D> tcg}/svm_helper.c | 0 target/i386/{ =3D> tcg}/tcg-stub.c | 0 target/i386/{ =3D> tcg}/translate.c | 0 target/i386/meson.build | 14 +------------- target/i386/tcg/meson.build | 13 +++++++++++++ 15 files changed, 14 insertions(+), 13 deletions(-) rename target/i386/{ =3D> tcg}/bpt_helper.c (100%) rename target/i386/{ =3D> tcg}/cc_helper.c (100%) rename target/i386/{ =3D> tcg}/excp_helper.c (100%) rename target/i386/{ =3D> tcg}/fpu_helper.c (100%) rename target/i386/{ =3D> tcg}/int_helper.c (100%) rename target/i386/{ =3D> tcg}/mem_helper.c (100%) rename target/i386/{ =3D> tcg}/misc_helper.c (100%) rename target/i386/{ =3D> tcg}/mpx_helper.c (100%) rename target/i386/{ =3D> tcg}/seg_helper.c (100%) rename target/i386/{ =3D> tcg}/smm_helper.c (100%) rename target/i386/{ =3D> tcg}/svm_helper.c (100%) rename target/i386/{ =3D> tcg}/tcg-stub.c (100%) rename target/i386/{ =3D> tcg}/translate.c (100%) create mode 100644 target/i386/tcg/meson.build diff --git a/target/i386/bpt_helper.c b/target/i386/tcg/bpt_helper.c similarity index 100% rename from target/i386/bpt_helper.c rename to target/i386/tcg/bpt_helper.c diff --git a/target/i386/cc_helper.c b/target/i386/tcg/cc_helper.c similarity index 100% rename from target/i386/cc_helper.c rename to target/i386/tcg/cc_helper.c diff --git a/target/i386/excp_helper.c b/target/i386/tcg/excp_helper.c similarity index 100% rename from target/i386/excp_helper.c rename to target/i386/tcg/excp_helper.c diff --git a/target/i386/fpu_helper.c b/target/i386/tcg/fpu_helper.c similarity index 100% rename from target/i386/fpu_helper.c rename to target/i386/tcg/fpu_helper.c diff --git a/target/i386/int_helper.c b/target/i386/tcg/int_helper.c similarity index 100% rename from target/i386/int_helper.c rename to target/i386/tcg/int_helper.c diff --git a/target/i386/mem_helper.c b/target/i386/tcg/mem_helper.c similarity index 100% rename from target/i386/mem_helper.c rename to target/i386/tcg/mem_helper.c diff --git a/target/i386/misc_helper.c b/target/i386/tcg/misc_helper.c similarity index 100% rename from target/i386/misc_helper.c rename to target/i386/tcg/misc_helper.c diff --git a/target/i386/mpx_helper.c b/target/i386/tcg/mpx_helper.c similarity index 100% rename from target/i386/mpx_helper.c rename to target/i386/tcg/mpx_helper.c diff --git a/target/i386/seg_helper.c b/target/i386/tcg/seg_helper.c similarity index 100% rename from target/i386/seg_helper.c rename to target/i386/tcg/seg_helper.c diff --git a/target/i386/smm_helper.c b/target/i386/tcg/smm_helper.c similarity index 100% rename from target/i386/smm_helper.c rename to target/i386/tcg/smm_helper.c diff --git a/target/i386/svm_helper.c b/target/i386/tcg/svm_helper.c similarity index 100% rename from target/i386/svm_helper.c rename to target/i386/tcg/svm_helper.c diff --git a/target/i386/tcg-stub.c b/target/i386/tcg/tcg-stub.c similarity index 100% rename from target/i386/tcg-stub.c rename to target/i386/tcg/tcg-stub.c diff --git a/target/i386/translate.c b/target/i386/tcg/translate.c similarity index 100% rename from target/i386/translate.c rename to target/i386/tcg/translate.c diff --git a/target/i386/meson.build b/target/i386/meson.build index 284d52ab81..750471c9f3 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -5,19 +5,6 @@ i386_ss.add(files( 'helper.c', 'xsave_helper.c', )) -i386_ss.add(when: 'CONFIG_TCG', if_true: files( - 'bpt_helper.c', - 'cc_helper.c', - 'excp_helper.c', - 'fpu_helper.c', - 'int_helper.c', - 'mem_helper.c', - 'misc_helper.c', - 'mpx_helper.c', - 'seg_helper.c', - 'smm_helper.c', - 'svm_helper.c', - 'translate.c'), if_false: files('tcg-stub.c')) i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('= sev-stub.c')) =20 i386_softmmu_ss =3D ss.source_set() @@ -32,6 +19,7 @@ subdir('kvm') subdir('hax') subdir('whpx') subdir('hvf') +subdir('tcg') =20 target_arch +=3D {'i386': i386_ss} target_softmmu_arch +=3D {'i386': i386_softmmu_ss} diff --git a/target/i386/tcg/meson.build b/target/i386/tcg/meson.build new file mode 100644 index 0000000000..02794226c2 --- /dev/null +++ b/target/i386/tcg/meson.build @@ -0,0 +1,13 @@ +i386_ss.add(when: 'CONFIG_TCG', if_true: files( + 'bpt_helper.c', + 'cc_helper.c', + 'excp_helper.c', + 'fpu_helper.c', + 'int_helper.c', + 'mem_helper.c', + 'misc_helper.c', + 'mpx_helper.c', + 'seg_helper.c', + 'smm_helper.c', + 'svm_helper.c', + 'translate.c'), if_false: files('tcg-stub.c')) --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607605119; cv=none; d=zohomail.com; s=zohoarc; b=fqTULOjR3fVkC81ReFr0nJu3avO0XaWz8A/tOY7/vkZ+ikQdpiffdZViBB4JagGg9MALzVEHbe3x2m3ETCnXmPOTPrLOIiZU/QR9kEpqJ1uBKnxbYoeacJl64I47yg7y8P9Hl7PyGq4YdNaq+75ytJKoTV8l+VXwvNU2sF1vZ1A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607605119; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=D7AdUssWaUWltmh2bCcae/77WpzLneRCK+6CfNqyqNI=; b=KmXiUehTq+yBGW9tAHwp3w8oILID+/Iajg8MtnFF3bzqftSP1WAZKzSgt0f2+pBUTE+e2CO+m9ICQUM5bdYgU1DzQYRhzmZK+bYJe8aXi27KTYj1CrYAorXU1U/wwK4RHHVdf5K+Or/cOk1c1EA8nLWCK2VN+cHbpAyM3Az0Ddw= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607605119404371.5507468384732; Thu, 10 Dec 2020 04:58:39 -0800 (PST) Received: from localhost ([::1]:42526 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knLWn-000079-Ro for importer@patchew.org; Thu, 10 Dec 2020 07:58:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56432) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoP-0002DU-Ay for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:12:45 -0500 Received: from mx2.suse.de ([195.135.220.15]:47284) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoJ-0006SE-Sg for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:12:45 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 90FC2AD29; Thu, 10 Dec 2020 12:12:38 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 09/32] i386: move cpu dump out of helper.c into cpu-dump.c Date: Thu, 10 Dec 2020 13:12:03 +0100 Message-Id: <20201210121226.19822-10-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e --- target/i386/cpu.h | 1 + target/i386/cpu-dump.c | 537 ++++++++++++++++++++++++++++++++++++++++ target/i386/helper.c | 514 -------------------------------------- target/i386/meson.build | 1 + 4 files changed, 539 insertions(+), 514 deletions(-) create mode 100644 target/i386/cpu-dump.c diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9ecda75aec..d6ed45c5d7 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2232,6 +2232,7 @@ void enable_compat_apic_id_mode(void); #define APIC_DEFAULT_ADDRESS 0xfee00000 #define APIC_SPACE_SIZE 0x100000 =20 +/* cpu-dump.c */ void x86_cpu_dump_local_apic_state(CPUState *cs, int flags); =20 /* cpu.c */ diff --git a/target/i386/cpu-dump.c b/target/i386/cpu-dump.c new file mode 100644 index 0000000000..aac21f1f60 --- /dev/null +++ b/target/i386/cpu-dump.c @@ -0,0 +1,537 @@ +/* + * i386 CPU dump to FILE + * + * Copyright (c) 2003 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "qemu/qemu-print.h" +#ifndef CONFIG_USER_ONLY +#include "hw/i386/apic_internal.h" +#endif + +/***********************************************************/ +/* x86 debug */ + +static const char *cc_op_str[CC_OP_NB] =3D { + "DYNAMIC", + "EFLAGS", + + "MULB", + "MULW", + "MULL", + "MULQ", + + "ADDB", + "ADDW", + "ADDL", + "ADDQ", + + "ADCB", + "ADCW", + "ADCL", + "ADCQ", + + "SUBB", + "SUBW", + "SUBL", + "SUBQ", + + "SBBB", + "SBBW", + "SBBL", + "SBBQ", + + "LOGICB", + "LOGICW", + "LOGICL", + "LOGICQ", + + "INCB", + "INCW", + "INCL", + "INCQ", + + "DECB", + "DECW", + "DECL", + "DECQ", + + "SHLB", + "SHLW", + "SHLL", + "SHLQ", + + "SARB", + "SARW", + "SARL", + "SARQ", + + "BMILGB", + "BMILGW", + "BMILGL", + "BMILGQ", + + "ADCX", + "ADOX", + "ADCOX", + + "CLR", +}; + +static void +cpu_x86_dump_seg_cache(CPUX86State *env, FILE *f, + const char *name, struct SegmentCache *sc) +{ +#ifdef TARGET_X86_64 + if (env->hflags & HF_CS64_MASK) { + qemu_fprintf(f, "%-3s=3D%04x %016" PRIx64 " %08x %08x", name, + sc->selector, sc->base, sc->limit, + sc->flags & 0x00ffff00); + } else +#endif + { + qemu_fprintf(f, "%-3s=3D%04x %08x %08x %08x", name, sc->selector, + (uint32_t)sc->base, sc->limit, + sc->flags & 0x00ffff00); + } + + if (!(env->hflags & HF_PE_MASK) || !(sc->flags & DESC_P_MASK)) + goto done; + + qemu_fprintf(f, " DPL=3D%d ", + (sc->flags & DESC_DPL_MASK) >> DESC_DPL_SHIFT); + if (sc->flags & DESC_S_MASK) { + if (sc->flags & DESC_CS_MASK) { + qemu_fprintf(f, (sc->flags & DESC_L_MASK) ? "CS64" : + ((sc->flags & DESC_B_MASK) ? "CS32" : "CS16")); + qemu_fprintf(f, " [%c%c", (sc->flags & DESC_C_MASK) ? 'C' : '-= ', + (sc->flags & DESC_R_MASK) ? 'R' : '-'); + } else { + qemu_fprintf(f, (sc->flags & DESC_B_MASK + || env->hflags & HF_LMA_MASK) + ? "DS " : "DS16"); + qemu_fprintf(f, " [%c%c", (sc->flags & DESC_E_MASK) ? 'E' : '-= ', + (sc->flags & DESC_W_MASK) ? 'W' : '-'); + } + qemu_fprintf(f, "%c]", (sc->flags & DESC_A_MASK) ? 'A' : '-'); + } else { + static const char *sys_type_name[2][16] =3D { + { /* 32 bit mode */ + "Reserved", "TSS16-avl", "LDT", "TSS16-busy", + "CallGate16", "TaskGate", "IntGate16", "TrapGate16", + "Reserved", "TSS32-avl", "Reserved", "TSS32-busy", + "CallGate32", "Reserved", "IntGate32", "TrapGate32" + }, + { /* 64 bit mode */ + "", "Reserved", "LDT", "Reserved", "Reserved", + "Reserved", "Reserved", "Reserved", "Reserved", + "TSS64-avl", "Reserved", "TSS64-busy", "CallGate64", + "Reserved", "IntGate64", "TrapGate64" + } + }; + qemu_fprintf(f, "%s", + sys_type_name[(env->hflags & HF_LMA_MASK) ? 1 : 0] + [(sc->flags & DESC_TYPE_MASK) >> DESC_TYPE_SHIFT]); + } +done: + qemu_fprintf(f, "\n"); +} + +#ifndef CONFIG_USER_ONLY + +/* ARRAY_SIZE check is not required because + * DeliveryMode(dm) has a size of 3 bit. + */ +static inline const char *dm2str(uint32_t dm) +{ + static const char *str[] =3D { + "Fixed", + "...", + "SMI", + "...", + "NMI", + "INIT", + "...", + "ExtINT" + }; + return str[dm]; +} + +static void dump_apic_lvt(const char *name, uint32_t lvt, bool is_timer) +{ + uint32_t dm =3D (lvt & APIC_LVT_DELIV_MOD) >> APIC_LVT_DELIV_MOD_SHIFT; + qemu_printf("%s\t 0x%08x %s %-5s %-6s %-7s %-12s %-6s", + name, lvt, + lvt & APIC_LVT_INT_POLARITY ? "active-lo" : "active-hi", + lvt & APIC_LVT_LEVEL_TRIGGER ? "level" : "edge", + lvt & APIC_LVT_MASKED ? "masked" : "", + lvt & APIC_LVT_DELIV_STS ? "pending" : "", + !is_timer ? + "" : lvt & APIC_LVT_TIMER_PERIODIC ? + "periodic" : lvt & APIC_LVT_TIMER_TSCDEADLINE ? + "tsc-deadline" : "one-shot", + dm2str(dm)); + if (dm !=3D APIC_DM_NMI) { + qemu_printf(" (vec %u)\n", lvt & APIC_VECTOR_MASK); + } else { + qemu_printf("\n"); + } +} + +/* ARRAY_SIZE check is not required because + * destination shorthand has a size of 2 bit. + */ +static inline const char *shorthand2str(uint32_t shorthand) +{ + const char *str[] =3D { + "no-shorthand", "self", "all-self", "all" + }; + return str[shorthand]; +} + +static inline uint8_t divider_conf(uint32_t divide_conf) +{ + uint8_t divide_val =3D ((divide_conf & 0x8) >> 1) | (divide_conf & 0x3= ); + + return divide_val =3D=3D 7 ? 1 : 2 << divide_val; +} + +static inline void mask2str(char *str, uint32_t val, uint8_t size) +{ + while (size--) { + *str++ =3D (val >> size) & 1 ? '1' : '0'; + } + *str =3D 0; +} + +#define MAX_LOGICAL_APIC_ID_MASK_SIZE 16 + +static void dump_apic_icr(APICCommonState *s, CPUX86State *env) +{ + uint32_t icr =3D s->icr[0], icr2 =3D s->icr[1]; + uint8_t dest_shorthand =3D \ + (icr & APIC_ICR_DEST_SHORT) >> APIC_ICR_DEST_SHORT_SHIFT; + bool logical_mod =3D icr & APIC_ICR_DEST_MOD; + char apic_id_str[MAX_LOGICAL_APIC_ID_MASK_SIZE + 1]; + uint32_t dest_field; + bool x2apic; + + qemu_printf("ICR\t 0x%08x %s %s %s %s\n", + icr, + logical_mod ? "logical" : "physical", + icr & APIC_ICR_TRIGGER_MOD ? "level" : "edge", + icr & APIC_ICR_LEVEL ? "assert" : "de-assert", + shorthand2str(dest_shorthand)); + + qemu_printf("ICR2\t 0x%08x", icr2); + if (dest_shorthand !=3D 0) { + qemu_printf("\n"); + return; + } + x2apic =3D env->features[FEAT_1_ECX] & CPUID_EXT_X2APIC; + dest_field =3D x2apic ? icr2 : icr2 >> APIC_ICR_DEST_SHIFT; + + if (!logical_mod) { + if (x2apic) { + qemu_printf(" cpu %u (X2APIC ID)\n", dest_field); + } else { + qemu_printf(" cpu %u (APIC ID)\n", + dest_field & APIC_LOGDEST_XAPIC_ID); + } + return; + } + + if (s->dest_mode =3D=3D 0xf) { /* flat mode */ + mask2str(apic_id_str, icr2 >> APIC_ICR_DEST_SHIFT, 8); + qemu_printf(" mask %s (APIC ID)\n", apic_id_str); + } else if (s->dest_mode =3D=3D 0) { /* cluster mode */ + if (x2apic) { + mask2str(apic_id_str, dest_field & APIC_LOGDEST_X2APIC_ID, 16); + qemu_printf(" cluster %u mask %s (X2APIC ID)\n", + dest_field >> APIC_LOGDEST_X2APIC_SHIFT, apic_id_s= tr); + } else { + mask2str(apic_id_str, dest_field & APIC_LOGDEST_XAPIC_ID, 4); + qemu_printf(" cluster %u mask %s (APIC ID)\n", + dest_field >> APIC_LOGDEST_XAPIC_SHIFT, apic_id_st= r); + } + } +} + +static void dump_apic_interrupt(const char *name, uint32_t *ireg_tab, + uint32_t *tmr_tab) +{ + int i, empty =3D true; + + qemu_printf("%s\t ", name); + for (i =3D 0; i < 256; i++) { + if (apic_get_bit(ireg_tab, i)) { + qemu_printf("%u%s ", i, + apic_get_bit(tmr_tab, i) ? "(level)" : ""); + empty =3D false; + } + } + qemu_printf("%s\n", empty ? "(none)" : ""); +} + +void x86_cpu_dump_local_apic_state(CPUState *cs, int flags) +{ + X86CPU *cpu =3D X86_CPU(cs); + APICCommonState *s =3D APIC_COMMON(cpu->apic_state); + if (!s) { + qemu_printf("local apic state not available\n"); + return; + } + uint32_t *lvt =3D s->lvt; + + qemu_printf("dumping local APIC state for CPU %-2u\n\n", + CPU(cpu)->cpu_index); + dump_apic_lvt("LVT0", lvt[APIC_LVT_LINT0], false); + dump_apic_lvt("LVT1", lvt[APIC_LVT_LINT1], false); + dump_apic_lvt("LVTPC", lvt[APIC_LVT_PERFORM], false); + dump_apic_lvt("LVTERR", lvt[APIC_LVT_ERROR], false); + dump_apic_lvt("LVTTHMR", lvt[APIC_LVT_THERMAL], false); + dump_apic_lvt("LVTT", lvt[APIC_LVT_TIMER], true); + + qemu_printf("Timer\t DCR=3D0x%x (divide by %u) initial_count =3D %u" + " current_count =3D %u\n", + s->divide_conf & APIC_DCR_MASK, + divider_conf(s->divide_conf), + s->initial_count, apic_get_current_count(s)); + + qemu_printf("SPIV\t 0x%08x APIC %s, focus=3D%s, spurious vec %u\n", + s->spurious_vec, + s->spurious_vec & APIC_SPURIO_ENABLED ? "enabled" : "disab= led", + s->spurious_vec & APIC_SPURIO_FOCUS ? "on" : "off", + s->spurious_vec & APIC_VECTOR_MASK); + + dump_apic_icr(s, &cpu->env); + + qemu_printf("ESR\t 0x%08x\n", s->esr); + + dump_apic_interrupt("ISR", s->isr, s->tmr); + dump_apic_interrupt("IRR", s->irr, s->tmr); + + qemu_printf("\nAPR 0x%02x TPR 0x%02x DFR 0x%02x LDR 0x%02x", + s->arb_id, s->tpr, s->dest_mode, s->log_dest); + if (s->dest_mode =3D=3D 0) { + qemu_printf("(cluster %u: id %u)", + s->log_dest >> APIC_LOGDEST_XAPIC_SHIFT, + s->log_dest & APIC_LOGDEST_XAPIC_ID); + } + qemu_printf(" PPR 0x%02x\n", apic_get_ppr(s)); +} +#else +void x86_cpu_dump_local_apic_state(CPUState *cs, int flags) +{ +} +#endif /* !CONFIG_USER_ONLY */ + +#define DUMP_CODE_BYTES_TOTAL 50 +#define DUMP_CODE_BYTES_BACKWARD 20 + +void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + int eflags, i, nb; + char cc_op_name[32]; + static const char *seg_name[6] =3D { "ES", "CS", "SS", "DS", "FS", "GS= " }; + + eflags =3D cpu_compute_eflags(env); +#ifdef TARGET_X86_64 + if (env->hflags & HF_CS64_MASK) { + qemu_fprintf(f, "RAX=3D%016" PRIx64 " RBX=3D%016" PRIx64 " RCX=3D%= 016" PRIx64 " RDX=3D%016" PRIx64 "\n" + "RSI=3D%016" PRIx64 " RDI=3D%016" PRIx64 " RBP=3D%016= " PRIx64 " RSP=3D%016" PRIx64 "\n" + "R8 =3D%016" PRIx64 " R9 =3D%016" PRIx64 " R10=3D%016= " PRIx64 " R11=3D%016" PRIx64 "\n" + "R12=3D%016" PRIx64 " R13=3D%016" PRIx64 " R14=3D%016= " PRIx64 " R15=3D%016" PRIx64 "\n" + "RIP=3D%016" PRIx64 " RFL=3D%08x [%c%c%c%c%c%c%c] CPL= =3D%d II=3D%d A20=3D%d SMM=3D%d HLT=3D%d\n", + env->regs[R_EAX], + env->regs[R_EBX], + env->regs[R_ECX], + env->regs[R_EDX], + env->regs[R_ESI], + env->regs[R_EDI], + env->regs[R_EBP], + env->regs[R_ESP], + env->regs[8], + env->regs[9], + env->regs[10], + env->regs[11], + env->regs[12], + env->regs[13], + env->regs[14], + env->regs[15], + env->eip, eflags, + eflags & DF_MASK ? 'D' : '-', + eflags & CC_O ? 'O' : '-', + eflags & CC_S ? 'S' : '-', + eflags & CC_Z ? 'Z' : '-', + eflags & CC_A ? 'A' : '-', + eflags & CC_P ? 'P' : '-', + eflags & CC_C ? 'C' : '-', + env->hflags & HF_CPL_MASK, + (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1, + (env->a20_mask >> 20) & 1, + (env->hflags >> HF_SMM_SHIFT) & 1, + cs->halted); + } else +#endif + { + qemu_fprintf(f, "EAX=3D%08x EBX=3D%08x ECX=3D%08x EDX=3D%08x\n" + "ESI=3D%08x EDI=3D%08x EBP=3D%08x ESP=3D%08x\n" + "EIP=3D%08x EFL=3D%08x [%c%c%c%c%c%c%c] CPL=3D%d II= =3D%d A20=3D%d SMM=3D%d HLT=3D%d\n", + (uint32_t)env->regs[R_EAX], + (uint32_t)env->regs[R_EBX], + (uint32_t)env->regs[R_ECX], + (uint32_t)env->regs[R_EDX], + (uint32_t)env->regs[R_ESI], + (uint32_t)env->regs[R_EDI], + (uint32_t)env->regs[R_EBP], + (uint32_t)env->regs[R_ESP], + (uint32_t)env->eip, eflags, + eflags & DF_MASK ? 'D' : '-', + eflags & CC_O ? 'O' : '-', + eflags & CC_S ? 'S' : '-', + eflags & CC_Z ? 'Z' : '-', + eflags & CC_A ? 'A' : '-', + eflags & CC_P ? 'P' : '-', + eflags & CC_C ? 'C' : '-', + env->hflags & HF_CPL_MASK, + (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1, + (env->a20_mask >> 20) & 1, + (env->hflags >> HF_SMM_SHIFT) & 1, + cs->halted); + } + + for(i =3D 0; i < 6; i++) { + cpu_x86_dump_seg_cache(env, f, seg_name[i], &env->segs[i]); + } + cpu_x86_dump_seg_cache(env, f, "LDT", &env->ldt); + cpu_x86_dump_seg_cache(env, f, "TR", &env->tr); + +#ifdef TARGET_X86_64 + if (env->hflags & HF_LMA_MASK) { + qemu_fprintf(f, "GDT=3D %016" PRIx64 " %08x\n", + env->gdt.base, env->gdt.limit); + qemu_fprintf(f, "IDT=3D %016" PRIx64 " %08x\n", + env->idt.base, env->idt.limit); + qemu_fprintf(f, "CR0=3D%08x CR2=3D%016" PRIx64 " CR3=3D%016" PRIx6= 4 " CR4=3D%08x\n", + (uint32_t)env->cr[0], + env->cr[2], + env->cr[3], + (uint32_t)env->cr[4]); + for(i =3D 0; i < 4; i++) + qemu_fprintf(f, "DR%d=3D%016" PRIx64 " ", i, env->dr[i]); + qemu_fprintf(f, "\nDR6=3D%016" PRIx64 " DR7=3D%016" PRIx64 "\n", + env->dr[6], env->dr[7]); + } else +#endif + { + qemu_fprintf(f, "GDT=3D %08x %08x\n", + (uint32_t)env->gdt.base, env->gdt.limit); + qemu_fprintf(f, "IDT=3D %08x %08x\n", + (uint32_t)env->idt.base, env->idt.limit); + qemu_fprintf(f, "CR0=3D%08x CR2=3D%08x CR3=3D%08x CR4=3D%08x\n", + (uint32_t)env->cr[0], + (uint32_t)env->cr[2], + (uint32_t)env->cr[3], + (uint32_t)env->cr[4]); + for(i =3D 0; i < 4; i++) { + qemu_fprintf(f, "DR%d=3D" TARGET_FMT_lx " ", i, env->dr[i]); + } + qemu_fprintf(f, "\nDR6=3D" TARGET_FMT_lx " DR7=3D" TARGET_FMT_lx "= \n", + env->dr[6], env->dr[7]); + } + if (flags & CPU_DUMP_CCOP) { + if ((unsigned)env->cc_op < CC_OP_NB) + snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->= cc_op]); + else + snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op); +#ifdef TARGET_X86_64 + if (env->hflags & HF_CS64_MASK) { + qemu_fprintf(f, "CCS=3D%016" PRIx64 " CCD=3D%016" PRIx64 " CCO= =3D%-8s\n", + env->cc_src, env->cc_dst, + cc_op_name); + } else +#endif + { + qemu_fprintf(f, "CCS=3D%08x CCD=3D%08x CCO=3D%-8s\n", + (uint32_t)env->cc_src, (uint32_t)env->cc_dst, + cc_op_name); + } + } + qemu_fprintf(f, "EFER=3D%016" PRIx64 "\n", env->efer); + if (flags & CPU_DUMP_FPU) { + int fptag; + fptag =3D 0; + for(i =3D 0; i < 8; i++) { + fptag |=3D ((!env->fptags[i]) << i); + } + update_mxcsr_from_sse_status(env); + qemu_fprintf(f, "FCW=3D%04x FSW=3D%04x [ST=3D%d] FTW=3D%02x MXCSR= =3D%08x\n", + env->fpuc, + (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11, + env->fpstt, + fptag, + env->mxcsr); + for(i=3D0;i<8;i++) { + CPU_LDoubleU u; + u.d =3D env->fpregs[i].d; + qemu_fprintf(f, "FPR%d=3D%016" PRIx64 " %04x", + i, u.l.lower, u.l.upper); + if ((i & 1) =3D=3D 1) + qemu_fprintf(f, "\n"); + else + qemu_fprintf(f, " "); + } + if (env->hflags & HF_CS64_MASK) + nb =3D 16; + else + nb =3D 8; + for(i=3D0;ixmm_regs[i].ZMM_L(3), + env->xmm_regs[i].ZMM_L(2), + env->xmm_regs[i].ZMM_L(1), + env->xmm_regs[i].ZMM_L(0)); + if ((i & 1) =3D=3D 1) + qemu_fprintf(f, "\n"); + else + qemu_fprintf(f, " "); + } + } + if (flags & CPU_DUMP_CODE) { + target_ulong base =3D env->segs[R_CS].base + env->eip; + target_ulong offs =3D MIN(env->eip, DUMP_CODE_BYTES_BACKWARD); + uint8_t code; + char codestr[3]; + + qemu_fprintf(f, "Code=3D"); + for (i =3D 0; i < DUMP_CODE_BYTES_TOTAL; i++) { + if (cpu_memory_rw_debug(cs, base - offs + i, &code, 1, 0) =3D= =3D 0) { + snprintf(codestr, sizeof(codestr), "%02x", code); + } else { + snprintf(codestr, sizeof(codestr), "??"); + } + qemu_fprintf(f, "%s%s%s%s", i > 0 ? " " : "", + i =3D=3D offs ? "<" : "", codestr, i =3D=3D offs = ? ">" : ""); + } + qemu_fprintf(f, "\n"); + } +} diff --git a/target/i386/helper.c b/target/i386/helper.c index a1b3367ab2..6e7e0f507c 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -21,8 +21,6 @@ #include "qapi/qapi-events-run-state.h" #include "cpu.h" #include "exec/exec-all.h" -#include "qemu/qemu-print.h" -#include "sysemu/kvm.h" #include "sysemu/runstate.h" #include "kvm/kvm_i386.h" #ifndef CONFIG_USER_ONLY @@ -88,518 +86,6 @@ int cpu_x86_support_mca_broadcast(CPUX86State *env) return 0; } =20 -/***********************************************************/ -/* x86 debug */ - -static const char *cc_op_str[CC_OP_NB] =3D { - "DYNAMIC", - "EFLAGS", - - "MULB", - "MULW", - "MULL", - "MULQ", - - "ADDB", - "ADDW", - "ADDL", - "ADDQ", - - "ADCB", - "ADCW", - "ADCL", - "ADCQ", - - "SUBB", - "SUBW", - "SUBL", - "SUBQ", - - "SBBB", - "SBBW", - "SBBL", - "SBBQ", - - "LOGICB", - "LOGICW", - "LOGICL", - "LOGICQ", - - "INCB", - "INCW", - "INCL", - "INCQ", - - "DECB", - "DECW", - "DECL", - "DECQ", - - "SHLB", - "SHLW", - "SHLL", - "SHLQ", - - "SARB", - "SARW", - "SARL", - "SARQ", - - "BMILGB", - "BMILGW", - "BMILGL", - "BMILGQ", - - "ADCX", - "ADOX", - "ADCOX", - - "CLR", -}; - -static void -cpu_x86_dump_seg_cache(CPUX86State *env, FILE *f, - const char *name, struct SegmentCache *sc) -{ -#ifdef TARGET_X86_64 - if (env->hflags & HF_CS64_MASK) { - qemu_fprintf(f, "%-3s=3D%04x %016" PRIx64 " %08x %08x", name, - sc->selector, sc->base, sc->limit, - sc->flags & 0x00ffff00); - } else -#endif - { - qemu_fprintf(f, "%-3s=3D%04x %08x %08x %08x", name, sc->selector, - (uint32_t)sc->base, sc->limit, - sc->flags & 0x00ffff00); - } - - if (!(env->hflags & HF_PE_MASK) || !(sc->flags & DESC_P_MASK)) - goto done; - - qemu_fprintf(f, " DPL=3D%d ", - (sc->flags & DESC_DPL_MASK) >> DESC_DPL_SHIFT); - if (sc->flags & DESC_S_MASK) { - if (sc->flags & DESC_CS_MASK) { - qemu_fprintf(f, (sc->flags & DESC_L_MASK) ? "CS64" : - ((sc->flags & DESC_B_MASK) ? "CS32" : "CS16")); - qemu_fprintf(f, " [%c%c", (sc->flags & DESC_C_MASK) ? 'C' : '-= ', - (sc->flags & DESC_R_MASK) ? 'R' : '-'); - } else { - qemu_fprintf(f, (sc->flags & DESC_B_MASK - || env->hflags & HF_LMA_MASK) - ? "DS " : "DS16"); - qemu_fprintf(f, " [%c%c", (sc->flags & DESC_E_MASK) ? 'E' : '-= ', - (sc->flags & DESC_W_MASK) ? 'W' : '-'); - } - qemu_fprintf(f, "%c]", (sc->flags & DESC_A_MASK) ? 'A' : '-'); - } else { - static const char *sys_type_name[2][16] =3D { - { /* 32 bit mode */ - "Reserved", "TSS16-avl", "LDT", "TSS16-busy", - "CallGate16", "TaskGate", "IntGate16", "TrapGate16", - "Reserved", "TSS32-avl", "Reserved", "TSS32-busy", - "CallGate32", "Reserved", "IntGate32", "TrapGate32" - }, - { /* 64 bit mode */ - "", "Reserved", "LDT", "Reserved", "Reserved", - "Reserved", "Reserved", "Reserved", "Reserved", - "TSS64-avl", "Reserved", "TSS64-busy", "CallGate64", - "Reserved", "IntGate64", "TrapGate64" - } - }; - qemu_fprintf(f, "%s", - sys_type_name[(env->hflags & HF_LMA_MASK) ? 1 : 0] - [(sc->flags & DESC_TYPE_MASK) >> DESC_TYPE_SHIFT]); - } -done: - qemu_fprintf(f, "\n"); -} - -#ifndef CONFIG_USER_ONLY - -/* ARRAY_SIZE check is not required because - * DeliveryMode(dm) has a size of 3 bit. - */ -static inline const char *dm2str(uint32_t dm) -{ - static const char *str[] =3D { - "Fixed", - "...", - "SMI", - "...", - "NMI", - "INIT", - "...", - "ExtINT" - }; - return str[dm]; -} - -static void dump_apic_lvt(const char *name, uint32_t lvt, bool is_timer) -{ - uint32_t dm =3D (lvt & APIC_LVT_DELIV_MOD) >> APIC_LVT_DELIV_MOD_SHIFT; - qemu_printf("%s\t 0x%08x %s %-5s %-6s %-7s %-12s %-6s", - name, lvt, - lvt & APIC_LVT_INT_POLARITY ? "active-lo" : "active-hi", - lvt & APIC_LVT_LEVEL_TRIGGER ? "level" : "edge", - lvt & APIC_LVT_MASKED ? "masked" : "", - lvt & APIC_LVT_DELIV_STS ? "pending" : "", - !is_timer ? - "" : lvt & APIC_LVT_TIMER_PERIODIC ? - "periodic" : lvt & APIC_LVT_TIMER_TSCDEADLINE ? - "tsc-deadline" : "one-shot", - dm2str(dm)); - if (dm !=3D APIC_DM_NMI) { - qemu_printf(" (vec %u)\n", lvt & APIC_VECTOR_MASK); - } else { - qemu_printf("\n"); - } -} - -/* ARRAY_SIZE check is not required because - * destination shorthand has a size of 2 bit. - */ -static inline const char *shorthand2str(uint32_t shorthand) -{ - const char *str[] =3D { - "no-shorthand", "self", "all-self", "all" - }; - return str[shorthand]; -} - -static inline uint8_t divider_conf(uint32_t divide_conf) -{ - uint8_t divide_val =3D ((divide_conf & 0x8) >> 1) | (divide_conf & 0x3= ); - - return divide_val =3D=3D 7 ? 1 : 2 << divide_val; -} - -static inline void mask2str(char *str, uint32_t val, uint8_t size) -{ - while (size--) { - *str++ =3D (val >> size) & 1 ? '1' : '0'; - } - *str =3D 0; -} - -#define MAX_LOGICAL_APIC_ID_MASK_SIZE 16 - -static void dump_apic_icr(APICCommonState *s, CPUX86State *env) -{ - uint32_t icr =3D s->icr[0], icr2 =3D s->icr[1]; - uint8_t dest_shorthand =3D \ - (icr & APIC_ICR_DEST_SHORT) >> APIC_ICR_DEST_SHORT_SHIFT; - bool logical_mod =3D icr & APIC_ICR_DEST_MOD; - char apic_id_str[MAX_LOGICAL_APIC_ID_MASK_SIZE + 1]; - uint32_t dest_field; - bool x2apic; - - qemu_printf("ICR\t 0x%08x %s %s %s %s\n", - icr, - logical_mod ? "logical" : "physical", - icr & APIC_ICR_TRIGGER_MOD ? "level" : "edge", - icr & APIC_ICR_LEVEL ? "assert" : "de-assert", - shorthand2str(dest_shorthand)); - - qemu_printf("ICR2\t 0x%08x", icr2); - if (dest_shorthand !=3D 0) { - qemu_printf("\n"); - return; - } - x2apic =3D env->features[FEAT_1_ECX] & CPUID_EXT_X2APIC; - dest_field =3D x2apic ? icr2 : icr2 >> APIC_ICR_DEST_SHIFT; - - if (!logical_mod) { - if (x2apic) { - qemu_printf(" cpu %u (X2APIC ID)\n", dest_field); - } else { - qemu_printf(" cpu %u (APIC ID)\n", - dest_field & APIC_LOGDEST_XAPIC_ID); - } - return; - } - - if (s->dest_mode =3D=3D 0xf) { /* flat mode */ - mask2str(apic_id_str, icr2 >> APIC_ICR_DEST_SHIFT, 8); - qemu_printf(" mask %s (APIC ID)\n", apic_id_str); - } else if (s->dest_mode =3D=3D 0) { /* cluster mode */ - if (x2apic) { - mask2str(apic_id_str, dest_field & APIC_LOGDEST_X2APIC_ID, 16); - qemu_printf(" cluster %u mask %s (X2APIC ID)\n", - dest_field >> APIC_LOGDEST_X2APIC_SHIFT, apic_id_s= tr); - } else { - mask2str(apic_id_str, dest_field & APIC_LOGDEST_XAPIC_ID, 4); - qemu_printf(" cluster %u mask %s (APIC ID)\n", - dest_field >> APIC_LOGDEST_XAPIC_SHIFT, apic_id_st= r); - } - } -} - -static void dump_apic_interrupt(const char *name, uint32_t *ireg_tab, - uint32_t *tmr_tab) -{ - int i, empty =3D true; - - qemu_printf("%s\t ", name); - for (i =3D 0; i < 256; i++) { - if (apic_get_bit(ireg_tab, i)) { - qemu_printf("%u%s ", i, - apic_get_bit(tmr_tab, i) ? "(level)" : ""); - empty =3D false; - } - } - qemu_printf("%s\n", empty ? "(none)" : ""); -} - -void x86_cpu_dump_local_apic_state(CPUState *cs, int flags) -{ - X86CPU *cpu =3D X86_CPU(cs); - APICCommonState *s =3D APIC_COMMON(cpu->apic_state); - if (!s) { - qemu_printf("local apic state not available\n"); - return; - } - uint32_t *lvt =3D s->lvt; - - qemu_printf("dumping local APIC state for CPU %-2u\n\n", - CPU(cpu)->cpu_index); - dump_apic_lvt("LVT0", lvt[APIC_LVT_LINT0], false); - dump_apic_lvt("LVT1", lvt[APIC_LVT_LINT1], false); - dump_apic_lvt("LVTPC", lvt[APIC_LVT_PERFORM], false); - dump_apic_lvt("LVTERR", lvt[APIC_LVT_ERROR], false); - dump_apic_lvt("LVTTHMR", lvt[APIC_LVT_THERMAL], false); - dump_apic_lvt("LVTT", lvt[APIC_LVT_TIMER], true); - - qemu_printf("Timer\t DCR=3D0x%x (divide by %u) initial_count =3D %u" - " current_count =3D %u\n", - s->divide_conf & APIC_DCR_MASK, - divider_conf(s->divide_conf), - s->initial_count, apic_get_current_count(s)); - - qemu_printf("SPIV\t 0x%08x APIC %s, focus=3D%s, spurious vec %u\n", - s->spurious_vec, - s->spurious_vec & APIC_SPURIO_ENABLED ? "enabled" : "disab= led", - s->spurious_vec & APIC_SPURIO_FOCUS ? "on" : "off", - s->spurious_vec & APIC_VECTOR_MASK); - - dump_apic_icr(s, &cpu->env); - - qemu_printf("ESR\t 0x%08x\n", s->esr); - - dump_apic_interrupt("ISR", s->isr, s->tmr); - dump_apic_interrupt("IRR", s->irr, s->tmr); - - qemu_printf("\nAPR 0x%02x TPR 0x%02x DFR 0x%02x LDR 0x%02x", - s->arb_id, s->tpr, s->dest_mode, s->log_dest); - if (s->dest_mode =3D=3D 0) { - qemu_printf("(cluster %u: id %u)", - s->log_dest >> APIC_LOGDEST_XAPIC_SHIFT, - s->log_dest & APIC_LOGDEST_XAPIC_ID); - } - qemu_printf(" PPR 0x%02x\n", apic_get_ppr(s)); -} -#else -void x86_cpu_dump_local_apic_state(CPUState *cs, int flags) -{ -} -#endif /* !CONFIG_USER_ONLY */ - -#define DUMP_CODE_BYTES_TOTAL 50 -#define DUMP_CODE_BYTES_BACKWARD 20 - -void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags) -{ - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - int eflags, i, nb; - char cc_op_name[32]; - static const char *seg_name[6] =3D { "ES", "CS", "SS", "DS", "FS", "GS= " }; - - eflags =3D cpu_compute_eflags(env); -#ifdef TARGET_X86_64 - if (env->hflags & HF_CS64_MASK) { - qemu_fprintf(f, "RAX=3D%016" PRIx64 " RBX=3D%016" PRIx64 " RCX=3D%= 016" PRIx64 " RDX=3D%016" PRIx64 "\n" - "RSI=3D%016" PRIx64 " RDI=3D%016" PRIx64 " RBP=3D%016= " PRIx64 " RSP=3D%016" PRIx64 "\n" - "R8 =3D%016" PRIx64 " R9 =3D%016" PRIx64 " R10=3D%016= " PRIx64 " R11=3D%016" PRIx64 "\n" - "R12=3D%016" PRIx64 " R13=3D%016" PRIx64 " R14=3D%016= " PRIx64 " R15=3D%016" PRIx64 "\n" - "RIP=3D%016" PRIx64 " RFL=3D%08x [%c%c%c%c%c%c%c] CPL= =3D%d II=3D%d A20=3D%d SMM=3D%d HLT=3D%d\n", - env->regs[R_EAX], - env->regs[R_EBX], - env->regs[R_ECX], - env->regs[R_EDX], - env->regs[R_ESI], - env->regs[R_EDI], - env->regs[R_EBP], - env->regs[R_ESP], - env->regs[8], - env->regs[9], - env->regs[10], - env->regs[11], - env->regs[12], - env->regs[13], - env->regs[14], - env->regs[15], - env->eip, eflags, - eflags & DF_MASK ? 'D' : '-', - eflags & CC_O ? 'O' : '-', - eflags & CC_S ? 'S' : '-', - eflags & CC_Z ? 'Z' : '-', - eflags & CC_A ? 'A' : '-', - eflags & CC_P ? 'P' : '-', - eflags & CC_C ? 'C' : '-', - env->hflags & HF_CPL_MASK, - (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1, - (env->a20_mask >> 20) & 1, - (env->hflags >> HF_SMM_SHIFT) & 1, - cs->halted); - } else -#endif - { - qemu_fprintf(f, "EAX=3D%08x EBX=3D%08x ECX=3D%08x EDX=3D%08x\n" - "ESI=3D%08x EDI=3D%08x EBP=3D%08x ESP=3D%08x\n" - "EIP=3D%08x EFL=3D%08x [%c%c%c%c%c%c%c] CPL=3D%d II= =3D%d A20=3D%d SMM=3D%d HLT=3D%d\n", - (uint32_t)env->regs[R_EAX], - (uint32_t)env->regs[R_EBX], - (uint32_t)env->regs[R_ECX], - (uint32_t)env->regs[R_EDX], - (uint32_t)env->regs[R_ESI], - (uint32_t)env->regs[R_EDI], - (uint32_t)env->regs[R_EBP], - (uint32_t)env->regs[R_ESP], - (uint32_t)env->eip, eflags, - eflags & DF_MASK ? 'D' : '-', - eflags & CC_O ? 'O' : '-', - eflags & CC_S ? 'S' : '-', - eflags & CC_Z ? 'Z' : '-', - eflags & CC_A ? 'A' : '-', - eflags & CC_P ? 'P' : '-', - eflags & CC_C ? 'C' : '-', - env->hflags & HF_CPL_MASK, - (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1, - (env->a20_mask >> 20) & 1, - (env->hflags >> HF_SMM_SHIFT) & 1, - cs->halted); - } - - for(i =3D 0; i < 6; i++) { - cpu_x86_dump_seg_cache(env, f, seg_name[i], &env->segs[i]); - } - cpu_x86_dump_seg_cache(env, f, "LDT", &env->ldt); - cpu_x86_dump_seg_cache(env, f, "TR", &env->tr); - -#ifdef TARGET_X86_64 - if (env->hflags & HF_LMA_MASK) { - qemu_fprintf(f, "GDT=3D %016" PRIx64 " %08x\n", - env->gdt.base, env->gdt.limit); - qemu_fprintf(f, "IDT=3D %016" PRIx64 " %08x\n", - env->idt.base, env->idt.limit); - qemu_fprintf(f, "CR0=3D%08x CR2=3D%016" PRIx64 " CR3=3D%016" PRIx6= 4 " CR4=3D%08x\n", - (uint32_t)env->cr[0], - env->cr[2], - env->cr[3], - (uint32_t)env->cr[4]); - for(i =3D 0; i < 4; i++) - qemu_fprintf(f, "DR%d=3D%016" PRIx64 " ", i, env->dr[i]); - qemu_fprintf(f, "\nDR6=3D%016" PRIx64 " DR7=3D%016" PRIx64 "\n", - env->dr[6], env->dr[7]); - } else -#endif - { - qemu_fprintf(f, "GDT=3D %08x %08x\n", - (uint32_t)env->gdt.base, env->gdt.limit); - qemu_fprintf(f, "IDT=3D %08x %08x\n", - (uint32_t)env->idt.base, env->idt.limit); - qemu_fprintf(f, "CR0=3D%08x CR2=3D%08x CR3=3D%08x CR4=3D%08x\n", - (uint32_t)env->cr[0], - (uint32_t)env->cr[2], - (uint32_t)env->cr[3], - (uint32_t)env->cr[4]); - for(i =3D 0; i < 4; i++) { - qemu_fprintf(f, "DR%d=3D" TARGET_FMT_lx " ", i, env->dr[i]); - } - qemu_fprintf(f, "\nDR6=3D" TARGET_FMT_lx " DR7=3D" TARGET_FMT_lx "= \n", - env->dr[6], env->dr[7]); - } - if (flags & CPU_DUMP_CCOP) { - if ((unsigned)env->cc_op < CC_OP_NB) - snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->= cc_op]); - else - snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op); -#ifdef TARGET_X86_64 - if (env->hflags & HF_CS64_MASK) { - qemu_fprintf(f, "CCS=3D%016" PRIx64 " CCD=3D%016" PRIx64 " CCO= =3D%-8s\n", - env->cc_src, env->cc_dst, - cc_op_name); - } else -#endif - { - qemu_fprintf(f, "CCS=3D%08x CCD=3D%08x CCO=3D%-8s\n", - (uint32_t)env->cc_src, (uint32_t)env->cc_dst, - cc_op_name); - } - } - qemu_fprintf(f, "EFER=3D%016" PRIx64 "\n", env->efer); - if (flags & CPU_DUMP_FPU) { - int fptag; - fptag =3D 0; - for(i =3D 0; i < 8; i++) { - fptag |=3D ((!env->fptags[i]) << i); - } - update_mxcsr_from_sse_status(env); - qemu_fprintf(f, "FCW=3D%04x FSW=3D%04x [ST=3D%d] FTW=3D%02x MXCSR= =3D%08x\n", - env->fpuc, - (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11, - env->fpstt, - fptag, - env->mxcsr); - for(i=3D0;i<8;i++) { - CPU_LDoubleU u; - u.d =3D env->fpregs[i].d; - qemu_fprintf(f, "FPR%d=3D%016" PRIx64 " %04x", - i, u.l.lower, u.l.upper); - if ((i & 1) =3D=3D 1) - qemu_fprintf(f, "\n"); - else - qemu_fprintf(f, " "); - } - if (env->hflags & HF_CS64_MASK) - nb =3D 16; - else - nb =3D 8; - for(i=3D0;ixmm_regs[i].ZMM_L(3), - env->xmm_regs[i].ZMM_L(2), - env->xmm_regs[i].ZMM_L(1), - env->xmm_regs[i].ZMM_L(0)); - if ((i & 1) =3D=3D 1) - qemu_fprintf(f, "\n"); - else - qemu_fprintf(f, " "); - } - } - if (flags & CPU_DUMP_CODE) { - target_ulong base =3D env->segs[R_CS].base + env->eip; - target_ulong offs =3D MIN(env->eip, DUMP_CODE_BYTES_BACKWARD); - uint8_t code; - char codestr[3]; - - qemu_fprintf(f, "Code=3D"); - for (i =3D 0; i < DUMP_CODE_BYTES_TOTAL; i++) { - if (cpu_memory_rw_debug(cs, base - offs + i, &code, 1, 0) =3D= =3D 0) { - snprintf(codestr, sizeof(codestr), "%02x", code); - } else { - snprintf(codestr, sizeof(codestr), "??"); - } - qemu_fprintf(f, "%s%s%s%s", i > 0 ? " " : "", - i =3D=3D offs ? "<" : "", codestr, i =3D=3D offs = ? ">" : ""); - } - qemu_fprintf(f, "\n"); - } -} - /***********************************************************/ /* x86 mmu */ /* XXX: add PGE support */ diff --git a/target/i386/meson.build b/target/i386/meson.build index 750471c9f3..c4bf20b319 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -4,6 +4,7 @@ i386_ss.add(files( 'gdbstub.c', 'helper.c', 'xsave_helper.c', + 'cpu-dump.c', )) i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('= sev-stub.c')) =20 --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607603574; cv=none; d=zohomail.com; s=zohoarc; b=KJ+Xj8qYtqZg6uM/q3tJh6oM37izkS1MDGTTwy/UX8p+npZeC5HwyKOo8gN26NV0GYlxe9JonW+QW9v0j3SmLbZBXYJVBcjnW/T6JwO4aJpHdALXf8JDDfZf0JrbeGReNwet1fW8RA1p+D9jV8bBQG0aZ02NVYaZuHizpKzezwQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607603574; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dKkOSYuQjcweEMj1oYA3iRVIq7VlLJMvoi4Y/CZX9Ok=; b=f1gwmBkbbmiJBu8tMQaPj9L+A+eHrFH9JuHeoMWe/LKCVcPXuCnTGr6FfjqhQWgMFBs4UFfZ0cJhYqD6ykmKXuEHWuW9BM8qLXUER+dFYl9p+u5b3cpYIgDZU8B/Fr30pey9ufhTthYalB94VE5OhDJJ0zU0pfqfjznU4qWhy34= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607603574013112.93302770362436; Thu, 10 Dec 2020 04:32:54 -0800 (PST) Received: from localhost ([::1]:34460 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knL7s-0006z1-MU for importer@patchew.org; Thu, 10 Dec 2020 07:32:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56500) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoY-0002Nf-VM for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:12:55 -0500 Received: from mx2.suse.de ([195.135.220.15]:47328) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoU-0006ST-Tg for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:12:54 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 8FA9CAD5C; Thu, 10 Dec 2020 12:12:39 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 10/32] i386: move TCG cpu class initialization out of helper.c Date: Thu, 10 Dec 2020 13:12:04 +0100 Message-Id: <20201210121226.19822-11-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: Claudio Fontana --- target/i386/cpu.h | 97 ++--------------------------- target/i386/tcg/helper-tcg.h | 112 ++++++++++++++++++++++++++++++++++ target/i386/tcg/tcg-cpu.h | 15 +++++ target/i386/cpu.c | 33 ++++------ target/i386/helper.c | 23 ------- target/i386/tcg/bpt_helper.c | 1 + target/i386/tcg/cc_helper.c | 1 + target/i386/tcg/excp_helper.c | 1 + target/i386/tcg/fpu_helper.c | 33 +++++----- target/i386/tcg/int_helper.c | 1 + target/i386/tcg/mem_helper.c | 1 + target/i386/tcg/misc_helper.c | 1 + target/i386/tcg/mpx_helper.c | 1 + target/i386/tcg/seg_helper.c | 1 + target/i386/tcg/smm_helper.c | 2 + target/i386/tcg/svm_helper.c | 1 + target/i386/tcg/tcg-cpu.c | 71 +++++++++++++++++++++ target/i386/tcg/translate.c | 1 + target/i386/tcg/meson.build | 1 + 19 files changed, 244 insertions(+), 153 deletions(-) create mode 100644 target/i386/tcg/helper-tcg.h create mode 100644 target/i386/tcg/tcg-cpu.h create mode 100644 target/i386/tcg/tcg-cpu.c diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d6ed45c5d7..a0d64613dc 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -31,9 +31,6 @@ =20 #define KVM_HAVE_MCE_INJECTION 1 =20 -/* Maximum instruction code size */ -#define TARGET_MAX_INSN_SIZE 16 - /* support for self modifying code even if the modified instruction is close to the modifying instruction */ #define TARGET_HAS_PRECISE_SMC @@ -1037,6 +1034,12 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; * using this information. Condition codes are not generated if they * are only needed for conditional branches. */ + +#define CC_DST (env->cc_dst) +#define CC_SRC (env->cc_src) +#define CC_SRC2 (env->cc_src2) +#define CC_OP (env->cc_op) + typedef enum { CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC =3D flags */ @@ -1765,12 +1768,6 @@ struct X86CPU { extern VMStateDescription vmstate_x86_cpu; #endif =20 -/** - * x86_cpu_do_interrupt: - * @cpu: vCPU the interrupt is to be handled by. - */ -void x86_cpu_do_interrupt(CPUState *cpu); -bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); =20 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, @@ -1793,9 +1790,6 @@ hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cp= u, vaddr addr, int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); =20 -void x86_cpu_exec_enter(CPUState *cpu); -void x86_cpu_exec_exit(CPUState *cpu); - void x86_cpu_list(void); int cpu_x86_support_mca_broadcast(CPUX86State *env); =20 @@ -1920,9 +1914,6 @@ void host_cpuid(uint32_t function, uint32_t count, void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); =20 /* helper.c */ -bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); void x86_cpu_set_a20(X86CPU *cpu, int a20_state); =20 #ifndef CONFIG_USER_ONLY @@ -1947,8 +1938,6 @@ void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t= val); void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); #endif =20 -void breakpoint_handler(CPUState *cs); - /* will be suppressed */ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); @@ -1958,16 +1947,6 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t n= ew_dr7); /* hw/pc.c */ uint64_t cpu_get_tsc(CPUX86State *env); =20 -/* XXX: This value should match the one returned by CPUID - * and in exec.c */ -# if defined(TARGET_X86_64) -# define TCG_PHYS_ADDR_BITS 40 -# else -# define TCG_PHYS_ADDR_BITS 36 -# endif - -#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS) - #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_X86_CPU @@ -1999,30 +1978,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *= env) ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; } =20 -#define CC_DST (env->cc_dst) -#define CC_SRC (env->cc_src) -#define CC_SRC2 (env->cc_src2) -#define CC_OP (env->cc_op) - -/* n must be a constant to be efficient */ -static inline target_long lshift(target_long x, int n) -{ - if (n >=3D 0) { - return x << n; - } else { - return x >> (-n); - } -} - -/* float macros */ -#define FT0 (env->ft0) -#define ST0 (env->fpregs[env->fpstt].d) -#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) -#define ST1 ST(1) - -/* translate.c */ -void tcg_x86_init(void); - typedef CPUX86State CPUArchState; typedef X86CPU ArchCPU; =20 @@ -2052,19 +2007,6 @@ void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, i= nt bank, uint64_t status, uint64_t mcg_status, uint64_t add= r, uint64_t misc, int flags); =20 -/* excp_helper.c */ -void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); -void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_inde= x, - uintptr_t retaddr); -void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_ind= ex, - int error_code); -void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_= index, - int error_code, uintptr_t retadd= r); -void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_in= t, - int error_code, int next_eip_addend); - -/* cc_helper.c */ -extern const uint8_t parity_table[256]; uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); =20 static inline uint32_t cpu_compute_eflags(CPUX86State *env) @@ -2076,18 +2018,6 @@ static inline uint32_t cpu_compute_eflags(CPUX86Stat= e *env) return eflags; } =20 -/* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS - * after generating a call to a helper that uses this. - */ -static inline void cpu_load_eflags(CPUX86State *env, int eflags, - int update_mask) -{ - CC_SRC =3D eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); - CC_OP =3D CC_OP_EFLAGS; - env->df =3D 1 - (2 * ((eflags >> 10) & 1)); - env->eflags =3D (env->eflags & ~update_mask) | - (eflags & update_mask) | 0x2; -} =20 /* load efer and update the corresponding hflags. XXX: do consistency checks with cpuid bits? */ @@ -2176,16 +2106,6 @@ void helper_lock_init(void); /* svm_helper.c */ void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, uint64_t param, uintptr_t retaddr); -void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, - uint64_t exit_info_1, uintptr_t retaddr); -void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1); - -/* seg_helper.c */ -void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); - -/* smm_helper.c */ -void do_smm_enter(X86CPU *cpu); - /* apic.c */ void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, @@ -2224,11 +2144,6 @@ typedef int X86CPUVersion; */ void x86_cpu_set_default_version(X86CPUVersion version); =20 -/* Return name of 32-bit register, from a R_* constant */ -const char *get_register_name_32(unsigned int reg); - -void enable_compat_apic_id_mode(void); - #define APIC_DEFAULT_ADDRESS 0xfee00000 #define APIC_SPACE_SIZE 0x100000 =20 diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h new file mode 100644 index 0000000000..57b4391a7d --- /dev/null +++ b/target/i386/tcg/helper-tcg.h @@ -0,0 +1,112 @@ +/* + * TCG specific prototypes for helpers + * + * Copyright (c) 2003 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef I386_HELPER_TCG_H +#define I386_HELPER_TCG_H + +#include "exec/exec-all.h" + +/* Maximum instruction code size */ +#define TARGET_MAX_INSN_SIZE 16 + +/* + * XXX: This value should match the one returned by CPUID + * and in exec.c + */ +# if defined(TARGET_X86_64) +# define TCG_PHYS_ADDR_BITS 40 +# else +# define TCG_PHYS_ADDR_BITS 36 +# endif + +#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS) + +/** + * x86_cpu_do_interrupt: + * @cpu: vCPU the interrupt is to be handled by. + */ +void x86_cpu_do_interrupt(CPUState *cpu); +bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); + +/* helper.c */ +bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + +void breakpoint_handler(CPUState *cs); + +/* n must be a constant to be efficient */ +static inline target_long lshift(target_long x, int n) +{ + if (n >=3D 0) { + return x << n; + } else { + return x >> (-n); + } +} + +/* float macros */ +#define FT0 (env->ft0) +#define ST0 (env->fpregs[env->fpstt].d) +#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) +#define ST1 ST(1) + +/* translate.c */ +void tcg_x86_init(void); + +/* excp_helper.c */ +void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); +void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_inde= x, + uintptr_t retaddr); +void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_ind= ex, + int error_code); +void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_= index, + int error_code, uintptr_t retadd= r); +void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_in= t, + int error_code, int next_eip_addend); + +/* cc_helper.c */ +extern const uint8_t parity_table[256]; + +/* + * NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS + * after generating a call to a helper that uses this. + */ +static inline void cpu_load_eflags(CPUX86State *env, int eflags, + int update_mask) +{ + CC_SRC =3D eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); + CC_OP =3D CC_OP_EFLAGS; + env->df =3D 1 - (2 * ((eflags >> 10) & 1)); + env->eflags =3D (env->eflags & ~update_mask) | + (eflags & update_mask) | 0x2; +} + +/* svm_helper.c */ +void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, + uint64_t exit_info_1, uintptr_t retaddr); +void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1); + +/* seg_helper.c */ +void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); + +/* smm_helper.c */ +void do_smm_enter(X86CPU *cpu); + +#endif /* I386_HELPER_TCG_H */ diff --git a/target/i386/tcg/tcg-cpu.h b/target/i386/tcg/tcg-cpu.h new file mode 100644 index 0000000000..81f02e562e --- /dev/null +++ b/target/i386/tcg/tcg-cpu.h @@ -0,0 +1,15 @@ +/* + * i386 TCG CPU class initialization + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef TCG_CPU_H +#define TCG_CPU_H + +void tcg_cpu_common_class_init(CPUClass *cc); + +#endif /* TCG_CPU_H */ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b9bd249c8f..f0aa6d1841 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -24,6 +24,8 @@ #include "qemu/qemu-print.h" =20 #include "cpu.h" +#include "tcg/tcg-cpu.h" +#include "tcg/helper-tcg.h" #include "exec/exec-all.h" #include "sysemu/kvm.h" #include "sysemu/reset.h" @@ -1495,7 +1497,8 @@ static inline uint64_t x86_cpu_xsave_components(X86CP= U *cpu) cpu->env.features[FEAT_XSAVE_COMP_LO]; } =20 -const char *get_register_name_32(unsigned int reg) +/* Return name of 32-bit register, from a R_* constant */ +static const char *get_register_name_32(unsigned int reg) { if (reg >=3D CPU_NB_REGS32) { return NULL; @@ -7012,13 +7015,6 @@ static void x86_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.eip =3D value; } =20 -static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) -{ - X86CPU *cpu =3D X86_CPU(cs); - - cpu->env.eip =3D tb->pc - tb->cs_base; -} - int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) { X86CPU *cpu =3D X86_CPU(cs); @@ -7252,17 +7248,18 @@ static void x86_cpu_common_class_init(ObjectClass *= oc, void *data) cc->class_by_name =3D x86_cpu_class_by_name; cc->parse_features =3D x86_cpu_parse_featurestr; cc->has_work =3D x86_cpu_has_work; + #ifdef CONFIG_TCG - cc->do_interrupt =3D x86_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D x86_cpu_exec_interrupt; -#endif + tcg_cpu_common_class_init(cc); +#endif /* CONFIG_TCG */ + cc->dump_state =3D x86_cpu_dump_state; cc->set_pc =3D x86_cpu_set_pc; - cc->synchronize_from_tb =3D x86_cpu_synchronize_from_tb; cc->gdb_read_register =3D x86_cpu_gdb_read_register; cc->gdb_write_register =3D x86_cpu_gdb_write_register; cc->get_arch_id =3D x86_cpu_get_arch_id; cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; + #ifndef CONFIG_USER_ONLY cc->asidx_from_attrs =3D x86_asidx_from_attrs; cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; @@ -7273,7 +7270,8 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->write_elf32_note =3D x86_cpu_write_elf32_note; cc->write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote; cc->vmsd =3D &vmstate_x86_cpu; -#endif +#endif /* !CONFIG_USER_ONLY */ + cc->gdb_arch_name =3D x86_gdb_arch_name; #ifdef TARGET_X86_64 cc->gdb_core_xml_file =3D "i386-64bit.xml"; @@ -7281,15 +7279,6 @@ static void x86_cpu_common_class_init(ObjectClass *o= c, void *data) #else cc->gdb_core_xml_file =3D "i386-32bit.xml"; cc->gdb_num_core_regs =3D 50; -#endif -#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) - cc->debug_excp_handler =3D breakpoint_handler; -#endif - cc->cpu_exec_enter =3D x86_cpu_exec_enter; - cc->cpu_exec_exit =3D x86_cpu_exec_exit; -#ifdef CONFIG_TCG - cc->tcg_initialize =3D tcg_x86_init; - cc->tlb_fill =3D x86_cpu_tlb_fill; #endif cc->disas_set_info =3D x86_disas_set_info; =20 diff --git a/target/i386/helper.c b/target/i386/helper.c index 6e7e0f507c..6bb0c53182 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -24,10 +24,8 @@ #include "sysemu/runstate.h" #include "kvm/kvm_i386.h" #ifndef CONFIG_USER_ONLY -#include "sysemu/tcg.h" #include "sysemu/hw_accel.h" #include "monitor/monitor.h" -#include "hw/i386/apic_internal.h" #endif =20 void cpu_sync_bndcs_hflags(CPUX86State *env) @@ -572,27 +570,6 @@ void do_cpu_sipi(X86CPU *cpu) } #endif =20 -/* Frob eflags into and out of the CPU temporary format. */ - -void x86_cpu_exec_enter(CPUState *cs) -{ - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - - CC_SRC =3D env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); - env->df =3D 1 - (2 * ((env->eflags >> 10) & 1)); - CC_OP =3D CC_OP_EFLAGS; - env->eflags &=3D ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); -} - -void x86_cpu_exec_exit(CPUState *cs) -{ - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - - env->eflags =3D cpu_compute_eflags(env); -} - #ifndef CONFIG_USER_ONLY uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr) { diff --git a/target/i386/tcg/bpt_helper.c b/target/i386/tcg/bpt_helper.c index e6cc2921e2..979230ac12 100644 --- a/target/i386/tcg/bpt_helper.c +++ b/target/i386/tcg/bpt_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" +#include "helper-tcg.h" =20 =20 #ifndef CONFIG_USER_ONLY diff --git a/target/i386/tcg/cc_helper.c b/target/i386/tcg/cc_helper.c index 924dd3cd57..cc7ea9e8b9 100644 --- a/target/i386/tcg/cc_helper.c +++ b/target/i386/tcg/cc_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" +#include "helper-tcg.h" =20 const uint8_t parity_table[256] =3D { CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, diff --git a/target/i386/tcg/excp_helper.c b/target/i386/tcg/excp_helper.c index 191471749f..a0f44431fe 100644 --- a/target/i386/tcg/excp_helper.c +++ b/target/i386/tcg/excp_helper.c @@ -23,6 +23,7 @@ #include "qemu/log.h" #include "sysemu/runstate.h" #include "exec/helper-proto.h" +#include "helper-tcg.h" =20 void helper_raise_interrupt(CPUX86State *env, int intno, int next_eip_adde= nd) { diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 03b35443a6..13f31b6ac7 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -26,6 +26,7 @@ #include "exec/cpu_ldst.h" #include "fpu/softfloat.h" #include "fpu/softfloat-macros.h" +#include "helper-tcg.h" =20 #ifdef CONFIG_SOFTMMU #include "hw/irq.h" @@ -2986,23 +2987,21 @@ void update_mxcsr_status(CPUX86State *env) =20 void update_mxcsr_from_sse_status(CPUX86State *env) { - if (tcg_enabled()) { - uint8_t flags =3D get_float_exception_flags(&env->sse_status); - /* - * The MXCSR denormal flag has opposite semantics to - * float_flag_input_denormal (the softfloat code sets that flag - * only when flushing input denormals to zero, but SSE sets it - * only when not flushing them to zero), so is not converted - * here. - */ - env->mxcsr |=3D ((flags & float_flag_invalid ? FPUS_IE : 0) | - (flags & float_flag_divbyzero ? FPUS_ZE : 0) | - (flags & float_flag_overflow ? FPUS_OE : 0) | - (flags & float_flag_underflow ? FPUS_UE : 0) | - (flags & float_flag_inexact ? FPUS_PE : 0) | - (flags & float_flag_output_denormal ? FPUS_UE | FPU= S_PE : - 0)); - } + uint8_t flags =3D get_float_exception_flags(&env->sse_status); + /* + * The MXCSR denormal flag has opposite semantics to + * float_flag_input_denormal (the softfloat code sets that flag + * only when flushing input denormals to zero, but SSE sets it + * only when not flushing them to zero), so is not converted + * here. + */ + env->mxcsr |=3D ((flags & float_flag_invalid ? FPUS_IE : 0) | + (flags & float_flag_divbyzero ? FPUS_ZE : 0) | + (flags & float_flag_overflow ? FPUS_OE : 0) | + (flags & float_flag_underflow ? FPUS_UE : 0) | + (flags & float_flag_inexact ? FPUS_PE : 0) | + (flags & float_flag_output_denormal ? FPUS_UE | FPUS_PE= : + 0)); } =20 void helper_update_mxcsr(CPUX86State *env) diff --git a/target/i386/tcg/int_helper.c b/target/i386/tcg/int_helper.c index 4f89436b53..87fa7280ee 100644 --- a/target/i386/tcg/int_helper.c +++ b/target/i386/tcg/int_helper.c @@ -24,6 +24,7 @@ #include "exec/helper-proto.h" #include "qapi/error.h" #include "qemu/guest-random.h" +#include "helper-tcg.h" =20 //#define DEBUG_MULDIV =20 diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c index 21ca3e3e88..e5cd2de1bf 100644 --- a/target/i386/tcg/mem_helper.c +++ b/target/i386/tcg/mem_helper.c @@ -25,6 +25,7 @@ #include "qemu/int128.h" #include "qemu/atomic128.h" #include "tcg/tcg.h" +#include "helper-tcg.h" =20 void helper_cmpxchg8b_unlocked(CPUX86State *env, target_ulong a0) { diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c index ae259d9145..c99370e5e3 100644 --- a/target/i386/tcg/misc_helper.c +++ b/target/i386/tcg/misc_helper.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "exec/address-spaces.h" +#include "helper-tcg.h" =20 void helper_outb(CPUX86State *env, uint32_t port, uint32_t data) { diff --git a/target/i386/tcg/mpx_helper.c b/target/i386/tcg/mpx_helper.c index fd966174b4..22423eedcd 100644 --- a/target/i386/tcg/mpx_helper.c +++ b/target/i386/tcg/mpx_helper.c @@ -22,6 +22,7 @@ #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "exec/exec-all.h" +#include "helper-tcg.h" =20 =20 void helper_bndck(CPUX86State *env, uint32_t fail) diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index 09b6554660..ed3e04a187 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -25,6 +25,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "exec/log.h" +#include "helper-tcg.h" =20 //#define DEBUG_PCALL =20 diff --git a/target/i386/tcg/smm_helper.c b/target/i386/tcg/smm_helper.c index d20e8edfdf..62d027abd3 100644 --- a/target/i386/tcg/smm_helper.c +++ b/target/i386/tcg/smm_helper.c @@ -22,6 +22,8 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/log.h" +#include "helper-tcg.h" + =20 /* SMM support */ =20 diff --git a/target/i386/tcg/svm_helper.c b/target/i386/tcg/svm_helper.c index 38931586e5..097bb9b83d 100644 --- a/target/i386/tcg/svm_helper.c +++ b/target/i386/tcg/svm_helper.c @@ -22,6 +22,7 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" +#include "helper-tcg.h" =20 /* Secure Virtual Machine helpers */ =20 diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c new file mode 100644 index 0000000000..628dd29fe7 --- /dev/null +++ b/target/i386/tcg/tcg-cpu.c @@ -0,0 +1,71 @@ +/* + * i386 TCG cpu class initialization + * + * Copyright (c) 2003 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "tcg-cpu.h" +#include "exec/exec-all.h" +#include "sysemu/runstate.h" +#include "helper-tcg.h" + +#if !defined(CONFIG_USER_ONLY) +#include "hw/i386/apic.h" +#endif + +/* Frob eflags into and out of the CPU temporary format. */ + +static void x86_cpu_exec_enter(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + + CC_SRC =3D env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); + env->df =3D 1 - (2 * ((env->eflags >> 10) & 1)); + CC_OP =3D CC_OP_EFLAGS; + env->eflags &=3D ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); +} + +static void x86_cpu_exec_exit(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + + env->eflags =3D cpu_compute_eflags(env); +} + +static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +{ + X86CPU *cpu =3D X86_CPU(cs); + + cpu->env.eip =3D tb->pc - tb->cs_base; +} + +void tcg_cpu_common_class_init(CPUClass *cc) +{ + cc->do_interrupt =3D x86_cpu_do_interrupt; + cc->cpu_exec_interrupt =3D x86_cpu_exec_interrupt; + cc->synchronize_from_tb =3D x86_cpu_synchronize_from_tb; + cc->cpu_exec_enter =3D x86_cpu_exec_enter; + cc->cpu_exec_exit =3D x86_cpu_exec_exit; + cc->tcg_initialize =3D tcg_x86_init; + cc->tlb_fill =3D x86_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY + cc->debug_excp_handler =3D breakpoint_handler; +#endif +} diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 4c57307e42..5988ea0289 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -28,6 +28,7 @@ =20 #include "exec/helper-proto.h" #include "exec/helper-gen.h" +#include "helper-tcg.h" =20 #include "trace-tcg.h" #include "exec/log.h" diff --git a/target/i386/tcg/meson.build b/target/i386/tcg/meson.build index 02794226c2..6a1a73cdbf 100644 --- a/target/i386/tcg/meson.build +++ b/target/i386/tcg/meson.build @@ -10,4 +10,5 @@ i386_ss.add(when: 'CONFIG_TCG', if_true: files( 'seg_helper.c', 'smm_helper.c', 'svm_helper.c', + 'tcg-cpu.c', 'translate.c'), if_false: files('tcg-stub.c')) --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 10 Dec 2020 04:27:11 -0800 (PST) Received: from localhost ([::1]:47326 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knL2M-0000jm-Mf for importer@patchew.org; Thu, 10 Dec 2020 07:27:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56472) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoX-0002MJ-Gs for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:12:53 -0500 Received: from mx2.suse.de ([195.135.220.15]:47358) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoV-0006T9-To for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:12:53 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 9B146AD3F; Thu, 10 Dec 2020 12:12:40 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 11/32] tcg: cpu_exec_{enter,exit} helpers Date: Thu, 10 Dec 2020 13:12:05 +0100 Message-Id: <20201210121226.19822-12-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; 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Cota" , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Eduardo Habkost Move invocation of CPUClass.cpu_exec_*() to separate helpers, to make it easier to refactor that code later. Signed-off-by: Eduardo Habkost Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e --- accel/tcg/cpu-exec.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 58aea605d8..8d31145ad2 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -236,9 +236,22 @@ static void cpu_exec_nocache(CPUState *cpu, int max_cy= cles, } #endif =20 +static void cpu_exec_enter(CPUState *cpu) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + cc->cpu_exec_enter(cpu); +} + +static void cpu_exec_exit(CPUState *cpu) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + cc->cpu_exec_exit(cpu); +} + void cpu_exec_step_atomic(CPUState *cpu) { - CPUClass *cc =3D CPU_GET_CLASS(cpu); TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; @@ -257,11 +270,11 @@ void cpu_exec_step_atomic(CPUState *cpu) =20 /* Since we got here, we know that parallel_cpus must be true. */ parallel_cpus =3D false; - cc->cpu_exec_enter(cpu); + cpu_exec_enter(cpu); /* execute the generated code */ trace_exec_tb(tb, pc); cpu_tb_exec(cpu, tb); - cc->cpu_exec_exit(cpu); + cpu_exec_exit(cpu); } else { /* * The mmap_lock is dropped by tb_gen_code if it runs out of @@ -713,7 +726,7 @@ int cpu_exec(CPUState *cpu) =20 rcu_read_lock(); =20 - cc->cpu_exec_enter(cpu); + cpu_exec_enter(cpu); =20 /* Calculate difference between guest clock and host clock. * This delay includes the delay of the last cycle, so @@ -775,7 +788,7 @@ int cpu_exec(CPUState *cpu) } } =20 - cc->cpu_exec_exit(cpu); + cpu_exec_exit(cpu); rcu_read_unlock(); =20 return ret; --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607603570; cv=none; d=zohomail.com; s=zohoarc; b=niYEfb5oqSAHPm6D3rZzisk8edvbRKeYIev5jkgdFabxdDQBN8JqyfKq7vV6b0jyZarCn3cex1e7TgLHyOSDxsBeIPzKTTYHvIce2+/r6tEl/kjB7kiw9Xhx1vz82MzO2BQ72ndE607/TaXjIr34lEOgbi//oPP7tY7OXFLEjaI= ARC-Message-Signature: i=1; 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Thu, 10 Dec 2020 07:32:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56520) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoa-0002OF-0Q for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:12:56 -0500 Received: from mx2.suse.de ([195.135.220.15]:47396) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoW-0006TX-Ui for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:12:55 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id A64F3AD45; Thu, 10 Dec 2020 12:12:41 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 12/32] tcg: make CPUClass.cpu_exec_* optional Date: Thu, 10 Dec 2020 13:12:06 +0100 Message-Id: <20201210121226.19822-13-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Colin Xu , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Eduardo Habkost This will let us simplify the code that initializes CPU class methods, when we move cpu_exec_*() to a separate struct. Signed-off-by: Eduardo Habkost Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e --- accel/tcg/cpu-exec.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 8d31145ad2..890b88861a 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -240,14 +240,18 @@ static void cpu_exec_enter(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - cc->cpu_exec_enter(cpu); + if (cc->cpu_exec_enter) { + cc->cpu_exec_enter(cpu); + } } =20 static void cpu_exec_exit(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - cc->cpu_exec_exit(cpu); + if (cc->cpu_exec_exit) { + cc->cpu_exec_exit(cpu); + } } =20 void cpu_exec_step_atomic(CPUState *cpu) @@ -619,7 +623,8 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, True when it is, and we should restart on a new TB, and via longjmp via cpu_loop_exit. */ else { - if (cc->cpu_exec_interrupt(cpu, interrupt_request)) { + if (cc->cpu_exec_interrupt && + cc->cpu_exec_interrupt(cpu, interrupt_request)) { if (need_replay_interrupt(interrupt_request)) { replay_interrupt(); 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Thu, 10 Dec 2020 12:12:42 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 13/32] tcg: Make CPUClass.debug_excp_handler optional Date: Thu, 10 Dec 2020 13:12:07 +0100 Message-Id: <20201210121226.19822-14-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Colin Xu , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Eduardo Habkost Signed-off-by: Eduardo Habkost Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e --- accel/tcg/cpu-exec.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 890b88861a..64cba89356 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -482,7 +482,9 @@ static inline void cpu_handle_debug_exception(CPUState = *cpu) } } =20 - cc->debug_excp_handler(cpu); + if (cc->debug_excp_handler) { + cc->debug_excp_handler(cpu); + } } =20 static inline bool cpu_handle_exception(CPUState *cpu, int *ret) --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607605438; cv=none; d=zohomail.com; s=zohoarc; b=BmFllEczA+eoFGyIBUCyZfxDDIm8iFsdIxJi2LXhi8XOYQgZwOtz/ylvIw9wD/i54PFDl4jAaB9FElyiXBozgKNRFR7680Ymboa1wc4PrzQb3JWpeDoDOSj3td25F22Xk2Mk/ujrfjmJ6jcotaYR6NnUjiIafd6aKZomKxWpIk0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607605438; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5Ia0mdn1ZKmDii1SSGmj3tauOKXHXE8csPa34Yp4b9U=; b=GOKdF+S1x4qVmlbSlwkkbyPY7Lbq9E5PjPKwEqx8mwn8308obErhfIjncwuH+pTIa95Okw+Yf9HwHrmuAqnCsrrrISfJhlby3Bk72J8ZjxhWjiq2fy+il3mjYy/fBE+0d2PwoVYAzzaLKHICbGF0bpW3qMsRAt3ien3u/nfgLl4= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 160760543888537.38657153761346; Thu, 10 Dec 2020 05:03:58 -0800 (PST) Received: from localhost ([::1]:50980 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knLbs-0003rh-RU for importer@patchew.org; Thu, 10 Dec 2020 08:03:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56546) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKob-0002QC-Q4 for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:12:57 -0500 Received: from mx2.suse.de ([195.135.220.15]:47458) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoZ-0006US-0g for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:12:57 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id B62AAAD6A; Thu, 10 Dec 2020 12:12:43 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 14/32] cpu: Remove unnecessary noop methods Date: Thu, 10 Dec 2020 13:12:08 +0100 Message-Id: <20201210121226.19822-15-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Colin Xu , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Eduardo Habkost Signed-off-by: Eduardo Habkost Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e --- hw/core/cpu.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 576fa1d7ba..994a12cb35 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -199,15 +199,6 @@ static bool cpu_common_virtio_is_big_endian(CPUState *= cpu) return target_words_bigendian(); } =20 -static void cpu_common_noop(CPUState *cpu) -{ -} - -static bool cpu_common_exec_interrupt(CPUState *cpu, int int_req) -{ - return false; -} - #if !defined(CONFIG_USER_ONLY) GuestPanicInformation *cpu_get_crash_info(CPUState *cpu) { @@ -410,11 +401,7 @@ static void cpu_class_init(ObjectClass *klass, void *d= ata) k->gdb_read_register =3D cpu_common_gdb_read_register; k->gdb_write_register =3D cpu_common_gdb_write_register; k->virtio_is_big_endian =3D cpu_common_virtio_is_big_endian; - k->debug_excp_handler =3D cpu_common_noop; k->debug_check_watchpoint =3D cpu_common_debug_check_watchpoint; - k->cpu_exec_enter =3D cpu_common_noop; - k->cpu_exec_exit =3D cpu_common_noop; - k->cpu_exec_interrupt =3D cpu_common_exec_interrupt; k->adjust_watchpoint_address =3D cpu_adjust_watchpoint_address; set_bit(DEVICE_CATEGORY_CPU, dc->categories); dc->realize =3D cpu_common_realizefn; --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607603400; cv=none; d=zohomail.com; s=zohoarc; b=n05RHBAaCTBsvoGv85GhhlKERYLdD1hUFAzj3Vha+2XwNbgh/NaTOzelFVa21dXOTajC9ze2R9FT4qeHCOiV87pueS/9VpSjtR1QRFglCQfX3Ul1bBiUcC+aW38dmGiTYjTkMNx6rWkSBp2s+6aGWSLzVT4V6IS7BdqXmDuCiPY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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Thu, 10 Dec 2020 07:13:01 -0500 Received: from mx2.suse.de ([195.135.220.15]:47502) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoa-0006UY-1X for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:13:00 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id BA099AD6B; Thu, 10 Dec 2020 12:12:44 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 15/32] cpu: Introduce TCGCpuOperations struct Date: Thu, 10 Dec 2020 13:12:09 +0100 Message-Id: <20201210121226.19822-16-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Colin Xu , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Eduardo Habkost The TCG-specific CPU methods will be moved to a separate struct, to make it easier to move accel-specific code outside generic CPU code in the future. Start by moving tcg_initialize(). The new CPUClass.tcg_opts field may eventually become a pointer, but keep it an embedded struct for now, to make code conversion easier. Signed-off-by: Eduardo Habkost [claudio: make the tcg code build for CONFIG_TCG only] Signed-off-by: Claudio Fontana Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e --- include/hw/core/cpu.h | 9 ++++++++- include/hw/core/tcg-cpu-ops.h | 25 +++++++++++++++++++++++++ cpu.c | 6 +++++- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/avr/cpu.c | 2 +- target/cris/cpu.c | 12 ++++++------ target/hppa/cpu.c | 2 +- target/i386/tcg/tcg-cpu.c | 2 +- target/lm32/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/moxie/cpu.c | 2 +- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tilegx/cpu.c | 2 +- target/tricore/cpu.c | 2 +- target/unicore32/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- MAINTAINERS | 1 + target/ppc/translate_init.c.inc | 2 +- 27 files changed, 67 insertions(+), 30 deletions(-) create mode 100644 include/hw/core/tcg-cpu-ops.h diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 3d92c967ff..c93b08a0fb 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -76,6 +76,10 @@ typedef struct CPUWatchpoint CPUWatchpoint; =20 struct TranslationBlock; =20 +#ifdef CONFIG_TCG +#include "tcg-cpu-ops.h" +#endif /* CONFIG_TCG */ + /** * CPUClass: * @class_by_name: Callback to map -cpu command line model name to an @@ -221,12 +225,15 @@ struct CPUClass { =20 void (*disas_set_info)(CPUState *cpu, disassemble_info *info); vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len); - void (*tcg_initialize)(void); =20 const char *deprecation_note; /* Keep non-pointer data at the end to minimize holes. */ int gdb_num_core_regs; bool gdb_stop_before_watchpoint; + +#ifdef CONFIG_TCG + TcgCpuOperations tcg_ops; +#endif /* CONFIG_TCG */ }; =20 /* diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h new file mode 100644 index 0000000000..4475ef0996 --- /dev/null +++ b/include/hw/core/tcg-cpu-ops.h @@ -0,0 +1,25 @@ +/* + * TCG-Specific operations that are not meaningful for hardware accelerato= rs + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef TCG_CPU_OPS_H +#define TCG_CPU_OPS_H + +/** + * struct TcgCpuOperations: TCG operations specific to a CPU class + */ +typedef struct TcgCpuOperations { + /** + * @initialize: Initalize TCG state + * + * Called when the first CPU is realized. + */ + void (*initialize)(void); +} TcgCpuOperations; + +#endif /* TCG_CPU_OPS_H */ diff --git a/cpu.c b/cpu.c index 0be5dcb6f3..27ad096cc4 100644 --- a/cpu.c +++ b/cpu.c @@ -174,14 +174,18 @@ void cpu_exec_initfn(CPUState *cpu) void cpu_exec_realizefn(CPUState *cpu, Error **errp) { CPUClass *cc =3D CPU_GET_CLASS(cpu); +#ifdef CONFIG_TCG static bool tcg_target_initialized; +#endif /* CONFIG_TCG */ =20 cpu_list_add(cpu); =20 +#ifdef CONFIG_TCG if (tcg_enabled() && !tcg_target_initialized) { tcg_target_initialized =3D true; - cc->tcg_initialize(); + cc->tcg_ops.initialize(); } +#endif /* CONFIG_TCG */ tlb_init(cpu); =20 qemu_plugin_vcpu_init_hook(cpu); diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index b3fd6643e8..d66f0351a9 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -231,7 +231,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) dc->vmsd =3D &vmstate_alpha_cpu; #endif cc->disas_set_info =3D alpha_cpu_disas_set_info; - cc->tcg_initialize =3D alpha_translate_init; + cc->tcg_ops.initialize =3D alpha_translate_init; =20 cc->gdb_num_core_regs =3D 67; } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 07492e9f9a..1fa9382a7c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2261,7 +2261,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_stop_before_watchpoint =3D true; cc->disas_set_info =3D arm_disas_set_info; #ifdef CONFIG_TCG - cc->tcg_initialize =3D arm_translate_init; + cc->tcg_ops.initialize =3D arm_translate_init; cc->tlb_fill =3D arm_cpu_tlb_fill; cc->debug_excp_handler =3D arm_debug_excp_handler; cc->debug_check_watchpoint =3D arm_debug_check_watchpoint; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 5d9c4ad5bf..94306a2aa0 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -206,7 +206,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->tlb_fill =3D avr_cpu_tlb_fill; cc->vmsd =3D &vms_avr_cpu; cc->disas_set_info =3D avr_cpu_disas_set_info; - cc->tcg_initialize =3D avr_cpu_tcg_init; + cc->tcg_ops.initialize =3D avr_cpu_tcg_init; cc->synchronize_from_tb =3D avr_cpu_synchronize_from_tb; cc->gdb_read_register =3D avr_cpu_gdb_read_register; cc->gdb_write_register =3D avr_cpu_gdb_write_register; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index cff6b9eabf..4328f8e6c9 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -201,7 +201,7 @@ static void crisv8_cpu_class_init(ObjectClass *oc, void= *data) ccc->vr =3D 8; cc->do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; - cc->tcg_initialize =3D cris_initialize_crisv10_tcg; + cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; } =20 static void crisv9_cpu_class_init(ObjectClass *oc, void *data) @@ -212,7 +212,7 @@ static void crisv9_cpu_class_init(ObjectClass *oc, void= *data) ccc->vr =3D 9; cc->do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; - cc->tcg_initialize =3D cris_initialize_crisv10_tcg; + cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; } =20 static void crisv10_cpu_class_init(ObjectClass *oc, void *data) @@ -223,7 +223,7 @@ static void crisv10_cpu_class_init(ObjectClass *oc, voi= d *data) ccc->vr =3D 10; cc->do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; - cc->tcg_initialize =3D cris_initialize_crisv10_tcg; + cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; } =20 static void crisv11_cpu_class_init(ObjectClass *oc, void *data) @@ -234,7 +234,7 @@ static void crisv11_cpu_class_init(ObjectClass *oc, voi= d *data) ccc->vr =3D 11; cc->do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; - cc->tcg_initialize =3D cris_initialize_crisv10_tcg; + cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; } =20 static void crisv17_cpu_class_init(ObjectClass *oc, void *data) @@ -245,7 +245,7 @@ static void crisv17_cpu_class_init(ObjectClass *oc, voi= d *data) ccc->vr =3D 17; cc->do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; - cc->tcg_initialize =3D cris_initialize_crisv10_tcg; + cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; } =20 static void crisv32_cpu_class_init(ObjectClass *oc, void *data) @@ -284,7 +284,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_stop_before_watchpoint =3D true; =20 cc->disas_set_info =3D cris_disas_set_info; - cc->tcg_initialize =3D cris_initialize_tcg; + cc->tcg_ops.initialize =3D cris_initialize_tcg; } =20 #define DEFINE_CRIS_CPU_TYPE(cpu_model, initfn) \ diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 71b6aca45d..4c778966c2 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -153,7 +153,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) #endif cc->do_unaligned_access =3D hppa_cpu_do_unaligned_access; cc->disas_set_info =3D hppa_cpu_disas_set_info; - cc->tcg_initialize =3D hppa_translate_init; + cc->tcg_ops.initialize =3D hppa_translate_init; =20 cc->gdb_num_core_regs =3D 128; } diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 628dd29fe7..1f2a3e881a 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -63,7 +63,7 @@ void tcg_cpu_common_class_init(CPUClass *cc) cc->synchronize_from_tb =3D x86_cpu_synchronize_from_tb; cc->cpu_exec_enter =3D x86_cpu_exec_enter; cc->cpu_exec_exit =3D x86_cpu_exec_exit; - cc->tcg_initialize =3D tcg_x86_init; + cc->tcg_ops.initialize =3D tcg_x86_init; cc->tlb_fill =3D x86_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->debug_excp_handler =3D breakpoint_handler; diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index c50ad5fa15..ef795b81a4 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -237,7 +237,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_stop_before_watchpoint =3D true; cc->debug_excp_handler =3D lm32_debug_excp_handler; cc->disas_set_info =3D lm32_cpu_disas_set_info; - cc->tcg_initialize =3D lm32_translate_init; + cc->tcg_ops.initialize =3D lm32_translate_init; } =20 #define DEFINE_LM32_CPU_TYPE(cpu_model, initfn) \ diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 72c545149e..b66d86c353 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -289,7 +289,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D m68k_cpu_disas_set_info; - cc->tcg_initialize =3D m68k_tcg_init; + cc->tcg_ops.initialize =3D m68k_tcg_init; =20 cc->gdb_num_core_regs =3D 18; =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 9b2482159d..bc10518fa3 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -335,7 +335,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->gdb_num_core_regs =3D 32 + 27; =20 cc->disas_set_info =3D mb_disas_set_info; - cc->tcg_initialize =3D mb_tcg_init; + cc->tcg_ops.initialize =3D mb_tcg_init; } =20 static const TypeInfo mb_cpu_type_info =3D { diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 76d50b00b4..bc48573763 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -249,7 +249,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) #endif cc->disas_set_info =3D mips_cpu_disas_set_info; #ifdef CONFIG_TCG - cc->tcg_initialize =3D mips_tcg_init; + cc->tcg_ops.initialize =3D mips_tcg_init; cc->tlb_fill =3D mips_cpu_tlb_fill; #endif =20 diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 6e0443ccb7..224cfc8361 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -116,7 +116,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) cc->vmsd =3D &vmstate_moxie_cpu; #endif cc->disas_set_info =3D moxie_cpu_disas_set_info; - cc->tcg_initialize =3D moxie_translate_init; + cc->tcg_ops.initialize =3D moxie_translate_init; } =20 static void moxielite_initfn(Object *obj) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 8f7011fcb9..29c9c6f634 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -205,7 +205,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D nios2_cpu_gdb_read_register; cc->gdb_write_register =3D nios2_cpu_gdb_write_register; cc->gdb_num_core_regs =3D 49; - cc->tcg_initialize =3D nios2_tcg_init; + cc->tcg_ops.initialize =3D nios2_tcg_init; } =20 static const TypeInfo nios2_cpu_type_info =3D { diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 5528c0918f..e442f4f97c 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -166,7 +166,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) dc->vmsd =3D &vmstate_openrisc_cpu; #endif cc->gdb_num_core_regs =3D 32 + 3; - cc->tcg_initialize =3D openrisc_translate_init; + cc->tcg_ops.initialize =3D openrisc_translate_init; cc->disas_set_info =3D openrisc_disas_set_info; } =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6a0264fc6b..a52e0ce466 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -562,7 +562,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->vmsd =3D &vmstate_riscv_cpu; #endif #ifdef CONFIG_TCG - cc->tcg_initialize =3D riscv_translate_init; + cc->tcg_ops.initialize =3D riscv_translate_init; cc->tlb_fill =3D riscv_cpu_tlb_fill; #endif device_class_set_props(dc, riscv_cpu_properties); diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 23ee17a701..a701a09b11 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -194,7 +194,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) cc->gdb_write_register =3D rx_cpu_gdb_write_register; cc->get_phys_page_debug =3D rx_cpu_get_phys_page_debug; cc->disas_set_info =3D rx_cpu_disas_set_info; - cc->tcg_initialize =3D rx_translate_init; + cc->tcg_ops.initialize =3D rx_translate_init; cc->tlb_fill =3D rx_cpu_tlb_fill; =20 cc->gdb_num_core_regs =3D 26; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 7b66718c44..697b94ff7b 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -512,7 +512,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) #endif cc->disas_set_info =3D s390_cpu_disas_set_info; #ifdef CONFIG_TCG - cc->tcg_initialize =3D s390x_translate_init; + cc->tcg_ops.initialize =3D s390x_translate_init; cc->tlb_fill =3D s390_cpu_tlb_fill; #endif =20 diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 3c68021c56..bdc5c9d90b 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -231,7 +231,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->get_phys_page_debug =3D superh_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D superh_cpu_disas_set_info; - cc->tcg_initialize =3D sh4_translate_init; + cc->tcg_ops.initialize =3D sh4_translate_init; =20 cc->gdb_num_core_regs =3D 59; =20 diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 701e794eac..07e48b86d1 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -879,7 +879,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->vmsd =3D &vmstate_sparc_cpu; #endif cc->disas_set_info =3D cpu_sparc_disas_set_info; - cc->tcg_initialize =3D sparc_tcg_init; + cc->tcg_ops.initialize =3D sparc_tcg_init; =20 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) cc->gdb_num_core_regs =3D 86; diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index 1fee87c094..cd24d0eb9d 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -153,7 +153,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void= *data) cc->set_pc =3D tilegx_cpu_set_pc; cc->tlb_fill =3D tilegx_cpu_tlb_fill; cc->gdb_num_core_regs =3D 0; - cc->tcg_initialize =3D tilegx_tcg_init; + cc->tcg_ops.initialize =3D tilegx_tcg_init; } =20 static const TypeInfo tilegx_cpu_type_info =3D { diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 2f2e5b029f..78b2925955 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -164,7 +164,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) cc->set_pc =3D tricore_cpu_set_pc; cc->synchronize_from_tb =3D tricore_cpu_synchronize_from_tb; cc->get_phys_page_debug =3D tricore_cpu_get_phys_page_debug; - cc->tcg_initialize =3D tricore_tcg_init; + cc->tcg_ops.initialize =3D tricore_tcg_init; cc->tlb_fill =3D tricore_cpu_tlb_fill; } =20 diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index b27fb9689f..226bf4226e 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -137,7 +137,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) cc->set_pc =3D uc32_cpu_set_pc; cc->tlb_fill =3D uc32_cpu_tlb_fill; cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; - cc->tcg_initialize =3D uc32_translate_init; + cc->tcg_ops.initialize =3D uc32_translate_init; dc->vmsd =3D &vmstate_uc32_cpu; } =20 diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 88a32268a1..5a6f5bf88b 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -209,7 +209,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) #endif cc->debug_excp_handler =3D xtensa_breakpoint_handler; cc->disas_set_info =3D xtensa_cpu_disas_set_info; - cc->tcg_initialize =3D xtensa_translate_init; + cc->tcg_ops.initialize =3D xtensa_translate_init; dc->vmsd =3D &vmstate_xtensa_cpu; } =20 diff --git a/MAINTAINERS b/MAINTAINERS index f53f2678d8..d876f504a6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1535,6 +1535,7 @@ F: qapi/machine.json F: qapi/machine-target.json F: include/hw/boards.h F: include/hw/core/cpu.h +F: include/hw/core/tcg-cpu-ops.h F: include/hw/cpu/cluster.h F: include/sysemu/numa.h T: git https://github.com/ehabkost/qemu.git machine-next diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 78cc8f043b..9a6932b774 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10945,7 +10945,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->virtio_is_big_endian =3D ppc_cpu_is_big_endian; #endif #ifdef CONFIG_TCG - cc->tcg_initialize =3D ppc_translate_init; + cc->tcg_ops.initialize =3D ppc_translate_init; cc->tlb_fill =3D ppc_cpu_tlb_fill; #endif #ifndef CONFIG_USER_ONLY --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607603722; cv=none; d=zohomail.com; s=zohoarc; b=dtG52QFrz4UIQJwPrjG7HT8CAgYmq7ZBQRgMm8TpjmJLCvq3sZs/dcu4QuKDNiuVQiywyhl53ZI2uBjuuBjSqqh0ebx324MfBCdTGINCIc/lpJc+sO6UlORBbVnd3RlmbDY9/oh/Cegs03vQ8JpCF1hI23aW5YU1IoTnh6S59qE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607603722; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=TN6e/mHm0WxDiwdct7Z80VYxPiflAtn65VWL50VZdWY=; b=n8D+wHnCdHLPFGPqQwURrlqzu2tngW5tgMGwumBd4yXtcjwOAmjbrGLXf/wwvz3isgFABVuvzmXspvhaTTDhf1xBXEeaH0QP37F4RiZsqctlshgVWi0kPeDRcrUZNJ0lkULYEMI9lPrxaEqTuFebUBCPiDCRIB/1xW3mHHGpGpA= ARC-Authentication-Results: i=1; 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Thu, 10 Dec 2020 12:12:45 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 16/32] target/riscv: remove CONFIG_TCG, as it is always TCG Date: Thu, 10 Dec 2020 13:12:10 +0100 Message-Id: <20201210121226.19822-17-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Alistair Francis , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" for now only TCG is allowed as an accelerator for riscv, so remove the CONFIG_TCG use. Signed-off-by: Claudio Fontana Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a52e0ce466..27dd1645c9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -561,10 +561,9 @@ static void riscv_cpu_class_init(ObjectClass *c, void = *data) /* For now, mark unmigratable: */ cc->vmsd =3D &vmstate_riscv_cpu; #endif -#ifdef CONFIG_TCG cc->tcg_ops.initialize =3D riscv_translate_init; cc->tlb_fill =3D riscv_cpu_tlb_fill; -#endif + device_class_set_props(dc, riscv_cpu_properties); } =20 --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607633795; cv=none; d=zohomail.com; s=zohoarc; b=fNgz+cFXvfEe/p3sYAhZ7rFrmGuDQ6+xPCwDCRy/wyVPPu+VWpUg274wNz4w1VMhDe8GGv9qvBO9c2Feg/j/TqHKI2XEwc4rA6u8QhAJRs2I3ReYMBEf7izzfkVMNy23nlV4US1YwCYL3hE+MLupP4wsyOhwcMfN1l2DtFIbXQE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607633795; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YjPMvCRQHPhX5Y1gLxT9itYUd60yVxwF7orGpgsBiC4=; b=f6KL+l9Id+I7k6qJG5sbk6jYyGKFNs7awtAAqxtoZzt873T6Eb7AQR7zThywV6tIQ8bvozRsaQYzcQUMg3eovwY6BgjS/O/fSyBUNFj4GiDy1H/lQphLJphGQvbRn6sPjc58kbW/tM/HoCgkXLCWznT8Y5sfDwKrQwTqAu2f1HM= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607633795438802.8645757221262; Thu, 10 Dec 2020 12:56:35 -0800 (PST) Received: from localhost ([::1]:59496 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knLgJ-0007PK-C0 for importer@patchew.org; Thu, 10 Dec 2020 08:08:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56588) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoe-0002T7-SK for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:13:01 -0500 Received: from mx2.suse.de ([195.135.220.15]:47592) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKob-0006VT-W0 for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:13:00 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id BC815AD29; Thu, 10 Dec 2020 12:12:46 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 17/32] accel/tcg: split TCG-only code from cpu_exec_realizefn Date: Thu, 10 Dec 2020 13:12:11 +0100 Message-Id: <20201210121226.19822-18-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" move away TCG-only code, make it compile only on TCG. Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e --- include/hw/core/cpu.h | 8 +++++ accel/tcg/cpu-exec.c | 28 +++++++++++++++++ cpu.c | 70 ++++++++++++++++++++----------------------- hw/core/cpu.c | 6 +++- 4 files changed, 74 insertions(+), 38 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index c93b08a0fb..ea648d52ad 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1119,10 +1119,18 @@ AddressSpace *cpu_get_address_space(CPUState *cpu, = int asidx); void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...) GCC_FMT_ATTR(2, 3); extern Property cpu_common_props[]; + +/* $(top_srcdir)/cpu.c */ void cpu_exec_initfn(CPUState *cpu); void cpu_exec_realizefn(CPUState *cpu, Error **errp); void cpu_exec_unrealizefn(CPUState *cpu); =20 +#ifdef CONFIG_TCG +/* accel/tcg/cpu-exec.c */ +void tcg_exec_realizefn(CPUState *cpu, Error **errp); +void tcg_exec_unrealizefn(CPUState *cpu); +#endif /* CONFIG_TCG */ + /** * target_words_bigendian: * Returns true if the (default) endianness of the target is big endian, diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 64cba89356..50eb92d217 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -801,6 +801,34 @@ int cpu_exec(CPUState *cpu) return ret; } =20 +void tcg_exec_realizefn(CPUState *cpu, Error **errp) +{ + static bool tcg_target_initialized; + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + if (!tcg_target_initialized) { + cc->tcg_ops.initialize(); + tcg_target_initialized =3D true; + } + tlb_init(cpu); + qemu_plugin_vcpu_init_hook(cpu); + +#ifndef CONFIG_USER_ONLY + tcg_iommu_init_notifier_list(cpu); +#endif /* !CONFIG_USER_ONLY */ +} + +/* undo the initializations in reverse order */ +void tcg_exec_unrealizefn(CPUState *cpu) +{ +#ifndef CONFIG_USER_ONLY + tcg_iommu_free_notifier_list(cpu); +#endif /* !CONFIG_USER_ONLY */ + + qemu_plugin_vcpu_exit_hook(cpu); + tlb_destroy(cpu); +} + #ifndef CONFIG_USER_ONLY =20 void dump_drift_info(void) diff --git a/cpu.c b/cpu.c index 27ad096cc4..5cc8f181be 100644 --- a/cpu.c +++ b/cpu.c @@ -124,13 +124,35 @@ const VMStateDescription vmstate_cpu_common =3D { }; #endif =20 +void cpu_exec_realizefn(CPUState *cpu, Error **errp) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + cpu_list_add(cpu); + +#ifdef CONFIG_TCG + /* NB: errp parameter is unused currently */ + if (tcg_enabled()) { + tcg_exec_realizefn(cpu, errp); + } +#endif /* CONFIG_TCG */ + +#ifdef CONFIG_USER_ONLY + assert(cc->vmsd =3D=3D NULL); +#else + if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { + vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); + } + if (cc->vmsd !=3D NULL) { + vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu); + } +#endif /* CONFIG_USER_ONLY */ +} + void cpu_exec_unrealizefn(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - tlb_destroy(cpu); - cpu_list_remove(cpu); - #ifdef CONFIG_USER_ONLY assert(cc->vmsd =3D=3D NULL); #else @@ -140,8 +162,15 @@ void cpu_exec_unrealizefn(CPUState *cpu) if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { vmstate_unregister(NULL, &vmstate_cpu_common, cpu); } - tcg_iommu_free_notifier_list(cpu); #endif +#ifdef CONFIG_TCG + /* NB: errp parameter is unused currently */ + if (tcg_enabled()) { + tcg_exec_unrealizefn(cpu); + } +#endif /* CONFIG_TCG */ + + cpu_list_remove(cpu); } =20 Property cpu_common_props[] =3D { @@ -171,39 +200,6 @@ void cpu_exec_initfn(CPUState *cpu) #endif } =20 -void cpu_exec_realizefn(CPUState *cpu, Error **errp) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); -#ifdef CONFIG_TCG - static bool tcg_target_initialized; -#endif /* CONFIG_TCG */ - - cpu_list_add(cpu); - -#ifdef CONFIG_TCG - if (tcg_enabled() && !tcg_target_initialized) { - tcg_target_initialized =3D true; - cc->tcg_ops.initialize(); - } -#endif /* CONFIG_TCG */ - tlb_init(cpu); - - qemu_plugin_vcpu_init_hook(cpu); - -#ifdef CONFIG_USER_ONLY - assert(cc->vmsd =3D=3D NULL); -#else /* !CONFIG_USER_ONLY */ - if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { - vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); - } - if (cc->vmsd !=3D NULL) { - vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu); - } - - tcg_iommu_init_notifier_list(cpu); -#endif -} - const char *parse_cpu_option(const char *cpu_option) { ObjectClass *oc; diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 994a12cb35..1f04aab16b 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -199,6 +199,10 @@ static bool cpu_common_virtio_is_big_endian(CPUState *= cpu) return target_words_bigendian(); } =20 +/* + * XXX the following #if is always true because this is a common_ss + * module, so target CONFIG_* is never defined. + */ #if !defined(CONFIG_USER_ONLY) GuestPanicInformation *cpu_get_crash_info(CPUState *cpu) { @@ -340,9 +344,9 @@ static void cpu_common_realizefn(DeviceState *dev, Erro= r **errp) static void cpu_common_unrealizefn(DeviceState *dev) { CPUState *cpu =3D CPU(dev); + /* NOTE: latest generic point before the cpu is fully unrealized */ trace_fini_vcpu(cpu); - qemu_plugin_vcpu_exit_hook(cpu); cpu_exec_unrealizefn(cpu); } =20 --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607603877; cv=none; d=zohomail.com; s=zohoarc; b=ifr3VoMcKbcg/BFKatqouna1qs2hmLGPgTVLeVX2/DVAGO7iGniW82JJeQdVluK77f5ZJAidS3x9MOsY0BTUCnEsiz7bRhWu7IUuD1C03HH2FZ2GCL+Zqe4rt5pLWJZe//b8hJY6RCdd0uqtmK91muzVvxzXoP6u4YOhu4A6FZk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607603877; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6eetIb6SqFeNaiwDJqaDOP7O/FXRJZ3thSmOeU+DzJc=; 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Thu, 10 Dec 2020 07:13:02 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id CADA4AD75; Thu, 10 Dec 2020 12:12:47 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 18/32] cpu: Move synchronize_from_tb() to tcg_ops Date: Thu, 10 Dec 2020 13:12:12 +0100 Message-Id: <20201210121226.19822-19-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Colin Xu , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Eduardo Habkost Signed-off-by: Eduardo Habkost [claudio: wrapped in CONFIG_TCG] Signed-off-by: Claudio Fontana Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e --- include/hw/core/cpu.h | 8 -------- include/hw/core/tcg-cpu-ops.h | 12 ++++++++++++ accel/tcg/cpu-exec.c | 4 ++-- target/arm/cpu.c | 2 +- target/avr/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/tcg/tcg-cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 2 +- 14 files changed, 25 insertions(+), 21 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index ea648d52ad..83007d262c 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -110,13 +110,6 @@ struct TranslationBlock; * If the target behaviour here is anything other than "set * the PC register to the value passed in" then the target must * also implement the synchronize_from_tb hook. - * @synchronize_from_tb: Callback for synchronizing state from a TCG - * #TranslationBlock. This is called when we abandon execution - * of a TB before starting it, and must set all parts of the CPU - * state which the previous TB in the chain may not have updated. - * This always includes at least the program counter; some targets - * will need to do more. If this hook is not implemented then the - * default is to call @set_pc(tb->pc). * @tlb_fill: Callback for handling a softmmu tlb miss or user-only * address fault. For system mode, if the access is valid, call * tlb_set_page and return true; if the access is invalid, and @@ -193,7 +186,6 @@ struct CPUClass { void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); - void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb= ); bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 4475ef0996..e1d50b3c8b 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -10,6 +10,8 @@ #ifndef TCG_CPU_OPS_H #define TCG_CPU_OPS_H =20 +#include "hw/core/cpu.h" + /** * struct TcgCpuOperations: TCG operations specific to a CPU class */ @@ -20,6 +22,16 @@ typedef struct TcgCpuOperations { * Called when the first CPU is realized. */ void (*initialize)(void); + /** + * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock + * + * This is called when we abandon execution of a TB before + * starting it, and must set all parts of the CPU state which + * the previous TB in the chain may not have updated. This + * will need to do more. If this hook is not implemented then + * the default is to call @set_pc(tb->pc). + */ + void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb= ); } TcgCpuOperations; =20 #endif /* TCG_CPU_OPS_H */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 50eb92d217..05dba7f2cc 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -192,8 +192,8 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cp= u, TranslationBlock *itb) TARGET_FMT_lx "] %s\n", last_tb->tc.ptr, last_tb->pc, lookup_symbol(last_tb->pc)); - if (cc->synchronize_from_tb) { - cc->synchronize_from_tb(cpu, last_tb); + if (cc->tcg_ops.synchronize_from_tb) { + cc->tcg_ops.synchronize_from_tb(cpu, last_tb); } else { assert(cc->set_pc); cc->set_pc(cpu, last_tb->pc); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1fa9382a7c..2f9e27c248 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2242,7 +2242,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->cpu_exec_interrupt =3D arm_cpu_exec_interrupt; cc->dump_state =3D arm_cpu_dump_state; cc->set_pc =3D arm_cpu_set_pc; - cc->synchronize_from_tb =3D arm_cpu_synchronize_from_tb; cc->gdb_read_register =3D arm_cpu_gdb_read_register; cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY @@ -2262,6 +2261,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->disas_set_info =3D arm_disas_set_info; #ifdef CONFIG_TCG cc->tcg_ops.initialize =3D arm_translate_init; + cc->tcg_ops.synchronize_from_tb =3D arm_cpu_synchronize_from_tb; cc->tlb_fill =3D arm_cpu_tlb_fill; cc->debug_excp_handler =3D arm_debug_excp_handler; cc->debug_check_watchpoint =3D arm_debug_check_watchpoint; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 94306a2aa0..f753c15768 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -207,7 +207,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->vmsd =3D &vms_avr_cpu; cc->disas_set_info =3D avr_cpu_disas_set_info; cc->tcg_ops.initialize =3D avr_cpu_tcg_init; - cc->synchronize_from_tb =3D avr_cpu_synchronize_from_tb; + cc->tcg_ops.synchronize_from_tb =3D avr_cpu_synchronize_from_tb; cc->gdb_read_register =3D avr_cpu_gdb_read_register; cc->gdb_write_register =3D avr_cpu_gdb_write_register; cc->gdb_num_core_regs =3D 35; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 4c778966c2..12a09e93ae 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -143,7 +143,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->cpu_exec_interrupt =3D hppa_cpu_exec_interrupt; cc->dump_state =3D hppa_cpu_dump_state; cc->set_pc =3D hppa_cpu_set_pc; - cc->synchronize_from_tb =3D hppa_cpu_synchronize_from_tb; + cc->tcg_ops.synchronize_from_tb =3D hppa_cpu_synchronize_from_tb; cc->gdb_read_register =3D hppa_cpu_gdb_read_register; cc->gdb_write_register =3D hppa_cpu_gdb_write_register; cc->tlb_fill =3D hppa_cpu_tlb_fill; diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 1f2a3e881a..d1414e2970 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -60,7 +60,7 @@ void tcg_cpu_common_class_init(CPUClass *cc) { cc->do_interrupt =3D x86_cpu_do_interrupt; cc->cpu_exec_interrupt =3D x86_cpu_exec_interrupt; - cc->synchronize_from_tb =3D x86_cpu_synchronize_from_tb; + cc->tcg_ops.synchronize_from_tb =3D x86_cpu_synchronize_from_tb; cc->cpu_exec_enter =3D x86_cpu_exec_enter; cc->cpu_exec_exit =3D x86_cpu_exec_exit; cc->tcg_ops.initialize =3D tcg_x86_init; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index bc10518fa3..97d94d9c27 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -322,7 +322,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->cpu_exec_interrupt =3D mb_cpu_exec_interrupt; cc->dump_state =3D mb_cpu_dump_state; cc->set_pc =3D mb_cpu_set_pc; - cc->synchronize_from_tb =3D mb_cpu_synchronize_from_tb; + cc->tcg_ops.synchronize_from_tb =3D mb_cpu_synchronize_from_tb; cc->gdb_read_register =3D mb_cpu_gdb_read_register; cc->gdb_write_register =3D mb_cpu_gdb_write_register; cc->tlb_fill =3D mb_cpu_tlb_fill; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index bc48573763..71c488f3dd 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -238,7 +238,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->cpu_exec_interrupt =3D mips_cpu_exec_interrupt; cc->dump_state =3D mips_cpu_dump_state; cc->set_pc =3D mips_cpu_set_pc; - cc->synchronize_from_tb =3D mips_cpu_synchronize_from_tb; cc->gdb_read_register =3D mips_cpu_gdb_read_register; cc->gdb_write_register =3D mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY @@ -250,6 +249,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->disas_set_info =3D mips_cpu_disas_set_info; #ifdef CONFIG_TCG cc->tcg_ops.initialize =3D mips_tcg_init; + cc->tcg_ops.synchronize_from_tb =3D mips_cpu_synchronize_from_tb; cc->tlb_fill =3D mips_cpu_tlb_fill; #endif =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 27dd1645c9..a9c30879d3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -543,7 +543,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->cpu_exec_interrupt =3D riscv_cpu_exec_interrupt; cc->dump_state =3D riscv_cpu_dump_state; cc->set_pc =3D riscv_cpu_set_pc; - cc->synchronize_from_tb =3D riscv_cpu_synchronize_from_tb; + cc->tcg_ops.synchronize_from_tb =3D riscv_cpu_synchronize_from_tb; cc->gdb_read_register =3D riscv_cpu_gdb_read_register; cc->gdb_write_register =3D riscv_cpu_gdb_write_register; cc->gdb_num_core_regs =3D 33; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index a701a09b11..d03c4e0b05 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -189,7 +189,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) cc->cpu_exec_interrupt =3D rx_cpu_exec_interrupt; cc->dump_state =3D rx_cpu_dump_state; cc->set_pc =3D rx_cpu_set_pc; - cc->synchronize_from_tb =3D rx_cpu_synchronize_from_tb; + cc->tcg_ops.synchronize_from_tb =3D rx_cpu_synchronize_from_tb; cc->gdb_read_register =3D rx_cpu_gdb_read_register; cc->gdb_write_register =3D rx_cpu_gdb_write_register; cc->get_phys_page_debug =3D rx_cpu_get_phys_page_debug; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index bdc5c9d90b..a33025b5c8 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -222,7 +222,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->cpu_exec_interrupt =3D superh_cpu_exec_interrupt; cc->dump_state =3D superh_cpu_dump_state; cc->set_pc =3D superh_cpu_set_pc; - cc->synchronize_from_tb =3D superh_cpu_synchronize_from_tb; + cc->tcg_ops.synchronize_from_tb =3D superh_cpu_synchronize_from_tb; cc->gdb_read_register =3D superh_cpu_gdb_read_register; cc->gdb_write_register =3D superh_cpu_gdb_write_register; cc->tlb_fill =3D superh_cpu_tlb_fill; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 07e48b86d1..baf6c5b587 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -868,7 +868,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->memory_rw_debug =3D sparc_cpu_memory_rw_debug; #endif cc->set_pc =3D sparc_cpu_set_pc; - cc->synchronize_from_tb =3D sparc_cpu_synchronize_from_tb; + cc->tcg_ops.synchronize_from_tb =3D sparc_cpu_synchronize_from_tb; cc->gdb_read_register =3D sparc_cpu_gdb_read_register; cc->gdb_write_register =3D sparc_cpu_gdb_write_register; cc->tlb_fill =3D sparc_cpu_tlb_fill; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 78b2925955..5edf96c600 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -162,7 +162,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) =20 cc->dump_state =3D tricore_cpu_dump_state; cc->set_pc =3D tricore_cpu_set_pc; - cc->synchronize_from_tb =3D tricore_cpu_synchronize_from_tb; + cc->tcg_ops.synchronize_from_tb =3D tricore_cpu_synchronize_from_tb; cc->get_phys_page_debug =3D tricore_cpu_get_phys_page_debug; cc->tcg_ops.initialize =3D tricore_tcg_init; cc->tlb_fill =3D tricore_cpu_tlb_fill; --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607604128; cv=none; d=zohomail.com; s=zohoarc; b=McUWs6/O9RIEkG0gxTZPd54o10X2/stDRCXNX8a+UtliMjC5mxqLFM10XH5N21fKym85YCOTM5ENVXdaR5+50YAbKGHmS7QqgydZvKIjNQcifN0htNvDi9CY4wOI6L7/1OTCnIQnWbFDOtEqP2AuONADG7iaiU6p9bdxI/oeGOg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607604128; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Thu, 10 Dec 2020 07:13:04 -0500 Received: from mx2.suse.de ([195.135.220.15]:47664) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoe-0006Vc-Vp for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:13:03 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id CCD44AD7C; Thu, 10 Dec 2020 12:12:48 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 19/32] cpu: Move cpu_exec_* to tcg_ops Date: Thu, 10 Dec 2020 13:12:13 +0100 Message-Id: <20201210121226.19822-20-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Cota" , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Eduardo Habkost Signed-off-by: Eduardo Habkost [claudio: wrapped in CONFIG_TCG] Signed-off-by: Claudio Fontana Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e --- include/hw/core/cpu.h | 6 ------ include/hw/core/tcg-cpu-ops.h | 6 ++++++ accel/tcg/cpu-exec.c | 12 ++++++------ target/alpha/cpu.c | 3 ++- target/arm/cpu.c | 2 +- target/arm/cpu64.c | 5 ++++- target/arm/cpu_tcg.c | 5 ++++- target/avr/cpu.c | 2 +- target/cris/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/tcg/tcg-cpu.c | 6 +++--- target/lm32/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tilegx/cpu.c | 2 +- target/unicore32/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- target/ppc/translate_init.c.inc | 10 +++++----- 26 files changed, 48 insertions(+), 41 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 83007d262c..52142e9094 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -146,9 +146,6 @@ struct TranslationBlock; * @gdb_get_dynamic_xml: Callback to return dynamically generated XML for = the * gdb stub. Returns a pointer to the XML contents for the specified XML= file * or NULL if the CPU doesn't have a dynamically generated content for i= t. - * @cpu_exec_enter: Callback for cpu_exec preparation. - * @cpu_exec_exit: Callback for cpu_exec cleanup. - * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec. * @disas_set_info: Setup architecture specific components of disassembly = info * @adjust_watchpoint_address: Perform a target-specific adjustment to an * address before attempting to match it against watchpoints. @@ -211,9 +208,6 @@ struct CPUClass { const char *gdb_core_xml_file; gchar * (*gdb_arch_name)(CPUState *cpu); const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname= ); - void (*cpu_exec_enter)(CPUState *cpu); - void (*cpu_exec_exit)(CPUState *cpu); - bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); =20 void (*disas_set_info)(CPUState *cpu, disassemble_info *info); vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len); diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index e1d50b3c8b..fbd579c2a6 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -32,6 +32,12 @@ typedef struct TcgCpuOperations { * the default is to call @set_pc(tb->pc). */ void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb= ); + /** @cpu_exec_enter: Callback for cpu_exec preparation */ + void (*cpu_exec_enter)(CPUState *cpu); + /** @cpu_exec_exit: Callback for cpu_exec cleanup */ + void (*cpu_exec_exit)(CPUState *cpu); + /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exe= c */ + bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); } TcgCpuOperations; =20 #endif /* TCG_CPU_OPS_H */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 05dba7f2cc..502f6a53ae 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -240,8 +240,8 @@ static void cpu_exec_enter(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->cpu_exec_enter) { - cc->cpu_exec_enter(cpu); + if (cc->tcg_ops.cpu_exec_enter) { + cc->tcg_ops.cpu_exec_enter(cpu); } } =20 @@ -249,8 +249,8 @@ static void cpu_exec_exit(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->cpu_exec_exit) { - cc->cpu_exec_exit(cpu); + if (cc->tcg_ops.cpu_exec_exit) { + cc->tcg_ops.cpu_exec_exit(cpu); } } =20 @@ -625,8 +625,8 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, True when it is, and we should restart on a new TB, and via longjmp via cpu_loop_exit. */ else { - if (cc->cpu_exec_interrupt && - cc->cpu_exec_interrupt(cpu, interrupt_request)) { + if (cc->tcg_ops.cpu_exec_interrupt && + cc->tcg_ops.cpu_exec_interrupt(cpu, interrupt_request)) { if (need_replay_interrupt(interrupt_request)) { replay_interrupt(); } diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index d66f0351a9..4f206c154d 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -218,7 +218,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->class_by_name =3D alpha_cpu_class_by_name; cc->has_work =3D alpha_cpu_has_work; cc->do_interrupt =3D alpha_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D alpha_cpu_exec_interrupt; cc->dump_state =3D alpha_cpu_dump_state; cc->set_pc =3D alpha_cpu_set_pc; cc->gdb_read_register =3D alpha_cpu_gdb_read_register; @@ -234,6 +233,8 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->tcg_ops.initialize =3D alpha_translate_init; =20 cc->gdb_num_core_regs =3D 67; + + cc->tcg_ops.cpu_exec_interrupt =3D alpha_cpu_exec_interrupt; } =20 #define DEFINE_ALPHA_CPU_TYPE(base_type, cpu_model, initfn) \ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2f9e27c248..470b7b48c3 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2239,7 +2239,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) =20 cc->class_by_name =3D arm_cpu_class_by_name; cc->has_work =3D arm_cpu_has_work; - cc->cpu_exec_interrupt =3D arm_cpu_exec_interrupt; cc->dump_state =3D arm_cpu_dump_state; cc->set_pc =3D arm_cpu_set_pc; cc->gdb_read_register =3D arm_cpu_gdb_read_register; @@ -2261,6 +2260,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->disas_set_info =3D arm_disas_set_info; #ifdef CONFIG_TCG cc->tcg_ops.initialize =3D arm_translate_init; + cc->tcg_ops.cpu_exec_interrupt =3D arm_cpu_exec_interrupt; cc->tcg_ops.synchronize_from_tb =3D arm_cpu_synchronize_from_tb; cc->tlb_fill =3D arm_cpu_tlb_fill; cc->debug_excp_handler =3D arm_debug_excp_handler; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 649213082f..ebc53c8bdc 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -784,7 +784,10 @@ static void aarch64_cpu_class_init(ObjectClass *oc, vo= id *data) { CPUClass *cc =3D CPU_CLASS(oc); =20 - cc->cpu_exec_interrupt =3D arm_cpu_exec_interrupt; +#ifdef CONFIG_TCG + cc->tcg_ops.cpu_exec_interrupt =3D arm_cpu_exec_interrupt; +#endif /* CONFIG_TCG */ + cc->gdb_read_register =3D aarch64_cpu_gdb_read_register; cc->gdb_write_register =3D aarch64_cpu_gdb_write_register; cc->gdb_num_core_regs =3D 34; diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 0013e25412..a6538d3a96 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -628,7 +628,10 @@ static void arm_v7m_class_init(ObjectClass *oc, void *= data) cc->do_interrupt =3D arm_v7m_cpu_do_interrupt; #endif =20 - cc->cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt; +#ifdef CONFIG_TCG + cc->tcg_ops.cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt; +#endif /* CONFIG_TCG */ + cc->gdb_core_xml_file =3D "arm-m-profile.xml"; } =20 diff --git a/target/avr/cpu.c b/target/avr/cpu.c index f753c15768..277b00dbfc 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -198,7 +198,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) =20 cc->has_work =3D avr_cpu_has_work; cc->do_interrupt =3D avr_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D avr_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D avr_cpu_exec_interrupt; cc->dump_state =3D avr_cpu_dump_state; cc->set_pc =3D avr_cpu_set_pc; cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 4328f8e6c9..7489fc20c8 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -269,7 +269,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->class_by_name =3D cris_cpu_class_by_name; cc->has_work =3D cris_cpu_has_work; cc->do_interrupt =3D cris_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D cris_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D cris_cpu_exec_interrupt; cc->dump_state =3D cris_cpu_dump_state; cc->set_pc =3D cris_cpu_set_pc; cc->gdb_read_register =3D cris_cpu_gdb_read_register; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 12a09e93ae..61444753f2 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -140,7 +140,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->class_by_name =3D hppa_cpu_class_by_name; cc->has_work =3D hppa_cpu_has_work; cc->do_interrupt =3D hppa_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D hppa_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D hppa_cpu_exec_interrupt; cc->dump_state =3D hppa_cpu_dump_state; cc->set_pc =3D hppa_cpu_set_pc; cc->tcg_ops.synchronize_from_tb =3D hppa_cpu_synchronize_from_tb; diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index d1414e2970..5e0f2a2fae 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -59,10 +59,10 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, T= ranslationBlock *tb) void tcg_cpu_common_class_init(CPUClass *cc) { cc->do_interrupt =3D x86_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D x86_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D x86_cpu_exec_interrupt; cc->tcg_ops.synchronize_from_tb =3D x86_cpu_synchronize_from_tb; - cc->cpu_exec_enter =3D x86_cpu_exec_enter; - cc->cpu_exec_exit =3D x86_cpu_exec_exit; + cc->tcg_ops.cpu_exec_enter =3D x86_cpu_exec_enter; + cc->tcg_ops.cpu_exec_exit =3D x86_cpu_exec_exit; cc->tcg_ops.initialize =3D tcg_x86_init; cc->tlb_fill =3D x86_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index ef795b81a4..eea2d3e515 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -223,7 +223,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) cc->class_by_name =3D lm32_cpu_class_by_name; cc->has_work =3D lm32_cpu_has_work; cc->do_interrupt =3D lm32_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D lm32_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D lm32_cpu_exec_interrupt; cc->dump_state =3D lm32_cpu_dump_state; cc->set_pc =3D lm32_cpu_set_pc; cc->gdb_read_register =3D lm32_cpu_gdb_read_register; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index b66d86c353..c0fa517fc3 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -278,7 +278,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->class_by_name =3D m68k_cpu_class_by_name; cc->has_work =3D m68k_cpu_has_work; cc->do_interrupt =3D m68k_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D m68k_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D m68k_cpu_exec_interrupt; cc->dump_state =3D m68k_cpu_dump_state; cc->set_pc =3D m68k_cpu_set_pc; cc->gdb_read_register =3D m68k_cpu_gdb_read_register; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 97d94d9c27..833d7f2d59 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -319,7 +319,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->has_work =3D mb_cpu_has_work; cc->do_interrupt =3D mb_cpu_do_interrupt; cc->do_unaligned_access =3D mb_cpu_do_unaligned_access; - cc->cpu_exec_interrupt =3D mb_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D mb_cpu_exec_interrupt; cc->dump_state =3D mb_cpu_dump_state; cc->set_pc =3D mb_cpu_set_pc; cc->tcg_ops.synchronize_from_tb =3D mb_cpu_synchronize_from_tb; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 71c488f3dd..344ee402fc 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -235,7 +235,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->class_by_name =3D mips_cpu_class_by_name; cc->has_work =3D mips_cpu_has_work; cc->do_interrupt =3D mips_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D mips_cpu_exec_interrupt; cc->dump_state =3D mips_cpu_dump_state; cc->set_pc =3D mips_cpu_set_pc; cc->gdb_read_register =3D mips_cpu_gdb_read_register; @@ -249,6 +248,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->disas_set_info =3D mips_cpu_disas_set_info; #ifdef CONFIG_TCG cc->tcg_ops.initialize =3D mips_tcg_init; + cc->tcg_ops.cpu_exec_interrupt =3D mips_cpu_exec_interrupt; cc->tcg_ops.synchronize_from_tb =3D mips_cpu_synchronize_from_tb; cc->tlb_fill =3D mips_cpu_tlb_fill; #endif diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 29c9c6f634..9eeb01fb5b 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -193,7 +193,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) cc->class_by_name =3D nios2_cpu_class_by_name; cc->has_work =3D nios2_cpu_has_work; cc->do_interrupt =3D nios2_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D nios2_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D nios2_cpu_exec_interrupt; cc->dump_state =3D nios2_cpu_dump_state; cc->set_pc =3D nios2_cpu_set_pc; cc->disas_set_info =3D nios2_cpu_disas_set_info; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index e442f4f97c..df8a41f956 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -155,7 +155,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->class_by_name =3D openrisc_cpu_class_by_name; cc->has_work =3D openrisc_cpu_has_work; cc->do_interrupt =3D openrisc_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt; cc->dump_state =3D openrisc_cpu_dump_state; cc->set_pc =3D openrisc_cpu_set_pc; cc->gdb_read_register =3D openrisc_cpu_gdb_read_register; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a9c30879d3..15d58698a6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -540,7 +540,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->class_by_name =3D riscv_cpu_class_by_name; cc->has_work =3D riscv_cpu_has_work; cc->do_interrupt =3D riscv_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D riscv_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D riscv_cpu_exec_interrupt; cc->dump_state =3D riscv_cpu_dump_state; cc->set_pc =3D riscv_cpu_set_pc; cc->tcg_ops.synchronize_from_tb =3D riscv_cpu_synchronize_from_tb; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index d03c4e0b05..3ba93590d2 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -186,7 +186,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) cc->class_by_name =3D rx_cpu_class_by_name; cc->has_work =3D rx_cpu_has_work; cc->do_interrupt =3D rx_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D rx_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D rx_cpu_exec_interrupt; cc->dump_state =3D rx_cpu_dump_state; cc->set_pc =3D rx_cpu_set_pc; cc->tcg_ops.synchronize_from_tb =3D rx_cpu_synchronize_from_tb; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 697b94ff7b..add2f4b21f 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -505,7 +505,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->get_crash_info =3D s390_cpu_get_crash_info; cc->write_elf64_note =3D s390_cpu_write_elf64_note; #ifdef CONFIG_TCG - cc->cpu_exec_interrupt =3D s390_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D s390_cpu_exec_interrupt; cc->debug_excp_handler =3D s390x_cpu_debug_excp_handler; cc->do_unaligned_access =3D s390x_cpu_do_unaligned_access; #endif diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index a33025b5c8..0574194cd0 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -219,7 +219,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->class_by_name =3D superh_cpu_class_by_name; cc->has_work =3D superh_cpu_has_work; cc->do_interrupt =3D superh_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D superh_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D superh_cpu_exec_interrupt; cc->dump_state =3D superh_cpu_dump_state; cc->set_pc =3D superh_cpu_set_pc; cc->tcg_ops.synchronize_from_tb =3D superh_cpu_synchronize_from_tb; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index baf6c5b587..c559f15e14 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -862,7 +862,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->parse_features =3D sparc_cpu_parse_features; cc->has_work =3D sparc_cpu_has_work; cc->do_interrupt =3D sparc_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D sparc_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D sparc_cpu_exec_interrupt; cc->dump_state =3D sparc_cpu_dump_state; #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) cc->memory_rw_debug =3D sparc_cpu_memory_rw_debug; diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index cd24d0eb9d..4c6176d26e 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -148,7 +148,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void= *data) cc->class_by_name =3D tilegx_cpu_class_by_name; cc->has_work =3D tilegx_cpu_has_work; cc->do_interrupt =3D tilegx_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D tilegx_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D tilegx_cpu_exec_interrupt; cc->dump_state =3D tilegx_cpu_dump_state; cc->set_pc =3D tilegx_cpu_set_pc; cc->tlb_fill =3D tilegx_cpu_tlb_fill; diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 226bf4226e..84c3419989 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -132,7 +132,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) cc->class_by_name =3D uc32_cpu_class_by_name; cc->has_work =3D uc32_cpu_has_work; cc->do_interrupt =3D uc32_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D uc32_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D uc32_cpu_exec_interrupt; cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; cc->tlb_fill =3D uc32_cpu_tlb_fill; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 5a6f5bf88b..42a5e4ebe8 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -195,7 +195,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->class_by_name =3D xtensa_cpu_class_by_name; cc->has_work =3D xtensa_cpu_has_work; cc->do_interrupt =3D xtensa_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D xtensa_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt =3D xtensa_cpu_exec_interrupt; cc->dump_state =3D xtensa_cpu_dump_state; cc->set_pc =3D xtensa_cpu_set_pc; cc->gdb_read_register =3D xtensa_cpu_gdb_read_register; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 9a6932b774..e0edbac999 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10909,7 +10909,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->parse_features =3D ppc_cpu_parse_featurestr; cc->has_work =3D ppc_cpu_has_work; cc->do_interrupt =3D ppc_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D ppc_cpu_exec_interrupt; cc->dump_state =3D ppc_cpu_dump_state; cc->dump_statistics =3D ppc_cpu_dump_statistics; cc->set_pc =3D ppc_cpu_set_pc; @@ -10946,12 +10945,13 @@ static void ppc_cpu_class_init(ObjectClass *oc, v= oid *data) #endif #ifdef CONFIG_TCG cc->tcg_ops.initialize =3D ppc_translate_init; + cc->tcg_ops.cpu_exec_interrupt =3D ppc_cpu_exec_interrupt; cc->tlb_fill =3D ppc_cpu_tlb_fill; -#endif #ifndef CONFIG_USER_ONLY - cc->cpu_exec_enter =3D ppc_cpu_exec_enter; - cc->cpu_exec_exit =3D ppc_cpu_exec_exit; -#endif + cc->tcg_ops.cpu_exec_enter =3D ppc_cpu_exec_enter; + cc->tcg_ops.cpu_exec_exit =3D ppc_cpu_exec_exit; +#endif /* !CONFIG_USER_ONLY */ +#endif /* CONFIG_TCG */ =20 cc->disas_set_info =3D ppc_disas_set_info; =20 --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607603604; cv=none; d=zohomail.com; s=zohoarc; b=mxsr8wfFD0/PGIuLKkup52VCrOkxbXMyZUYgQHMxzGB/BMmsuYBpw4gEB3dno2Xo6IkGjzRrpNpOVLWqJXCxsgfTJcfIGXFoKdfsCjE2gsqOGFHxoVGhRIkQ4Xr5NHQRbO7TxMH0klzqOb1V8lPVeu1eSdmRnI4TcdCCiQDILeY= ARC-Message-Signature: i=1; a=rsa-sha256; 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Thu, 10 Dec 2020 07:33:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56628) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoi-0002Vy-Sc for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:13:04 -0500 Received: from mx2.suse.de ([195.135.220.15]:47696) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKof-0006Vl-5K for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:13:04 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id D8EFAAB91; Thu, 10 Dec 2020 12:12:49 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 20/32] cpu: Move tlb_fill to tcg_ops Date: Thu, 10 Dec 2020 13:12:14 +0100 Message-Id: <20201210121226.19822-21-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; 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Cota" , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Eduardo Habkost Signed-off-by: Eduardo Habkost [claudio: wrapped in CONFIG_TCG] Signed-off-by: Claudio Fontana Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e --- include/hw/core/cpu.h | 9 --------- include/hw/core/tcg-cpu-ops.h | 12 ++++++++++++ accel/tcg/cputlb.c | 6 +++--- accel/tcg/user-exec.c | 6 +++--- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/avr/cpu.c | 2 +- target/cris/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/tcg/tcg-cpu.c | 2 +- target/lm32/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/moxie/cpu.c | 2 +- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tilegx/cpu.c | 2 +- target/tricore/cpu.c | 2 +- target/unicore32/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- target/ppc/translate_init.c.inc | 2 +- 27 files changed, 41 insertions(+), 38 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 52142e9094..c82ef261c6 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -110,12 +110,6 @@ struct TranslationBlock; * If the target behaviour here is anything other than "set * the PC register to the value passed in" then the target must * also implement the synchronize_from_tb hook. - * @tlb_fill: Callback for handling a softmmu tlb miss or user-only - * address fault. For system mode, if the access is valid, call - * tlb_set_page and return true; if the access is invalid, and - * probe is true, return false; otherwise raise an exception and - * do not return. For user-only mode, always raise an exception - * and do not return. * @get_phys_page_debug: Callback for obtaining a physical address. * @get_phys_page_attrs_debug: Callback for obtaining a physical address a= nd the * associated memory transaction attributes to use for the access. @@ -183,9 +177,6 @@ struct CPUClass { void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); - bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index fbd579c2a6..deeabbcf33 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -38,6 +38,18 @@ typedef struct TcgCpuOperations { void (*cpu_exec_exit)(CPUState *cpu); /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exe= c */ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); + /** + * @tlb_fill: Handle a softmmu tlb miss or user-only address fault + * + * For system mode, if the access is valid, call tlb_set_page + * and return true; if the access is invalid, and probe is + * true, return false; otherwise raise an exception and do + * not return. For user-only mode, always raise an exception + * and do not return. + */ + bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); } TcgCpuOperations; =20 #endif /* TCG_CPU_OPS_H */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 42ab79c1a5..2dc71b5528 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1286,7 +1286,7 @@ static void tlb_fill(CPUState *cpu, target_ulong addr= , int size, * This is not a probe, so only valid return is success; failure * should result in exception + longjmp to the cpu loop. */ - ok =3D cc->tlb_fill(cpu, addr, size, access_type, mmu_idx, false, reta= ddr); + ok =3D cc->tcg_ops.tlb_fill(cpu, addr, size, access_type, mmu_idx, fal= se, retaddr); assert(ok); } =20 @@ -1557,8 +1557,8 @@ static int probe_access_internal(CPUArchState *env, t= arget_ulong addr, CPUState *cs =3D env_cpu(env); CPUClass *cc =3D CPU_GET_CLASS(cs); =20 - if (!cc->tlb_fill(cs, addr, fault_size, access_type, - mmu_idx, nonfault, retaddr)) { + if (!cc->tcg_ops.tlb_fill(cs, addr, fault_size, access_type, + mmu_idx, nonfault, retaddr)) { /* Non-faulting page table read failed. */ *phost =3D NULL; return TLB_INVALID_MASK; diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 4ebe25461a..7f53992251 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -186,7 +186,7 @@ static inline int handle_cpu_signal(uintptr_t pc, sigin= fo_t *info, clear_helper_retaddr(); =20 cc =3D CPU_GET_CLASS(cpu); - cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc); + cc->tcg_ops.tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false= , pc); g_assert_not_reached(); } =20 @@ -216,8 +216,8 @@ static int probe_access_internal(CPUArchState *env, tar= get_ulong addr, } else { CPUState *cpu =3D env_cpu(env); CPUClass *cc =3D CPU_GET_CLASS(cpu); - cc->tlb_fill(cpu, addr, fault_size, access_type, - MMU_USER_IDX, false, ra); + cc->tcg_ops.tlb_fill(cpu, addr, fault_size, access_type, + MMU_USER_IDX, false, ra); g_assert_not_reached(); } } diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 4f206c154d..0369d5a99c 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -222,7 +222,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->set_pc =3D alpha_cpu_set_pc; cc->gdb_read_register =3D alpha_cpu_gdb_read_register; cc->gdb_write_register =3D alpha_cpu_gdb_write_register; - cc->tlb_fill =3D alpha_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D alpha_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->do_transaction_failed =3D alpha_cpu_do_transaction_failed; cc->do_unaligned_access =3D alpha_cpu_do_unaligned_access; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 470b7b48c3..0dac097367 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2262,7 +2262,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->tcg_ops.initialize =3D arm_translate_init; cc->tcg_ops.cpu_exec_interrupt =3D arm_cpu_exec_interrupt; cc->tcg_ops.synchronize_from_tb =3D arm_cpu_synchronize_from_tb; - cc->tlb_fill =3D arm_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D arm_cpu_tlb_fill; cc->debug_excp_handler =3D arm_debug_excp_handler; cc->debug_check_watchpoint =3D arm_debug_check_watchpoint; cc->do_unaligned_access =3D arm_cpu_do_unaligned_access; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 277b00dbfc..699055de7c 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -203,7 +203,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->set_pc =3D avr_cpu_set_pc; cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; cc->get_phys_page_debug =3D avr_cpu_get_phys_page_debug; - cc->tlb_fill =3D avr_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D avr_cpu_tlb_fill; cc->vmsd =3D &vms_avr_cpu; cc->disas_set_info =3D avr_cpu_disas_set_info; cc->tcg_ops.initialize =3D avr_cpu_tcg_init; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 7489fc20c8..9222717f3e 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -274,7 +274,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->set_pc =3D cris_cpu_set_pc; cc->gdb_read_register =3D cris_cpu_gdb_read_register; cc->gdb_write_register =3D cris_cpu_gdb_write_register; - cc->tlb_fill =3D cris_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D cris_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D cris_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_cris_cpu; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 61444753f2..e2d79f954e 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -146,7 +146,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->tcg_ops.synchronize_from_tb =3D hppa_cpu_synchronize_from_tb; cc->gdb_read_register =3D hppa_cpu_gdb_read_register; cc->gdb_write_register =3D hppa_cpu_gdb_write_register; - cc->tlb_fill =3D hppa_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D hppa_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_hppa_cpu; diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 5e0f2a2fae..8606dd6a3e 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -64,7 +64,7 @@ void tcg_cpu_common_class_init(CPUClass *cc) cc->tcg_ops.cpu_exec_enter =3D x86_cpu_exec_enter; cc->tcg_ops.cpu_exec_exit =3D x86_cpu_exec_exit; cc->tcg_ops.initialize =3D tcg_x86_init; - cc->tlb_fill =3D x86_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D x86_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->debug_excp_handler =3D breakpoint_handler; #endif diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index eea2d3e515..76dc728858 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -228,7 +228,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) cc->set_pc =3D lm32_cpu_set_pc; cc->gdb_read_register =3D lm32_cpu_gdb_read_register; cc->gdb_write_register =3D lm32_cpu_gdb_write_register; - cc->tlb_fill =3D lm32_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D lm32_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D lm32_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_lm32_cpu; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index c0fa517fc3..bc109faa21 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -283,7 +283,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->set_pc =3D m68k_cpu_set_pc; cc->gdb_read_register =3D m68k_cpu_gdb_read_register; cc->gdb_write_register =3D m68k_cpu_gdb_write_register; - cc->tlb_fill =3D m68k_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D m68k_cpu_tlb_fill; #if defined(CONFIG_SOFTMMU) cc->do_transaction_failed =3D m68k_cpu_transaction_failed; cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 833d7f2d59..6e660a27b8 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -325,7 +325,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->tcg_ops.synchronize_from_tb =3D mb_cpu_synchronize_from_tb; cc->gdb_read_register =3D mb_cpu_gdb_read_register; cc->gdb_write_register =3D mb_cpu_gdb_write_register; - cc->tlb_fill =3D mb_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D mb_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->do_transaction_failed =3D mb_cpu_transaction_failed; cc->get_phys_page_debug =3D mb_cpu_get_phys_page_debug; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 344ee402fc..1f7573d319 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -250,7 +250,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->tcg_ops.initialize =3D mips_tcg_init; cc->tcg_ops.cpu_exec_interrupt =3D mips_cpu_exec_interrupt; cc->tcg_ops.synchronize_from_tb =3D mips_cpu_synchronize_from_tb; - cc->tlb_fill =3D mips_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D mips_cpu_tlb_fill; #endif =20 cc->gdb_num_core_regs =3D 73; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 224cfc8361..1177d092c1 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -110,7 +110,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) cc->do_interrupt =3D moxie_cpu_do_interrupt; cc->dump_state =3D moxie_cpu_dump_state; cc->set_pc =3D moxie_cpu_set_pc; - cc->tlb_fill =3D moxie_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D moxie_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D moxie_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_moxie_cpu; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 9eeb01fb5b..a96b74b00c 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -197,7 +197,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) cc->dump_state =3D nios2_cpu_dump_state; cc->set_pc =3D nios2_cpu_set_pc; cc->disas_set_info =3D nios2_cpu_disas_set_info; - cc->tlb_fill =3D nios2_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D nios2_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->do_unaligned_access =3D nios2_cpu_do_unaligned_access; cc->get_phys_page_debug =3D nios2_cpu_get_phys_page_debug; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index df8a41f956..e6d1c9764b 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -160,7 +160,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->set_pc =3D openrisc_cpu_set_pc; cc->gdb_read_register =3D openrisc_cpu_gdb_read_register; cc->gdb_write_register =3D openrisc_cpu_gdb_write_register; - cc->tlb_fill =3D openrisc_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D openrisc_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_openrisc_cpu; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 15d58698a6..31a43f7bfb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -562,7 +562,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->vmsd =3D &vmstate_riscv_cpu; #endif cc->tcg_ops.initialize =3D riscv_translate_init; - cc->tlb_fill =3D riscv_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D riscv_cpu_tlb_fill; =20 device_class_set_props(dc, riscv_cpu_properties); } diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 3ba93590d2..c815533223 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -195,7 +195,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) cc->get_phys_page_debug =3D rx_cpu_get_phys_page_debug; cc->disas_set_info =3D rx_cpu_disas_set_info; cc->tcg_ops.initialize =3D rx_translate_init; - cc->tlb_fill =3D rx_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D rx_cpu_tlb_fill; =20 cc->gdb_num_core_regs =3D 26; cc->gdb_core_xml_file =3D "rx-core.xml"; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index add2f4b21f..6cd2b30192 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -513,7 +513,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->disas_set_info =3D s390_cpu_disas_set_info; #ifdef CONFIG_TCG cc->tcg_ops.initialize =3D s390x_translate_init; - cc->tlb_fill =3D s390_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D s390_cpu_tlb_fill; #endif =20 cc->gdb_num_core_regs =3D S390_NUM_CORE_REGS; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 0574194cd0..7a9019edec 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -225,7 +225,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->tcg_ops.synchronize_from_tb =3D superh_cpu_synchronize_from_tb; cc->gdb_read_register =3D superh_cpu_gdb_read_register; cc->gdb_write_register =3D superh_cpu_gdb_write_register; - cc->tlb_fill =3D superh_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D superh_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->do_unaligned_access =3D superh_cpu_do_unaligned_access; cc->get_phys_page_debug =3D superh_cpu_get_phys_page_debug; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index c559f15e14..760e0ea92c 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -871,7 +871,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->tcg_ops.synchronize_from_tb =3D sparc_cpu_synchronize_from_tb; cc->gdb_read_register =3D sparc_cpu_gdb_read_register; cc->gdb_write_register =3D sparc_cpu_gdb_write_register; - cc->tlb_fill =3D sparc_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D sparc_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->do_transaction_failed =3D sparc_cpu_do_transaction_failed; cc->do_unaligned_access =3D sparc_cpu_do_unaligned_access; diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index 4c6176d26e..75b3a4bae3 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -151,7 +151,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void= *data) cc->tcg_ops.cpu_exec_interrupt =3D tilegx_cpu_exec_interrupt; cc->dump_state =3D tilegx_cpu_dump_state; cc->set_pc =3D tilegx_cpu_set_pc; - cc->tlb_fill =3D tilegx_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D tilegx_cpu_tlb_fill; cc->gdb_num_core_regs =3D 0; cc->tcg_ops.initialize =3D tilegx_tcg_init; } diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 5edf96c600..89a14f81d7 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -165,7 +165,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) cc->tcg_ops.synchronize_from_tb =3D tricore_cpu_synchronize_from_tb; cc->get_phys_page_debug =3D tricore_cpu_get_phys_page_debug; cc->tcg_ops.initialize =3D tricore_tcg_init; - cc->tlb_fill =3D tricore_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D tricore_cpu_tlb_fill; } =20 #define DEFINE_TRICORE_CPU_TYPE(cpu_model, initfn) \ diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 84c3419989..a57d315d2f 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -135,7 +135,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) cc->tcg_ops.cpu_exec_interrupt =3D uc32_cpu_exec_interrupt; cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; - cc->tlb_fill =3D uc32_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D uc32_cpu_tlb_fill; cc->get_phys_page_debug =3D uc32_cpu_get_phys_page_debug; cc->tcg_ops.initialize =3D uc32_translate_init; dc->vmsd =3D &vmstate_uc32_cpu; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 42a5e4ebe8..e764dbeb73 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -201,7 +201,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_read_register =3D xtensa_cpu_gdb_read_register; cc->gdb_write_register =3D xtensa_cpu_gdb_write_register; cc->gdb_stop_before_watchpoint =3D true; - cc->tlb_fill =3D xtensa_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D xtensa_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->do_unaligned_access =3D xtensa_cpu_do_unaligned_access; cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index e0edbac999..e83000b2fb 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10946,7 +10946,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) #ifdef CONFIG_TCG cc->tcg_ops.initialize =3D ppc_translate_init; cc->tcg_ops.cpu_exec_interrupt =3D ppc_cpu_exec_interrupt; - cc->tlb_fill =3D ppc_cpu_tlb_fill; + cc->tcg_ops.tlb_fill =3D ppc_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->tcg_ops.cpu_exec_enter =3D ppc_cpu_exec_enter; cc->tcg_ops.cpu_exec_exit =3D ppc_cpu_exec_exit; --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607603875; cv=none; d=zohomail.com; s=zohoarc; b=S9vmuHSi40+Wn9WaTubvIbODH25gnnIMQq8S4PgnHEEAeeMvwEFfinMh8gbOyNRn0ERPOCefBeYUbDZSNOxZy8XK0wzhFdflWd2/rgtvyZ141/DkcIfc0TQLmA0RK5A0MYBfa0/13el2F56UpjkaOCVmG0/lf8FePjyIN43RkOY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607603875; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Thu, 10 Dec 2020 07:13:06 -0500 Received: from mx2.suse.de ([195.135.220.15]:47832) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoi-0006Wq-Ay for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:13:06 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id DE8CAAD87; Thu, 10 Dec 2020 12:12:50 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 21/32] cpu: Move debug_excp_handler to tcg_ops Date: Thu, 10 Dec 2020 13:12:15 +0100 Message-Id: <20201210121226.19822-22-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Colin Xu , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Eduardo Habkost Signed-off-by: Eduardo Habkost Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e --- include/hw/core/cpu.h | 2 -- include/hw/core/tcg-cpu-ops.h | 2 ++ accel/tcg/cpu-exec.c | 4 ++-- target/arm/cpu.c | 2 +- target/i386/tcg/tcg-cpu.c | 2 +- target/lm32/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- 8 files changed, 9 insertions(+), 9 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index c82ef261c6..f438abb785 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -121,7 +121,6 @@ struct TranslationBlock; * @gdb_write_register: Callback for letting GDB write a register. * @debug_check_watchpoint: Callback: return true if the architectural * watchpoint whose address has matched should really fire. - * @debug_excp_handler: Callback for handling debug exceptions. * @write_elf64_note: Callback for writing a CPU-specific ELF note to a * 64-bit VM coredump. * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF @@ -184,7 +183,6 @@ struct CPUClass { int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); - void (*debug_excp_handler)(CPUState *cpu); =20 int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, int cpuid, void *opaque); diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index deeabbcf33..322204c441 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -50,6 +50,8 @@ typedef struct TcgCpuOperations { bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); + /** @debug_excp_handler: Callback for handling debug exceptions */ + void (*debug_excp_handler)(CPUState *cpu); } TcgCpuOperations; =20 #endif /* TCG_CPU_OPS_H */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 502f6a53ae..17dc86af50 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -482,8 +482,8 @@ static inline void cpu_handle_debug_exception(CPUState = *cpu) } } =20 - if (cc->debug_excp_handler) { - cc->debug_excp_handler(cpu); + if (cc->tcg_ops.debug_excp_handler) { + cc->tcg_ops.debug_excp_handler(cpu); } } =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0dac097367..20cbfaea51 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2263,7 +2263,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->tcg_ops.cpu_exec_interrupt =3D arm_cpu_exec_interrupt; cc->tcg_ops.synchronize_from_tb =3D arm_cpu_synchronize_from_tb; cc->tcg_ops.tlb_fill =3D arm_cpu_tlb_fill; - cc->debug_excp_handler =3D arm_debug_excp_handler; + cc->tcg_ops.debug_excp_handler =3D arm_debug_excp_handler; cc->debug_check_watchpoint =3D arm_debug_check_watchpoint; cc->do_unaligned_access =3D arm_cpu_do_unaligned_access; #if !defined(CONFIG_USER_ONLY) diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 8606dd6a3e..38ed8bf6d3 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -66,6 +66,6 @@ void tcg_cpu_common_class_init(CPUClass *cc) cc->tcg_ops.initialize =3D tcg_x86_init; cc->tcg_ops.tlb_fill =3D x86_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY - cc->debug_excp_handler =3D breakpoint_handler; + cc->tcg_ops.debug_excp_handler =3D breakpoint_handler; #endif } diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index 76dc728858..bbe1405e32 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -235,7 +235,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) #endif cc->gdb_num_core_regs =3D 32 + 7; cc->gdb_stop_before_watchpoint =3D true; - cc->debug_excp_handler =3D lm32_debug_excp_handler; + cc->tcg_ops.debug_excp_handler =3D lm32_debug_excp_handler; cc->disas_set_info =3D lm32_cpu_disas_set_info; cc->tcg_ops.initialize =3D lm32_translate_init; } diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 6cd2b30192..04856076b3 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -506,7 +506,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->write_elf64_note =3D s390_cpu_write_elf64_note; #ifdef CONFIG_TCG cc->tcg_ops.cpu_exec_interrupt =3D s390_cpu_exec_interrupt; - cc->debug_excp_handler =3D s390x_cpu_debug_excp_handler; + cc->tcg_ops.debug_excp_handler =3D s390x_cpu_debug_excp_handler; cc->do_unaligned_access =3D s390x_cpu_do_unaligned_access; #endif #endif diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index e764dbeb73..b6f13ceb32 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -207,7 +207,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; cc->do_transaction_failed =3D xtensa_cpu_do_transaction_failed; #endif - cc->debug_excp_handler =3D xtensa_breakpoint_handler; + cc->tcg_ops.debug_excp_handler =3D xtensa_breakpoint_handler; cc->disas_set_info =3D xtensa_cpu_disas_set_info; cc->tcg_ops.initialize =3D xtensa_translate_init; dc->vmsd =3D &vmstate_xtensa_cpu; --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Thu, 10 Dec 2020 05:51:05 -0800 (PST) Received: from localhost ([::1]:39574 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knLkh-0002YV-ED for importer@patchew.org; Thu, 10 Dec 2020 08:12:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56674) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKol-0002ZR-Fe for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:13:09 -0500 Received: from mx2.suse.de ([195.135.220.15]:47830) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoi-0006Wp-M5 for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:13:07 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id E4448AD57; Thu, 10 Dec 2020 12:12:51 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 22/32] target/arm: do not use cc->do_interrupt for KVM directly Date: Thu, 10 Dec 2020 13:12:16 +0100 Message-Id: <20201210121226.19822-23-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" cc->do_interrupt is in theory a TCG callback used in accel/tcg only, to prepare the emulated architecture to take an interrupt as defined in the hardware specifications, but in reality the _do_interrupt style of functions in targets are also occasionally reused by KVM to prepare the architecture state in a similar way where userspace code has identified that it needs to deliver an exception to the guest. In the case of ARM, that includes: 1) the vcpu thread got a SIGBUS indicating a memory error, and we need to deliver a Synchronous External Abort to the guest to let it know about the error. 2) the kernel told us about a debug exception (breakpoint, watchpoint) but it is not for one of QEMU's own gdbstub breakpoints/watchpoints so it must be a breakpoint the guest itself has set up, therefore we need to deliver it to the guest. So in order to reuse code, the same arm_do_interrupt function is used. This is all fine, but we need to avoid calling it using the callback registered in CPUClass, since that one is now TCG-only. Fortunately this is easily solved by replacing calls to CPUClass::do_interrupt() with explicit calls to arm_do_interrupt(). Signed-off-by: Claudio Fontana Cc: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 4 ++++ target/arm/kvm64.c | 6 ++---- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 38cd35c049..bebaabf525 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9895,6 +9895,10 @@ static void handle_semihosting(CPUState *cs) * Do any appropriate logging, handle PSCI calls, and then hand off * to the AArch64-entry or AArch32-entry function depending on the * target exception level's register width. + * + * Note: this is used for both TCG (as the do_interrupt tcg op), + * and KVM to re-inject guest debug exceptions, and to + * inject a Synchronous-External-Abort. */ void arm_cpu_do_interrupt(CPUState *cs) { diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index f74bac2457..3728b3a336 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -944,7 +944,6 @@ static void kvm_inject_arm_sea(CPUState *c) { ARMCPU *cpu =3D ARM_CPU(c); CPUARMState *env =3D &cpu->env; - CPUClass *cc =3D CPU_GET_CLASS(c); uint32_t esr; bool same_el; =20 @@ -960,7 +959,7 @@ static void kvm_inject_arm_sea(CPUState *c) =20 env->exception.syndrome =3D esr; =20 - cc->do_interrupt(c); + arm_cpu_do_interrupt(c); } =20 #define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ @@ -1491,7 +1490,6 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_de= bug_exit_arch *debug_exit) { int hsr_ec =3D syn_get_ec(debug_exit->hsr); ARMCPU *cpu =3D ARM_CPU(cs); - CPUClass *cc =3D CPU_GET_CLASS(cs); CPUARMState *env =3D &cpu->env; =20 /* Ensure PC is synchronised */ @@ -1545,7 +1543,7 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_de= bug_exit_arch *debug_exit) env->exception.vaddress =3D debug_exit->far; env->exception.target_el =3D 1; qemu_mutex_lock_iothread(); - cc->do_interrupt(cs); + arm_cpu_do_interrupt(cs); qemu_mutex_unlock_iothread(); =20 return false; --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 10 Dec 2020 04:43:14 -0800 (PST) Received: from localhost ([::1]:33800 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knLHr-0001Nx-QU for importer@patchew.org; Thu, 10 Dec 2020 07:43:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56798) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKow-0002iC-Ub for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:13:20 -0500 Received: from mx2.suse.de ([195.135.220.15]:47870) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoj-0006X5-QM for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:13:18 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id F030DAD8C; Thu, 10 Dec 2020 12:12:52 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 23/32] cpu: move cc->do_interrupt to tcg_ops Date: Thu, 10 Dec 2020 13:12:17 +0100 Message-Id: <20201210121226.19822-24-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 2 -- include/hw/core/tcg-cpu-ops.h | 3 +++ accel/tcg/cpu-exec.c | 4 ++-- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 6 ++++-- target/arm/cpu_tcg.c | 9 ++++----- target/avr/cpu.c | 2 +- target/avr/helper.c | 4 ++-- target/cris/cpu.c | 12 ++++++------ target/cris/helper.c | 4 ++-- target/hppa/cpu.c | 2 +- target/i386/tcg/tcg-cpu.c | 2 +- target/lm32/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 6 ++++-- target/moxie/cpu.c | 2 +- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tilegx/cpu.c | 2 +- target/unicore32/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- target/ppc/translate_init.c.inc | 2 +- 28 files changed, 46 insertions(+), 42 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index f438abb785..b178549d48 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -87,7 +87,6 @@ struct TranslationBlock; * @parse_features: Callback to parse command line arguments. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. * @has_work: Callback for checking if there is work to do. - * @do_interrupt: Callback for interrupt handling. * @do_unaligned_access: Callback for unaligned access handling, if * the target defines #TARGET_ALIGNED_ONLY. * @do_transaction_failed: Callback for handling failed memory transactions @@ -157,7 +156,6 @@ struct CPUClass { =20 int reset_dump_flags; bool (*has_work)(CPUState *cpu); - void (*do_interrupt)(CPUState *cpu); void (*do_unaligned_access)(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 322204c441..a7387b5c39 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -38,6 +38,9 @@ typedef struct TcgCpuOperations { void (*cpu_exec_exit)(CPUState *cpu); /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exe= c */ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); + /** @do_interrupt: Callback for interrupt handling. */ + void (*do_interrupt)(CPUState *cpu); + /** * @tlb_fill: Handle a softmmu tlb miss or user-only address fault * diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 17dc86af50..eafd600085 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -517,7 +517,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, = int *ret) loop */ #if defined(TARGET_I386) CPUClass *cc =3D CPU_GET_CLASS(cpu); - cc->do_interrupt(cpu); + cc->tcg_ops.do_interrupt(cpu); #endif *ret =3D cpu->exception_index; cpu->exception_index =3D -1; @@ -526,7 +526,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, = int *ret) if (replay_exception()) { CPUClass *cc =3D CPU_GET_CLASS(cpu); qemu_mutex_lock_iothread(); - cc->do_interrupt(cpu); + cc->tcg_ops.do_interrupt(cpu); qemu_mutex_unlock_iothread(); cpu->exception_index =3D -1; =20 diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 0369d5a99c..fde5825ebc 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -217,7 +217,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) =20 cc->class_by_name =3D alpha_cpu_class_by_name; cc->has_work =3D alpha_cpu_has_work; - cc->do_interrupt =3D alpha_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D alpha_cpu_do_interrupt; cc->dump_state =3D alpha_cpu_dump_state; cc->set_pc =3D alpha_cpu_set_pc; cc->gdb_read_register =3D alpha_cpu_gdb_read_register; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 20cbfaea51..826cf8351b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -535,6 +535,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsi= gned int excp_idx, return unmasked || pstate_unmasked; } =20 +#ifdef CONFIG_TCG bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc =3D CPU_GET_CLASS(cs); @@ -584,9 +585,10 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) found: cs->exception_index =3D excp_idx; env->exception.target_el =3D target_el; - cc->do_interrupt(cs); + cc->tcg_ops.do_interrupt(cs); return true; } +#endif /* CONFIG_TCG */ =20 void arm_cpu_update_virq(ARMCPU *cpu) { @@ -2244,7 +2246,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D arm_cpu_gdb_read_register; cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->do_interrupt =3D arm_cpu_do_interrupt; cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs =3D arm_asidx_from_attrs; cc->vmsd =3D &vmstate_arm_cpu; @@ -2269,6 +2270,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) #if !defined(CONFIG_USER_ONLY) cc->do_transaction_failed =3D arm_cpu_do_transaction_failed; cc->adjust_watchpoint_address =3D arm_adjust_watchpoint_address; + cc->tcg_ops.do_interrupt =3D arm_cpu_do_interrupt; #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ #endif } diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index a6538d3a96..e64f18a5ee 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -33,7 +33,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int = interrupt_request) if (interrupt_request & CPU_INTERRUPT_HARD && (armv7m_nvic_can_take_pending_exception(env->nvic))) { cs->exception_index =3D EXCP_IRQ; - cc->do_interrupt(cs); + cc->tcg_ops.do_interrupt(cs); ret =3D true; } return ret; @@ -624,12 +624,11 @@ static void arm_v7m_class_init(ObjectClass *oc, void = *data) CPUClass *cc =3D CPU_CLASS(oc); =20 acc->info =3D data; -#ifndef CONFIG_USER_ONLY - cc->do_interrupt =3D arm_v7m_cpu_do_interrupt; -#endif - #ifdef CONFIG_TCG cc->tcg_ops.cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt; +#ifndef CONFIG_USER_ONLY + cc->tcg_ops.do_interrupt =3D arm_v7m_cpu_do_interrupt; +#endif #endif /* CONFIG_TCG */ =20 cc->gdb_core_xml_file =3D "arm-m-profile.xml"; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 699055de7c..5a5ae68444 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -197,7 +197,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->class_by_name =3D avr_cpu_class_by_name; =20 cc->has_work =3D avr_cpu_has_work; - cc->do_interrupt =3D avr_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D avr_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D avr_cpu_exec_interrupt; cc->dump_state =3D avr_cpu_dump_state; cc->set_pc =3D avr_cpu_set_pc; diff --git a/target/avr/helper.c b/target/avr/helper.c index d96d14372b..69d3b6181f 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -34,7 +34,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_r= equest) if (interrupt_request & CPU_INTERRUPT_RESET) { if (cpu_interrupts_enabled(env)) { cs->exception_index =3D EXCP_RESET; - cc->do_interrupt(cs); + cc->tcg_ops.do_interrupt(cs); =20 cs->interrupt_request &=3D ~CPU_INTERRUPT_RESET; =20 @@ -45,7 +45,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_r= equest) if (cpu_interrupts_enabled(env) && env->intsrc !=3D 0) { int index =3D ctz32(env->intsrc); cs->exception_index =3D EXCP_INT(index); - cc->do_interrupt(cs); + cc->tcg_ops.do_interrupt(cs); =20 env->intsrc &=3D env->intsrc - 1; /* clear the interrupt */ cs->interrupt_request &=3D ~CPU_INTERRUPT_HARD; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 9222717f3e..b65743e8ca 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -199,7 +199,7 @@ static void crisv8_cpu_class_init(ObjectClass *oc, void= *data) CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); =20 ccc->vr =3D 8; - cc->do_interrupt =3D crisv10_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; } @@ -210,7 +210,7 @@ static void crisv9_cpu_class_init(ObjectClass *oc, void= *data) CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); =20 ccc->vr =3D 9; - cc->do_interrupt =3D crisv10_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; } @@ -221,7 +221,7 @@ static void crisv10_cpu_class_init(ObjectClass *oc, voi= d *data) CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); =20 ccc->vr =3D 10; - cc->do_interrupt =3D crisv10_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; } @@ -232,7 +232,7 @@ static void crisv11_cpu_class_init(ObjectClass *oc, voi= d *data) CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); =20 ccc->vr =3D 11; - cc->do_interrupt =3D crisv10_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; } @@ -243,7 +243,7 @@ static void crisv17_cpu_class_init(ObjectClass *oc, voi= d *data) CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); =20 ccc->vr =3D 17; - cc->do_interrupt =3D crisv10_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D crisv10_cpu_do_interrupt; cc->gdb_read_register =3D crisv10_cpu_gdb_read_register; cc->tcg_ops.initialize =3D cris_initialize_crisv10_tcg; } @@ -268,7 +268,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) =20 cc->class_by_name =3D cris_cpu_class_by_name; cc->has_work =3D cris_cpu_has_work; - cc->do_interrupt =3D cris_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D cris_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D cris_cpu_exec_interrupt; cc->dump_state =3D cris_cpu_dump_state; cc->set_pc =3D cris_cpu_set_pc; diff --git a/target/cris/helper.c b/target/cris/helper.c index ed45c3d9b7..1f4d6f7d45 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -299,7 +299,7 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) && (env->pregs[PR_CCS] & I_FLAG) && !env->locked_irq) { cs->exception_index =3D EXCP_IRQ; - cc->do_interrupt(cs); + cc->tcg_ops.do_interrupt(cs); ret =3D true; } if (interrupt_request & CPU_INTERRUPT_NMI) { @@ -311,7 +311,7 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) } if ((env->pregs[PR_CCS] & m_flag_archval)) { cs->exception_index =3D EXCP_NMI; - cc->do_interrupt(cs); + cc->tcg_ops.do_interrupt(cs); ret =3D true; } } diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index e2d79f954e..cce6ae6213 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -139,7 +139,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) =20 cc->class_by_name =3D hppa_cpu_class_by_name; cc->has_work =3D hppa_cpu_has_work; - cc->do_interrupt =3D hppa_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D hppa_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D hppa_cpu_exec_interrupt; cc->dump_state =3D hppa_cpu_dump_state; cc->set_pc =3D hppa_cpu_set_pc; diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 38ed8bf6d3..d2dd521612 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -58,7 +58,7 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, Tra= nslationBlock *tb) =20 void tcg_cpu_common_class_init(CPUClass *cc) { - cc->do_interrupt =3D x86_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D x86_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D x86_cpu_exec_interrupt; cc->tcg_ops.synchronize_from_tb =3D x86_cpu_synchronize_from_tb; cc->tcg_ops.cpu_exec_enter =3D x86_cpu_exec_enter; diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index bbe1405e32..fb3761b749 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -222,7 +222,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) =20 cc->class_by_name =3D lm32_cpu_class_by_name; cc->has_work =3D lm32_cpu_has_work; - cc->do_interrupt =3D lm32_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D lm32_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D lm32_cpu_exec_interrupt; cc->dump_state =3D lm32_cpu_dump_state; cc->set_pc =3D lm32_cpu_set_pc; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index bc109faa21..3e84de772c 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -277,7 +277,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) =20 cc->class_by_name =3D m68k_cpu_class_by_name; cc->has_work =3D m68k_cpu_has_work; - cc->do_interrupt =3D m68k_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D m68k_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D m68k_cpu_exec_interrupt; cc->dump_state =3D m68k_cpu_dump_state; cc->set_pc =3D m68k_cpu_set_pc; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 6e660a27b8..4f95248b2e 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -317,7 +317,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) =20 cc->class_by_name =3D mb_cpu_class_by_name; cc->has_work =3D mb_cpu_has_work; - cc->do_interrupt =3D mb_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D mb_cpu_do_interrupt; cc->do_unaligned_access =3D mb_cpu_do_unaligned_access; cc->tcg_ops.cpu_exec_interrupt =3D mb_cpu_exec_interrupt; cc->dump_state =3D mb_cpu_dump_state; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 1f7573d319..dd5fb78e6c 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -234,7 +234,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) =20 cc->class_by_name =3D mips_cpu_class_by_name; cc->has_work =3D mips_cpu_has_work; - cc->do_interrupt =3D mips_cpu_do_interrupt; cc->dump_state =3D mips_cpu_dump_state; cc->set_pc =3D mips_cpu_set_pc; cc->gdb_read_register =3D mips_cpu_gdb_read_register; @@ -251,7 +250,10 @@ static void mips_cpu_class_init(ObjectClass *c, void *= data) cc->tcg_ops.cpu_exec_interrupt =3D mips_cpu_exec_interrupt; cc->tcg_ops.synchronize_from_tb =3D mips_cpu_synchronize_from_tb; cc->tcg_ops.tlb_fill =3D mips_cpu_tlb_fill; -#endif +#ifndef CONFIG_USER_ONLY + cc->tcg_ops.do_interrupt =3D mips_cpu_do_interrupt; +#endif /* CONFIG_USER_ONLY */ +#endif /* CONFIG_TCG */ =20 cc->gdb_num_core_regs =3D 73; cc->gdb_stop_before_watchpoint =3D true; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 1177d092c1..36bef4d357 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -107,7 +107,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) cc->class_by_name =3D moxie_cpu_class_by_name; =20 cc->has_work =3D moxie_cpu_has_work; - cc->do_interrupt =3D moxie_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D moxie_cpu_do_interrupt; cc->dump_state =3D moxie_cpu_dump_state; cc->set_pc =3D moxie_cpu_set_pc; cc->tcg_ops.tlb_fill =3D moxie_cpu_tlb_fill; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index a96b74b00c..2b959f0e49 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -192,7 +192,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) =20 cc->class_by_name =3D nios2_cpu_class_by_name; cc->has_work =3D nios2_cpu_has_work; - cc->do_interrupt =3D nios2_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D nios2_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D nios2_cpu_exec_interrupt; cc->dump_state =3D nios2_cpu_dump_state; cc->set_pc =3D nios2_cpu_set_pc; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index e6d1c9764b..27105c5c09 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -154,7 +154,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) =20 cc->class_by_name =3D openrisc_cpu_class_by_name; cc->has_work =3D openrisc_cpu_has_work; - cc->do_interrupt =3D openrisc_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D openrisc_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt; cc->dump_state =3D openrisc_cpu_dump_state; cc->set_pc =3D openrisc_cpu_set_pc; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 31a43f7bfb..6a815569cc 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -539,7 +539,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) =20 cc->class_by_name =3D riscv_cpu_class_by_name; cc->has_work =3D riscv_cpu_has_work; - cc->do_interrupt =3D riscv_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D riscv_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D riscv_cpu_exec_interrupt; cc->dump_state =3D riscv_cpu_dump_state; cc->set_pc =3D riscv_cpu_set_pc; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index c815533223..dc7d1c3c57 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -185,7 +185,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) =20 cc->class_by_name =3D rx_cpu_class_by_name; cc->has_work =3D rx_cpu_has_work; - cc->do_interrupt =3D rx_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D rx_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D rx_cpu_exec_interrupt; cc->dump_state =3D rx_cpu_dump_state; cc->set_pc =3D rx_cpu_set_pc; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 04856076b3..b838bd61a4 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -493,7 +493,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->class_by_name =3D s390_cpu_class_by_name, cc->has_work =3D s390_cpu_has_work; #ifdef CONFIG_TCG - cc->do_interrupt =3D s390_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D s390_cpu_do_interrupt; #endif cc->dump_state =3D s390_cpu_dump_state; cc->set_pc =3D s390_cpu_set_pc; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 7a9019edec..ff835d4bc1 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -218,7 +218,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->class_by_name =3D superh_cpu_class_by_name; cc->has_work =3D superh_cpu_has_work; - cc->do_interrupt =3D superh_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D superh_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D superh_cpu_exec_interrupt; cc->dump_state =3D superh_cpu_dump_state; cc->set_pc =3D superh_cpu_set_pc; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 760e0ea92c..3f23aa5962 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -861,7 +861,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->class_by_name =3D sparc_cpu_class_by_name; cc->parse_features =3D sparc_cpu_parse_features; cc->has_work =3D sparc_cpu_has_work; - cc->do_interrupt =3D sparc_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D sparc_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D sparc_cpu_exec_interrupt; cc->dump_state =3D sparc_cpu_dump_state; #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index 75b3a4bae3..7d4ead4ef1 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -147,7 +147,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->class_by_name =3D tilegx_cpu_class_by_name; cc->has_work =3D tilegx_cpu_has_work; - cc->do_interrupt =3D tilegx_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D tilegx_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D tilegx_cpu_exec_interrupt; cc->dump_state =3D tilegx_cpu_dump_state; cc->set_pc =3D tilegx_cpu_set_pc; diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index a57d315d2f..e27ffc571a 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -131,7 +131,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *= data) =20 cc->class_by_name =3D uc32_cpu_class_by_name; cc->has_work =3D uc32_cpu_has_work; - cc->do_interrupt =3D uc32_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D uc32_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D uc32_cpu_exec_interrupt; cc->dump_state =3D uc32_cpu_dump_state; cc->set_pc =3D uc32_cpu_set_pc; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index b6f13ceb32..3ff025f0fe 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -194,7 +194,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) =20 cc->class_by_name =3D xtensa_cpu_class_by_name; cc->has_work =3D xtensa_cpu_has_work; - cc->do_interrupt =3D xtensa_cpu_do_interrupt; + cc->tcg_ops.do_interrupt =3D xtensa_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D xtensa_cpu_exec_interrupt; cc->dump_state =3D xtensa_cpu_dump_state; cc->set_pc =3D xtensa_cpu_set_pc; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index e83000b2fb..0471da0d08 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10908,7 +10908,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) pcc->parent_parse_features =3D cc->parse_features; cc->parse_features =3D ppc_cpu_parse_featurestr; cc->has_work =3D ppc_cpu_has_work; - cc->do_interrupt =3D ppc_cpu_do_interrupt; cc->dump_state =3D ppc_cpu_dump_state; cc->dump_statistics =3D ppc_cpu_dump_statistics; cc->set_pc =3D ppc_cpu_set_pc; @@ -10946,6 +10945,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) #ifdef CONFIG_TCG cc->tcg_ops.initialize =3D ppc_translate_init; cc->tcg_ops.cpu_exec_interrupt =3D ppc_cpu_exec_interrupt; + cc->tcg_ops.do_interrupt =3D ppc_cpu_do_interrupt; cc->tcg_ops.tlb_fill =3D ppc_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->tcg_ops.cpu_exec_enter =3D ppc_cpu_exec_enter; --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607603778; cv=none; d=zohomail.com; s=zohoarc; b=OjxXntb2NwSUfsqXuGE1yhwIJY+ZoQplqHJVx9Sc8I4Kr5wWEt9I3ONbH1FpRCgsicfpigOyBWUPGG/9RU4mKPYv4mM1R8IevkLLFYz1Wpgm+duU+7YE6CMXiz7DfmJBs60+9Yqsl3xmRDNYeXt5+eMsO/ILSjnIk1D6HR+prHw= ARC-Message-Signature: i=1; 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Thu, 10 Dec 2020 07:36:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56714) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKop-0002az-21 for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:13:11 -0500 Received: from mx2.suse.de ([195.135.220.15]:47868) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoj-0006X4-Qr for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:13:10 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id F2485AD3F; Thu, 10 Dec 2020 12:12:53 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 24/32] cpu: move cc->transaction_failed to tcg_ops Date: Thu, 10 Dec 2020 13:12:18 +0100 Message-Id: <20201210121226.19822-25-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e --- include/hw/core/cpu.h | 18 +++++++----------- include/hw/core/tcg-cpu-ops.h | 10 ++++++++++ hw/mips/jazz.c | 9 +++++++-- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 4 ++-- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- 11 files changed, 33 insertions(+), 22 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index b178549d48..0c6c17fb48 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -89,8 +89,6 @@ struct TranslationBlock; * @has_work: Callback for checking if there is work to do. * @do_unaligned_access: Callback for unaligned access handling, if * the target defines #TARGET_ALIGNED_ONLY. - * @do_transaction_failed: Callback for handling failed memory transactions - * (ie bus faults or external aborts; not MMU faults) * @virtio_is_big_endian: Callback to return %true if a CPU which supports * runtime configurable endianness is currently big-endian. Non-configurab= le * CPUs can use the default implementation of this method. This method sho= uld @@ -159,10 +157,6 @@ struct CPUClass { void (*do_unaligned_access)(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); - void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr ad= dr, - unsigned size, MMUAccessType access_type, - int mmu_idx, MemTxAttrs attrs, - MemTxResult response, uintptr_t retaddr); bool (*virtio_is_big_endian)(CPUState *cpu); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); @@ -848,7 +842,7 @@ static inline void cpu_unaligned_access(CPUState *cpu, = vaddr addr, =20 cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr); } - +#ifdef CONFIG_TCG static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, @@ -858,12 +852,14 @@ static inline void cpu_transaction_failed(CPUState *c= pu, hwaddr physaddr, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (!cpu->ignore_memory_transaction_failures && cc->do_transaction_fai= led) { - cc->do_transaction_failed(cpu, physaddr, addr, size, access_type, - mmu_idx, attrs, response, retaddr); + if (!cpu->ignore_memory_transaction_failures && + cc->tcg_ops.do_transaction_failed) { + cc->tcg_ops.do_transaction_failed(cpu, physaddr, addr, size, acces= s_type, + mmu_idx, attrs, response, retadd= r); } } -#endif +#endif /* CONFIG_TCG */ +#endif /* CONFIG_SOFTMMU */ =20 #endif /* NEED_CPU_H */ =20 diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index a7387b5c39..3cc2733410 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -11,6 +11,7 @@ #define TCG_CPU_OPS_H =20 #include "hw/core/cpu.h" +#include "exec/memattrs.h" =20 /** * struct TcgCpuOperations: TCG operations specific to a CPU class @@ -41,6 +42,15 @@ typedef struct TcgCpuOperations { /** @do_interrupt: Callback for interrupt handling. */ void (*do_interrupt)(CPUState *cpu); =20 + /** + * @do_transaction_failed: Callback for handling failed memory transac= tions + * (ie bus faults or external aborts; not MMU faults) + */ + void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr ad= dr, + unsigned size, MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr); + /** * @tlb_fill: Handle a softmmu tlb miss or user-only address fault * diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c index 71448f72ac..2745ba3906 100644 --- a/hw/mips/jazz.c +++ b/hw/mips/jazz.c @@ -115,6 +115,8 @@ static const MemoryRegionOps dma_dummy_ops =3D { #define MAGNUM_BIOS_SIZE_MAX 0x7e000 #define MAGNUM_BIOS_SIZE = \ (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_M= AX) + +#ifdef CONFIG_TCG static void (*real_do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, @@ -136,6 +138,7 @@ static void mips_jazz_do_transaction_failed(CPUState *c= s, hwaddr physaddr, (*real_do_transaction_failed)(cs, physaddr, addr, size, access_type, mmu_idx, attrs, response, retaddr); } +#endif /* CONFIG_TCG */ =20 static void mips_jazz_init(MachineState *machine, enum jazz_model_e jazz_model) @@ -204,8 +207,10 @@ static void mips_jazz_init(MachineState *machine, * memory region that catches all memory accesses, as we do on Malta. */ cc =3D CPU_GET_CLASS(cpu); - real_do_transaction_failed =3D cc->do_transaction_failed; - cc->do_transaction_failed =3D mips_jazz_do_transaction_failed; +#ifdef CONFIG_TCG + real_do_transaction_failed =3D cc->tcg_ops.do_transaction_failed; + cc->tcg_ops.do_transaction_failed =3D mips_jazz_do_transaction_failed; +#endif /* CONFIG_TCG */ =20 /* allocate RAM */ memory_region_add_subregion(address_space, 0, machine->ram); diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index fde5825ebc..3e651b246f 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -224,7 +224,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D alpha_cpu_gdb_write_register; cc->tcg_ops.tlb_fill =3D alpha_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY - cc->do_transaction_failed =3D alpha_cpu_do_transaction_failed; + cc->tcg_ops.do_transaction_failed =3D alpha_cpu_do_transaction_failed; cc->do_unaligned_access =3D alpha_cpu_do_unaligned_access; cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_alpha_cpu; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 826cf8351b..5e9202ed86 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2268,11 +2268,11 @@ static void arm_cpu_class_init(ObjectClass *oc, voi= d *data) cc->debug_check_watchpoint =3D arm_debug_check_watchpoint; cc->do_unaligned_access =3D arm_cpu_do_unaligned_access; #if !defined(CONFIG_USER_ONLY) - cc->do_transaction_failed =3D arm_cpu_do_transaction_failed; + cc->tcg_ops.do_transaction_failed =3D arm_cpu_do_transaction_failed; cc->adjust_watchpoint_address =3D arm_adjust_watchpoint_address; cc->tcg_ops.do_interrupt =3D arm_cpu_do_interrupt; #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ -#endif +#endif /* CONFIG_TCG */ } =20 #ifdef CONFIG_KVM diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 3e84de772c..3f60c99865 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -285,7 +285,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_write_register =3D m68k_cpu_gdb_write_register; cc->tcg_ops.tlb_fill =3D m68k_cpu_tlb_fill; #if defined(CONFIG_SOFTMMU) - cc->do_transaction_failed =3D m68k_cpu_transaction_failed; + cc->tcg_ops.do_transaction_failed =3D m68k_cpu_transaction_failed; cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D m68k_cpu_disas_set_info; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 4f95248b2e..fa57a324dc 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -327,7 +327,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->gdb_write_register =3D mb_cpu_gdb_write_register; cc->tcg_ops.tlb_fill =3D mb_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY - cc->do_transaction_failed =3D mb_cpu_transaction_failed; + cc->tcg_ops.do_transaction_failed =3D mb_cpu_transaction_failed; cc->get_phys_page_debug =3D mb_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_mb_cpu; #endif diff --git a/target/mips/cpu.c b/target/mips/cpu.c index dd5fb78e6c..259bb791f7 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -239,7 +239,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_read_register =3D mips_cpu_gdb_read_register; cc->gdb_write_register =3D mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->do_transaction_failed =3D mips_cpu_do_transaction_failed; cc->do_unaligned_access =3D mips_cpu_do_unaligned_access; cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_mips_cpu; @@ -252,6 +251,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->tcg_ops.tlb_fill =3D mips_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->tcg_ops.do_interrupt =3D mips_cpu_do_interrupt; + cc->tcg_ops.do_transaction_failed =3D mips_cpu_do_transaction_failed; #endif /* CONFIG_USER_ONLY */ #endif /* CONFIG_TCG */ =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6a815569cc..7dfd8d7339 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -555,7 +555,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->gdb_stop_before_watchpoint =3D true; cc->disas_set_info =3D riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY - cc->do_transaction_failed =3D riscv_cpu_do_transaction_failed; + cc->tcg_ops.do_transaction_failed =3D riscv_cpu_do_transaction_failed; cc->do_unaligned_access =3D riscv_cpu_do_unaligned_access; cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; /* For now, mark unmigratable: */ diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 3f23aa5962..009d0f07c3 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -873,7 +873,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D sparc_cpu_gdb_write_register; cc->tcg_ops.tlb_fill =3D sparc_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY - cc->do_transaction_failed =3D sparc_cpu_do_transaction_failed; + cc->tcg_ops.do_transaction_failed =3D sparc_cpu_do_transaction_failed; cc->do_unaligned_access =3D sparc_cpu_do_unaligned_access; cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_sparc_cpu; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 3ff025f0fe..fc52fde696 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -205,7 +205,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) #ifndef CONFIG_USER_ONLY cc->do_unaligned_access =3D xtensa_cpu_do_unaligned_access; cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; - cc->do_transaction_failed =3D xtensa_cpu_do_transaction_failed; + cc->tcg_ops.do_transaction_failed =3D xtensa_cpu_do_transaction_failed; #endif cc->tcg_ops.debug_excp_handler =3D xtensa_breakpoint_handler; cc->disas_set_info =3D xtensa_cpu_disas_set_info; --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" make it consistently SOFTMMU-only. Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e --- include/hw/core/cpu.h | 17 +++-------------- include/hw/core/tcg-cpu-ops.h | 7 +++++++ target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/hppa/cpu.c | 4 +++- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 3 ++- target/nios2/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- target/ppc/translate_init.c.inc | 2 +- 14 files changed, 25 insertions(+), 26 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 0c6c17fb48..db54223983 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -87,8 +87,6 @@ struct TranslationBlock; * @parse_features: Callback to parse command line arguments. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. * @has_work: Callback for checking if there is work to do. - * @do_unaligned_access: Callback for unaligned access handling, if - * the target defines #TARGET_ALIGNED_ONLY. * @virtio_is_big_endian: Callback to return %true if a CPU which supports * runtime configurable endianness is currently big-endian. Non-configurab= le * CPUs can use the default implementation of this method. This method sho= uld @@ -154,9 +152,6 @@ struct CPUClass { =20 int reset_dump_flags; bool (*has_work)(CPUState *cpu); - void (*do_unaligned_access)(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); bool (*virtio_is_big_endian)(CPUState *cpu); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); @@ -831,18 +826,15 @@ CPUState *cpu_by_arch_id(int64_t id); =20 void cpu_interrupt(CPUState *cpu, int mask); =20 -#ifdef NEED_CPU_H - -#ifdef CONFIG_SOFTMMU +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr); + cc->tcg_ops.do_unaligned_access(cpu, addr, access_type, mmu_idx, retad= dr); } -#ifdef CONFIG_TCG static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, @@ -858,10 +850,7 @@ static inline void cpu_transaction_failed(CPUState *cp= u, hwaddr physaddr, mmu_idx, attrs, response, retadd= r); } } -#endif /* CONFIG_TCG */ -#endif /* CONFIG_SOFTMMU */ - -#endif /* NEED_CPU_H */ +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ =20 /** * cpu_set_pc: diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 3cc2733410..bac0165db6 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -50,6 +50,13 @@ typedef struct TcgCpuOperations { unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr); + /** + * @do_unaligned_access: Callback for unaligned access handling, if + * the target defines #TARGET_ALIGNED_ONLY. + */ + void (*do_unaligned_access)(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); =20 /** * @tlb_fill: Handle a softmmu tlb miss or user-only address fault diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 3e651b246f..0b5f5a78e3 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -225,7 +225,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->tcg_ops.tlb_fill =3D alpha_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->tcg_ops.do_transaction_failed =3D alpha_cpu_do_transaction_failed; - cc->do_unaligned_access =3D alpha_cpu_do_unaligned_access; + cc->tcg_ops.do_unaligned_access =3D alpha_cpu_do_unaligned_access; cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_alpha_cpu; #endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5e9202ed86..9a8c1dc2e1 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2266,9 +2266,9 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->tcg_ops.tlb_fill =3D arm_cpu_tlb_fill; cc->tcg_ops.debug_excp_handler =3D arm_debug_excp_handler; cc->debug_check_watchpoint =3D arm_debug_check_watchpoint; - cc->do_unaligned_access =3D arm_cpu_do_unaligned_access; #if !defined(CONFIG_USER_ONLY) cc->tcg_ops.do_transaction_failed =3D arm_cpu_do_transaction_failed; + cc->tcg_ops.do_unaligned_access =3D arm_cpu_do_unaligned_access; cc->adjust_watchpoint_address =3D arm_adjust_watchpoint_address; cc->tcg_ops.do_interrupt =3D arm_cpu_do_interrupt; #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index cce6ae6213..0985b3661f 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -70,6 +70,7 @@ static void hppa_cpu_disas_set_info(CPUState *cs, disasse= mble_info *info) info->print_insn =3D print_insn_hppa; } =20 +#ifndef CONFIG_USER_ONLY static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) @@ -86,6 +87,7 @@ static void hppa_cpu_do_unaligned_access(CPUState *cs, va= ddr addr, =20 cpu_loop_exit_restore(cs, retaddr); } +#endif /* CONFIG_USER_ONLY */ =20 static void hppa_cpu_realizefn(DeviceState *dev, Error **errp) { @@ -149,9 +151,9 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->tcg_ops.tlb_fill =3D hppa_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; + cc->tcg_ops.do_unaligned_access =3D hppa_cpu_do_unaligned_access; dc->vmsd =3D &vmstate_hppa_cpu; #endif - cc->do_unaligned_access =3D hppa_cpu_do_unaligned_access; cc->disas_set_info =3D hppa_cpu_disas_set_info; cc->tcg_ops.initialize =3D hppa_translate_init; =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index fa57a324dc..395f4a300f 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -318,7 +318,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->class_by_name =3D mb_cpu_class_by_name; cc->has_work =3D mb_cpu_has_work; cc->tcg_ops.do_interrupt =3D mb_cpu_do_interrupt; - cc->do_unaligned_access =3D mb_cpu_do_unaligned_access; cc->tcg_ops.cpu_exec_interrupt =3D mb_cpu_exec_interrupt; cc->dump_state =3D mb_cpu_dump_state; cc->set_pc =3D mb_cpu_set_pc; @@ -328,6 +327,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->tcg_ops.tlb_fill =3D mb_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->tcg_ops.do_transaction_failed =3D mb_cpu_transaction_failed; + cc->tcg_ops.do_unaligned_access =3D mb_cpu_do_unaligned_access; cc->get_phys_page_debug =3D mb_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_mb_cpu; #endif diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 259bb791f7..236d0d707b 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -239,7 +239,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_read_register =3D mips_cpu_gdb_read_register; cc->gdb_write_register =3D mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->do_unaligned_access =3D mips_cpu_do_unaligned_access; cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_mips_cpu; #endif @@ -252,6 +251,8 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) #ifndef CONFIG_USER_ONLY cc->tcg_ops.do_interrupt =3D mips_cpu_do_interrupt; cc->tcg_ops.do_transaction_failed =3D mips_cpu_do_transaction_failed; + cc->tcg_ops.do_unaligned_access =3D mips_cpu_do_unaligned_access; + #endif /* CONFIG_USER_ONLY */ #endif /* CONFIG_TCG */ =20 diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 2b959f0e49..059eea8c94 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -199,7 +199,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) cc->disas_set_info =3D nios2_cpu_disas_set_info; cc->tcg_ops.tlb_fill =3D nios2_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY - cc->do_unaligned_access =3D nios2_cpu_do_unaligned_access; + cc->tcg_ops.do_unaligned_access =3D nios2_cpu_do_unaligned_access; cc->get_phys_page_debug =3D nios2_cpu_get_phys_page_debug; #endif cc->gdb_read_register =3D nios2_cpu_gdb_read_register; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7dfd8d7339..e5626862c2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -556,7 +556,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->disas_set_info =3D riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY cc->tcg_ops.do_transaction_failed =3D riscv_cpu_do_transaction_failed; - cc->do_unaligned_access =3D riscv_cpu_do_unaligned_access; + cc->tcg_ops.do_unaligned_access =3D riscv_cpu_do_unaligned_access; cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; /* For now, mark unmigratable: */ cc->vmsd =3D &vmstate_riscv_cpu; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index b838bd61a4..86f654fd6b 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -507,7 +507,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) #ifdef CONFIG_TCG cc->tcg_ops.cpu_exec_interrupt =3D s390_cpu_exec_interrupt; cc->tcg_ops.debug_excp_handler =3D s390x_cpu_debug_excp_handler; - cc->do_unaligned_access =3D s390x_cpu_do_unaligned_access; + cc->tcg_ops.do_unaligned_access =3D s390x_cpu_do_unaligned_access; #endif #endif cc->disas_set_info =3D s390_cpu_disas_set_info; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index ff835d4bc1..fbd5f42675 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -227,7 +227,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_write_register =3D superh_cpu_gdb_write_register; cc->tcg_ops.tlb_fill =3D superh_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY - cc->do_unaligned_access =3D superh_cpu_do_unaligned_access; + cc->tcg_ops.do_unaligned_access =3D superh_cpu_do_unaligned_access; cc->get_phys_page_debug =3D superh_cpu_get_phys_page_debug; #endif cc->disas_set_info =3D superh_cpu_disas_set_info; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 009d0f07c3..3b53ef2390 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -874,7 +874,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->tcg_ops.tlb_fill =3D sparc_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->tcg_ops.do_transaction_failed =3D sparc_cpu_do_transaction_failed; - cc->do_unaligned_access =3D sparc_cpu_do_unaligned_access; + cc->tcg_ops.do_unaligned_access =3D sparc_cpu_do_unaligned_access; cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_sparc_cpu; #endif diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index fc52fde696..4b6381569f 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -203,7 +203,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_stop_before_watchpoint =3D true; cc->tcg_ops.tlb_fill =3D xtensa_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY - cc->do_unaligned_access =3D xtensa_cpu_do_unaligned_access; + cc->tcg_ops.do_unaligned_access =3D xtensa_cpu_do_unaligned_access; cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; cc->tcg_ops.do_transaction_failed =3D xtensa_cpu_do_transaction_failed; #endif diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 0471da0d08..18ce389947 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10913,7 +10913,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->set_pc =3D ppc_cpu_set_pc; cc->gdb_read_register =3D ppc_cpu_gdb_read_register; cc->gdb_write_register =3D ppc_cpu_gdb_write_register; - cc->do_unaligned_access =3D ppc_cpu_do_unaligned_access; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D ppc_cpu_get_phys_page_debug; cc->vmsd =3D &vmstate_ppc_cpu; @@ -10950,6 +10949,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) #ifndef CONFIG_USER_ONLY cc->tcg_ops.cpu_exec_enter =3D ppc_cpu_exec_enter; cc->tcg_ops.cpu_exec_exit =3D ppc_cpu_exec_exit; + cc->tcg_ops.do_unaligned_access =3D ppc_cpu_do_unaligned_access; #endif /* !CONFIG_USER_ONLY */ #endif /* CONFIG_TCG */ =20 --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607607806; cv=none; d=zohomail.com; s=zohoarc; b=bVhddmUkjyq7DTgFM6r84rrjKjxHLpCQC7UpObdjJFXiyxw7erd+FgWqR2CIb/p1LkpJufsXcY9qXhHNXiNHQTERn/6wfJk6zs6mtwIGO/nyrE7LSNHoGMXYWAn1vIhQiKLim2sqDjVKCCC0k+PYdg5wXxPXRdNTxNLsWX9xVqY= ARC-Message-Signature: i=1; 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Thu, 10 Dec 2020 08:18:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56730) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKor-0002fA-8C for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:13:15 -0500 Received: from mx2.suse.de ([195.135.220.15]:47926) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKol-0006XT-IF for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:13:13 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 10E13AD45; Thu, 10 Dec 2020 12:12:56 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 26/32] accel: extend AccelState and AccelClass to user-mode Date: Thu, 10 Dec 2020 13:12:20 +0100 Message-Id: <20201210121226.19822-27-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e --- include/hw/boards.h | 2 +- include/{sysemu =3D> qemu}/accel.h | 14 +++++---- include/sysemu/hvf.h | 2 +- include/sysemu/kvm.h | 2 +- include/sysemu/kvm_int.h | 2 +- target/i386/hvf/hvf-i386.h | 2 +- accel/accel-common.c | 50 ++++++++++++++++++++++++++++++ accel/{accel.c =3D> accel-softmmu.c} | 27 ++-------------- accel/accel-user.c | 24 ++++++++++++++ accel/qtest/qtest.c | 2 +- accel/tcg/tcg-all.c | 13 ++++++-- accel/xen/xen-all.c | 2 +- bsd-user/main.c | 6 +++- linux-user/main.c | 6 +++- softmmu/memory.c | 2 +- softmmu/qtest.c | 2 +- softmmu/vl.c | 2 +- target/i386/hax/hax-all.c | 2 +- target/i386/hvf/hvf.c | 2 +- target/i386/hvf/x86_task.c | 2 +- target/i386/whpx/whpx-all.c | 2 +- MAINTAINERS | 2 +- accel/meson.build | 4 ++- accel/tcg/meson.build | 2 +- 24 files changed, 124 insertions(+), 52 deletions(-) rename include/{sysemu =3D> qemu}/accel.h (95%) create mode 100644 accel/accel-common.c rename accel/{accel.c =3D> accel-softmmu.c} (75%) create mode 100644 accel/accel-user.c diff --git a/include/hw/boards.h b/include/hw/boards.h index f94f4ad5d8..f8ae50c49c 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -6,7 +6,7 @@ #include "exec/memory.h" #include "sysemu/hostmem.h" #include "sysemu/blockdev.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "qapi/qapi-types-machine.h" #include "qemu/module.h" #include "qom/object.h" diff --git a/include/sysemu/accel.h b/include/qemu/accel.h similarity index 95% rename from include/sysemu/accel.h rename to include/qemu/accel.h index e08b8ab8fa..fac4a18703 100644 --- a/include/sysemu/accel.h +++ b/include/qemu/accel.h @@ -20,8 +20,8 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN * THE SOFTWARE. */ -#ifndef HW_ACCEL_H -#define HW_ACCEL_H +#ifndef QEMU_ACCEL_H +#define QEMU_ACCEL_H =20 #include "qom/object.h" #include "exec/hwaddr.h" @@ -37,8 +37,8 @@ typedef struct AccelClass { /*< public >*/ =20 const char *name; -#ifndef CONFIG_USER_ONLY int (*init_machine)(MachineState *ms); +#ifndef CONFIG_USER_ONLY void (*setup_post)(MachineState *ms, AccelState *accel); bool (*has_memory)(MachineState *ms, AddressSpace *as, hwaddr start_addr, hwaddr size); @@ -67,11 +67,13 @@ typedef struct AccelClass { OBJECT_GET_CLASS(AccelClass, (obj), TYPE_ACCEL) =20 AccelClass *accel_find(const char *opt_name); +AccelState *current_accel(void); + +#ifndef CONFIG_USER_ONLY int accel_init_machine(AccelState *accel, MachineState *ms); =20 /* Called just before os_setup_post (ie just before drop OS privs) */ void accel_setup_post(MachineState *ms); +#endif /* !CONFIG_USER_ONLY */ =20 -AccelState *current_accel(void); - -#endif +#endif /* QEMU_ACCEL_H */ diff --git a/include/sysemu/hvf.h b/include/sysemu/hvf.h index f893768df9..c98636bc81 100644 --- a/include/sysemu/hvf.h +++ b/include/sysemu/hvf.h @@ -13,7 +13,7 @@ #ifndef HVF_H #define HVF_H =20 -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "qom/object.h" =20 #ifdef CONFIG_HVF diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index bb5d5cf497..739682f3c3 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -17,7 +17,7 @@ #include "qemu/queue.h" #include "hw/core/cpu.h" #include "exec/memattrs.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "qom/object.h" =20 #ifdef NEED_CPU_H diff --git a/include/sysemu/kvm_int.h b/include/sysemu/kvm_int.h index 65740806da..ccb8869f01 100644 --- a/include/sysemu/kvm_int.h +++ b/include/sysemu/kvm_int.h @@ -10,7 +10,7 @@ #define QEMU_KVM_INT_H =20 #include "exec/memory.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "sysemu/kvm.h" =20 typedef struct KVMSlot diff --git a/target/i386/hvf/hvf-i386.h b/target/i386/hvf/hvf-i386.h index e0edffd077..50b914fd67 100644 --- a/target/i386/hvf/hvf-i386.h +++ b/target/i386/hvf/hvf-i386.h @@ -16,7 +16,7 @@ #ifndef HVF_I386_H #define HVF_I386_H =20 -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "sysemu/hvf.h" #include "cpu.h" #include "x86.h" diff --git a/accel/accel-common.c b/accel/accel-common.c new file mode 100644 index 0000000000..ddec8cb5ae --- /dev/null +++ b/accel/accel-common.c @@ -0,0 +1,50 @@ +/* + * QEMU accel class, components common to system emulation and user mode + * + * Copyright (c) 2003-2008 Fabrice Bellard + * Copyright (c) 2014 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu/accel.h" + +static const TypeInfo accel_type =3D { + .name =3D TYPE_ACCEL, + .parent =3D TYPE_OBJECT, + .class_size =3D sizeof(AccelClass), + .instance_size =3D sizeof(AccelState), +}; + +/* Lookup AccelClass from opt_name. Returns NULL if not found */ +AccelClass *accel_find(const char *opt_name) +{ + char *class_name =3D g_strdup_printf(ACCEL_CLASS_NAME("%s"), opt_name); + AccelClass *ac =3D ACCEL_CLASS(object_class_by_name(class_name)); + g_free(class_name); + return ac; +} + +static void register_accel_types(void) +{ + type_register_static(&accel_type); +} + +type_init(register_accel_types); diff --git a/accel/accel.c b/accel/accel-softmmu.c similarity index 75% rename from accel/accel.c rename to accel/accel-softmmu.c index cb555e3b06..f89da8f9d1 100644 --- a/accel/accel.c +++ b/accel/accel-softmmu.c @@ -1,5 +1,5 @@ /* - * QEMU System Emulator, accelerator interfaces + * QEMU accel class, system emulation components * * Copyright (c) 2003-2008 Fabrice Bellard * Copyright (c) 2014 Red Hat Inc. @@ -24,28 +24,12 @@ */ =20 #include "qemu/osdep.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "hw/boards.h" #include "sysemu/arch_init.h" #include "sysemu/sysemu.h" #include "qom/object.h" =20 -static const TypeInfo accel_type =3D { - .name =3D TYPE_ACCEL, - .parent =3D TYPE_OBJECT, - .class_size =3D sizeof(AccelClass), - .instance_size =3D sizeof(AccelState), -}; - -/* Lookup AccelClass from opt_name. Returns NULL if not found */ -AccelClass *accel_find(const char *opt_name) -{ - char *class_name =3D g_strdup_printf(ACCEL_CLASS_NAME("%s"), opt_name); - AccelClass *ac =3D ACCEL_CLASS(object_class_by_name(class_name)); - g_free(class_name); - return ac; -} - int accel_init_machine(AccelState *accel, MachineState *ms) { AccelClass *acc =3D ACCEL_GET_CLASS(accel); @@ -76,10 +60,3 @@ void accel_setup_post(MachineState *ms) acc->setup_post(ms, accel); } } - -static void register_accel_types(void) -{ - type_register_static(&accel_type); -} - -type_init(register_accel_types); diff --git a/accel/accel-user.c b/accel/accel-user.c new file mode 100644 index 0000000000..26bdda6236 --- /dev/null +++ b/accel/accel-user.c @@ -0,0 +1,24 @@ +/* + * QEMU accel class, user-mode components + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/accel.h" + +AccelState *current_accel(void) +{ + static AccelState *accel; + + if (!accel) { + AccelClass *ac =3D accel_find("tcg"); + + g_assert(ac !=3D NULL); + accel =3D ACCEL(object_new_with_class(OBJECT_CLASS(ac))); + } + return accel; +} diff --git a/accel/qtest/qtest.c b/accel/qtest/qtest.c index b282cea5cf..b4e731cb2b 100644 --- a/accel/qtest/qtest.c +++ b/accel/qtest/qtest.c @@ -17,7 +17,7 @@ #include "qemu/module.h" #include "qemu/option.h" #include "qemu/config-file.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "sysemu/qtest.h" #include "sysemu/cpus.h" #include "sysemu/cpu-timers.h" diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 1ac0b76515..7125d0cc29 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -30,9 +30,12 @@ #include "tcg/tcg.h" #include "qapi/error.h" #include "qemu/error-report.h" -#include "hw/boards.h" +#include "qemu/accel.h" #include "qapi/qapi-builtin-visit.h" + +#ifndef CONFIG_USER_ONLY #include "tcg-cpus.h" +#endif /* CONFIG_USER_ONLY */ =20 struct TCGState { AccelState parent_obj; @@ -106,8 +109,12 @@ static int tcg_init(MachineState *ms) mttcg_enabled =3D s->mttcg_enabled; =20 /* - * Initialize TCG regions + * Initialize TCG regions only for softmmu. + * + * This needs to be done later for user mode, because the prologue + * generation needs to be delayed so that GUEST_BASE is already set. */ +#ifndef CONFIG_USER_ONLY tcg_region_init(); =20 if (mttcg_enabled) { @@ -117,6 +124,8 @@ static int tcg_init(MachineState *ms) } else { cpus_register_accel(&tcg_cpus_rr); } +#endif /* !CONFIG_USER_ONLY */ + return 0; } =20 diff --git a/accel/xen/xen-all.c b/accel/xen/xen-all.c index 878a4089d9..594aaf6b49 100644 --- a/accel/xen/xen-all.c +++ b/accel/xen/xen-all.c @@ -15,7 +15,7 @@ #include "hw/xen/xen-legacy-backend.h" #include "hw/xen/xen_pt.h" #include "chardev/char.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "sysemu/cpus.h" #include "sysemu/xen.h" #include "sysemu/runstate.h" diff --git a/bsd-user/main.c b/bsd-user/main.c index 0a918e8f74..ff295bcb29 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu-common.h" #include "qemu/units.h" +#include "qemu/accel.h" #include "sysemu/tcg.h" #include "qemu-version.h" #include @@ -908,8 +909,11 @@ int main(int argc, char **argv) } =20 /* init tcg before creating CPUs and to get qemu_host_page_size */ - tcg_exec_init(0); + { + AccelClass *ac =3D ACCEL_GET_CLASS(current_accel()); =20 + ac->init_machine(NULL); + } cpu_type =3D parse_cpu_option(cpu_model); cpu =3D cpu_create(cpu_type); env =3D cpu->env_ptr; diff --git a/linux-user/main.c b/linux-user/main.c index 24d1eb73ad..5c059a8445 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu-common.h" #include "qemu/units.h" +#include "qemu/accel.h" #include "sysemu/tcg.h" #include "qemu-version.h" #include @@ -703,8 +704,11 @@ int main(int argc, char **argv, char **envp) cpu_type =3D parse_cpu_option(cpu_model); =20 /* init tcg before creating CPUs and to get qemu_host_page_size */ - tcg_exec_init(0); + { + AccelClass *ac =3D ACCEL_GET_CLASS(current_accel()); =20 + ac->init_machine(NULL); + } cpu =3D cpu_create(cpu_type); env =3D cpu->env_ptr; cpu_reset(cpu); diff --git a/softmmu/memory.c b/softmmu/memory.c index 22bacbbc78..585ec6f8dc 100644 --- a/softmmu/memory.c +++ b/softmmu/memory.c @@ -32,7 +32,7 @@ #include "sysemu/kvm.h" #include "sysemu/runstate.h" #include "sysemu/tcg.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "hw/boards.h" #include "migration/vmstate.h" =20 diff --git a/softmmu/qtest.c b/softmmu/qtest.c index 7965dc9a16..130c366615 100644 --- a/softmmu/qtest.c +++ b/softmmu/qtest.c @@ -20,7 +20,7 @@ #include "exec/ioport.h" #include "exec/memory.h" #include "hw/irq.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "sysemu/cpu-timers.h" #include "qemu/config-file.h" #include "qemu/option.h" diff --git a/softmmu/vl.c b/softmmu/vl.c index e6e0ad5a92..bc20c526d2 100644 --- a/softmmu/vl.c +++ b/softmmu/vl.c @@ -40,7 +40,7 @@ =20 #include "qemu/error-report.h" #include "qemu/sockets.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "hw/usb.h" #include "hw/isa/isa.h" #include "hw/scsi/scsi.h" diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c index fecfe8cd6e..d7f4bb44a7 100644 --- a/target/i386/hax/hax-all.c +++ b/target/i386/hax/hax-all.c @@ -28,7 +28,7 @@ #include "exec/address-spaces.h" =20 #include "qemu-common.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" #include "hw/boards.h" diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index ed9356565c..ffc9efa40f 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -69,7 +69,7 @@ #include "exec/address-spaces.h" #include "hw/i386/apic_internal.h" #include "qemu/main-loop.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "target/i386/cpu.h" =20 #include "hvf-cpus.h" diff --git a/target/i386/hvf/x86_task.c b/target/i386/hvf/x86_task.c index 6f04478b3a..d66dfd7669 100644 --- a/target/i386/hvf/x86_task.c +++ b/target/i386/hvf/x86_task.c @@ -28,7 +28,7 @@ =20 #include "hw/i386/apic_internal.h" #include "qemu/main-loop.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "target/i386/cpu.h" =20 // TODO: taskswitch handling diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index f4f3e33eac..ee6b606194 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -13,7 +13,7 @@ #include "exec/address-spaces.h" #include "exec/ioport.h" #include "qemu-common.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "sysemu/whpx.h" #include "sysemu/cpus.h" #include "sysemu/runstate.h" diff --git a/MAINTAINERS b/MAINTAINERS index d876f504a6..6235dd3a9f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -434,7 +434,7 @@ Overall M: Richard Henderson R: Paolo Bonzini S: Maintained -F: include/sysemu/accel.h +F: include/qemu/accel.h F: accel/accel.c F: accel/Makefile.objs F: accel/stubs/Makefile.objs diff --git a/accel/meson.build b/accel/meson.build index b26cca227a..b44ba30c86 100644 --- a/accel/meson.build +++ b/accel/meson.build @@ -1,4 +1,6 @@ -softmmu_ss.add(files('accel.c')) +specific_ss.add(files('accel-common.c')) +softmmu_ss.add(files('accel-softmmu.c')) +user_ss.add(files('accel-user.c')) =20 subdir('qtest') subdir('kvm') diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index f39aab0a0c..424d9bb1fc 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -1,5 +1,6 @@ tcg_ss =3D ss.source_set() tcg_ss.add(files( + 'tcg-all.c', 'cpu-exec-common.c', 'cpu-exec.c', 'tcg-runtime-gvec.c', @@ -13,7 +14,6 @@ tcg_ss.add(when: 'CONFIG_PLUGIN', if_true: [files('plugin= -gen.c'), libdl]) specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss) =20 specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files( - 'tcg-all.c', 'cputlb.c', 'tcg-cpus.c', 'tcg-cpus-mttcg.c', --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 10 Dec 2020 04:39:08 -0800 (PST) Received: from localhost ([::1]:53448 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knLDv-0006GE-7J for importer@patchew.org; Thu, 10 Dec 2020 07:39:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56788) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKow-0002hZ-DG for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:13:18 -0500 Received: from mx2.suse.de ([195.135.220.15]:47958) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKon-0006Xc-02 for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:13:18 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 105FAAD4D; Thu, 10 Dec 2020 12:12:57 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 27/32] accel: replace struct CpusAccel with AccelOpsClass Date: Thu, 10 Dec 2020 13:12:21 +0100 Message-Id: <20201210121226.19822-28-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" also centralize the registration of the cpus.c module accelerator operations in accel/accel-softmmu.c Consequently, rename all tcg-cpus.c, kvm-cpus.c etc to tcg-accel-ops.c, kvm-accel-ops.c etc, also matching the object type names. Signed-off-by: Claudio Fontana --- accel/accel-softmmu.h | 15 ++++++ accel/kvm/kvm-cpus.h | 2 - ...g-cpus-icount.h =3D> tcg-accel-ops-icount.h} | 2 + accel/tcg/tcg-accel-ops-mttcg.h | 19 ++++++++ .../tcg/{tcg-cpus-rr.h =3D> tcg-accel-ops-rr.h} | 0 accel/tcg/{tcg-cpus.h =3D> tcg-accel-ops.h} | 6 +-- include/qemu/accel.h | 2 + include/sysemu/accel-ops.h | 45 ++++++++++++++++++ include/sysemu/cpus.h | 26 ++-------- .../i386/hax/{hax-cpus.h =3D> hax-accel-ops.h} | 2 - target/i386/hax/hax-windows.h | 2 +- .../i386/hvf/{hvf-cpus.h =3D> hvf-accel-ops.h} | 2 - .../whpx/{whpx-cpus.h =3D> whpx-accel-ops.h} | 2 - accel/accel-common.c | 11 +++++ accel/accel-softmmu.c | 43 +++++++++++++++-- accel/kvm/{kvm-cpus.c =3D> kvm-accel-ops.c} | 26 +++++++--- accel/kvm/kvm-all.c | 2 - accel/qtest/qtest.c | 23 ++++++--- ...g-cpus-icount.c =3D> tcg-accel-ops-icount.c} | 21 +++------ ...tcg-cpus-mttcg.c =3D> tcg-accel-ops-mttcg.c} | 14 ++---- .../tcg/{tcg-cpus-rr.c =3D> tcg-accel-ops-rr.c} | 13 ++--- accel/tcg/{tcg-cpus.c =3D> tcg-accel-ops.c} | 47 ++++++++++++++++++- accel/tcg/tcg-all.c | 12 ----- accel/xen/xen-all.c | 22 ++++++--- bsd-user/main.c | 3 +- linux-user/main.c | 1 + softmmu/cpus.c | 12 ++--- softmmu/vl.c | 6 ++- .../i386/hax/{hax-cpus.c =3D> hax-accel-ops.c} | 31 ++++++++---- target/i386/hax/hax-all.c | 5 +- target/i386/hax/hax-mem.c | 2 +- target/i386/hax/hax-posix.c | 2 +- target/i386/hax/hax-windows.c | 2 +- .../i386/hvf/{hvf-cpus.c =3D> hvf-accel-ops.c} | 29 +++++++++--- target/i386/hvf/hvf.c | 3 +- target/i386/hvf/x86hvf.c | 2 +- .../whpx/{whpx-cpus.c =3D> whpx-accel-ops.c} | 31 ++++++++---- target/i386/whpx/whpx-all.c | 4 +- MAINTAINERS | 3 +- accel/kvm/meson.build | 2 +- accel/tcg/meson.build | 8 ++-- target/i386/hax/meson.build | 2 +- target/i386/hvf/meson.build | 2 +- target/i386/whpx/meson.build | 2 +- 44 files changed, 349 insertions(+), 162 deletions(-) create mode 100644 accel/accel-softmmu.h rename accel/tcg/{tcg-cpus-icount.h =3D> tcg-accel-ops-icount.h} (88%) create mode 100644 accel/tcg/tcg-accel-ops-mttcg.h rename accel/tcg/{tcg-cpus-rr.h =3D> tcg-accel-ops-rr.h} (100%) rename accel/tcg/{tcg-cpus.h =3D> tcg-accel-ops.h} (72%) create mode 100644 include/sysemu/accel-ops.h rename target/i386/hax/{hax-cpus.h =3D> hax-accel-ops.h} (95%) rename target/i386/hvf/{hvf-cpus.h =3D> hvf-accel-ops.h} (94%) rename target/i386/whpx/{whpx-cpus.h =3D> whpx-accel-ops.h} (96%) rename accel/kvm/{kvm-cpus.c =3D> kvm-accel-ops.c} (72%) rename accel/tcg/{tcg-cpus-icount.c =3D> tcg-accel-ops-icount.c} (89%) rename accel/tcg/{tcg-cpus-mttcg.c =3D> tcg-accel-ops-mttcg.c} (92%) rename accel/tcg/{tcg-cpus-rr.c =3D> tcg-accel-ops-rr.c} (97%) rename accel/tcg/{tcg-cpus.c =3D> tcg-accel-ops.c} (63%) rename target/i386/hax/{hax-cpus.c =3D> hax-accel-ops.c} (69%) rename target/i386/hvf/{hvf-cpus.c =3D> hvf-accel-ops.c} (84%) rename target/i386/whpx/{whpx-cpus.c =3D> whpx-accel-ops.c} (72%) diff --git a/accel/accel-softmmu.h b/accel/accel-softmmu.h new file mode 100644 index 0000000000..2877b5c234 --- /dev/null +++ b/accel/accel-softmmu.h @@ -0,0 +1,15 @@ +/* + * QEMU System Emulation accel internal functions + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef ACCEL_SOFTMMU_H +#define ACCEL_SOFTMMU_H + +void accel_init_ops_interfaces(AccelClass *ac); + +#endif /* ACCEL_SOFTMMU_H */ diff --git a/accel/kvm/kvm-cpus.h b/accel/kvm/kvm-cpus.h index 3df732b816..bf0bd1bee4 100644 --- a/accel/kvm/kvm-cpus.h +++ b/accel/kvm/kvm-cpus.h @@ -12,8 +12,6 @@ =20 #include "sysemu/cpus.h" =20 -extern const CpusAccel kvm_cpus; - int kvm_init_vcpu(CPUState *cpu, Error **errp); int kvm_cpu_exec(CPUState *cpu); void kvm_destroy_vcpu(CPUState *cpu); diff --git a/accel/tcg/tcg-cpus-icount.h b/accel/tcg/tcg-accel-ops-icount.h similarity index 88% rename from accel/tcg/tcg-cpus-icount.h rename to accel/tcg/tcg-accel-ops-icount.h index b695939dfa..d884aa2aaa 100644 --- a/accel/tcg/tcg-cpus-icount.h +++ b/accel/tcg/tcg-accel-ops-icount.h @@ -14,4 +14,6 @@ void icount_handle_deadline(void); void icount_prepare_for_run(CPUState *cpu); void icount_process_data(CPUState *cpu); =20 +void icount_handle_interrupt(CPUState *cpu, int mask); + #endif /* TCG_CPUS_ICOUNT_H */ diff --git a/accel/tcg/tcg-accel-ops-mttcg.h b/accel/tcg/tcg-accel-ops-mttc= g.h new file mode 100644 index 0000000000..0af91dd3b3 --- /dev/null +++ b/accel/tcg/tcg-accel-ops-mttcg.h @@ -0,0 +1,19 @@ +/* + * QEMU TCG Multi Threaded vCPUs implementation + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef TCG_CPUS_MTTCG_H +#define TCG_CPUS_MTTCG_H + +/* kick MTTCG vCPU thread */ +void mttcg_kick_vcpu_thread(CPUState *cpu); + +/* start an mttcg vCPU thread */ +void mttcg_start_vcpu_thread(CPUState *cpu); + +#endif /* TCG_CPUS_MTTCG_H */ diff --git a/accel/tcg/tcg-cpus-rr.h b/accel/tcg/tcg-accel-ops-rr.h similarity index 100% rename from accel/tcg/tcg-cpus-rr.h rename to accel/tcg/tcg-accel-ops-rr.h diff --git a/accel/tcg/tcg-cpus.h b/accel/tcg/tcg-accel-ops.h similarity index 72% rename from accel/tcg/tcg-cpus.h rename to accel/tcg/tcg-accel-ops.h index d6893a32f8..48130006de 100644 --- a/accel/tcg/tcg-cpus.h +++ b/accel/tcg/tcg-accel-ops.h @@ -14,12 +14,8 @@ =20 #include "sysemu/cpus.h" =20 -extern const CpusAccel tcg_cpus_mttcg; -extern const CpusAccel tcg_cpus_icount; -extern const CpusAccel tcg_cpus_rr; - void tcg_cpus_destroy(CPUState *cpu); int tcg_cpus_exec(CPUState *cpu); -void tcg_cpus_handle_interrupt(CPUState *cpu, int mask); +void tcg_handle_interrupt(CPUState *cpu, int mask); =20 #endif /* TCG_CPUS_H */ diff --git a/include/qemu/accel.h b/include/qemu/accel.h index fac4a18703..b9d6d69eb8 100644 --- a/include/qemu/accel.h +++ b/include/qemu/accel.h @@ -69,6 +69,8 @@ typedef struct AccelClass { AccelClass *accel_find(const char *opt_name); AccelState *current_accel(void); =20 +void accel_init_interfaces(AccelClass *ac); + #ifndef CONFIG_USER_ONLY int accel_init_machine(AccelState *accel, MachineState *ms); =20 diff --git a/include/sysemu/accel-ops.h b/include/sysemu/accel-ops.h new file mode 100644 index 0000000000..6102d2f80d --- /dev/null +++ b/include/sysemu/accel-ops.h @@ -0,0 +1,45 @@ +/* + * Accelerator OPS, used for cpus.c module + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef ACCEL_OPS_H +#define ACCEL_OPS_H + +#include "qom/object.h" + +#define ACCEL_OPS_SUFFIX "-ops" +#define TYPE_ACCEL_OPS "accel" ACCEL_OPS_SUFFIX +#define ACCEL_OPS_NAME(name) (name "-" TYPE_ACCEL_OPS) + +typedef struct AccelOpsClass AccelOpsClass; +DECLARE_CLASS_CHECKERS(AccelOpsClass, ACCEL_OPS, TYPE_ACCEL_OPS) + +/* cpus.c operations interface */ +struct AccelOpsClass { + /*< private >*/ + ObjectClass parent_class; + /*< public >*/ + + /* initialization function called when accel is chosen */ + void (*ops_init)(AccelOpsClass *ops); + + void (*create_vcpu_thread)(CPUState *cpu); /* MANDATORY NON-NULL */ + void (*kick_vcpu_thread)(CPUState *cpu); + + void (*synchronize_post_reset)(CPUState *cpu); + void (*synchronize_post_init)(CPUState *cpu); + void (*synchronize_state)(CPUState *cpu); + void (*synchronize_pre_loadvm)(CPUState *cpu); + + void (*handle_interrupt)(CPUState *cpu, int mask); + + int64_t (*get_virtual_clock)(void); + int64_t (*get_elapsed_ticks)(void); +}; + +#endif /* ACCEL_OPS_H */ diff --git a/include/sysemu/cpus.h b/include/sysemu/cpus.h index e8156728c6..2cd74392e0 100644 --- a/include/sysemu/cpus.h +++ b/include/sysemu/cpus.h @@ -2,30 +2,14 @@ #define QEMU_CPUS_H =20 #include "qemu/timer.h" +#include "sysemu/accel-ops.h" =20 -/* cpus.c */ +/* register accel-specific operations */ +void cpus_register_accel(const AccelOpsClass *i); =20 -/* CPU execution threads */ +/* accel/dummy-cpus.c */ =20 -typedef struct CpusAccel { - void (*create_vcpu_thread)(CPUState *cpu); /* MANDATORY */ - void (*kick_vcpu_thread)(CPUState *cpu); - - void (*synchronize_post_reset)(CPUState *cpu); - void (*synchronize_post_init)(CPUState *cpu); - void (*synchronize_state)(CPUState *cpu); - void (*synchronize_pre_loadvm)(CPUState *cpu); - - void (*handle_interrupt)(CPUState *cpu, int mask); - - int64_t (*get_virtual_clock)(void); - int64_t (*get_elapsed_ticks)(void); -} CpusAccel; - -/* register accel-specific cpus interface implementation */ -void cpus_register_accel(const CpusAccel *i); - -/* Create a dummy vcpu for CpusAccel->create_vcpu_thread */ +/* Create a dummy vcpu for AccelOpsClass->create_vcpu_thread */ void dummy_start_vcpu_thread(CPUState *); =20 /* interface available for cpus accelerator threads */ diff --git a/target/i386/hax/hax-cpus.h b/target/i386/hax/hax-accel-ops.h similarity index 95% rename from target/i386/hax/hax-cpus.h rename to target/i386/hax/hax-accel-ops.h index ee8ab7a631..c7698519cd 100644 --- a/target/i386/hax/hax-cpus.h +++ b/target/i386/hax/hax-accel-ops.h @@ -12,8 +12,6 @@ =20 #include "sysemu/cpus.h" =20 -extern const CpusAccel hax_cpus; - #include "hax-interface.h" #include "hax-i386.h" =20 diff --git a/target/i386/hax/hax-windows.h b/target/i386/hax/hax-windows.h index a5ce12d663..b1f5d4f32f 100644 --- a/target/i386/hax/hax-windows.h +++ b/target/i386/hax/hax-windows.h @@ -23,7 +23,7 @@ #include #include =20 -#include "hax-cpus.h" +#include "hax-accel-ops.h" =20 #define HAX_INVALID_FD INVALID_HANDLE_VALUE =20 diff --git a/target/i386/hvf/hvf-cpus.h b/target/i386/hvf/hvf-accel-ops.h similarity index 94% rename from target/i386/hvf/hvf-cpus.h rename to target/i386/hvf/hvf-accel-ops.h index ced31b82c0..8f992da168 100644 --- a/target/i386/hvf/hvf-cpus.h +++ b/target/i386/hvf/hvf-accel-ops.h @@ -12,8 +12,6 @@ =20 #include "sysemu/cpus.h" =20 -extern const CpusAccel hvf_cpus; - int hvf_init_vcpu(CPUState *); int hvf_vcpu_exec(CPUState *); void hvf_cpu_synchronize_state(CPUState *); diff --git a/target/i386/whpx/whpx-cpus.h b/target/i386/whpx/whpx-accel-ops= .h similarity index 96% rename from target/i386/whpx/whpx-cpus.h rename to target/i386/whpx/whpx-accel-ops.h index bdb367d1d0..2dee6d61ea 100644 --- a/target/i386/whpx/whpx-cpus.h +++ b/target/i386/whpx/whpx-accel-ops.h @@ -12,8 +12,6 @@ =20 #include "sysemu/cpus.h" =20 -extern const CpusAccel whpx_cpus; - int whpx_init_vcpu(CPUState *cpu); int whpx_vcpu_exec(CPUState *cpu); void whpx_destroy_vcpu(CPUState *cpu); diff --git a/accel/accel-common.c b/accel/accel-common.c index ddec8cb5ae..6b59873419 100644 --- a/accel/accel-common.c +++ b/accel/accel-common.c @@ -26,6 +26,10 @@ #include "qemu/osdep.h" #include "qemu/accel.h" =20 +#ifndef CONFIG_USER_ONLY +#include "accel-softmmu.h" +#endif /* !CONFIG_USER_ONLY */ + static const TypeInfo accel_type =3D { .name =3D TYPE_ACCEL, .parent =3D TYPE_OBJECT, @@ -42,6 +46,13 @@ AccelClass *accel_find(const char *opt_name) return ac; } =20 +void accel_init_interfaces(AccelClass *ac) +{ +#ifndef CONFIG_USER_ONLY + accel_init_ops_interfaces(ac); +#endif /* !CONFIG_USER_ONLY */ +} + static void register_accel_types(void) { type_register_static(&accel_type); diff --git a/accel/accel-softmmu.c b/accel/accel-softmmu.c index f89da8f9d1..2d15d3f2f4 100644 --- a/accel/accel-softmmu.c +++ b/accel/accel-softmmu.c @@ -26,9 +26,9 @@ #include "qemu/osdep.h" #include "qemu/accel.h" #include "hw/boards.h" -#include "sysemu/arch_init.h" -#include "sysemu/sysemu.h" -#include "qom/object.h" +#include "sysemu/cpus.h" + +#include "accel-softmmu.h" =20 int accel_init_machine(AccelState *accel, MachineState *ms) { @@ -60,3 +60,40 @@ void accel_setup_post(MachineState *ms) acc->setup_post(ms, accel); } } + +/* initialize the arch-independent accel operation interfaces */ +void accel_init_ops_interfaces(AccelClass *ac) +{ + const char *ac_name; + char *ops_name; + AccelOpsClass *ops; + + ac_name =3D object_class_get_name(OBJECT_CLASS(ac)); + g_assert(ac_name !=3D NULL); + + ops_name =3D g_strdup_printf("%s" ACCEL_OPS_SUFFIX, ac_name); + ops =3D ACCEL_OPS_CLASS(object_class_by_name(ops_name)); + g_free(ops_name); + + /* + * all accelerators need to define ops, providing at least a mandatory + * non-NULL create_vcpu_thread operation. + */ + g_assert(ops !=3D NULL); + if (ops->ops_init) { + ops->ops_init(ops); + } + cpus_register_accel(ops); +} + +static const TypeInfo accel_ops_type_info =3D { + .name =3D TYPE_ACCEL_OPS, + .parent =3D TYPE_OBJECT, + .abstract =3D true, + .class_size =3D sizeof(AccelOpsClass), +}; +static void accel_softmmu_register_types(void) +{ + type_register_static(&accel_ops_type_info); +} +type_init(accel_softmmu_register_types); diff --git a/accel/kvm/kvm-cpus.c b/accel/kvm/kvm-accel-ops.c similarity index 72% rename from accel/kvm/kvm-cpus.c rename to accel/kvm/kvm-accel-ops.c index d809b1e74c..430d09de03 100644 --- a/accel/kvm/kvm-cpus.c +++ b/accel/kvm/kvm-accel-ops.c @@ -74,11 +74,25 @@ static void kvm_start_vcpu_thread(CPUState *cpu) cpu, QEMU_THREAD_JOINABLE); } =20 -const CpusAccel kvm_cpus =3D { - .create_vcpu_thread =3D kvm_start_vcpu_thread, +static void kvm_accel_ops_class_init(ObjectClass *oc, void *data) +{ + AccelOpsClass *ops =3D ACCEL_OPS_CLASS(oc); =20 - .synchronize_post_reset =3D kvm_cpu_synchronize_post_reset, - .synchronize_post_init =3D kvm_cpu_synchronize_post_init, - .synchronize_state =3D kvm_cpu_synchronize_state, - .synchronize_pre_loadvm =3D kvm_cpu_synchronize_pre_loadvm, + ops->create_vcpu_thread =3D kvm_start_vcpu_thread; + ops->synchronize_post_reset =3D kvm_cpu_synchronize_post_reset; + ops->synchronize_post_init =3D kvm_cpu_synchronize_post_init; + ops->synchronize_state =3D kvm_cpu_synchronize_state; + ops->synchronize_pre_loadvm =3D kvm_cpu_synchronize_pre_loadvm; }; +static const TypeInfo kvm_accel_ops_type =3D { + .name =3D ACCEL_OPS_NAME("kvm"), + + .parent =3D TYPE_ACCEL_OPS, + .class_init =3D kvm_accel_ops_class_init, + .abstract =3D true, +}; +static void kvm_accel_ops_register_types(void) +{ + type_register_static(&kvm_accel_ops_type); +} +type_init(kvm_accel_ops_register_types); diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index baaa54249d..18be3cd113 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -2253,8 +2253,6 @@ static int kvm_init(MachineState *ms) ret =3D ram_block_discard_disable(true); assert(!ret); } - - cpus_register_accel(&kvm_cpus); return 0; =20 err: diff --git a/accel/qtest/qtest.c b/accel/qtest/qtest.c index b4e731cb2b..edb29f6fa4 100644 --- a/accel/qtest/qtest.c +++ b/accel/qtest/qtest.c @@ -25,14 +25,8 @@ #include "qemu/main-loop.h" #include "hw/core/cpu.h" =20 -const CpusAccel qtest_cpus =3D { - .create_vcpu_thread =3D dummy_start_vcpu_thread, - .get_virtual_clock =3D qtest_get_virtual_clock, -}; - static int qtest_init_accel(MachineState *ms) { - cpus_register_accel(&qtest_cpus); return 0; } =20 @@ -52,9 +46,26 @@ static const TypeInfo qtest_accel_type =3D { .class_init =3D qtest_accel_class_init, }; =20 +static void qtest_accel_ops_class_init(ObjectClass *oc, void *data) +{ + AccelOpsClass *ops =3D ACCEL_OPS_CLASS(oc); + + ops->create_vcpu_thread =3D dummy_start_vcpu_thread; + ops->get_virtual_clock =3D qtest_get_virtual_clock; +}; + +static const TypeInfo qtest_accel_ops_type =3D { + .name =3D ACCEL_OPS_NAME("qtest"), + + .parent =3D TYPE_ACCEL_OPS, + .class_init =3D qtest_accel_ops_class_init, + .abstract =3D true, +}; + static void qtest_type_init(void) { type_register_static(&qtest_accel_type); + type_register_static(&qtest_accel_ops_type); } =20 type_init(qtest_type_init); diff --git a/accel/tcg/tcg-cpus-icount.c b/accel/tcg/tcg-accel-ops-icount.c similarity index 89% rename from accel/tcg/tcg-cpus-icount.c rename to accel/tcg/tcg-accel-ops-icount.c index 9f45432275..87762b469c 100644 --- a/accel/tcg/tcg-cpus-icount.c +++ b/accel/tcg/tcg-accel-ops-icount.c @@ -32,9 +32,9 @@ #include "exec/exec-all.h" #include "hw/boards.h" =20 -#include "tcg-cpus.h" -#include "tcg-cpus-icount.h" -#include "tcg-cpus-rr.h" +#include "tcg-accel-ops.h" +#include "tcg-accel-ops-icount.h" +#include "tcg-accel-ops-rr.h" =20 static int64_t icount_get_limit(void) { @@ -93,7 +93,7 @@ void icount_prepare_for_run(CPUState *cpu) /* * These should always be cleared by icount_process_data after * each vCPU execution. However u16.high can be raised - * asynchronously by cpu_exit/cpu_interrupt/tcg_cpus_handle_interrupt + * asynchronously by cpu_exit/cpu_interrupt/tcg_handle_interrupt */ g_assert(cpu_neg(cpu)->icount_decr.u16.low =3D=3D 0); g_assert(cpu->icount_extra =3D=3D 0); @@ -125,23 +125,14 @@ void icount_process_data(CPUState *cpu) replay_mutex_unlock(); } =20 -static void icount_handle_interrupt(CPUState *cpu, int mask) +void icount_handle_interrupt(CPUState *cpu, int mask) { int old_mask =3D cpu->interrupt_request; =20 - tcg_cpus_handle_interrupt(cpu, mask); + tcg_handle_interrupt(cpu, mask); if (qemu_cpu_is_self(cpu) && !cpu->can_do_io && (mask & ~old_mask) !=3D 0) { cpu_abort(cpu, "Raised interrupt while not in I/O function"); } } - -const CpusAccel tcg_cpus_icount =3D { - .create_vcpu_thread =3D rr_start_vcpu_thread, - .kick_vcpu_thread =3D rr_kick_vcpu_thread, - - .handle_interrupt =3D icount_handle_interrupt, - .get_virtual_clock =3D icount_get, - .get_elapsed_ticks =3D icount_get, -}; diff --git a/accel/tcg/tcg-cpus-mttcg.c b/accel/tcg/tcg-accel-ops-mttcg.c similarity index 92% rename from accel/tcg/tcg-cpus-mttcg.c rename to accel/tcg/tcg-accel-ops-mttcg.c index 9c3767d260..42973fb062 100644 --- a/accel/tcg/tcg-cpus-mttcg.c +++ b/accel/tcg/tcg-accel-ops-mttcg.c @@ -32,7 +32,8 @@ #include "exec/exec-all.h" #include "hw/boards.h" =20 -#include "tcg-cpus.h" +#include "tcg-accel-ops.h" +#include "tcg-accel-ops-mttcg.h" =20 /* * In the multi-threaded case each vCPU has its own thread. The TLS @@ -103,12 +104,12 @@ static void *mttcg_cpu_thread_fn(void *arg) return NULL; } =20 -static void mttcg_kick_vcpu_thread(CPUState *cpu) +void mttcg_kick_vcpu_thread(CPUState *cpu) { cpu_exit(cpu); } =20 -static void mttcg_start_vcpu_thread(CPUState *cpu) +void mttcg_start_vcpu_thread(CPUState *cpu) { char thread_name[VCPU_THREAD_NAME_SIZE]; =20 @@ -131,10 +132,3 @@ static void mttcg_start_vcpu_thread(CPUState *cpu) cpu->hThread =3D qemu_thread_get_handle(cpu->thread); #endif } - -const CpusAccel tcg_cpus_mttcg =3D { - .create_vcpu_thread =3D mttcg_start_vcpu_thread, - .kick_vcpu_thread =3D mttcg_kick_vcpu_thread, - - .handle_interrupt =3D tcg_cpus_handle_interrupt, -}; diff --git a/accel/tcg/tcg-cpus-rr.c b/accel/tcg/tcg-accel-ops-rr.c similarity index 97% rename from accel/tcg/tcg-cpus-rr.c rename to accel/tcg/tcg-accel-ops-rr.c index 0181d2e4eb..4a66055e0d 100644 --- a/accel/tcg/tcg-cpus-rr.c +++ b/accel/tcg/tcg-accel-ops-rr.c @@ -32,9 +32,9 @@ #include "exec/exec-all.h" #include "hw/boards.h" =20 -#include "tcg-cpus.h" -#include "tcg-cpus-rr.h" -#include "tcg-cpus-icount.h" +#include "tcg-accel-ops.h" +#include "tcg-accel-ops-rr.h" +#include "tcg-accel-ops-icount.h" =20 /* Kick all RR vCPUs */ void rr_kick_vcpu_thread(CPUState *unused) @@ -296,10 +296,3 @@ void rr_start_vcpu_thread(CPUState *cpu) cpu->created =3D true; } } - -const CpusAccel tcg_cpus_rr =3D { - .create_vcpu_thread =3D rr_start_vcpu_thread, - .kick_vcpu_thread =3D rr_kick_vcpu_thread, - - .handle_interrupt =3D tcg_cpus_handle_interrupt, -}; diff --git a/accel/tcg/tcg-cpus.c b/accel/tcg/tcg-accel-ops.c similarity index 63% rename from accel/tcg/tcg-cpus.c rename to accel/tcg/tcg-accel-ops.c index e335f9f155..3017f66dd7 100644 --- a/accel/tcg/tcg-cpus.c +++ b/accel/tcg/tcg-accel-ops.c @@ -34,7 +34,10 @@ #include "exec/exec-all.h" #include "hw/boards.h" =20 -#include "tcg-cpus.h" +#include "tcg-accel-ops.h" +#include "tcg-accel-ops-mttcg.h" +#include "tcg-accel-ops-rr.h" +#include "tcg-accel-ops-icount.h" =20 /* common functionality among all TCG variants */ =20 @@ -64,7 +67,7 @@ int tcg_cpus_exec(CPUState *cpu) } =20 /* mask must never be zero, except for A20 change call */ -void tcg_cpus_handle_interrupt(CPUState *cpu, int mask) +void tcg_handle_interrupt(CPUState *cpu, int mask) { g_assert(qemu_mutex_iothread_locked()); =20 @@ -80,3 +83,43 @@ void tcg_cpus_handle_interrupt(CPUState *cpu, int mask) qatomic_set(&cpu_neg(cpu)->icount_decr.u16.high, -1); } } + +static void tcg_accel_ops_init(AccelOpsClass *ops) +{ + if (qemu_tcg_mttcg_enabled()) { + ops->create_vcpu_thread =3D mttcg_start_vcpu_thread; + ops->kick_vcpu_thread =3D mttcg_kick_vcpu_thread; + ops->handle_interrupt =3D tcg_handle_interrupt; + + } else if (icount_enabled()) { + ops->create_vcpu_thread =3D rr_start_vcpu_thread; + ops->kick_vcpu_thread =3D rr_kick_vcpu_thread; + ops->handle_interrupt =3D icount_handle_interrupt; + ops->get_virtual_clock =3D icount_get; + ops->get_elapsed_ticks =3D icount_get; + + } else { + ops->create_vcpu_thread =3D rr_start_vcpu_thread; + ops->kick_vcpu_thread =3D rr_kick_vcpu_thread; + ops->handle_interrupt =3D tcg_handle_interrupt; + } +} + +static void tcg_accel_ops_class_init(ObjectClass *oc, void *data) +{ + AccelOpsClass *ops =3D ACCEL_OPS_CLASS(oc); + + ops->ops_init =3D tcg_accel_ops_init; +}; +static const TypeInfo tcg_accel_ops_type =3D { + .name =3D ACCEL_OPS_NAME("tcg"), + + .parent =3D TYPE_ACCEL_OPS, + .class_init =3D tcg_accel_ops_class_init, + .abstract =3D true, +}; +static void tcg_accel_ops_register_types(void) +{ + type_register_static(&tcg_accel_ops_type); +} +type_init(tcg_accel_ops_register_types); diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 7125d0cc29..f0d97b4b21 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -33,10 +33,6 @@ #include "qemu/accel.h" #include "qapi/qapi-builtin-visit.h" =20 -#ifndef CONFIG_USER_ONLY -#include "tcg-cpus.h" -#endif /* CONFIG_USER_ONLY */ - struct TCGState { AccelState parent_obj; =20 @@ -116,14 +112,6 @@ static int tcg_init(MachineState *ms) */ #ifndef CONFIG_USER_ONLY tcg_region_init(); - - if (mttcg_enabled) { - cpus_register_accel(&tcg_cpus_mttcg); - } else if (icount_enabled()) { - cpus_register_accel(&tcg_cpus_icount); - } else { - cpus_register_accel(&tcg_cpus_rr); - } #endif /* !CONFIG_USER_ONLY */ =20 return 0; diff --git a/accel/xen/xen-all.c b/accel/xen/xen-all.c index 594aaf6b49..82fc21f1ce 100644 --- a/accel/xen/xen-all.c +++ b/accel/xen/xen-all.c @@ -154,10 +154,6 @@ static void xen_setup_post(MachineState *ms, AccelStat= e *accel) } } =20 -const CpusAccel xen_cpus =3D { - .create_vcpu_thread =3D dummy_start_vcpu_thread, -}; - static int xen_init(MachineState *ms) { MachineClass *mc =3D MACHINE_GET_CLASS(ms); @@ -185,9 +181,6 @@ static int xen_init(MachineState *ms) * opt out of system RAM being allocated by generic code */ mc->default_ram_id =3D NULL; - - cpus_register_accel(&xen_cpus); - return 0; } =20 @@ -222,9 +215,24 @@ static const TypeInfo xen_accel_type =3D { .class_init =3D xen_accel_class_init, }; =20 +static void xen_accel_ops_class_init(ObjectClass *oc, void *data) +{ + AccelOpsClass *ops =3D ACCEL_OPS_CLASS(oc); + + ops->create_vcpu_thread =3D dummy_start_vcpu_thread; +}; +static const TypeInfo xen_accel_ops_type =3D { + .name =3D ACCEL_OPS_NAME("xen"), + + .parent =3D TYPE_ACCEL_OPS, + .class_init =3D xen_accel_ops_class_init, + .abstract =3D true, +}; + static void xen_type_init(void) { type_register_static(&xen_accel_type); + type_register_static(&xen_accel_ops_type); } =20 type_init(xen_type_init); diff --git a/bsd-user/main.c b/bsd-user/main.c index ff295bcb29..a68ce5f446 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -908,13 +908,14 @@ int main(int argc, char **argv) #endif } =20 + cpu_type =3D parse_cpu_option(cpu_model); /* init tcg before creating CPUs and to get qemu_host_page_size */ { AccelClass *ac =3D ACCEL_GET_CLASS(current_accel()); =20 ac->init_machine(NULL); + accel_init_interfaces(ac); } - cpu_type =3D parse_cpu_option(cpu_model); cpu =3D cpu_create(cpu_type); env =3D cpu->env_ptr; #if defined(TARGET_SPARC) || defined(TARGET_PPC) diff --git a/linux-user/main.c b/linux-user/main.c index 5c059a8445..e28d016c6f 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -708,6 +708,7 @@ int main(int argc, char **argv, char **envp) AccelClass *ac =3D ACCEL_GET_CLASS(current_accel()); =20 ac->init_machine(NULL); + accel_init_interfaces(ac); } cpu =3D cpu_create(cpu_type); env =3D cpu->env_ptr; diff --git a/softmmu/cpus.c b/softmmu/cpus.c index e46ac68ad0..659617e7ef 100644 --- a/softmmu/cpus.c +++ b/softmmu/cpus.c @@ -127,7 +127,7 @@ void hw_error(const char *fmt, ...) /* * The chosen accelerator is supposed to register this. */ -static const CpusAccel *cpus_accel; +static const AccelOpsClass *cpus_accel; =20 void cpu_synchronize_all_states(void) { @@ -593,11 +593,11 @@ void cpu_remove_sync(CPUState *cpu) qemu_mutex_lock_iothread(); } =20 -void cpus_register_accel(const CpusAccel *ca) +void cpus_register_accel(const AccelOpsClass *ops) { - assert(ca !=3D NULL); - assert(ca->create_vcpu_thread !=3D NULL); /* mandatory */ - cpus_accel =3D ca; + assert(ops !=3D NULL); + assert(ops->create_vcpu_thread !=3D NULL); /* mandatory */ + cpus_accel =3D ops; } =20 void qemu_init_vcpu(CPUState *cpu) @@ -617,7 +617,7 @@ void qemu_init_vcpu(CPUState *cpu) cpu_address_space_init(cpu, 0, "cpu-memory", cpu->memory); } =20 - /* accelerators all implement the CpusAccel interface */ + /* accelerators all implement the AccelOpsClass */ g_assert(cpus_accel !=3D NULL && cpus_accel->create_vcpu_thread !=3D N= ULL); cpus_accel->create_vcpu_thread(cpu); =20 diff --git a/softmmu/vl.c b/softmmu/vl.c index bc20c526d2..b97708300e 100644 --- a/softmmu/vl.c +++ b/softmmu/vl.c @@ -2558,7 +2558,7 @@ static bool object_create_initial(const char *type, Q= emuOpts *opts) } =20 /* Memory allocation by backends needs to be done - * after configure_accelerator() (due to the tcg_enabled() + * after do_configure_accelerator() (due to the tcg_enabled() * checks at memory_region_init_*()). * * Also, allocation of large amounts of memory may delay @@ -4186,7 +4186,7 @@ void qemu_init(int argc, char **argv, char **envp) * * Machine compat properties: object_set_machine_compat_props(). * Accelerator compat props: object_set_accelerator_compat_props(), - * called from configure_accelerator(). + * called from do_configure_accelerator(). */ =20 if (!qtest_enabled() && machine_class->deprecation_reason) { @@ -4321,6 +4321,8 @@ void qemu_init(int argc, char **argv, char **envp) if (cpu_option) { current_machine->cpu_type =3D parse_cpu_option(cpu_option); } + /* NB: for machine none cpu_type could STILL be NULL here! */ + accel_init_interfaces(ACCEL_GET_CLASS(current_machine->accelerator)); =20 if (current_machine->ram_memdev_id) { Object *backend; diff --git a/target/i386/hax/hax-cpus.c b/target/i386/hax/hax-accel-ops.c similarity index 69% rename from target/i386/hax/hax-cpus.c rename to target/i386/hax/hax-accel-ops.c index f72c85bd49..f66042c61e 100644 --- a/target/i386/hax/hax-cpus.c +++ b/target/i386/hax/hax-accel-ops.c @@ -26,7 +26,7 @@ #include "sysemu/cpus.h" #include "qemu/guest-random.h" =20 -#include "hax-cpus.h" +#include "hax-accel-ops.h" =20 static void *hax_cpu_thread_fn(void *arg) { @@ -74,12 +74,27 @@ static void hax_start_vcpu_thread(CPUState *cpu) #endif } =20 -const CpusAccel hax_cpus =3D { - .create_vcpu_thread =3D hax_start_vcpu_thread, - .kick_vcpu_thread =3D hax_kick_vcpu_thread, +static void hax_accel_ops_class_init(ObjectClass *oc, void *data) +{ + AccelOpsClass *ops =3D ACCEL_OPS_CLASS(oc); =20 - .synchronize_post_reset =3D hax_cpu_synchronize_post_reset, - .synchronize_post_init =3D hax_cpu_synchronize_post_init, - .synchronize_state =3D hax_cpu_synchronize_state, - .synchronize_pre_loadvm =3D hax_cpu_synchronize_pre_loadvm, + ops->create_vcpu_thread =3D hax_start_vcpu_thread; + ops->kick_vcpu_thread =3D hax_kick_vcpu_thread; + + ops->synchronize_post_reset =3D hax_cpu_synchronize_post_reset; + ops->synchronize_post_init =3D hax_cpu_synchronize_post_init; + ops->synchronize_state =3D hax_cpu_synchronize_state; + ops->synchronize_pre_loadvm =3D hax_cpu_synchronize_pre_loadvm; +}; +static const TypeInfo hax_accel_ops_type =3D { + .name =3D ACCEL_OPS_NAME("hax"), + + .parent =3D TYPE_ACCEL_OPS, + .class_init =3D hax_accel_ops_class_init, + .abstract =3D true, }; +static void hax_accel_ops_register_types(void) +{ + type_register_static(&hax_accel_ops_type); +} +type_init(hax_accel_ops_register_types); diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c index d7f4bb44a7..bf65ed6fa9 100644 --- a/target/i386/hax/hax-all.c +++ b/target/i386/hax/hax-all.c @@ -33,7 +33,7 @@ #include "sysemu/runstate.h" #include "hw/boards.h" =20 -#include "hax-cpus.h" +#include "hax-accel-ops.h" =20 #define DEBUG_HAX 0 =20 @@ -364,9 +364,6 @@ static int hax_accel_init(MachineState *ms) !ret ? "working" : "not working", !ret ? "fast virt" : "emulation"); } - if (ret =3D=3D 0) { - cpus_register_accel(&hax_cpus); - } return ret; } =20 diff --git a/target/i386/hax/hax-mem.c b/target/i386/hax/hax-mem.c index 71e637cf16..35495f5e82 100644 --- a/target/i386/hax/hax-mem.c +++ b/target/i386/hax/hax-mem.c @@ -13,7 +13,7 @@ #include "exec/address-spaces.h" #include "qemu/error-report.h" =20 -#include "hax-cpus.h" +#include "hax-accel-ops.h" #include "qemu/queue.h" =20 #define DEBUG_HAX_MEM 0 diff --git a/target/i386/hax/hax-posix.c b/target/i386/hax/hax-posix.c index 735a749d4b..ac1a51096e 100644 --- a/target/i386/hax/hax-posix.c +++ b/target/i386/hax/hax-posix.c @@ -15,7 +15,7 @@ #include =20 #include "sysemu/cpus.h" -#include "hax-cpus.h" +#include "hax-accel-ops.h" =20 hax_fd hax_mod_open(void) { diff --git a/target/i386/hax/hax-windows.c b/target/i386/hax/hax-windows.c index 6c82dfb54f..59afa213a6 100644 --- a/target/i386/hax/hax-windows.c +++ b/target/i386/hax/hax-windows.c @@ -12,7 +12,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "hax-cpus.h" +#include "hax-accel-ops.h" =20 /* * return 0 when success, -1 when driver not loaded, diff --git a/target/i386/hvf/hvf-cpus.c b/target/i386/hvf/hvf-accel-ops.c similarity index 84% rename from target/i386/hvf/hvf-cpus.c rename to target/i386/hvf/hvf-accel-ops.c index 817b3d7452..cbaad238e0 100644 --- a/target/i386/hvf/hvf-cpus.c +++ b/target/i386/hvf/hvf-accel-ops.c @@ -55,7 +55,7 @@ #include "target/i386/cpu.h" #include "qemu/guest-random.h" =20 -#include "hvf-cpus.h" +#include "hvf-accel-ops.h" =20 /* * The HVF-specific vCPU thread function. This one should only run when th= e host @@ -121,11 +121,26 @@ static void hvf_start_vcpu_thread(CPUState *cpu) cpu, QEMU_THREAD_JOINABLE); } =20 -const CpusAccel hvf_cpus =3D { - .create_vcpu_thread =3D hvf_start_vcpu_thread, +static void hvf_accel_ops_class_init(ObjectClass *oc, void *data) +{ + AccelOpsClass *ops =3D ACCEL_OPS_CLASS(oc); =20 - .synchronize_post_reset =3D hvf_cpu_synchronize_post_reset, - .synchronize_post_init =3D hvf_cpu_synchronize_post_init, - .synchronize_state =3D hvf_cpu_synchronize_state, - .synchronize_pre_loadvm =3D hvf_cpu_synchronize_pre_loadvm, + ops->create_vcpu_thread =3D hvf_start_vcpu_thread; + + ops->synchronize_post_reset =3D hvf_cpu_synchronize_post_reset; + ops->synchronize_post_init =3D hvf_cpu_synchronize_post_init; + ops->synchronize_state =3D hvf_cpu_synchronize_state; + ops->synchronize_pre_loadvm =3D hvf_cpu_synchronize_pre_loadvm; +}; +static const TypeInfo hvf_accel_ops_type =3D { + .name =3D ACCEL_OPS_NAME("hvf"), + + .parent =3D TYPE_ACCEL_OPS, + .class_init =3D hvf_accel_ops_class_init, + .abstract =3D true, }; +static void hvf_accel_ops_register_types(void) +{ + type_register_static(&hvf_accel_ops_type); +} +type_init(hvf_accel_ops_register_types); diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index ffc9efa40f..5b90dcdf88 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -72,7 +72,7 @@ #include "qemu/accel.h" #include "target/i386/cpu.h" =20 -#include "hvf-cpus.h" +#include "hvf-accel-ops.h" =20 HVFState *hvf_state; =20 @@ -887,7 +887,6 @@ static int hvf_accel_init(MachineState *ms) =20 hvf_state =3D s; memory_listener_register(&hvf_memory_listener, &address_space_memory); - cpus_register_accel(&hvf_cpus); return 0; } =20 diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c index bbec412b6c..0d7533742e 100644 --- a/target/i386/hvf/x86hvf.c +++ b/target/i386/hvf/x86hvf.c @@ -32,7 +32,7 @@ #include #include =20 -#include "hvf-cpus.h" +#include "hvf-accel-ops.h" =20 void hvf_set_segment(struct CPUState *cpu, struct vmx_segment *vmx_seg, SegmentCache *qseg, bool is_tr) diff --git a/target/i386/whpx/whpx-cpus.c b/target/i386/whpx/whpx-accel-ops= .c similarity index 72% rename from target/i386/whpx/whpx-cpus.c rename to target/i386/whpx/whpx-accel-ops.c index d9bd5a2d36..b880947cc2 100644 --- a/target/i386/whpx/whpx-cpus.c +++ b/target/i386/whpx/whpx-accel-ops.c @@ -15,7 +15,7 @@ #include "qemu/guest-random.h" =20 #include "sysemu/whpx.h" -#include "whpx-cpus.h" +#include "whpx-accel-ops.h" =20 #include #include @@ -85,12 +85,27 @@ static void whpx_kick_vcpu_thread(CPUState *cpu) } } =20 -const CpusAccel whpx_cpus =3D { - .create_vcpu_thread =3D whpx_start_vcpu_thread, - .kick_vcpu_thread =3D whpx_kick_vcpu_thread, +static void whpx_accel_ops_class_init(ObjectClass *oc, void *data) +{ + AccelOpsClass *ops =3D ACCEL_OPS_CLASS(oc); =20 - .synchronize_post_reset =3D whpx_cpu_synchronize_post_reset, - .synchronize_post_init =3D whpx_cpu_synchronize_post_init, - .synchronize_state =3D whpx_cpu_synchronize_state, - .synchronize_pre_loadvm =3D whpx_cpu_synchronize_pre_loadvm, + ops->create_vcpu_thread =3D whpx_start_vcpu_thread; + ops->kick_vcpu_thread =3D whpx_kick_vcpu_thread; + + ops->synchronize_post_reset =3D whpx_cpu_synchronize_post_reset; + ops->synchronize_post_init =3D whpx_cpu_synchronize_post_init; + ops->synchronize_state =3D whpx_cpu_synchronize_state; + ops->synchronize_pre_loadvm =3D whpx_cpu_synchronize_pre_loadvm; +}; +static const TypeInfo whpx_accel_ops_type =3D { + .name =3D ACCEL_OPS_NAME("whpx"), + + .parent =3D TYPE_ACCEL_OPS, + .class_init =3D whpx_accel_ops_class_init, + .abstract =3D true, }; +static void whpx_accel_ops_register_types(void) +{ + type_register_static(&whpx_accel_ops_type); +} +type_init(whpx_accel_ops_register_types); diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index ee6b606194..fbac300ada 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -24,7 +24,7 @@ #include "migration/blocker.h" #include "whp-dispatch.h" =20 -#include "whpx-cpus.h" +#include "whpx-accel-ops.h" =20 #include #include @@ -1642,8 +1642,6 @@ static int whpx_accel_init(MachineState *ms) =20 whpx_memory_init(); =20 - cpus_register_accel(&whpx_cpus); - printf("Windows Hypervisor Platform accelerator is operational\n"); return 0; =20 diff --git a/MAINTAINERS b/MAINTAINERS index 6235dd3a9f..8f0e773a47 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -435,7 +435,8 @@ M: Richard Henderson R: Paolo Bonzini S: Maintained F: include/qemu/accel.h -F: accel/accel.c +F: include/sysemu/accel-ops.h +F: accel/accel-*.c F: accel/Makefile.objs F: accel/stubs/Makefile.objs =20 diff --git a/accel/kvm/meson.build b/accel/kvm/meson.build index 7e9dafe24c..8d219bea50 100644 --- a/accel/kvm/meson.build +++ b/accel/kvm/meson.build @@ -1,7 +1,7 @@ kvm_ss =3D ss.source_set() kvm_ss.add(files( 'kvm-all.c', - 'kvm-cpus.c', + 'kvm-accel-ops.c', )) kvm_ss.add(when: 'CONFIG_SEV', if_false: files('sev-stub.c')) =20 diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 424d9bb1fc..1236ac7b91 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -15,8 +15,8 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss) =20 specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files( 'cputlb.c', - 'tcg-cpus.c', - 'tcg-cpus-mttcg.c', - 'tcg-cpus-icount.c', - 'tcg-cpus-rr.c' + 'tcg-accel-ops.c', + 'tcg-accel-ops-mttcg.c', + 'tcg-accel-ops-icount.c', + 'tcg-accel-ops-rr.c' )) diff --git a/target/i386/hax/meson.build b/target/i386/hax/meson.build index 77ea431b30..d6c520fb6b 100644 --- a/target/i386/hax/meson.build +++ b/target/i386/hax/meson.build @@ -1,7 +1,7 @@ i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files( 'hax-all.c', 'hax-mem.c', - 'hax-cpus.c', + 'hax-accel-ops.c', )) i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('= hax-posix.c')) i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('= hax-windows.c')) diff --git a/target/i386/hvf/meson.build b/target/i386/hvf/meson.build index 409c9a3f14..e9eb5a5da8 100644 --- a/target/i386/hvf/meson.build +++ b/target/i386/hvf/meson.build @@ -1,6 +1,6 @@ i386_softmmu_ss.add(when: [hvf, 'CONFIG_HVF'], if_true: files( 'hvf.c', - 'hvf-cpus.c', + 'hvf-accel-ops.c', 'x86.c', 'x86_cpuid.c', 'x86_decode.c', diff --git a/target/i386/whpx/meson.build b/target/i386/whpx/meson.build index 94a72c8efc..e790b42992 100644 --- a/target/i386/whpx/meson.build +++ b/target/i386/whpx/meson.build @@ -1,4 +1,4 @@ i386_softmmu_ss.add(when: 'CONFIG_WHPX', if_true: files( 'whpx-all.c', - 'whpx-cpus.c', + 'whpx-accel-ops.c', )) --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 10 Dec 2020 04:51:10 -0800 (PST) Received: from localhost ([::1]:50860 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knLPY-0000B2-Sg for importer@patchew.org; Thu, 10 Dec 2020 07:51:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56760) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKou-0002fQ-Nh for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:13:16 -0500 Received: from mx2.suse.de ([195.135.220.15]:48008) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKon-0006Xp-AJ for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:13:16 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 126E1AD6A; Thu, 10 Dec 2020 12:12:58 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 28/32] accel: introduce AccelCPUClass extending CPUClass Date: Thu, 10 Dec 2020 13:12:22 +0100 Message-Id: <20201210121226.19822-29-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" add a new optional interface to CPUClass, which allows accelerators to extend the CPUClass with additional accelerator-specific initializations. Signed-off-by: Claudio Fontana --- include/hw/core/accel-cpu.h | 25 +++++++++++++++++++++ include/hw/core/cpu.h | 13 +++++++++++ accel/accel-common.c | 44 +++++++++++++++++++++++++++++++++++++ MAINTAINERS | 1 + 4 files changed, 83 insertions(+) create mode 100644 include/hw/core/accel-cpu.h diff --git a/include/hw/core/accel-cpu.h b/include/hw/core/accel-cpu.h new file mode 100644 index 0000000000..dce08a9100 --- /dev/null +++ b/include/hw/core/accel-cpu.h @@ -0,0 +1,25 @@ +/* + * Accelerator interface, specializes CPUClass + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef ACCEL_CPU_H +#define ACCEL_CPU_H + +/* + * these defines cannot be in cpu.h, because we are using + * CPU_RESOLVING_TYPE here. + * Use this header to define your accelerator-specific + * cpu-specific accelerator interfaces. + */ + +#define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE +#define ACCEL_CPU_NAME(name) (name "-" TYPE_ACCEL_CPU) +typedef struct AccelCPUClass AccelCPUClass; +DECLARE_CLASS_CHECKERS(AccelCPUClass, ACCEL_CPU, TYPE_ACCEL_CPU) + +#endif /* ACCEL_CPU_H */ diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index db54223983..97e1dd8279 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -76,6 +76,17 @@ typedef struct CPUWatchpoint CPUWatchpoint; =20 struct TranslationBlock; =20 +/* see also accel-cpu.h */ +typedef struct AccelCPUClass { + /*< private >*/ + ObjectClass parent_class; + /*< public >*/ + + void (*cpu_class_init)(CPUClass *cc); + void (*cpu_instance_init)(CPUState *cpu); + void (*cpu_realizefn)(CPUState *cpu, Error **errp); +} AccelCPUClass; + #ifdef CONFIG_TCG #include "tcg-cpu-ops.h" #endif /* CONFIG_TCG */ @@ -196,6 +207,8 @@ struct CPUClass { #ifdef CONFIG_TCG TcgCpuOperations tcg_ops; #endif /* CONFIG_TCG */ + + AccelCPUClass *accel_cpu_interface; }; =20 /* diff --git a/accel/accel-common.c b/accel/accel-common.c index 6b59873419..ef73c761fc 100644 --- a/accel/accel-common.c +++ b/accel/accel-common.c @@ -26,6 +26,9 @@ #include "qemu/osdep.h" #include "qemu/accel.h" =20 +#include "cpu.h" +#include "hw/core/accel-cpu.h" + #ifndef CONFIG_USER_ONLY #include "accel-softmmu.h" #endif /* !CONFIG_USER_ONLY */ @@ -46,16 +49,57 @@ AccelClass *accel_find(const char *opt_name) return ac; } =20 +static void accel_init_cpu_int_aux(ObjectClass *klass, void *opaque) +{ + CPUClass *cc =3D CPU_CLASS(klass); + AccelCPUClass *accel_cpu_interface =3D opaque; + + cc->accel_cpu_interface =3D accel_cpu_interface; + if (accel_cpu_interface->cpu_class_init) { + accel_cpu_interface->cpu_class_init(cc); + } +} + +/* initialize the arch-specific accel CpuClass interfaces */ +static void accel_init_cpu_interfaces(AccelClass *ac) +{ + const char *ac_name; /* AccelClass name */ + char *acc_name; /* AccelCPUClass name */ + ObjectClass *acc; /* AccelCPUClass */ + + ac_name =3D object_class_get_name(OBJECT_CLASS(ac)); + g_assert(ac_name !=3D NULL); + + acc_name =3D g_strdup_printf("%s-%s", ac_name, CPU_RESOLVING_TYPE); + acc =3D object_class_by_name(acc_name); + g_free(acc_name); + + if (acc) { + object_class_foreach(accel_init_cpu_int_aux, + CPU_RESOLVING_TYPE, false, acc); + } +} + void accel_init_interfaces(AccelClass *ac) { #ifndef CONFIG_USER_ONLY accel_init_ops_interfaces(ac); #endif /* !CONFIG_USER_ONLY */ + + accel_init_cpu_interfaces(ac); } =20 +static const TypeInfo accel_cpu_type =3D { + .name =3D TYPE_ACCEL_CPU, + .parent =3D TYPE_OBJECT, + .abstract =3D true, + .class_size =3D sizeof(AccelCPUClass), +}; + static void register_accel_types(void) { type_register_static(&accel_type); + type_register_static(&accel_cpu_type); } =20 type_init(register_accel_types); diff --git a/MAINTAINERS b/MAINTAINERS index 8f0e773a47..f084d73f6b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -436,6 +436,7 @@ R: Paolo Bonzini S: Maintained F: include/qemu/accel.h F: include/sysemu/accel-ops.h +F: include/hw/core/accel-cpu.h F: accel/accel-*.c F: accel/Makefile.objs F: accel/stubs/Makefile.objs --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607604847; cv=none; d=zohomail.com; s=zohoarc; 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Thu, 10 Dec 2020 04:54:07 -0800 (PST) Received: from localhost ([::1]:59598 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knLSQ-0003zP-HQ for importer@patchew.org; Thu, 10 Dec 2020 07:54:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56828) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKp1-0002k0-21 for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:13:23 -0500 Received: from mx2.suse.de ([195.135.220.15]:48044) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoo-0006Y2-Ae for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:13:22 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 0CC52AD8D; Thu, 10 Dec 2020 12:12:59 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 29/32] i386: split cpu accelerators from cpu.c, using AccelCPUClass Date: Thu, 10 Dec 2020 13:12:23 +0100 Message-Id: <20201210121226.19822-30-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" i386 is the first user of AccelCPUClass, allowing to split cpu.c into: cpu.c cpuid and common x86 cpu functionality host-cpu.c host x86 cpu functions and "host" cpu type kvm/kvm-cpu.c KVM x86 AccelCPUClass hvf/hvf-cpu.c HVF x86 AccelCPUClass tcg/tcg-cpu.c TCG x86 AccelCPUClass Signed-off-by: Claudio Fontana --- target/i386/cpu.h | 20 +- target/i386/host-cpu.h | 19 ++ target/i386/kvm/kvm-cpu.h | 41 ++++ target/i386/tcg/tcg-cpu.h | 15 -- hw/i386/pc_piix.c | 1 + target/i386/cpu.c | 386 ++++-------------------------------- target/i386/host-cpu.c | 198 ++++++++++++++++++ target/i386/hvf/hvf-cpu.c | 65 ++++++ target/i386/kvm/kvm-cpu.c | 148 ++++++++++++++ target/i386/kvm/kvm.c | 3 +- target/i386/tcg/tcg-cpu.c | 116 ++++++++++- MAINTAINERS | 2 +- target/i386/hvf/meson.build | 1 + target/i386/kvm/meson.build | 7 +- target/i386/meson.build | 6 +- 15 files changed, 644 insertions(+), 384 deletions(-) create mode 100644 target/i386/host-cpu.h create mode 100644 target/i386/kvm/kvm-cpu.h delete mode 100644 target/i386/tcg/tcg-cpu.h create mode 100644 target/i386/host-cpu.c create mode 100644 target/i386/hvf/hvf-cpu.c create mode 100644 target/i386/kvm/kvm-cpu.c diff --git a/target/i386/cpu.h b/target/i386/cpu.h index a0d64613dc..b3e39fc631 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1905,13 +1905,20 @@ int cpu_x86_signal_handler(int host_signum, void *p= info, void *puc); =20 /* cpu.c */ +void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, + uint32_t vendor2, uint32_t vendor3); +typedef struct PropValue { + const char *prop, *value; +} PropValue; +void x86_cpu_apply_props(X86CPU *cpu, PropValue *props); + +/* cpu.c other functions (cpuid) */ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); void cpu_clear_apic_feature(CPUX86State *env); void host_cpuid(uint32_t function, uint32_t count, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx= ); -void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); =20 /* helper.c */ void x86_cpu_set_a20(X86CPU *cpu, int a20_state); @@ -2111,17 +2118,6 @@ void cpu_report_tpr_access(CPUX86State *env, TPRAcce= ss access); void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, TPRAccess access); =20 - -/* Change the value of a KVM-specific default - * - * If value is NULL, no default will be set and the original - * value from the CPU model table will be kept. - * - * It is valid to call this function only for properties that - * are already present in the kvm_default_props table. - */ -void x86_cpu_change_kvm_default(const char *prop, const char *value); - /* Special values for X86CPUVersion: */ =20 /* Resolve to latest CPU version */ diff --git a/target/i386/host-cpu.h b/target/i386/host-cpu.h new file mode 100644 index 0000000000..d1f2644422 --- /dev/null +++ b/target/i386/host-cpu.h @@ -0,0 +1,19 @@ +/* + * x86 host CPU type initialization and host CPU functions + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef HOST_CPU_H +#define HOST_CPU_H + +void host_cpu_instance_init(X86CPU *cpu); +void host_cpu_max_instance_init(X86CPU *cpu); +void host_cpu_realizefn(CPUState *cs, Error **errp); + +void host_cpu_vendor_fms(char *vendor, int *family, int *model, int *stepp= ing); + +#endif /* HOST_CPU_H */ diff --git a/target/i386/kvm/kvm-cpu.h b/target/i386/kvm/kvm-cpu.h new file mode 100644 index 0000000000..e858ca21e5 --- /dev/null +++ b/target/i386/kvm/kvm-cpu.h @@ -0,0 +1,41 @@ +/* + * i386 KVM CPU type and functions + * + * Copyright (c) 2003 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef KVM_CPU_H +#define KVM_CPU_H + +#ifdef CONFIG_KVM +/* + * Change the value of a KVM-specific default + * + * If value is NULL, no default will be set and the original + * value from the CPU model table will be kept. + * + * It is valid to call this function only for properties that + * are already present in the kvm_default_props table. + */ +void x86_cpu_change_kvm_default(const char *prop, const char *value); + +#else /* !CONFIG_KVM */ + +#define x86_cpu_change_kvm_default(a, b) + +#endif /* CONFIG_KVM */ + +#endif /* KVM_CPU_H */ diff --git a/target/i386/tcg/tcg-cpu.h b/target/i386/tcg/tcg-cpu.h deleted file mode 100644 index 81f02e562e..0000000000 --- a/target/i386/tcg/tcg-cpu.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * i386 TCG CPU class initialization - * - * Copyright 2020 SUSE LLC - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - */ - -#ifndef TCG_CPU_H -#define TCG_CPU_H - -void tcg_cpu_common_class_init(CPUClass *cc); - -#endif /* TCG_CPU_H */ diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 6188c3e97e..3abcb425bb 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -64,6 +64,7 @@ #include "hw/hyperv/vmbus-bridge.h" #include "hw/mem/nvdimm.h" #include "hw/i386/acpi-build.h" +#include "kvm/kvm-cpu.h" =20 #define MAX_IDE_BUS 2 =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f0aa6d1841..5414523651 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -22,37 +22,24 @@ #include "qemu/cutils.h" #include "qemu/bitops.h" #include "qemu/qemu-print.h" - #include "cpu.h" -#include "tcg/tcg-cpu.h" #include "tcg/helper-tcg.h" #include "exec/exec-all.h" #include "sysemu/kvm.h" #include "sysemu/reset.h" #include "sysemu/hvf.h" -#include "sysemu/cpus.h" +#include "hw/core/accel-cpu.h" #include "sysemu/xen.h" #include "kvm/kvm_i386.h" #include "sev_i386.h" - -#include "qemu/error-report.h" #include "qemu/module.h" -#include "qemu/option.h" -#include "qemu/config-file.h" -#include "qapi/error.h" #include "qapi/qapi-visit-machine.h" #include "qapi/qapi-visit-run-state.h" #include "qapi/qmp/qdict.h" #include "qapi/qmp/qerror.h" -#include "qapi/visitor.h" #include "qom/qom-qobject.h" -#include "sysemu/arch_init.h" #include "qapi/qapi-commands-machine-target.h" - #include "standard-headers/asm-x86/kvm_para.h" - -#include "sysemu/sysemu.h" -#include "sysemu/tcg.h" #include "hw/qdev-properties.h" #include "hw/i386/topology.h" #ifndef CONFIG_USER_ONLY @@ -594,8 +581,8 @@ static CPUCacheInfo legacy_l3_cache =3D { #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32= K,64K */ =20 -static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, - uint32_t vendor2, uint32_t vendor3) +void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, + uint32_t vendor2, uint32_t vendor3) { int i; for (i =3D 0; i < 4; i++) { @@ -1563,25 +1550,6 @@ void host_cpuid(uint32_t function, uint32_t count, *edx =3D vec[3]; } =20 -void host_vendor_fms(char *vendor, int *family, int *model, int *stepping) -{ - uint32_t eax, ebx, ecx, edx; - - host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx); - x86_cpu_vendor_words2str(vendor, ebx, edx, ecx); - - host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx); - if (family) { - *family =3D ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF); - } - if (model) { - *model =3D ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12); - } - if (stepping) { - *stepping =3D eax & 0x0F; - } -} - /* CPU class name definitions: */ =20 /* Return type name for a given CPU model name @@ -1606,10 +1574,6 @@ static char *x86_cpu_class_get_model_name(X86CPUClas= s *cc) strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX)); } =20 -typedef struct PropValue { - const char *prop, *value; -} PropValue; - typedef struct X86CPUVersionDefinition { X86CPUVersion version; const char *alias; @@ -4106,31 +4070,6 @@ static X86CPUDefinition builtin_x86_defs[] =3D { }, }; =20 -/* KVM-specific features that are automatically added/removed - * from all CPU models when KVM is enabled. - */ -static PropValue kvm_default_props[] =3D { - { "kvmclock", "on" }, - { "kvm-nopiodelay", "on" }, - { "kvm-asyncpf", "on" }, - { "kvm-steal-time", "on" }, - { "kvm-pv-eoi", "on" }, - { "kvmclock-stable-bit", "on" }, - { "x2apic", "on" }, - { "acpi", "off" }, - { "monitor", "off" }, - { "svm", "off" }, - { NULL, NULL }, -}; - -/* TCG-specific defaults that override all CPU models when using TCG - */ -static PropValue tcg_default_props[] =3D { - { "vme", "off" }, - { NULL, NULL }, -}; - - /* * We resolve CPU model aliases using -v1 when using "-machine * none", but this is just for compatibility while libvirt isn't @@ -4172,61 +4111,6 @@ static X86CPUVersion x86_cpu_model_resolve_version(c= onst X86CPUModel *model) return v; } =20 -void x86_cpu_change_kvm_default(const char *prop, const char *value) -{ - PropValue *pv; - for (pv =3D kvm_default_props; pv->prop; pv++) { - if (!strcmp(pv->prop, prop)) { - pv->value =3D value; - break; - } - } - - /* It is valid to call this function only for properties that - * are already present in the kvm_default_props table. - */ - assert(pv->prop); -} - -static bool lmce_supported(void) -{ - uint64_t mce_cap =3D 0; - -#ifdef CONFIG_KVM - if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0)= { - return false; - } -#endif - - return !!(mce_cap & MCG_LMCE_P); -} - -#define CPUID_MODEL_ID_SZ 48 - -/** - * cpu_x86_fill_model_id: - * Get CPUID model ID string from host CPU. - * - * @str should have at least CPUID_MODEL_ID_SZ bytes - * - * The function does NOT add a null terminator to the string - * automatically. - */ -static int cpu_x86_fill_model_id(char *str) -{ - uint32_t eax =3D 0, ebx =3D 0, ecx =3D 0, edx =3D 0; - int i; - - for (i =3D 0; i < 3; i++) { - host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx); - memcpy(str + i * 16 + 0, &eax, 4); - memcpy(str + i * 16 + 4, &ebx, 4); - memcpy(str + i * 16 + 8, &ecx, 4); - memcpy(str + i * 16 + 12, &edx, 4); - } - return 0; -} - static Property max_x86_cpu_properties[] =3D { DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, fa= lse), @@ -4249,61 +4133,25 @@ static void max_x86_cpu_class_init(ObjectClass *oc,= void *data) static void max_x86_cpu_initfn(Object *obj) { X86CPU *cpu =3D X86_CPU(obj); - CPUX86State *env =3D &cpu->env; - KVMState *s =3D kvm_state; =20 /* We can't fill the features array here because we don't know yet if * "migratable" is true or false. */ cpu->max_features =3D true; - - if (accel_uses_host_cpuid()) { - char vendor[CPUID_VENDOR_SZ + 1] =3D { 0 }; - char model_id[CPUID_MODEL_ID_SZ + 1] =3D { 0 }; - int family, model, stepping; - - host_vendor_fms(vendor, &family, &model, &stepping); - cpu_x86_fill_model_id(model_id); - - object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abor= t); - object_property_set_int(OBJECT(cpu), "family", family, &error_abor= t); - object_property_set_int(OBJECT(cpu), "model", model, &error_abort); - object_property_set_int(OBJECT(cpu), "stepping", stepping, - &error_abort); - object_property_set_str(OBJECT(cpu), "model-id", model_id, - &error_abort); - - if (kvm_enabled()) { - env->cpuid_min_level =3D - kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX); - env->cpuid_min_xlevel =3D - kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX); - env->cpuid_min_xlevel2 =3D - kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX); - } else { - env->cpuid_min_level =3D - hvf_get_supported_cpuid(0x0, 0, R_EAX); - env->cpuid_min_xlevel =3D - hvf_get_supported_cpuid(0x80000000, 0, R_EAX); - env->cpuid_min_xlevel2 =3D - hvf_get_supported_cpuid(0xC0000000, 0, R_EAX); - } - - if (lmce_supported()) { - object_property_set_bool(OBJECT(cpu), "lmce", true, &error_abo= rt); - } - } else { - object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, - &error_abort); - object_property_set_int(OBJECT(cpu), "family", 6, &error_abort); - object_property_set_int(OBJECT(cpu), "model", 6, &error_abort); - object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort); - object_property_set_str(OBJECT(cpu), "model-id", - "QEMU TCG CPU version " QEMU_HW_VERSION, - &error_abort); - } - object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); + + /* + * these defaults are used for TCG and all other accelerators + * besides KVM and HVF, which overwrite these values + */ + object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, + &error_abort); + object_property_set_int(OBJECT(cpu), "family", 6, &error_abort); + object_property_set_int(OBJECT(cpu), "model", 6, &error_abort); + object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort); + object_property_set_str(OBJECT(cpu), "model-id", + "QEMU TCG CPU version " QEMU_HW_VERSION, + &error_abort); } =20 static const TypeInfo max_x86_cpu_type_info =3D { @@ -4313,31 +4161,6 @@ static const TypeInfo max_x86_cpu_type_info =3D { .class_init =3D max_x86_cpu_class_init, }; =20 -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) -static void host_x86_cpu_class_init(ObjectClass *oc, void *data) -{ - X86CPUClass *xcc =3D X86_CPU_CLASS(oc); - - xcc->host_cpuid_required =3D true; - xcc->ordering =3D 8; - -#if defined(CONFIG_KVM) - xcc->model_description =3D - "KVM processor with all supported host features "; -#elif defined(CONFIG_HVF) - xcc->model_description =3D - "HVF processor with all supported host features "; -#endif -} - -static const TypeInfo host_x86_cpu_type_info =3D { - .name =3D X86_CPU_TYPE_NAME("host"), - .parent =3D X86_CPU_TYPE_NAME("max"), - .class_init =3D host_x86_cpu_class_init, -}; - -#endif - static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) { assert(f->type =3D=3D CPUID_FEATURE_WORD || f->type =3D=3D MSR_FEATURE= _WORD); @@ -5063,7 +4886,7 @@ static uint64_t x86_cpu_get_supported_feature_word(Fe= atureWord w, return r; } =20 -static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) +void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) { PropValue *pv; for (pv =3D props; pv->prop; pv++) { @@ -5110,8 +4933,6 @@ static void x86_cpu_load_model(X86CPU *cpu, X86CPUMod= el *model) { X86CPUDefinition *def =3D model->cpudef; CPUX86State *env =3D &cpu->env; - const char *vendor; - char host_vendor[CPUID_VENDOR_SZ + 1]; FeatureWord w; =20 /*NOTE: any property set by this function should be returned by @@ -5138,18 +4959,6 @@ static void x86_cpu_load_model(X86CPU *cpu, X86CPUMo= del *model) /* legacy-cache defaults to 'off' if CPU model provides cache info */ cpu->legacy_cache =3D !def->cache_info; =20 - /* Special cases not set in the X86CPUDefinition structs: */ - /* TODO: in-kernel irqchip for hvf */ - if (kvm_enabled()) { - if (!kvm_irqchip_in_kernel()) { - x86_cpu_change_kvm_default("x2apic", "off"); - } - - x86_cpu_apply_props(cpu, kvm_default_props); - } else if (tcg_enabled()) { - x86_cpu_apply_props(cpu, tcg_default_props); - } - env->features[FEAT_1_ECX] |=3D CPUID_EXT_HYPERVISOR; =20 /* sysenter isn't supported in compatibility mode on AMD, @@ -5159,15 +4968,12 @@ static void x86_cpu_load_model(X86CPU *cpu, X86CPUM= odel *model) * KVM's sysenter/syscall emulation in compatibility mode and * when doing cross vendor migration */ - vendor =3D def->vendor; - if (accel_uses_host_cpuid()) { - uint32_t ebx =3D 0, ecx =3D 0, edx =3D 0; - host_cpuid(0, 0, NULL, &ebx, &ecx, &edx); - x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx); - vendor =3D host_vendor; - } =20 - object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort); + /* + * vendor property is set here but then overloaded with the + * host cpu vendor for KVM and HVF. + */ + object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abo= rt); =20 x86_cpu_apply_version_props(cpu, model); =20 @@ -6192,53 +5998,12 @@ static void x86_cpu_apic_realize(X86CPU *cpu, Error= **errp) apic_mmio_map_once =3D true; } } - -static void x86_cpu_machine_done(Notifier *n, void *unused) -{ - X86CPU *cpu =3D container_of(n, X86CPU, machine_done); - MemoryRegion *smram =3D - (MemoryRegion *) object_resolve_path("/machine/smram", NULL); - - if (smram) { - cpu->smram =3D g_new(MemoryRegion, 1); - memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram", - smram, 0, 4 * GiB); - memory_region_set_enabled(cpu->smram, true); - memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smra= m, 1); - } -} #else static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp) { } #endif =20 -/* Note: Only safe for use on x86(-64) hosts */ -static uint32_t x86_host_phys_bits(void) -{ - uint32_t eax; - uint32_t host_phys_bits; - - host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL); - if (eax >=3D 0x80000008) { - host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL); - /* Note: According to AMD doc 25481 rev 2.34 they have a field - * at 23:16 that can specify a maximum physical address bits for - * the guest that can override this value; but I've not seen - * anything with that set. - */ - host_phys_bits =3D eax & 0xff; - } else { - /* It's an odd 64 bit machine that doesn't have the leaf for - * physical address bits; fall back to 36 that's most older - * Intel. - */ - host_phys_bits =3D 36; - } - - return host_phys_bits; -} - static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t valu= e) { if (*min < value) { @@ -6515,33 +6280,22 @@ static void x86_cpu_filter_features(X86CPU *cpu, bo= ol verbose) static void x86_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); + CPUClass *cc =3D CPU_GET_CLASS(cs); X86CPU *cpu =3D X86_CPU(dev); X86CPUClass *xcc =3D X86_CPU_GET_CLASS(dev); CPUX86State *env =3D &cpu->env; Error *local_err =3D NULL; static bool ht_warned; =20 - if (xcc->host_cpuid_required) { - if (!accel_uses_host_cpuid()) { - g_autofree char *name =3D x86_cpu_class_get_model_name(xcc); - error_setg(&local_err, "CPU model '%s' requires KVM", name); - goto out; - } + /* The accelerator realizefn needs to be called first. */ + if (cc->accel_cpu_interface) { + cc->accel_cpu_interface->cpu_realizefn(cs, errp); } =20 - if (cpu->max_features && accel_uses_host_cpuid()) { - if (enable_cpu_pm) { - host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx, - &cpu->mwait.ecx, &cpu->mwait.edx); - env->features[FEAT_1_ECX] |=3D CPUID_EXT_MONITOR; - if (kvm_enabled() && kvm_has_waitpkg()) { - env->features[FEAT_7_0_ECX] |=3D CPUID_7_0_ECX_WAITPKG; - } - } - if (kvm_enabled() && cpu->ucode_rev =3D=3D 0) { - cpu->ucode_rev =3D kvm_arch_get_supported_msr_feature(kvm_stat= e, - MSR_IA32_U= CODE_REV); - } + if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { + g_autofree char *name =3D x86_cpu_class_get_model_name(xcc); + error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); + goto out; } =20 if (cpu->ucode_rev =3D=3D 0) { @@ -6593,39 +6347,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) * consumer AMD devices but nothing else. */ if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { - if (accel_uses_host_cpuid()) { - uint32_t host_phys_bits =3D x86_host_phys_bits(); - static bool warned; - - /* Print a warning if the user set it to a value that's not the - * host value. - */ - if (cpu->phys_bits !=3D host_phys_bits && cpu->phys_bits !=3D = 0 && - !warned) { - warn_report("Host physical bits (%u)" - " does not match phys-bits property (%u)", - host_phys_bits, cpu->phys_bits); - warned =3D true; - } - - if (cpu->host_phys_bits) { - /* The user asked for us to use the host physical bits */ - cpu->phys_bits =3D host_phys_bits; - if (cpu->host_phys_bits_limit && - cpu->phys_bits > cpu->host_phys_bits_limit) { - cpu->phys_bits =3D cpu->host_phys_bits_limit; - } - } - - if (cpu->phys_bits && - (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || - cpu->phys_bits < 32)) { - error_setg(errp, "phys-bits should be between 32 and %u " - " (but is %u)", - TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bi= ts); - return; - } - } else { + if (!accel_uses_host_cpuid()) { if (cpu->phys_bits && cpu->phys_bits !=3D TCG_PHYS_ADDR_BITS) { error_setg(errp, "TCG only supports phys-bits=3D%u", TCG_PHYS_ADDR_BITS); @@ -6633,8 +6355,8 @@ static void x86_cpu_realizefn(DeviceState *dev, Error= **errp) } } /* 0 means it was not explicitly set by the user (or by machine - * compat_props or by the host code above). In this case, the defa= ult - * is the value used by TCG (40). + * compat_props or by the host code in host-cpu.c). + * In this case, the default is the value used by TCG (40). */ if (cpu->phys_bits =3D=3D 0) { cpu->phys_bits =3D TCG_PHYS_ADDR_BITS; @@ -6704,33 +6426,6 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) =20 mce_init(cpu); =20 -#ifndef CONFIG_USER_ONLY - if (tcg_enabled()) { - cpu->cpu_as_mem =3D g_new(MemoryRegion, 1); - cpu->cpu_as_root =3D g_new(MemoryRegion, 1); - - /* Outer container... */ - memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull); - memory_region_set_enabled(cpu->cpu_as_root, true); - - /* ... with two regions inside: normal system memory with low - * priority, and... - */ - memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory", - get_system_memory(), 0, ~0ull); - memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_= as_mem, 0); - memory_region_set_enabled(cpu->cpu_as_mem, true); - - cs->num_ases =3D 2; - cpu_address_space_init(cs, 0, "cpu-memory", cs->memory); - cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root); - - /* ... SMRAM with higher priority, linked from /machine/smram. */ - cpu->machine_done.notify =3D x86_cpu_machine_done; - qemu_add_machine_init_done_notifier(&cpu->machine_done); - } -#endif - qemu_init_vcpu(cs); =20 /* @@ -6936,6 +6631,8 @@ static void x86_cpu_initfn(Object *obj) { X86CPU *cpu =3D X86_CPU(obj); X86CPUClass *xcc =3D X86_CPU_GET_CLASS(obj); + CPUClass *cc =3D CPU_CLASS(xcc); + CPUX86State *env =3D &cpu->env; FeatureWord w; =20 @@ -6992,6 +6689,11 @@ static void x86_cpu_initfn(Object *obj) if (xcc->model) { x86_cpu_load_model(cpu, xcc->model); } + + /* if required, do the accelerator-specific cpu initialization */ + if (cc->accel_cpu_interface) { + cc->accel_cpu_interface->cpu_instance_init(CPU(obj)); + } } =20 static int64_t x86_cpu_get_arch_id(CPUState *cs) @@ -7248,11 +6950,6 @@ static void x86_cpu_common_class_init(ObjectClass *o= c, void *data) cc->class_by_name =3D x86_cpu_class_by_name; cc->parse_features =3D x86_cpu_parse_featurestr; cc->has_work =3D x86_cpu_has_work; - -#ifdef CONFIG_TCG - tcg_cpu_common_class_init(cc); -#endif /* CONFIG_TCG */ - cc->dump_state =3D x86_cpu_dump_state; cc->set_pc =3D x86_cpu_set_pc; cc->gdb_read_register =3D x86_cpu_gdb_read_register; @@ -7357,9 +7054,6 @@ static void x86_cpu_register_types(void) } type_register_static(&max_x86_cpu_type_info); type_register_static(&x86_base_cpu_type_info); -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) - type_register_static(&host_x86_cpu_type_info); -#endif } =20 type_init(x86_cpu_register_types) diff --git a/target/i386/host-cpu.c b/target/i386/host-cpu.c new file mode 100644 index 0000000000..3ce2bc9a84 --- /dev/null +++ b/target/i386/host-cpu.c @@ -0,0 +1,198 @@ +/* + * x86 host CPU functions, and "host" cpu type initialization + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "host-cpu.h" +#include "qapi/error.h" +#include "sysemu/sysemu.h" + +/* Note: Only safe for use on x86(-64) hosts */ +static uint32_t host_cpu_phys_bits(void) +{ + uint32_t eax; + uint32_t host_phys_bits; + + host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL); + if (eax >=3D 0x80000008) { + host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL); + /* + * Note: According to AMD doc 25481 rev 2.34 they have a field + * at 23:16 that can specify a maximum physical address bits for + * the guest that can override this value; but I've not seen + * anything with that set. + */ + host_phys_bits =3D eax & 0xff; + } else { + /* + * It's an odd 64 bit machine that doesn't have the leaf for + * physical address bits; fall back to 36 that's most older + * Intel. + */ + host_phys_bits =3D 36; + } + + return host_phys_bits; +} + +static void host_cpu_enable_cpu_pm(X86CPU *cpu) +{ + CPUX86State *env =3D &cpu->env; + + host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx, + &cpu->mwait.ecx, &cpu->mwait.edx); + env->features[FEAT_1_ECX] |=3D CPUID_EXT_MONITOR; +} + +static uint32_t host_cpu_adjust_phys_bits(X86CPU *cpu, Error **errp) +{ + uint32_t host_phys_bits =3D host_cpu_phys_bits(); + uint32_t phys_bits =3D cpu->phys_bits; + static bool warned; + + /* + * Print a warning if the user set it to a value that's not the + * host value. + */ + if (phys_bits !=3D host_phys_bits && phys_bits !=3D 0 && + !warned) { + warn_report("Host physical bits (%u)" + " does not match phys-bits property (%u)", + host_phys_bits, phys_bits); + warned =3D true; + } + + if (cpu->host_phys_bits) { + /* The user asked for us to use the host physical bits */ + phys_bits =3D host_phys_bits; + if (cpu->host_phys_bits_limit && + phys_bits > cpu->host_phys_bits_limit) { + phys_bits =3D cpu->host_phys_bits_limit; + } + } + + if (phys_bits && + (phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || + phys_bits < 32)) { + error_setg(errp, "phys-bits should be between 32 and %u " + " (but is %u)", + TARGET_PHYS_ADDR_SPACE_BITS, phys_bits); + } + + return phys_bits; +} + +void host_cpu_realizefn(CPUState *cs, Error **errp) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + + if (cpu->max_features && enable_cpu_pm) { + host_cpu_enable_cpu_pm(cpu); + } + if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { + cpu->phys_bits =3D host_cpu_adjust_phys_bits(cpu, errp); + } +} + +#define CPUID_MODEL_ID_SZ 48 +/** + * cpu_x86_fill_model_id: + * Get CPUID model ID string from host CPU. + * + * @str should have at least CPUID_MODEL_ID_SZ bytes + * + * The function does NOT add a null terminator to the string + * automatically. + */ +static int host_cpu_fill_model_id(char *str) +{ + uint32_t eax =3D 0, ebx =3D 0, ecx =3D 0, edx =3D 0; + int i; + + for (i =3D 0; i < 3; i++) { + host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx); + memcpy(str + i * 16 + 0, &eax, 4); + memcpy(str + i * 16 + 4, &ebx, 4); + memcpy(str + i * 16 + 8, &ecx, 4); + memcpy(str + i * 16 + 12, &edx, 4); + } + return 0; +} + +void host_cpu_vendor_fms(char *vendor, int *family, int *model, int *stepp= ing) +{ + uint32_t eax, ebx, ecx, edx; + + host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx); + x86_cpu_vendor_words2str(vendor, ebx, edx, ecx); + + host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx); + if (family) { + *family =3D ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF); + } + if (model) { + *model =3D ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12); + } + if (stepping) { + *stepping =3D eax & 0x0F; + } +} + +void host_cpu_instance_init(X86CPU *cpu) +{ + uint32_t ebx =3D 0, ecx =3D 0, edx =3D 0; + char vendor[CPUID_VENDOR_SZ + 1]; + + host_cpuid(0, 0, NULL, &ebx, &ecx, &edx); + x86_cpu_vendor_words2str(vendor, ebx, edx, ecx); + + object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort); +} + +void host_cpu_max_instance_init(X86CPU *cpu) +{ + char vendor[CPUID_VENDOR_SZ + 1] =3D { 0 }; + char model_id[CPUID_MODEL_ID_SZ + 1] =3D { 0 }; + int family, model, stepping; + + host_cpu_vendor_fms(vendor, &family, &model, &stepping); + host_cpu_fill_model_id(model_id); + + object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort); + object_property_set_int(OBJECT(cpu), "family", family, &error_abort); + object_property_set_int(OBJECT(cpu), "model", model, &error_abort); + object_property_set_int(OBJECT(cpu), "stepping", stepping, + &error_abort); + object_property_set_str(OBJECT(cpu), "model-id", model_id, + &error_abort); +} + +static void host_cpu_class_init(ObjectClass *oc, void *data) +{ + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); + + xcc->host_cpuid_required =3D true; + xcc->ordering =3D 8; + xcc->model_description =3D + g_strdup_printf("processor with all supported host features "); +} + +static const TypeInfo host_cpu_type_info =3D { + .name =3D X86_CPU_TYPE_NAME("host"), + .parent =3D X86_CPU_TYPE_NAME("max"), + .class_init =3D host_cpu_class_init, +}; + +static void host_cpu_type_init(void) +{ + type_register_static(&host_cpu_type_info); +} + +type_init(host_cpu_type_init); diff --git a/target/i386/hvf/hvf-cpu.c b/target/i386/hvf/hvf-cpu.c new file mode 100644 index 0000000000..d6579571f1 --- /dev/null +++ b/target/i386/hvf/hvf-cpu.c @@ -0,0 +1,65 @@ +/* + * x86 HVF CPU type initialization + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "host-cpu.h" +#include "qapi/error.h" +#include "sysemu/sysemu.h" +#include "hw/boards.h" +#include "sysemu/hvf.h" +#include "hw/core/accel-cpu.h" + +static void hvf_cpu_max_instance_init(X86CPU *cpu) +{ + CPUX86State *env =3D &cpu->env; + + host_cpu_max_instance_init(cpu); + + env->cpuid_min_level =3D + hvf_get_supported_cpuid(0x0, 0, R_EAX); + env->cpuid_min_xlevel =3D + hvf_get_supported_cpuid(0x80000000, 0, R_EAX); + env->cpuid_min_xlevel2 =3D + hvf_get_supported_cpuid(0xC0000000, 0, R_EAX); +} + +static void hvf_cpu_instance_init(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + + host_cpu_instance_init(cpu); + + /* Special cases not set in the X86CPUDefinition structs: */ + /* TODO: in-kernel irqchip for hvf */ + + if (cpu->max_features) { + hvf_cpu_max_instance_init(cpu); + } +} + +static void hvf_cpu_accel_class_init(ObjectClass *oc, void *data) +{ + AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); + + acc->cpu_realizefn =3D host_cpu_realizefn; + acc->cpu_instance_init =3D hvf_cpu_instance_init; +}; +static const TypeInfo hvf_cpu_accel_type_info =3D { + .name =3D ACCEL_CPU_NAME("hvf"), + + .parent =3D TYPE_ACCEL_CPU, + .class_init =3D hvf_cpu_accel_class_init, + .abstract =3D true, +}; +static void hvf_cpu_accel_register_types(void) +{ + type_register_static(&hvf_cpu_accel_type_info); +} +type_init(hvf_cpu_accel_register_types); diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c new file mode 100644 index 0000000000..adc5120cf6 --- /dev/null +++ b/target/i386/kvm/kvm-cpu.c @@ -0,0 +1,148 @@ +/* + * x86 KVM CPU type initialization + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "host-cpu.h" +#include "kvm-cpu.h" +#include "qapi/error.h" +#include "sysemu/sysemu.h" +#include "hw/boards.h" + +#include "kvm_i386.h" +#include "hw/core/accel-cpu.h" + +static void kvm_cpu_realizefn(CPUState *cs, Error **errp) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + + /* + * The realize order is important, since x86_cpu_realize() checks if + * nothing else has been set by the user (or by accelerators) in + * cpu->ucode_rev and cpu->phys_bits. + * + * realize order: + * kvm_cpu -> host_cpu -> x86_cpu + */ + if (cpu->max_features) { + if (enable_cpu_pm && kvm_has_waitpkg()) { + env->features[FEAT_7_0_ECX] |=3D CPUID_7_0_ECX_WAITPKG; + } + if (cpu->ucode_rev =3D=3D 0) { + cpu->ucode_rev =3D + kvm_arch_get_supported_msr_feature(kvm_state, + MSR_IA32_UCODE_REV); + } + } + host_cpu_realizefn(cs, errp); +} + +/* + * KVM-specific features that are automatically added/removed + * from all CPU models when KVM is enabled. + */ +static PropValue kvm_default_props[] =3D { + { "kvmclock", "on" }, + { "kvm-nopiodelay", "on" }, + { "kvm-asyncpf", "on" }, + { "kvm-steal-time", "on" }, + { "kvm-pv-eoi", "on" }, + { "kvmclock-stable-bit", "on" }, + { "x2apic", "on" }, + { "acpi", "off" }, + { "monitor", "off" }, + { "svm", "off" }, + { NULL, NULL }, +}; + +void x86_cpu_change_kvm_default(const char *prop, const char *value) +{ + PropValue *pv; + for (pv =3D kvm_default_props; pv->prop; pv++) { + if (!strcmp(pv->prop, prop)) { + pv->value =3D value; + break; + } + } + + /* + * It is valid to call this function only for properties that + * are already present in the kvm_default_props table. + */ + assert(pv->prop); +} + +static bool lmce_supported(void) +{ + uint64_t mce_cap =3D 0; + + if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0)= { + return false; + } + return !!(mce_cap & MCG_LMCE_P); +} + +static void kvm_cpu_max_instance_init(X86CPU *cpu) +{ + CPUX86State *env =3D &cpu->env; + KVMState *s =3D kvm_state; + + host_cpu_max_instance_init(cpu); + + if (lmce_supported()) { + object_property_set_bool(OBJECT(cpu), "lmce", true, &error_abort); + } + + env->cpuid_min_level =3D + kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX); + env->cpuid_min_xlevel =3D + kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX); + env->cpuid_min_xlevel2 =3D + kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX); +} + +static void kvm_cpu_instance_init(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + + host_cpu_instance_init(cpu); + + if (!kvm_irqchip_in_kernel()) { + x86_cpu_change_kvm_default("x2apic", "off"); + } + + /* Special cases not set in the X86CPUDefinition structs: */ + + x86_cpu_apply_props(cpu, kvm_default_props); + + if (cpu->max_features) { + kvm_cpu_max_instance_init(cpu); + } +} + +static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) +{ + AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); + + acc->cpu_realizefn =3D kvm_cpu_realizefn; + acc->cpu_instance_init =3D kvm_cpu_instance_init; +} +static const TypeInfo kvm_cpu_accel_type_info =3D { + .name =3D ACCEL_CPU_NAME("kvm"), + + .parent =3D TYPE_ACCEL_CPU, + .class_init =3D kvm_cpu_accel_class_init, + .abstract =3D true, +}; +static void kvm_cpu_accel_register_types(void) +{ + type_register_static(&kvm_cpu_accel_type_info); +} +type_init(kvm_cpu_accel_register_types); diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index a2934dda02..35c86fdba6 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -22,6 +22,7 @@ #include "standard-headers/asm-x86/kvm_para.h" =20 #include "cpu.h" +#include "host-cpu.h" #include "sysemu/sysemu.h" #include "sysemu/hw_accel.h" #include "sysemu/kvm_int.h" @@ -285,7 +286,7 @@ static bool host_tsx_broken(void) int family, model, stepping;\ char vendor[CPUID_VENDOR_SZ + 1]; =20 - host_vendor_fms(vendor, &family, &model, &stepping); + host_cpu_vendor_fms(vendor, &family, &model, &stepping); =20 /* Check if we are running on a Haswell host known to have broken TSX = */ return !strcmp(vendor, CPUID_VENDOR_INTEL) && diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index d2dd521612..45262de5fb 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -19,13 +19,14 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "tcg-cpu.h" -#include "exec/exec-all.h" -#include "sysemu/runstate.h" #include "helper-tcg.h" +#include "qemu/accel.h" +#include "hw/core/accel-cpu.h" =20 -#if !defined(CONFIG_USER_ONLY) -#include "hw/i386/apic.h" +#ifndef CONFIG_USER_ONLY +#include "sysemu/sysemu.h" +#include "qemu/units.h" +#include "exec/address-spaces.h" #endif =20 /* Frob eflags into and out of the CPU temporary format. */ @@ -56,7 +57,72 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, Tr= anslationBlock *tb) cpu->env.eip =3D tb->pc - tb->cs_base; } =20 -void tcg_cpu_common_class_init(CPUClass *cc) +#ifndef CONFIG_USER_ONLY + +static void x86_cpu_machine_done(Notifier *n, void *unused) +{ + X86CPU *cpu =3D container_of(n, X86CPU, machine_done); + MemoryRegion *smram =3D + (MemoryRegion *) object_resolve_path("/machine/smram", NULL); + + if (smram) { + cpu->smram =3D g_new(MemoryRegion, 1); + memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram", + smram, 0, 4 * GiB); + memory_region_set_enabled(cpu->smram, true); + memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, + cpu->smram, 1); + } +} + +static void tcg_cpu_realizefn(CPUState *cs, Error **errp) +{ + X86CPU *cpu =3D X86_CPU(cs); + + /* + * The realize order is important, since x86_cpu_realize() checks if + * nothing else has been set by the user (or by accelerators) in + * cpu->ucode_rev and cpu->phys_bits, and the memory regions + * initialized here are needed for the vcpu initialization. + * + * realize order: + * tcg_cpu -> host_cpu -> x86_cpu + */ + cpu->cpu_as_mem =3D g_new(MemoryRegion, 1); + cpu->cpu_as_root =3D g_new(MemoryRegion, 1); + + /* Outer container... */ + memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull); + memory_region_set_enabled(cpu->cpu_as_root, true); + + /* + * ... with two regions inside: normal system memory with low + * priority, and... + */ + memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory", + get_system_memory(), 0, ~0ull); + memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_m= em, 0); + memory_region_set_enabled(cpu->cpu_as_mem, true); + + cs->num_ases =3D 2; + cpu_address_space_init(cs, 0, "cpu-memory", cs->memory); + cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root); + + /* ... SMRAM with higher priority, linked from /machine/smram. */ + cpu->machine_done.notify =3D x86_cpu_machine_done; + qemu_add_machine_init_done_notifier(&cpu->machine_done); +} + +#else /* CONFIG_USER_ONLY */ + +static void tcg_cpu_realizefn(CPUState *cs, Error **errp) +{ +} + +#endif /* !CONFIG_USER_ONLY */ + + +static void tcg_cpu_class_init(CPUClass *cc) { cc->tcg_ops.do_interrupt =3D x86_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt =3D x86_cpu_exec_interrupt; @@ -67,5 +133,41 @@ void tcg_cpu_common_class_init(CPUClass *cc) cc->tcg_ops.tlb_fill =3D x86_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->tcg_ops.debug_excp_handler =3D breakpoint_handler; -#endif +#endif /* !CONFIG_USER_ONLY */ } + +/* + * TCG-specific defaults that override all CPU models when using TCG + */ +static PropValue tcg_default_props[] =3D { + { "vme", "off" }, + { NULL, NULL }, +}; + +static void tcg_cpu_instance_init(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + /* Special cases not set in the X86CPUDefinition structs: */ + x86_cpu_apply_props(cpu, tcg_default_props); +} + +static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data) +{ + AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); + + acc->cpu_realizefn =3D tcg_cpu_realizefn; + acc->cpu_class_init =3D tcg_cpu_class_init; + acc->cpu_instance_init =3D tcg_cpu_instance_init; +} +static const TypeInfo tcg_cpu_accel_type_info =3D { + .name =3D ACCEL_CPU_NAME("tcg"), + + .parent =3D TYPE_ACCEL_CPU, + .class_init =3D tcg_cpu_accel_class_init, + .abstract =3D true, +}; +static void tcg_cpu_accel_register_types(void) +{ + type_register_static(&tcg_cpu_accel_type_info); +} +type_init(tcg_cpu_accel_register_types); diff --git a/MAINTAINERS b/MAINTAINERS index f084d73f6b..4f3f1e8b18 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -337,7 +337,7 @@ M: Paolo Bonzini M: Richard Henderson M: Eduardo Habkost S: Maintained -F: target/i386/ +F: target/i386/tcg/ F: tests/tcg/i386/ F: tests/tcg/x86_64/ F: hw/i386/ diff --git a/target/i386/hvf/meson.build b/target/i386/hvf/meson.build index e9eb5a5da8..d253d5fd10 100644 --- a/target/i386/hvf/meson.build +++ b/target/i386/hvf/meson.build @@ -10,4 +10,5 @@ i386_softmmu_ss.add(when: [hvf, 'CONFIG_HVF'], if_true: f= iles( 'x86_mmu.c', 'x86_task.c', 'x86hvf.c', + 'hvf-cpu.c', )) diff --git a/target/i386/kvm/meson.build b/target/i386/kvm/meson.build index 1d66559187..0a533411ca 100644 --- a/target/i386/kvm/meson.build +++ b/target/i386/kvm/meson.build @@ -1,3 +1,8 @@ i386_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) -i386_softmmu_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) + +i386_softmmu_ss.add(when: 'CONFIG_KVM', if_true: files( + 'kvm.c', + 'kvm-cpu.c', +)) + i386_softmmu_ss.add(when: 'CONFIG_HYPERV', if_true: files('hyperv.c'), if_= false: files('hyperv-stub.c')) diff --git a/target/i386/meson.build b/target/i386/meson.build index c4bf20b319..fd24479590 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -6,7 +6,11 @@ i386_ss.add(files( 'xsave_helper.c', 'cpu-dump.c', )) -i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('= sev-stub.c')) +i386_ss.add(when: 'CONFIG_SEV', if_true: files('host-cpu.c', 'sev.c'), if_= false: files('sev-stub.c')) + +# x86 cpu type +i386_ss.add(when: 'CONFIG_KVM', if_true: files('host-cpu.c')) +i386_ss.add(when: 'CONFIG_HVF', if_true: files('host-cpu.c')) =20 i386_softmmu_ss =3D ss.source_set() i386_softmmu_ss.add(files( --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" move the call to the accel_cpu_interface method to the general cpu_exec_realizefn from target/i386, so it does not need to be called for every target explicitly as we enable more targets. Signed-off-by: Claudio Fontana --- cpu.c | 5 +++++ target/i386/cpu.c | 15 ++++----------- 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/cpu.c b/cpu.c index 5cc8f181be..a59a909cfe 100644 --- a/cpu.c +++ b/cpu.c @@ -130,6 +130,11 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp) =20 cpu_list_add(cpu); =20 + if (cc->accel_cpu_interface) { + /* NB: errp parameter is unused currently */ + cc->accel_cpu_interface->cpu_realizefn(cpu, errp); + } + #ifdef CONFIG_TCG /* NB: errp parameter is unused currently */ if (tcg_enabled()) { diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5414523651..0fedf6c160 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6280,16 +6280,16 @@ static void x86_cpu_filter_features(X86CPU *cpu, bo= ol verbose) static void x86_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); - CPUClass *cc =3D CPU_GET_CLASS(cs); X86CPU *cpu =3D X86_CPU(dev); X86CPUClass *xcc =3D X86_CPU_GET_CLASS(dev); CPUX86State *env =3D &cpu->env; Error *local_err =3D NULL; static bool ht_warned; =20 - /* The accelerator realizefn needs to be called first. */ - if (cc->accel_cpu_interface) { - cc->accel_cpu_interface->cpu_realizefn(cs, errp); + cpu_exec_realizefn(cs, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; } =20 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { @@ -6405,13 +6405,6 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) env->cache_info_amd.l3_cache =3D &legacy_l3_cache; } =20 - - cpu_exec_realizefn(cs, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; - } - #ifndef CONFIG_USER_ONLY MachineState *ms =3D MACHINE(qdev_get_machine()); qemu_register_reset(x86_cpu_machine_reset_cb, cpu); --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Thu, 10 Dec 2020 04:41:44 -0800 (PST) Received: from localhost ([::1]:59392 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knLGR-0000J4-Br for importer@patchew.org; Thu, 10 Dec 2020 07:41:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56808) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoy-0002ic-Rd for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:13:20 -0500 Received: from mx2.suse.de ([195.135.220.15]:48146) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoq-0006ZH-Ce for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:13:20 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 010FEAD29; Thu, 10 Dec 2020 12:13:01 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 31/32] hw/core/cpu: call qemu_init_vcpu in cpu_common_realizefn Date: Thu, 10 Dec 2020 13:12:25 +0100 Message-Id: <20201210121226.19822-32-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" move the call to qemu_init_vcpu inside cpu_common_realizefn, so it does not need to be done explicitly in each target cpu. This makes it a little bit better, but still the way realize is done continues to be bad; ideally the cpu_list_add would be done in common_cpu, and in this case we could avoid even more additional calls in target/xxx/cpu.c, but this cannot happen because target cpu code, plugins, etc now all rely on cpu->index, since no particular order was defined previously, so we are stuck with the freak call order for the target cpu realizefn. After this patch the target/xxx/cpu.c realizefn body is now: void mycpu_realizefn(DeviceState *dev, Error **errp) { /* ... */ cpu_exec_realizefn(CPU_STATE(dev), errp); /* ... anything that needs done pre-qemu_vcpu_init */ xcc->parent_realize(dev, errp); /* does qemu_vcpu_init */ /* ... anything that needs to be done after qemu_vcpu_init */ } Note: better do some testing for all targets for this. Signed-off-by: Claudio Fontana --- hw/core/cpu.c | 2 ++ target/alpha/cpu.c | 5 +---- target/arm/cpu.c | 4 +--- target/avr/cpu.c | 3 +-- target/cris/cpu.c | 2 -- target/hppa/cpu.c | 1 - target/i386/cpu.c | 5 +---- target/lm32/cpu.c | 3 --- target/m68k/cpu.c | 2 -- target/microblaze/cpu.c | 9 +++------ target/mips/cpu.c | 2 -- target/moxie/cpu.c | 4 +--- target/nios2/cpu.c | 4 +--- target/openrisc/cpu.c | 4 +--- target/riscv/cpu.c | 8 +++----- target/rx/cpu.c | 8 +++----- target/s390x/cpu.c | 3 +-- target/sh4/cpu.c | 2 -- target/sparc/cpu.c | 4 +--- target/tilegx/cpu.c | 2 -- target/tricore/cpu.c | 2 -- target/unicore32/cpu.c | 6 +----- target/xtensa/cpu.c | 2 -- target/ppc/translate_init.c.inc | 5 ++--- 24 files changed, 23 insertions(+), 69 deletions(-) diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 1f04aab16b..f41c009e6c 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -318,6 +318,8 @@ static void cpu_common_realizefn(DeviceState *dev, Erro= r **errp) CPUState *cpu =3D CPU(dev); Object *machine =3D qdev_get_machine(); =20 + qemu_init_vcpu(cpu); + /* qdev_get_machine() can return something that's not TYPE_MACHINE * if this is one of the user-only emulators; in that case there's * no need to check the ignore_memory_transaction_failures board flag. diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 0b5f5a78e3..d43abbbac1 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -56,18 +56,15 @@ static void alpha_cpu_disas_set_info(CPUState *cpu, dis= assemble_info *info) =20 static void alpha_cpu_realizefn(DeviceState *dev, Error **errp) { - CPUState *cs =3D CPU(dev); AlphaCPUClass *acc =3D ALPHA_CPU_GET_CLASS(dev); Error *local_err =3D NULL; =20 - cpu_exec_realizefn(cs, &local_err); + cpu_exec_realizefn(CPU(dev), &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); return; } =20 - qemu_init_vcpu(cs); - acc->parent_realize(dev, errp); } =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9a8c1dc2e1..6366c6af59 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1859,10 +1859,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) } } =20 - qemu_init_vcpu(cs); - cpu_reset(cs); - acc->parent_realize(dev, errp); + cpu_reset(cs); } =20 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 5a5ae68444..43f91f650d 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -97,10 +97,9 @@ static void avr_cpu_realizefn(DeviceState *dev, Error **= errp) error_propagate(errp, local_err); return; } - qemu_init_vcpu(cs); - cpu_reset(cs); =20 mcc->parent_realize(dev, errp); + cpu_reset(cs); } =20 static void avr_cpu_set_int(void *opaque, int irq, int level) diff --git a/target/cris/cpu.c b/target/cris/cpu.c index b65743e8ca..42a497d9fe 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -135,8 +135,6 @@ static void cris_cpu_realizefn(DeviceState *dev, Error = **errp) } =20 cpu_reset(cs); - qemu_init_vcpu(cs); - ccc->parent_realize(dev, errp); } =20 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 0985b3661f..979714c62e 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -101,7 +101,6 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error = **errp) return; } =20 - qemu_init_vcpu(cs); acc->parent_realize(dev, errp); =20 #ifndef CONFIG_USER_ONLY diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0fedf6c160..5615d9e8bc 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6419,8 +6419,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error= **errp) =20 mce_init(cpu); =20 - qemu_init_vcpu(cs); - + xcc->parent_realize(dev, &local_err); /* * Most Intel and certain AMD CPUs support hyperthreading. Even though= QEMU * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_00= 08_ECX @@ -6447,8 +6446,6 @@ static void x86_cpu_realizefn(DeviceState *dev, Error= **errp) } cpu_reset(cs); =20 - xcc->parent_realize(dev, &local_err); - out: if (local_err !=3D NULL) { error_propagate(errp, local_err); diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index fb3761b749..99196c22a4 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -133,9 +133,6 @@ static void lm32_cpu_realizefn(DeviceState *dev, Error = **errp) } =20 cpu_reset(cs); - - qemu_init_vcpu(cs); - lcc->parent_realize(dev, errp); } =20 diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 3f60c99865..41d3b2c11e 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -248,8 +248,6 @@ static void m68k_cpu_realizefn(DeviceState *dev, Error = **errp) m68k_cpu_init_gdb(cpu); =20 cpu_reset(cs); - qemu_init_vcpu(cs); - mcc->parent_realize(dev, errp); } =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 395f4a300f..6e068b2ae0 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -145,15 +145,14 @@ static void mb_disas_set_info(CPUState *cpu, disassem= ble_info *info) =20 static void mb_cpu_realizefn(DeviceState *dev, Error **errp) { - CPUState *cs =3D CPU(dev); MicroBlazeCPUClass *mcc =3D MICROBLAZE_CPU_GET_CLASS(dev); - MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); + MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(dev); uint8_t version_code =3D 0; const char *version; int i =3D 0; Error *local_err =3D NULL; =20 - cpu_exec_realizefn(cs, &local_err); + cpu_exec_realizefn(CPU(dev), &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); return; @@ -165,7 +164,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **= errp) return; } =20 - qemu_init_vcpu(cs); + mcc->parent_realize(dev, errp); =20 version =3D cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION; for (i =3D 0; mb_cpu_lookup[i].name && version; i++) { @@ -231,8 +230,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **= errp) cpu->cfg.mmu_tlb_access =3D 3; cpu->cfg.mmu_zones =3D 16; cpu->cfg.addr_mask =3D MAKE_64BIT_MASK(0, cpu->cfg.addr_size); - - mcc->parent_realize(dev, errp); } =20 static void mb_cpu_initfn(Object *obj) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 236d0d707b..68cc62c08e 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -182,8 +182,6 @@ static void mips_cpu_realizefn(DeviceState *dev, Error = **errp) cpu_mips_realize_env(&cpu->env); =20 cpu_reset(cs); - qemu_init_vcpu(cs); - mcc->parent_realize(dev, errp); } =20 diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 36bef4d357..4dfd2936af 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -66,10 +66,8 @@ static void moxie_cpu_realizefn(DeviceState *dev, Error = **errp) return; } =20 - qemu_init_vcpu(cs); - cpu_reset(cs); - mcc->parent_realize(dev, errp); + cpu_reset(cs); } =20 static void moxie_cpu_initfn(Object *obj) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 059eea8c94..46440d6ad8 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -92,10 +92,8 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error = **errp) return; } =20 - qemu_init_vcpu(cs); - cpu_reset(cs); - ncc->parent_realize(dev, errp); + cpu_reset(cs); } =20 static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 27105c5c09..e16b66fd14 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -77,10 +77,8 @@ static void openrisc_cpu_realizefn(DeviceState *dev, Err= or **errp) return; } =20 - qemu_init_vcpu(cs); - cpu_reset(cs); - occ->parent_realize(dev, errp); + cpu_reset(cs); } =20 static void openrisc_cpu_initfn(Object *obj) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e5626862c2..6b4eadfdeb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -341,7 +341,7 @@ static void riscv_cpu_disas_set_info(CPUState *s, disas= semble_info *info) #endif } =20 -static void riscv_cpu_realize(DeviceState *dev, Error **errp) +static void riscv_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); RISCVCPU *cpu =3D RISCV_CPU(dev); @@ -486,10 +486,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) =20 riscv_cpu_register_gdb_regs_for_features(cs); =20 - qemu_init_vcpu(cs); - cpu_reset(cs); - mcc->parent_realize(dev, errp); + cpu_reset(cs); } =20 static void riscv_cpu_init(Object *obj) @@ -532,7 +530,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) CPUClass *cc =3D CPU_CLASS(c); DeviceClass *dc =3D DEVICE_CLASS(c); =20 - device_class_set_parent_realize(dc, riscv_cpu_realize, + device_class_set_parent_realize(dc, riscv_cpu_realizefn, &mcc->parent_realize); =20 device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); diff --git a/target/rx/cpu.c b/target/rx/cpu.c index dc7d1c3c57..75ee2866dc 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -105,7 +105,7 @@ static ObjectClass *rx_cpu_class_by_name(const char *cp= u_model) return oc; } =20 -static void rx_cpu_realize(DeviceState *dev, Error **errp) +static void rx_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); RXCPUClass *rcc =3D RX_CPU_GET_CLASS(dev); @@ -117,10 +117,8 @@ static void rx_cpu_realize(DeviceState *dev, Error **e= rrp) return; } =20 - qemu_init_vcpu(cs); - cpu_reset(cs); - rcc->parent_realize(dev, errp); + cpu_reset(cs); } =20 static void rx_cpu_set_irq(void *opaque, int no, int request) @@ -178,7 +176,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) CPUClass *cc =3D CPU_CLASS(klass); RXCPUClass *rcc =3D RX_CPU_CLASS(klass); =20 - device_class_set_parent_realize(dc, rx_cpu_realize, + device_class_set_parent_realize(dc, rx_cpu_realizefn, &rcc->parent_realize); device_class_set_parent_reset(dc, rx_cpu_reset, &rcc->parent_reset); diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 86f654fd6b..d67ae110af 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -232,8 +232,8 @@ static void s390_cpu_realizefn(DeviceState *dev, Error = **errp) qemu_register_reset(s390_cpu_machine_reset_cb, cpu); #endif s390_cpu_gdb_init(cs); - qemu_init_vcpu(cs); =20 + scc->parent_realize(dev, &err); /* * KVM requires the initial CPU reset ioctl to be executed on the targ= et * CPU thread. CPU hotplug under single-threaded TCG will not work with @@ -246,7 +246,6 @@ static void s390_cpu_realizefn(DeviceState *dev, Error = **errp) cpu_reset(cs); } =20 - scc->parent_realize(dev, &err); out: error_propagate(errp, err); } diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index fbd5f42675..b9380cce83 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -185,8 +185,6 @@ static void superh_cpu_realizefn(DeviceState *dev, Erro= r **errp) } =20 cpu_reset(cs); - qemu_init_vcpu(cs); - scc->parent_realize(dev, errp); } =20 diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 3b53ef2390..0b604372d3 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -738,9 +738,9 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error= **errp) { CPUState *cs =3D CPU(dev); SPARCCPUClass *scc =3D SPARC_CPU_GET_CLASS(dev); - Error *local_err =3D NULL; SPARCCPU *cpu =3D SPARC_CPU(dev); CPUSPARCState *env =3D &cpu->env; + Error *local_err =3D NULL; =20 #if defined(CONFIG_USER_ONLY) if ((env->def.features & CPU_FEATURE_FLOAT)) { @@ -768,8 +768,6 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error= **errp) return; } =20 - qemu_init_vcpu(cs); - scc->parent_realize(dev, errp); } =20 diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index 7d4ead4ef1..01db5bdbcf 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -93,8 +93,6 @@ static void tilegx_cpu_realizefn(DeviceState *dev, Error = **errp) } =20 cpu_reset(cs); - qemu_init_vcpu(cs); - tcc->parent_realize(dev, errp); } =20 diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 89a14f81d7..ac57239f87 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -93,8 +93,6 @@ static void tricore_cpu_realizefn(DeviceState *dev, Error= **errp) set_feature(env, TRICORE_FEATURE_13); } cpu_reset(cs); - qemu_init_vcpu(cs); - tcc->parent_realize(dev, errp); } =20 diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index e27ffc571a..fe4ae21700 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -84,18 +84,14 @@ static void uc32_any_cpu_initfn(Object *obj) =20 static void uc32_cpu_realizefn(DeviceState *dev, Error **errp) { - CPUState *cs =3D CPU(dev); UniCore32CPUClass *ucc =3D UNICORE32_CPU_GET_CLASS(dev); Error *local_err =3D NULL; =20 - cpu_exec_realizefn(cs, &local_err); + cpu_exec_realizefn(CPU(dev), &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); return; } - - qemu_init_vcpu(cs); - ucc->parent_realize(dev, errp); } =20 diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 4b6381569f..7387d90cc6 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -153,8 +153,6 @@ static void xtensa_cpu_realizefn(DeviceState *dev, Erro= r **errp) =20 cs->gdb_num_regs =3D xcc->config->gdb_regmap.num_regs; =20 - qemu_init_vcpu(cs); - xcc->parent_realize(dev, errp); } =20 diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 18ce389947..637fb389db 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10093,7 +10093,7 @@ static int ppc_fixup_cpu(PowerPCCPU *cpu) return 0; } =20 -static void ppc_cpu_realize(DeviceState *dev, Error **errp) +static void ppc_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); PowerPCCPU *cpu =3D POWERPC_CPU(dev); @@ -10143,7 +10143,6 @@ static void ppc_cpu_realize(DeviceState *dev, Error= **errp) gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg, pcc->gdb_num_sprs, "power-spr.xml", 0); #endif - qemu_init_vcpu(cs); =20 pcc->parent_realize(dev, errp); =20 @@ -10894,7 +10893,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) CPUClass *cc =3D CPU_CLASS(oc); DeviceClass *dc =3D DEVICE_CLASS(oc); =20 - device_class_set_parent_realize(dc, ppc_cpu_realize, + device_class_set_parent_realize(dc, ppc_cpu_realizefn, &pcc->parent_realize); device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, &pcc->parent_unrealize); --=20 2.26.2 From nobody Tue May 14 18:30:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1607611894; cv=none; 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Thu, 10 Dec 2020 06:51:34 -0800 (PST) Received: from localhost ([::1]:33738 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knLvn-0003Xh-8M for importer@patchew.org; Thu, 10 Dec 2020 08:24:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56812) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKoz-0002jM-4y for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:13:22 -0500 Received: from mx2.suse.de ([195.135.220.15]:48180) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKor-0006ZU-Ai for qemu-devel@nongnu.org; Thu, 10 Dec 2020 07:13:20 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id EE2DBAC6A; Thu, 10 Dec 2020 12:13:01 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v10 32/32] cpu: introduce cpu_accel_instance_init Date: Thu, 10 Dec 2020 13:12:26 +0100 Message-Id: <20201210121226.19822-33-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201210121226.19822-1-cfontana@suse.de> References: <20201210121226.19822-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" centralize the calls to cpu->accel_cpu_interface Signed-off-by: Claudio Fontana --- include/hw/core/cpu.h | 6 ++++++ hw/core/cpu.c | 9 +++++++++ target/i386/cpu.c | 9 ++------- 3 files changed, 17 insertions(+), 7 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 97e1dd8279..cc05c8fc96 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -664,6 +664,12 @@ void cpu_list_remove(CPUState *cpu); */ void cpu_reset(CPUState *cpu); =20 +/** + * cpu_accel_instance_init: + * @cpu: The CPU that needs to do accel-specific object initializations. + */ +void cpu_accel_instance_init(CPUState *cpu); + /** * cpu_class_by_name: * @typename: The CPU base type. diff --git a/hw/core/cpu.c b/hw/core/cpu.c index f41c009e6c..873cf5e4ef 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -242,6 +242,15 @@ void cpu_reset(CPUState *cpu) trace_guest_cpu_reset(cpu); } =20 +void cpu_accel_instance_init(CPUState *cpu) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + if (cc->accel_cpu_interface) { + cc->accel_cpu_interface->cpu_instance_init(cpu); + } +} + static void cpu_common_reset(DeviceState *dev) { CPUState *cpu =3D CPU(dev); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5615d9e8bc..8ee39bea24 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -28,7 +28,6 @@ #include "sysemu/kvm.h" #include "sysemu/reset.h" #include "sysemu/hvf.h" -#include "hw/core/accel-cpu.h" #include "sysemu/xen.h" #include "kvm/kvm_i386.h" #include "sev_i386.h" @@ -6621,8 +6620,6 @@ static void x86_cpu_initfn(Object *obj) { X86CPU *cpu =3D X86_CPU(obj); X86CPUClass *xcc =3D X86_CPU_GET_CLASS(obj); - CPUClass *cc =3D CPU_CLASS(xcc); - CPUX86State *env =3D &cpu->env; FeatureWord w; =20 @@ -6680,10 +6677,8 @@ static void x86_cpu_initfn(Object *obj) x86_cpu_load_model(cpu, xcc->model); } =20 - /* if required, do the accelerator-specific cpu initialization */ - if (cc->accel_cpu_interface) { - cc->accel_cpu_interface->cpu_instance_init(CPU(obj)); - } + /* if required, do accelerator-specific cpu initializations */ + cpu_accel_instance_init(CPU(obj)); } =20 static int64_t x86_cpu_get_arch_id(CPUState *cs) --=20 2.26.2