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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 31/36] hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit
Date: Thu, 10 Dec 2020 11:47:51 +0000
Message-Id: <20201210114756.16501-32-peter.maydell@linaro.org>
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v8.1M introduces a new TRD flag in the CCR register, which enables
checking for stack frame integrity signatures on SG instructions.
This bit is not banked, and is always RAZ/WI to Non-secure code.
Adjust the code for handling CCR reads and writes to handle this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-23-peter.maydell@linaro.org
---
target/arm/cpu.h | 2 ++
hw/intc/armv7m_nvic.c | 26 ++++++++++++++++++--------
2 files changed, 20 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 47cb5032ce9..22c55c81933 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1611,6 +1611,8 @@ FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
FIELD(V7M_CCR, DC, 16, 1)
FIELD(V7M_CCR, IC, 17, 1)
FIELD(V7M_CCR, BP, 18, 1)
+FIELD(V7M_CCR, LOB, 19, 1)
+FIELD(V7M_CCR, TRD, 20, 1)
=20
/* V7M SCR bits */
FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index effc4a784ca..6f94f88a795 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -1095,8 +1095,9 @@ static uint32_t nvic_readl(NVICState *s, uint32_t off=
set, MemTxAttrs attrs)
}
return cpu->env.v7m.scr[attrs.secure];
case 0xd14: /* Configuration Control. */
- /* The BFHFNMIGN bit is the only non-banked bit; we
- * keep it in the non-secure copy of the register.
+ /*
+ * Non-banked bits: BFHFNMIGN (stored in the NS copy of the regist=
er)
+ * and TRD (stored in the S copy of the register)
*/
val =3D cpu->env.v7m.ccr[attrs.secure];
val |=3D cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;
@@ -1639,17 +1640,25 @@ static void nvic_writel(NVICState *s, uint32_t offs=
et, uint32_t value,
cpu->env.v7m.scr[attrs.secure] =3D value;
break;
case 0xd14: /* Configuration Control. */
+ {
+ uint32_t mask;
+
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
}
=20
/* Enforce RAZ/WI on reserved and must-RAZ/WI bits */
- value &=3D (R_V7M_CCR_STKALIGN_MASK |
- R_V7M_CCR_BFHFNMIGN_MASK |
- R_V7M_CCR_DIV_0_TRP_MASK |
- R_V7M_CCR_UNALIGN_TRP_MASK |
- R_V7M_CCR_USERSETMPEND_MASK |
- R_V7M_CCR_NONBASETHRDENA_MASK);
+ mask =3D R_V7M_CCR_STKALIGN_MASK |
+ R_V7M_CCR_BFHFNMIGN_MASK |
+ R_V7M_CCR_DIV_0_TRP_MASK |
+ R_V7M_CCR_UNALIGN_TRP_MASK |
+ R_V7M_CCR_USERSETMPEND_MASK |
+ R_V7M_CCR_NONBASETHRDENA_MASK;
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8_1M) && attrs.secure) {
+ /* TRD is always RAZ/WI from NS */
+ mask |=3D R_V7M_CCR_TRD_MASK;
+ }
+ value &=3D mask;
=20
if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
/* v8M makes NONBASETHRDENA and STKALIGN be RES1 */
@@ -1666,6 +1675,7 @@ static void nvic_writel(NVICState *s, uint32_t offset=
, uint32_t value,
=20
cpu->env.v7m.ccr[attrs.secure] =3D value;
break;
+ }
case 0xd24: /* System Handler Control and State (SHCSR) */
if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) {
goto bad_offset;
--=20
2.20.1