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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 29/36] target/arm: Implement new v8.1M NOCP check for exception
return
Date: Thu, 10 Dec 2020 11:47:49 +0000
Message-Id: <20201210114756.16501-30-peter.maydell@linaro.org>
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In v8.1M a new exception return check is added which may cause a NOCP
UsageFault (see rule R_XLTP): before we clear s0..s15 and the FPSCR
we must check whether access to CP10 from the Security state of the
returning exception is disabled; if it is then we must take a fault.
(Note that for our implementation CPPWR is always RAZ/WI and so can
never cause CP10 accesses to fail.)
The other v8.1M change to this register-clearing code is that if MVE
is implemented VPR must also be cleared, so add a TODO comment to
that effect.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-20-peter.maydell@linaro.org
---
target/arm/m_helper.c | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index 9cdc8a64c29..0bdd3cc10e9 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -1515,7 +1515,27 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
v7m_exception_taken(cpu, excret, true, false);
return;
} else {
- /* Clear s0..s15 and FPSCR */
+ if (arm_feature(env, ARM_FEATURE_V8_1M)) {
+ /* v8.1M adds this NOCP check */
+ bool nsacr_pass =3D exc_secure ||
+ extract32(env->v7m.nsacr, 10, 1);
+ bool cpacr_pass =3D v7m_cpacr_pass(env, exc_secure, true);
+ if (!nsacr_pass) {
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, =
true);
+ env->v7m.cfsr[M_REG_S] |=3D R_V7M_CFSR_NOCP_MASK;
+ qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on ex=
isting "
+ "stackframe: NSACR prevents clearing FPU registers=
\n");
+ v7m_exception_taken(cpu, excret, true, false);
+ } else if (!cpacr_pass) {
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,
+ exc_secure);
+ env->v7m.cfsr[exc_secure] |=3D R_V7M_CFSR_NOCP_MASK;
+ qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on ex=
isting "
+ "stackframe: CPACR prevents clearing FPU registers=
\n");
+ v7m_exception_taken(cpu, excret, true, false);
+ }
+ }
+ /* Clear s0..s15 and FPSCR; TODO also VPR when MVE is implemen=
ted */
int i;
=20
for (i =3D 0; i < 16; i +=3D 2) {
--=20
2.20.1