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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 22/36] target/arm: Use new FPCR_NZCV_MASK constant
Date: Thu, 10 Dec 2020 11:47:42 +0000
Message-Id: <20201210114756.16501-23-peter.maydell@linaro.org>
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We defined a constant name for the mask of NZCV bits in the FPCR/FPSCR
in the previous commit; use it in a couple of places in existing code,
where we're masking out everything except NZCV for the "load to Rt=3D15
sets CPSR.NZCV" special case.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-12-peter.maydell@linaro.org
---
target/arm/translate-vfp.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index d698f3e1cd1..cd8d5b4f28b 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -744,7 +744,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int r=
egno,
* helper call for the "VMRS to CPSR.NZCV" insn.
*/
tmp =3D load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
- tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
+ tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
storefn(s, opaque, tmp);
break;
default:
@@ -885,7 +885,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_V=
MRS *a)
case ARM_VFP_FPSCR:
if (a->rt =3D=3D 15) {
tmp =3D load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
- tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
+ tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
} else {
tmp =3D tcg_temp_new_i32();
gen_helper_vfp_get_fpscr(tmp, cpu_env);
--=20
2.20.1