From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607601500; cv=none; d=zohomail.com; s=zohoarc; b=dc/DVdJdTLgfD/WBEO+lp1gDk6IzTlKkJqfPjFAD7YtAFjLJbCO+v0HWQ5YrZmB/71uz/LLqNO+MKdkpnK4xYBUH0fyX9iykNsf7/zO3H1iXFpeB3UgylTHuOhzvJbfESkQIIfh0sm5K8hwiA4D1odnPdCRBLKZDjocNb0ZQMFM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607601500; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=p66ItyVUUDgsJmX+asFUUV4x21/M0eoLBAxP7LbbHO0=; b=HcDWeh7HwQ1mic7A+5T/ca/4piT4jlQNEm+HkvkftE2/KyfmWYlDCAW9omTYC42j7zr88x8A6tRetqTILjnnyP3M6SpH6nRm1NdRBmIoSm/84xsvPqGeY4ZNN291amk3ZWiJkEXb1ZPl1gS2USic+7780ltzNZwCivrSRfb3q0M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607601500280994.9114819780038; Thu, 10 Dec 2020 03:58:20 -0800 (PST) Received: from localhost ([::1]:55430 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKaQ-0002TE-I5 for importer@patchew.org; Thu, 10 Dec 2020 06:58:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51136) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKQo-0001Mc-Mu for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:22 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:52151) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKQT-0006wv-ST for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:22 -0500 Received: by mail-wm1-x333.google.com with SMTP id v14so4386142wml.1 for ; Thu, 10 Dec 2020 03:48:01 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.47.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:47:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=p66ItyVUUDgsJmX+asFUUV4x21/M0eoLBAxP7LbbHO0=; b=O5F/9Bs0TsHbgM4IWfkeFDQdoIXjcWv5lKM8ymAmS4HPV8+kgDU8Emf8bY0PYVsQPu igdYuSdsM2i76pp6fKAIMFtGJho7TTG+QaGkaxN1jb6WHFuDCLDmjEJCVeB9DJzGygjd 8k3N8oCmcyMc3NmI1HRs2xk5dnFP0zgg4BD7NsO1idZma+PVzTExA8I/cJQQh7lm07sl CEuroaXDW3qa/N/671G5+c6X6cfXHXaCUk90hejhhHAS8tbpNUUOrMn4Yizukfecnkhq ZjueQ9ArvNIOX3RB1qsdc47RFY9rRaiWD4ZkKYPlmIcEj141ySsLOyY/pP3P45a+ceAa wv6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=p66ItyVUUDgsJmX+asFUUV4x21/M0eoLBAxP7LbbHO0=; b=LHei/tsXsfnD6a9mpfkNs1WmQPBmbr3vDCOkXTfN7Da8B0BCulKpBvRSndjuSLVtlo A0pN7vpBZ+D9DqQUbPqZ3LhpQjo7DlahoLoUiKQCkiOhjsHv9koP+M2XnqCDm+M0Ra8W xSw7NxGduPbxwwUhF0ytD4h8miBhf/2SmJXOtWxofLVeYqwmEEY56reXh7jsdfbBm0RD ABNeJQu3/1fxR8N4sPYr2VbgB0p1FgXyaRlqa8fDflyWC9u6D3ULff6KiRiTjlAHRxGm +3T1xe2iph+dCvV58rO61ks14nB0Gthi3Yu2xJGZgQc/85HIXoy6sZAJAnGwwRYjHp0F IKZQ== X-Gm-Message-State: AOAM532NQyWJnpiosbMsRB0Eq2vtLfT0bEH7thcLuhnj5HidkZ8JuUvG sEq0F35e2RopamK49Wxt2vpiMtIVrgbVvg== X-Google-Smtp-Source: ABdhPJworMboWkFRvwy/ZBQ554fCcvZIx6heGRP6Oa4zB3dA97umCOvJA2p4iBsQtJ2j7U4HJmAKTg== X-Received: by 2002:a1c:35c2:: with SMTP id c185mr7905612wma.74.1607600880034; Thu, 10 Dec 2020 03:48:00 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/36] hw/arm/smmuv3: Fix up L1STD_SPAN decoding Date: Thu, 10 Dec 2020 11:47:21 +0000 Message-Id: <20201210114756.16501-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Kunkun Jiang Accroding to the SMMUv3 spec, the SPAN field of Level1 Stream Table Descriptor is 5 bits([4:0]). Fixes: 9bde7f0674f(hw/arm/smmuv3: Implement translate callback) Signed-off-by: Kunkun Jiang Message-id: 20201124023711.1184-1-jiangkunkun@huawei.com Reviewed-by: Peter Maydell Acked-by: Eric Auger Signed-off-by: Peter Maydell --- hw/arm/smmuv3-internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index fa3c088972e..b6f7e53b7c7 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -633,6 +633,6 @@ static inline uint64_t l1std_l2ptr(STEDesc *desc) return hi << 32 | lo; } =20 -#define L1STD_SPAN(stm) (extract32((stm)->word[0], 0, 4)) +#define L1STD_SPAN(stm) (extract32((stm)->word[0], 0, 5)) =20 #endif --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607601263; cv=none; d=zohomail.com; s=zohoarc; b=j6rZz1qJGrNA7ZnnIJunwE0Tb0aHPcbr7rku9uxUAIIrlAoPxuePkE3Pq+25o4Y4lLnvHGCinsDRkUncI2h2dXjmuUcykI0n8lyxVF1mUY4ySY7j7irAV2BXDnPij8IgO071rfWPjE5YkycwaBJZN2JkZ2lcdlasdkfzQTRgseo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607601263; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=akQLSoNN08SKAJpXldnp6iHfpPSy05zG5xxvrJS8YtU=; b=ipKeEjVfEwVzKU19RXCuX1xgHzjHUktzxUXRLIkCOJspQGD7jUoqh1jvz8qBNuA093Gnr9NyyS86rfNHTuSeEkhhsvf8hHG6GWJ1+2nBOmx+nftpkKRoWIq11IV3yN/unKxc0FM44y1w+ryKJt6INm//Qo5fK7EIQiVBLaG0/1g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607601263491646.5974863247541; Thu, 10 Dec 2020 03:54:23 -0800 (PST) Received: from localhost ([::1]:45560 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKWb-0006mI-4P for importer@patchew.org; Thu, 10 Dec 2020 06:54:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51174) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKQs-0001PU-Oi for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:28 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:45732) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKQW-0006yS-JE for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:26 -0500 Received: by mail-wr1-x434.google.com with SMTP id t4so5138652wrr.12 for ; Thu, 10 Dec 2020 03:48:04 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=akQLSoNN08SKAJpXldnp6iHfpPSy05zG5xxvrJS8YtU=; b=k0SLX3grFErx3+xKp+eOHrLClKMVpo2dI/hOFl2mftW4MpPdRcbzXQa5SqQCZtjJ3J J/qDJJyIcKijyHtnSCHgvlL4g0b6LjJGiCj8FGEa/sPiq3RlBziZjnG1xmloLhXz9Y8D 1sTmdbznXJ9ZFGUjqBsGg00zWOkHriOYWIvzWvof2h0gZLtgQX61GjsS9lN31mytv5Be b3AApPm2SS6NQgkRZvw+FQwDiGhSXSLUhsPN6GumWw2aO3ndRrqh6VD58NSISBdNTcPV PtGyY4K/IGxpEfbVbg8TMR5Kg8ZYEittuiDPK/Ojqel3tyBKFn1yWBPWcTnpuSkNV+rW TEIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=akQLSoNN08SKAJpXldnp6iHfpPSy05zG5xxvrJS8YtU=; b=hhUlGMl8IGJWcFmgwx5m65WbiWklyq9BMD+7vHUXR+VzjIsNF0Hdr8aQnSHZlzVpmg ewBF6XcIyLRCIBjXFU3HMvSsnTZ89L9N02NQ4DUssJuFUQQNK5ukdL9Bp+j+Hv7kuq55 S6+HW72Ec23pnWw3Q7Uk7oUF4oa/6jZHbXtegQvhbj4WeXNDzO+M+0JO3qCy3Utf0/Sb r2KgBbK1TDNv3RLVuovjF5BJFi7huf01GXHCg8+NYvPqhsr6uGo4pXqpP5GMx0uwXTge DDV627wOrJ1Obh0yOzZLWbV++n/iwfpON9njc3HvUlNi0Ibyd+4nEjkEbRx0Wu6FdOdx 17mw== X-Gm-Message-State: AOAM530klxHSyLN/x5yvVlKcEFa2rPzzxkVQI5Kd3NT2ihsw+TEYBJAL 6GoYS2kgp1InEiKyKg6pjxOgSfx/AEFr2Q== X-Google-Smtp-Source: ABdhPJwrYPGNBeJ+hT4Ps9gdLZ+mY9c1gW4sq4Zfpew8IgrqnI11eEpI5efGB2NdoyuRFxlgh/piog== X-Received: by 2002:adf:e44d:: with SMTP id t13mr7756718wrm.144.1607600881976; Thu, 10 Dec 2020 03:48:01 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/36] hw/net/can: Introduce Xilinx ZynqMP CAN controller Date: Thu, 10 Dec 2020 11:47:22 +0000 Message-Id: <20201210114756.16501-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Vikram Garhwal The Xilinx ZynqMP CAN controller is developed based on SocketCAN, QEMU CAN = bus implementation. Bus connection and socketCAN connection for each CAN module can be set through command lines. Example for using single CAN: -object can-bus,id=3Dcanbus0 \ -machine xlnx-zcu102.canbus0=3Dcanbus0 \ -object can-host-socketcan,id=3Dsocketcan0,if=3Dvcan0,canbus=3Dcanbus0 Example for connecting both CAN to same virtual CAN on host machine: -object can-bus,id=3Dcanbus0 -object can-bus,id=3Dcanbus1 \ -machine xlnx-zcu102.canbus0=3Dcanbus0 \ -machine xlnx-zcu102.canbus1=3Dcanbus1 \ -object can-host-socketcan,id=3Dsocketcan0,if=3Dvcan0,canbus=3Dcanbus0 \ -object can-host-socketcan,id=3Dsocketcan1,if=3Dvcan0,canbus=3Dcanbus1 To create virtual CAN on the host machine, please check the QEMU CAN docs: https://github.com/qemu/qemu/blob/master/docs/can.txt Signed-off-by: Vikram Garhwal Message-id: 1605728926-352690-2-git-send-email-fnu.vikram@xilinx.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- meson.build | 1 + hw/net/can/trace.h | 1 + include/hw/net/xlnx-zynqmp-can.h | 78 ++ hw/net/can/xlnx-zynqmp-can.c | 1161 ++++++++++++++++++++++++++++++ hw/Kconfig | 1 + hw/net/can/meson.build | 1 + hw/net/can/trace-events | 9 + 7 files changed, 1252 insertions(+) create mode 100644 hw/net/can/trace.h create mode 100644 include/hw/net/xlnx-zynqmp-can.h create mode 100644 hw/net/can/xlnx-zynqmp-can.c create mode 100644 hw/net/can/trace-events diff --git a/meson.build b/meson.build index 732b29a1f37..9ea05ab49fa 100644 --- a/meson.build +++ b/meson.build @@ -1433,6 +1433,7 @@ if have_system 'hw/misc', 'hw/misc/macio', 'hw/net', + 'hw/net/can', 'hw/nvram', 'hw/pci', 'hw/pci-host', diff --git a/hw/net/can/trace.h b/hw/net/can/trace.h new file mode 100644 index 00000000000..d391c649012 --- /dev/null +++ b/hw/net/can/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_net_can.h" diff --git a/include/hw/net/xlnx-zynqmp-can.h b/include/hw/net/xlnx-zynqmp-= can.h new file mode 100644 index 00000000000..eb1558708bb --- /dev/null +++ b/include/hw/net/xlnx-zynqmp-can.h @@ -0,0 +1,78 @@ +/* + * QEMU model of the Xilinx ZynqMP CAN controller. + * + * Copyright (c) 2020 Xilinx Inc. + * + * Written-by: Vikram Garhwal + * + * Based on QEMU CAN Device emulation implemented by Jin Yang, Deniz Eren = and + * Pavel Pisa. + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef XLNX_ZYNQMP_CAN_H +#define XLNX_ZYNQMP_CAN_H + +#include "hw/register.h" +#include "net/can_emu.h" +#include "net/can_host.h" +#include "qemu/fifo32.h" +#include "hw/ptimer.h" +#include "hw/qdev-clock.h" + +#define TYPE_XLNX_ZYNQMP_CAN "xlnx.zynqmp-can" + +#define XLNX_ZYNQMP_CAN(obj) \ + OBJECT_CHECK(XlnxZynqMPCANState, (obj), TYPE_XLNX_ZYNQMP_CAN) + +#define MAX_CAN_CTRLS 2 +#define XLNX_ZYNQMP_CAN_R_MAX (0x84 / 4) +#define MAILBOX_CAPACITY 64 +#define CAN_TIMER_MAX 0XFFFFUL +#define CAN_DEFAULT_CLOCK (24 * 1000 * 1000) + +/* Each CAN_FRAME will have 4 * 32bit size. */ +#define CAN_FRAME_SIZE 4 +#define RXFIFO_SIZE (MAILBOX_CAPACITY * CAN_FRAME_SIZE) + +typedef struct XlnxZynqMPCANState { + SysBusDevice parent_obj; + MemoryRegion iomem; + + qemu_irq irq; + + CanBusClientState bus_client; + CanBusState *canbus; + + struct { + uint32_t ext_clk_freq; + } cfg; + + RegisterInfo reg_info[XLNX_ZYNQMP_CAN_R_MAX]; + uint32_t regs[XLNX_ZYNQMP_CAN_R_MAX]; + + Fifo32 rx_fifo; + Fifo32 tx_fifo; + Fifo32 txhpb_fifo; + + ptimer_state *can_timer; +} XlnxZynqMPCANState; + +#endif diff --git a/hw/net/can/xlnx-zynqmp-can.c b/hw/net/can/xlnx-zynqmp-can.c new file mode 100644 index 00000000000..affa21a5ed3 --- /dev/null +++ b/hw/net/can/xlnx-zynqmp-can.c @@ -0,0 +1,1161 @@ +/* + * QEMU model of the Xilinx ZynqMP CAN controller. + * This implementation is based on the following datasheet: + * https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ul= trascale-trm.pdf + * + * Copyright (c) 2020 Xilinx Inc. + * + * Written-by: Vikram Garhwal + * + * Based on QEMU CAN Device emulation implemented by Jin Yang, Deniz Eren = and + * Pavel Pisa + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/register.h" +#include "hw/irq.h" +#include "qapi/error.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qemu/cutils.h" +#include "sysemu/sysemu.h" +#include "migration/vmstate.h" +#include "hw/qdev-properties.h" +#include "net/can_emu.h" +#include "net/can_host.h" +#include "qemu/event_notifier.h" +#include "qom/object_interfaces.h" +#include "hw/net/xlnx-zynqmp-can.h" +#include "trace.h" + +#ifndef XLNX_ZYNQMP_CAN_ERR_DEBUG +#define XLNX_ZYNQMP_CAN_ERR_DEBUG 0 +#endif + +#define MAX_DLC 8 +#undef ERROR + +REG32(SOFTWARE_RESET_REGISTER, 0x0) + FIELD(SOFTWARE_RESET_REGISTER, CEN, 1, 1) + FIELD(SOFTWARE_RESET_REGISTER, SRST, 0, 1) +REG32(MODE_SELECT_REGISTER, 0x4) + FIELD(MODE_SELECT_REGISTER, SNOOP, 2, 1) + FIELD(MODE_SELECT_REGISTER, LBACK, 1, 1) + FIELD(MODE_SELECT_REGISTER, SLEEP, 0, 1) +REG32(ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, 0x8) + FIELD(ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, BRP, 0, 8) +REG32(ARBITRATION_PHASE_BIT_TIMING_REGISTER, 0xc) + FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, SJW, 7, 2) + FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, TS2, 4, 3) + FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, TS1, 0, 4) +REG32(ERROR_COUNTER_REGISTER, 0x10) + FIELD(ERROR_COUNTER_REGISTER, REC, 8, 8) + FIELD(ERROR_COUNTER_REGISTER, TEC, 0, 8) +REG32(ERROR_STATUS_REGISTER, 0x14) + FIELD(ERROR_STATUS_REGISTER, ACKER, 4, 1) + FIELD(ERROR_STATUS_REGISTER, BERR, 3, 1) + FIELD(ERROR_STATUS_REGISTER, STER, 2, 1) + FIELD(ERROR_STATUS_REGISTER, FMER, 1, 1) + FIELD(ERROR_STATUS_REGISTER, CRCER, 0, 1) +REG32(STATUS_REGISTER, 0x18) + FIELD(STATUS_REGISTER, SNOOP, 12, 1) + FIELD(STATUS_REGISTER, ACFBSY, 11, 1) + FIELD(STATUS_REGISTER, TXFLL, 10, 1) + FIELD(STATUS_REGISTER, TXBFLL, 9, 1) + FIELD(STATUS_REGISTER, ESTAT, 7, 2) + FIELD(STATUS_REGISTER, ERRWRN, 6, 1) + FIELD(STATUS_REGISTER, BBSY, 5, 1) + FIELD(STATUS_REGISTER, BIDLE, 4, 1) + FIELD(STATUS_REGISTER, NORMAL, 3, 1) + FIELD(STATUS_REGISTER, SLEEP, 2, 1) + FIELD(STATUS_REGISTER, LBACK, 1, 1) + FIELD(STATUS_REGISTER, CONFIG, 0, 1) +REG32(INTERRUPT_STATUS_REGISTER, 0x1c) + FIELD(INTERRUPT_STATUS_REGISTER, TXFEMP, 14, 1) + FIELD(INTERRUPT_STATUS_REGISTER, TXFWMEMP, 13, 1) + FIELD(INTERRUPT_STATUS_REGISTER, RXFWMFLL, 12, 1) + FIELD(INTERRUPT_STATUS_REGISTER, WKUP, 11, 1) + FIELD(INTERRUPT_STATUS_REGISTER, SLP, 10, 1) + FIELD(INTERRUPT_STATUS_REGISTER, BSOFF, 9, 1) + FIELD(INTERRUPT_STATUS_REGISTER, ERROR, 8, 1) + FIELD(INTERRUPT_STATUS_REGISTER, RXNEMP, 7, 1) + FIELD(INTERRUPT_STATUS_REGISTER, RXOFLW, 6, 1) + FIELD(INTERRUPT_STATUS_REGISTER, RXUFLW, 5, 1) + FIELD(INTERRUPT_STATUS_REGISTER, RXOK, 4, 1) + FIELD(INTERRUPT_STATUS_REGISTER, TXBFLL, 3, 1) + FIELD(INTERRUPT_STATUS_REGISTER, TXFLL, 2, 1) + FIELD(INTERRUPT_STATUS_REGISTER, TXOK, 1, 1) + FIELD(INTERRUPT_STATUS_REGISTER, ARBLST, 0, 1) +REG32(INTERRUPT_ENABLE_REGISTER, 0x20) + FIELD(INTERRUPT_ENABLE_REGISTER, ETXFEMP, 14, 1) + FIELD(INTERRUPT_ENABLE_REGISTER, ETXFWMEMP, 13, 1) + FIELD(INTERRUPT_ENABLE_REGISTER, ERXFWMFLL, 12, 1) + FIELD(INTERRUPT_ENABLE_REGISTER, EWKUP, 11, 1) + FIELD(INTERRUPT_ENABLE_REGISTER, ESLP, 10, 1) + FIELD(INTERRUPT_ENABLE_REGISTER, EBSOFF, 9, 1) + FIELD(INTERRUPT_ENABLE_REGISTER, EERROR, 8, 1) + FIELD(INTERRUPT_ENABLE_REGISTER, ERXNEMP, 7, 1) + FIELD(INTERRUPT_ENABLE_REGISTER, ERXOFLW, 6, 1) + FIELD(INTERRUPT_ENABLE_REGISTER, ERXUFLW, 5, 1) + FIELD(INTERRUPT_ENABLE_REGISTER, ERXOK, 4, 1) + FIELD(INTERRUPT_ENABLE_REGISTER, ETXBFLL, 3, 1) + FIELD(INTERRUPT_ENABLE_REGISTER, ETXFLL, 2, 1) + FIELD(INTERRUPT_ENABLE_REGISTER, ETXOK, 1, 1) + FIELD(INTERRUPT_ENABLE_REGISTER, EARBLST, 0, 1) +REG32(INTERRUPT_CLEAR_REGISTER, 0x24) + FIELD(INTERRUPT_CLEAR_REGISTER, CTXFEMP, 14, 1) + FIELD(INTERRUPT_CLEAR_REGISTER, CTXFWMEMP, 13, 1) + FIELD(INTERRUPT_CLEAR_REGISTER, CRXFWMFLL, 12, 1) + FIELD(INTERRUPT_CLEAR_REGISTER, CWKUP, 11, 1) + FIELD(INTERRUPT_CLEAR_REGISTER, CSLP, 10, 1) + FIELD(INTERRUPT_CLEAR_REGISTER, CBSOFF, 9, 1) + FIELD(INTERRUPT_CLEAR_REGISTER, CERROR, 8, 1) + FIELD(INTERRUPT_CLEAR_REGISTER, CRXNEMP, 7, 1) + FIELD(INTERRUPT_CLEAR_REGISTER, CRXOFLW, 6, 1) + FIELD(INTERRUPT_CLEAR_REGISTER, CRXUFLW, 5, 1) + FIELD(INTERRUPT_CLEAR_REGISTER, CRXOK, 4, 1) + FIELD(INTERRUPT_CLEAR_REGISTER, CTXBFLL, 3, 1) + FIELD(INTERRUPT_CLEAR_REGISTER, CTXFLL, 2, 1) + FIELD(INTERRUPT_CLEAR_REGISTER, CTXOK, 1, 1) + FIELD(INTERRUPT_CLEAR_REGISTER, CARBLST, 0, 1) +REG32(TIMESTAMP_REGISTER, 0x28) + FIELD(TIMESTAMP_REGISTER, CTS, 0, 1) +REG32(WIR, 0x2c) + FIELD(WIR, EW, 8, 8) + FIELD(WIR, FW, 0, 8) +REG32(TXFIFO_ID, 0x30) + FIELD(TXFIFO_ID, IDH, 21, 11) + FIELD(TXFIFO_ID, SRRRTR, 20, 1) + FIELD(TXFIFO_ID, IDE, 19, 1) + FIELD(TXFIFO_ID, IDL, 1, 18) + FIELD(TXFIFO_ID, RTR, 0, 1) +REG32(TXFIFO_DLC, 0x34) + FIELD(TXFIFO_DLC, DLC, 28, 4) +REG32(TXFIFO_DATA1, 0x38) + FIELD(TXFIFO_DATA1, DB0, 24, 8) + FIELD(TXFIFO_DATA1, DB1, 16, 8) + FIELD(TXFIFO_DATA1, DB2, 8, 8) + FIELD(TXFIFO_DATA1, DB3, 0, 8) +REG32(TXFIFO_DATA2, 0x3c) + FIELD(TXFIFO_DATA2, DB4, 24, 8) + FIELD(TXFIFO_DATA2, DB5, 16, 8) + FIELD(TXFIFO_DATA2, DB6, 8, 8) + FIELD(TXFIFO_DATA2, DB7, 0, 8) +REG32(TXHPB_ID, 0x40) + FIELD(TXHPB_ID, IDH, 21, 11) + FIELD(TXHPB_ID, SRRRTR, 20, 1) + FIELD(TXHPB_ID, IDE, 19, 1) + FIELD(TXHPB_ID, IDL, 1, 18) + FIELD(TXHPB_ID, RTR, 0, 1) +REG32(TXHPB_DLC, 0x44) + FIELD(TXHPB_DLC, DLC, 28, 4) +REG32(TXHPB_DATA1, 0x48) + FIELD(TXHPB_DATA1, DB0, 24, 8) + FIELD(TXHPB_DATA1, DB1, 16, 8) + FIELD(TXHPB_DATA1, DB2, 8, 8) + FIELD(TXHPB_DATA1, DB3, 0, 8) +REG32(TXHPB_DATA2, 0x4c) + FIELD(TXHPB_DATA2, DB4, 24, 8) + FIELD(TXHPB_DATA2, DB5, 16, 8) + FIELD(TXHPB_DATA2, DB6, 8, 8) + FIELD(TXHPB_DATA2, DB7, 0, 8) +REG32(RXFIFO_ID, 0x50) + FIELD(RXFIFO_ID, IDH, 21, 11) + FIELD(RXFIFO_ID, SRRRTR, 20, 1) + FIELD(RXFIFO_ID, IDE, 19, 1) + FIELD(RXFIFO_ID, IDL, 1, 18) + FIELD(RXFIFO_ID, RTR, 0, 1) +REG32(RXFIFO_DLC, 0x54) + FIELD(RXFIFO_DLC, DLC, 28, 4) + FIELD(RXFIFO_DLC, RXT, 0, 16) +REG32(RXFIFO_DATA1, 0x58) + FIELD(RXFIFO_DATA1, DB0, 24, 8) + FIELD(RXFIFO_DATA1, DB1, 16, 8) + FIELD(RXFIFO_DATA1, DB2, 8, 8) + FIELD(RXFIFO_DATA1, DB3, 0, 8) +REG32(RXFIFO_DATA2, 0x5c) + FIELD(RXFIFO_DATA2, DB4, 24, 8) + FIELD(RXFIFO_DATA2, DB5, 16, 8) + FIELD(RXFIFO_DATA2, DB6, 8, 8) + FIELD(RXFIFO_DATA2, DB7, 0, 8) +REG32(AFR, 0x60) + FIELD(AFR, UAF4, 3, 1) + FIELD(AFR, UAF3, 2, 1) + FIELD(AFR, UAF2, 1, 1) + FIELD(AFR, UAF1, 0, 1) +REG32(AFMR1, 0x64) + FIELD(AFMR1, AMIDH, 21, 11) + FIELD(AFMR1, AMSRR, 20, 1) + FIELD(AFMR1, AMIDE, 19, 1) + FIELD(AFMR1, AMIDL, 1, 18) + FIELD(AFMR1, AMRTR, 0, 1) +REG32(AFIR1, 0x68) + FIELD(AFIR1, AIIDH, 21, 11) + FIELD(AFIR1, AISRR, 20, 1) + FIELD(AFIR1, AIIDE, 19, 1) + FIELD(AFIR1, AIIDL, 1, 18) + FIELD(AFIR1, AIRTR, 0, 1) +REG32(AFMR2, 0x6c) + FIELD(AFMR2, AMIDH, 21, 11) + FIELD(AFMR2, AMSRR, 20, 1) + FIELD(AFMR2, AMIDE, 19, 1) + FIELD(AFMR2, AMIDL, 1, 18) + FIELD(AFMR2, AMRTR, 0, 1) +REG32(AFIR2, 0x70) + FIELD(AFIR2, AIIDH, 21, 11) + FIELD(AFIR2, AISRR, 20, 1) + FIELD(AFIR2, AIIDE, 19, 1) + FIELD(AFIR2, AIIDL, 1, 18) + FIELD(AFIR2, AIRTR, 0, 1) +REG32(AFMR3, 0x74) + FIELD(AFMR3, AMIDH, 21, 11) + FIELD(AFMR3, AMSRR, 20, 1) + FIELD(AFMR3, AMIDE, 19, 1) + FIELD(AFMR3, AMIDL, 1, 18) + FIELD(AFMR3, AMRTR, 0, 1) +REG32(AFIR3, 0x78) + FIELD(AFIR3, AIIDH, 21, 11) + FIELD(AFIR3, AISRR, 20, 1) + FIELD(AFIR3, AIIDE, 19, 1) + FIELD(AFIR3, AIIDL, 1, 18) + FIELD(AFIR3, AIRTR, 0, 1) +REG32(AFMR4, 0x7c) + FIELD(AFMR4, AMIDH, 21, 11) + FIELD(AFMR4, AMSRR, 20, 1) + FIELD(AFMR4, AMIDE, 19, 1) + FIELD(AFMR4, AMIDL, 1, 18) + FIELD(AFMR4, AMRTR, 0, 1) +REG32(AFIR4, 0x80) + FIELD(AFIR4, AIIDH, 21, 11) + FIELD(AFIR4, AISRR, 20, 1) + FIELD(AFIR4, AIIDE, 19, 1) + FIELD(AFIR4, AIIDL, 1, 18) + FIELD(AFIR4, AIRTR, 0, 1) + +static void can_update_irq(XlnxZynqMPCANState *s) +{ + uint32_t irq; + + /* Watermark register interrupts. */ + if ((fifo32_num_free(&s->tx_fifo) / CAN_FRAME_SIZE) > + ARRAY_FIELD_EX32(s->regs, WIR, EW)) { + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXFWMEMP, 1); + } + + if ((fifo32_num_used(&s->rx_fifo) / CAN_FRAME_SIZE) > + ARRAY_FIELD_EX32(s->regs, WIR, FW)) { + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFWMFLL, 1); + } + + /* RX Interrupts. */ + if (fifo32_num_used(&s->rx_fifo) >=3D CAN_FRAME_SIZE) { + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXNEMP, 1); + } + + /* TX interrupts. */ + if (fifo32_is_empty(&s->tx_fifo)) { + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXFEMP, 1); + } + + if (fifo32_is_full(&s->tx_fifo)) { + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXFLL, 1); + } + + if (fifo32_is_full(&s->txhpb_fifo)) { + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXBFLL, 1); + } + + irq =3D s->regs[R_INTERRUPT_STATUS_REGISTER]; + irq &=3D s->regs[R_INTERRUPT_ENABLE_REGISTER]; + + trace_xlnx_can_update_irq(s->regs[R_INTERRUPT_STATUS_REGISTER], + s->regs[R_INTERRUPT_ENABLE_REGISTER], irq); + qemu_set_irq(s->irq, irq); +} + +static void can_ier_post_write(RegisterInfo *reg, uint64_t val) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(reg->opaque); + + can_update_irq(s); +} + +static uint64_t can_icr_pre_write(RegisterInfo *reg, uint64_t val) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(reg->opaque); + + s->regs[R_INTERRUPT_STATUS_REGISTER] &=3D ~val; + can_update_irq(s); + + return 0; +} + +static void can_config_reset(XlnxZynqMPCANState *s) +{ + /* Reset all the configuration registers. */ + register_reset(&s->reg_info[R_SOFTWARE_RESET_REGISTER]); + register_reset(&s->reg_info[R_MODE_SELECT_REGISTER]); + register_reset( + &s->reg_info[R_ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTE= R]); + register_reset(&s->reg_info[R_ARBITRATION_PHASE_BIT_TIMING_REGISTER]); + register_reset(&s->reg_info[R_STATUS_REGISTER]); + register_reset(&s->reg_info[R_INTERRUPT_STATUS_REGISTER]); + register_reset(&s->reg_info[R_INTERRUPT_ENABLE_REGISTER]); + register_reset(&s->reg_info[R_INTERRUPT_CLEAR_REGISTER]); + register_reset(&s->reg_info[R_WIR]); +} + +static void can_config_mode(XlnxZynqMPCANState *s) +{ + register_reset(&s->reg_info[R_ERROR_COUNTER_REGISTER]); + register_reset(&s->reg_info[R_ERROR_STATUS_REGISTER]); + + /* Put XlnxZynqMPCAN in configuration mode. */ + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 1); + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, WKUP, 0); + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, SLP, 0); + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, BSOFF, 0); + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, ERROR, 0); + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOFLW, 0); + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 0); + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXOK, 0); + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, ARBLST, 0); + + can_update_irq(s); +} + +static void update_status_register_mode_bits(XlnxZynqMPCANState *s) +{ + bool sleep_status =3D ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP= ); + bool sleep_mode =3D ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SL= EEP); + /* Wake up interrupt bit. */ + bool wakeup_irq_val =3D sleep_status && (sleep_mode =3D=3D 0); + /* Sleep interrupt bit. */ + bool sleep_irq_val =3D sleep_mode && (sleep_status =3D=3D 0); + + /* Clear previous core mode status bits. */ + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 0); + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 0); + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 0); + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 0); + + /* set current mode bit and generate irqs accordingly. */ + if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, LBACK)) { + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 1); + } else if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SLEEP)) { + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 1); + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, SLP, + sleep_irq_val); + } else if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SNOOP)) { + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 1); + } else { + /* + * If all bits are zero then XlnxZynqMPCAN is set in normal mode. + */ + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 1); + /* Set wakeup interrupt bit. */ + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, WKUP, + wakeup_irq_val); + } + + can_update_irq(s); +} + +static void can_exit_sleep_mode(XlnxZynqMPCANState *s) +{ + ARRAY_FIELD_DP32(s->regs, MODE_SELECT_REGISTER, SLEEP, 0); + update_status_register_mode_bits(s); +} + +static void generate_frame(qemu_can_frame *frame, uint32_t *data) +{ + frame->can_id =3D data[0]; + frame->can_dlc =3D FIELD_EX32(data[1], TXFIFO_DLC, DLC); + + frame->data[0] =3D FIELD_EX32(data[2], TXFIFO_DATA1, DB3); + frame->data[1] =3D FIELD_EX32(data[2], TXFIFO_DATA1, DB2); + frame->data[2] =3D FIELD_EX32(data[2], TXFIFO_DATA1, DB1); + frame->data[3] =3D FIELD_EX32(data[2], TXFIFO_DATA1, DB0); + + frame->data[4] =3D FIELD_EX32(data[3], TXFIFO_DATA2, DB7); + frame->data[5] =3D FIELD_EX32(data[3], TXFIFO_DATA2, DB6); + frame->data[6] =3D FIELD_EX32(data[3], TXFIFO_DATA2, DB5); + frame->data[7] =3D FIELD_EX32(data[3], TXFIFO_DATA2, DB4); +} + +static bool tx_ready_check(XlnxZynqMPCANState *s) +{ + if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, SRST)) { + g_autofree char *path =3D object_get_canonical_path(OBJECT(s)); + + qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer data wh= ile" + " data while controller is in reset mode.\n", + path); + return false; + } + + if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) =3D=3D 0) { + g_autofree char *path =3D object_get_canonical_path(OBJECT(s)); + + qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer" + " data while controller is in configuration mode. Re= set" + " the core so operations can start fresh.\n", + path); + return false; + } + + if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SNOOP)) { + g_autofree char *path =3D object_get_canonical_path(OBJECT(s)); + + qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer" + " data while controller is in SNOOP MODE.\n", + path); + return false; + } + + return true; +} + +static void transfer_fifo(XlnxZynqMPCANState *s, Fifo32 *fifo) +{ + qemu_can_frame frame; + uint32_t data[CAN_FRAME_SIZE]; + int i; + bool can_tx =3D tx_ready_check(s); + + if (!can_tx) { + g_autofree char *path =3D object_get_canonical_path(OBJECT(s)); + + qemu_log_mask(LOG_GUEST_ERROR, "%s: Controller is not enabled for = data" + " transfer.\n", path); + can_update_irq(s); + return; + } + + while (!fifo32_is_empty(fifo)) { + for (i =3D 0; i < CAN_FRAME_SIZE; i++) { + data[i] =3D fifo32_pop(fifo); + } + + if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, LBACK)) { + /* + * Controller is in loopback. In Loopback mode, the CAN core + * transmits a recessive bitstream on to the XlnxZynqMPCAN Bus. + * Any message transmitted is looped back to the RX line and + * acknowledged. The XlnxZynqMPCAN core receives any message + * that it transmits. + */ + if (fifo32_is_full(&s->rx_fifo)) { + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOFL= W, 1); + } else { + for (i =3D 0; i < CAN_FRAME_SIZE; i++) { + fifo32_push(&s->rx_fifo, data[i]); + } + + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK,= 1); + } + } else { + /* Normal mode Tx. */ + generate_frame(&frame, data); + + trace_xlnx_can_tx_data(frame.can_id, frame.can_dlc, + frame.data[0], frame.data[1], + frame.data[2], frame.data[3], + frame.data[4], frame.data[5], + frame.data[6], frame.data[7]); + can_bus_client_send(&s->bus_client, &frame, 1); + } + } + + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXOK, 1); + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, TXBFLL, 0); + + if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP)) { + can_exit_sleep_mode(s); + } + + can_update_irq(s); +} + +static uint64_t can_srr_pre_write(RegisterInfo *reg, uint64_t val) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(reg->opaque); + + ARRAY_FIELD_DP32(s->regs, SOFTWARE_RESET_REGISTER, CEN, + FIELD_EX32(val, SOFTWARE_RESET_REGISTER, CEN)); + + if (FIELD_EX32(val, SOFTWARE_RESET_REGISTER, SRST)) { + trace_xlnx_can_reset(val); + + /* First, core will do software reset then will enter in config mo= de. */ + can_config_reset(s); + } + + if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) =3D=3D 0) { + can_config_mode(s); + } else { + /* + * Leave config mode. Now XlnxZynqMPCAN core will enter normal, + * sleep, snoop or loopback mode depending upon LBACK, SLEEP, SNOOP + * register states. + */ + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 0); + + ptimer_transaction_begin(s->can_timer); + ptimer_set_count(s->can_timer, 0); + ptimer_transaction_commit(s->can_timer); + + /* XlnxZynqMPCAN is out of config mode. It will send pending data.= */ + transfer_fifo(s, &s->txhpb_fifo); + transfer_fifo(s, &s->tx_fifo); + } + + update_status_register_mode_bits(s); + + return s->regs[R_SOFTWARE_RESET_REGISTER]; +} + +static uint64_t can_msr_pre_write(RegisterInfo *reg, uint64_t val) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(reg->opaque); + uint8_t multi_mode; + + /* + * Multiple mode set check. This is done to make sure user doesn't set + * multiple modes. + */ + multi_mode =3D FIELD_EX32(val, MODE_SELECT_REGISTER, LBACK) + + FIELD_EX32(val, MODE_SELECT_REGISTER, SLEEP) + + FIELD_EX32(val, MODE_SELECT_REGISTER, SNOOP); + + if (multi_mode > 1) { + g_autofree char *path =3D object_get_canonical_path(OBJECT(s)); + + qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to config" + " several modes simultaneously. One mode will be sel= ected" + " according to their priority: LBACK > SLEEP > SNOOP= .\n", + path); + } + + if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) =3D=3D 0) { + /* We are in configuration mode, any mode can be selected. */ + s->regs[R_MODE_SELECT_REGISTER] =3D val; + } else { + bool sleep_mode_bit =3D FIELD_EX32(val, MODE_SELECT_REGISTER, SLEE= P); + + ARRAY_FIELD_DP32(s->regs, MODE_SELECT_REGISTER, SLEEP, sleep_mode_= bit); + + if (FIELD_EX32(val, MODE_SELECT_REGISTER, LBACK)) { + g_autofree char *path =3D object_get_canonical_path(OBJECT(s)); + + qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to set" + " LBACK mode without setting CEN bit as 0.\n", + path); + } else if (FIELD_EX32(val, MODE_SELECT_REGISTER, SNOOP)) { + g_autofree char *path =3D object_get_canonical_path(OBJECT(s)); + + qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to set" + " SNOOP mode without setting CEN bit as 0.\n", + path); + } + + update_status_register_mode_bits(s); + } + + return s->regs[R_MODE_SELECT_REGISTER]; +} + +static uint64_t can_brpr_pre_write(RegisterInfo *reg, uint64_t val) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(reg->opaque); + + /* Only allow writes when in config mode. */ + if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) { + return s->regs[R_ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER]; + } + + return val; +} + +static uint64_t can_btr_pre_write(RegisterInfo *reg, uint64_t val) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(reg->opaque); + + /* Only allow writes when in config mode. */ + if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) { + return s->regs[R_ARBITRATION_PHASE_BIT_TIMING_REGISTER]; + } + + return val; +} + +static uint64_t can_tcr_pre_write(RegisterInfo *reg, uint64_t val) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(reg->opaque); + + if (FIELD_EX32(val, TIMESTAMP_REGISTER, CTS)) { + ptimer_transaction_begin(s->can_timer); + ptimer_set_count(s->can_timer, 0); + ptimer_transaction_commit(s->can_timer); + } + + return 0; +} + +static void update_rx_fifo(XlnxZynqMPCANState *s, const qemu_can_frame *fr= ame) +{ + bool filter_pass =3D false; + uint16_t timestamp =3D 0; + + /* If no filter is enabled. Message will be stored in FIFO. */ + if (!((ARRAY_FIELD_EX32(s->regs, AFR, UAF1)) | + (ARRAY_FIELD_EX32(s->regs, AFR, UAF2)) | + (ARRAY_FIELD_EX32(s->regs, AFR, UAF3)) | + (ARRAY_FIELD_EX32(s->regs, AFR, UAF4)))) { + filter_pass =3D true; + } + + /* + * Messages that pass any of the acceptance filters will be stored in + * the RX FIFO. + */ + if (ARRAY_FIELD_EX32(s->regs, AFR, UAF1)) { + uint32_t id_masked =3D s->regs[R_AFMR1] & frame->can_id; + uint32_t filter_id_masked =3D s->regs[R_AFMR1] & s->regs[R_AFIR1]; + + if (filter_id_masked =3D=3D id_masked) { + filter_pass =3D true; + } + } + + if (ARRAY_FIELD_EX32(s->regs, AFR, UAF2)) { + uint32_t id_masked =3D s->regs[R_AFMR2] & frame->can_id; + uint32_t filter_id_masked =3D s->regs[R_AFMR2] & s->regs[R_AFIR2]; + + if (filter_id_masked =3D=3D id_masked) { + filter_pass =3D true; + } + } + + if (ARRAY_FIELD_EX32(s->regs, AFR, UAF3)) { + uint32_t id_masked =3D s->regs[R_AFMR3] & frame->can_id; + uint32_t filter_id_masked =3D s->regs[R_AFMR3] & s->regs[R_AFIR3]; + + if (filter_id_masked =3D=3D id_masked) { + filter_pass =3D true; + } + } + + if (ARRAY_FIELD_EX32(s->regs, AFR, UAF4)) { + uint32_t id_masked =3D s->regs[R_AFMR4] & frame->can_id; + uint32_t filter_id_masked =3D s->regs[R_AFMR4] & s->regs[R_AFIR4]; + + if (filter_id_masked =3D=3D id_masked) { + filter_pass =3D true; + } + } + + if (!filter_pass) { + trace_xlnx_can_rx_fifo_filter_reject(frame->can_id, frame->can_dlc= ); + return; + } + + /* Store the message in fifo if it passed through any of the filters. = */ + if (filter_pass && frame->can_dlc <=3D MAX_DLC) { + + if (fifo32_is_full(&s->rx_fifo)) { + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOFLW, 1= ); + } else { + timestamp =3D CAN_TIMER_MAX - ptimer_get_count(s->can_timer); + + fifo32_push(&s->rx_fifo, frame->can_id); + + fifo32_push(&s->rx_fifo, deposit32(0, R_RXFIFO_DLC_DLC_SHIFT, + R_RXFIFO_DLC_DLC_LENGTH, + frame->can_dlc) | + deposit32(0, R_RXFIFO_DLC_RXT_SHIFT, + R_RXFIFO_DLC_RXT_LENGTH, + timestamp)); + + /* First 32 bit of the data. */ + fifo32_push(&s->rx_fifo, deposit32(0, R_TXFIFO_DATA1_DB3_SHIFT, + R_TXFIFO_DATA1_DB3_LENGTH, + frame->data[0]) | + deposit32(0, R_TXFIFO_DATA1_DB2_SHIFT, + R_TXFIFO_DATA1_DB2_LENGTH, + frame->data[1]) | + deposit32(0, R_TXFIFO_DATA1_DB1_SHIFT, + R_TXFIFO_DATA1_DB1_LENGTH, + frame->data[2]) | + deposit32(0, R_TXFIFO_DATA1_DB0_SHIFT, + R_TXFIFO_DATA1_DB0_LENGTH, + frame->data[3])); + /* Last 32 bit of the data. */ + fifo32_push(&s->rx_fifo, deposit32(0, R_TXFIFO_DATA2_DB7_SHIFT, + R_TXFIFO_DATA2_DB7_LENGTH, + frame->data[4]) | + deposit32(0, R_TXFIFO_DATA2_DB6_SHIFT, + R_TXFIFO_DATA2_DB6_LENGTH, + frame->data[5]) | + deposit32(0, R_TXFIFO_DATA2_DB5_SHIFT, + R_TXFIFO_DATA2_DB5_LENGTH, + frame->data[6]) | + deposit32(0, R_TXFIFO_DATA2_DB4_SHIFT, + R_TXFIFO_DATA2_DB4_LENGTH, + frame->data[7])); + + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1); + trace_xlnx_can_rx_data(frame->can_id, frame->can_dlc, + frame->data[0], frame->data[1], + frame->data[2], frame->data[3], + frame->data[4], frame->data[5], + frame->data[6], frame->data[7]); + } + + can_update_irq(s); + } +} + +static uint64_t can_rxfifo_pre_read(RegisterInfo *reg, uint64_t val) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(reg->opaque); + + if (!fifo32_is_empty(&s->rx_fifo)) { + val =3D fifo32_pop(&s->rx_fifo); + } else { + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXUFLW, 1); + } + + can_update_irq(s); + return val; +} + +static void can_filter_enable_post_write(RegisterInfo *reg, uint64_t val) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(reg->opaque); + + if (ARRAY_FIELD_EX32(s->regs, AFR, UAF1) && + ARRAY_FIELD_EX32(s->regs, AFR, UAF2) && + ARRAY_FIELD_EX32(s->regs, AFR, UAF3) && + ARRAY_FIELD_EX32(s->regs, AFR, UAF4)) { + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, ACFBSY, 1); + } else { + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, ACFBSY, 0); + } +} + +static uint64_t can_filter_mask_pre_write(RegisterInfo *reg, uint64_t val) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(reg->opaque); + uint32_t reg_idx =3D (reg->access->addr) / 4; + uint32_t filter_number =3D (reg_idx - R_AFMR1) / 2; + + /* modify an acceptance filter, the corresponding UAF bit should be '0= '. */ + if (!(s->regs[R_AFR] & (1 << filter_number))) { + s->regs[reg_idx] =3D val; + + trace_xlnx_can_filter_mask_pre_write(filter_number, s->regs[reg_id= x]); + } else { + g_autofree char *path =3D object_get_canonical_path(OBJECT(s)); + + qemu_log_mask(LOG_GUEST_ERROR, "%s: Acceptance filter %d" + " mask is not set as corresponding UAF bit is not 0.= \n", + path, filter_number + 1); + } + + return s->regs[reg_idx]; +} + +static uint64_t can_filter_id_pre_write(RegisterInfo *reg, uint64_t val) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(reg->opaque); + uint32_t reg_idx =3D (reg->access->addr) / 4; + uint32_t filter_number =3D (reg_idx - R_AFIR1) / 2; + + if (!(s->regs[R_AFR] & (1 << filter_number))) { + s->regs[reg_idx] =3D val; + + trace_xlnx_can_filter_id_pre_write(filter_number, s->regs[reg_idx]= ); + } else { + g_autofree char *path =3D object_get_canonical_path(OBJECT(s)); + + qemu_log_mask(LOG_GUEST_ERROR, "%s: Acceptance filter %d" + " id is not set as corresponding UAF bit is not 0.\n= ", + path, filter_number + 1); + } + + return s->regs[reg_idx]; +} + +static void can_tx_post_write(RegisterInfo *reg, uint64_t val) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(reg->opaque); + + bool is_txhpb =3D reg->access->addr > A_TXFIFO_DATA2; + + bool initiate_transfer =3D (reg->access->addr =3D=3D A_TXFIFO_DATA2) || + (reg->access->addr =3D=3D A_TXHPB_DATA2); + + Fifo32 *f =3D is_txhpb ? &s->txhpb_fifo : &s->tx_fifo; + + if (!fifo32_is_full(f)) { + fifo32_push(f, val); + } else { + g_autofree char *path =3D object_get_canonical_path(OBJECT(s)); + + qemu_log_mask(LOG_GUEST_ERROR, "%s: TX FIFO is full.\n", path); + } + + /* Initiate the message send if TX register is written. */ + if (initiate_transfer && + ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) { + transfer_fifo(s, f); + } + + can_update_irq(s); +} + +static const RegisterAccessInfo can_regs_info[] =3D { + { .name =3D "SOFTWARE_RESET_REGISTER", + .addr =3D A_SOFTWARE_RESET_REGISTER, + .rsvd =3D 0xfffffffc, + .pre_write =3D can_srr_pre_write, + },{ .name =3D "MODE_SELECT_REGISTER", + .addr =3D A_MODE_SELECT_REGISTER, + .rsvd =3D 0xfffffff8, + .pre_write =3D can_msr_pre_write, + },{ .name =3D "ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER", + .addr =3D A_ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, + .rsvd =3D 0xffffff00, + .pre_write =3D can_brpr_pre_write, + },{ .name =3D "ARBITRATION_PHASE_BIT_TIMING_REGISTER", + .addr =3D A_ARBITRATION_PHASE_BIT_TIMING_REGISTER, + .rsvd =3D 0xfffffe00, + .pre_write =3D can_btr_pre_write, + },{ .name =3D "ERROR_COUNTER_REGISTER", + .addr =3D A_ERROR_COUNTER_REGISTER, + .rsvd =3D 0xffff0000, + .ro =3D 0xffffffff, + },{ .name =3D "ERROR_STATUS_REGISTER", + .addr =3D A_ERROR_STATUS_REGISTER, + .rsvd =3D 0xffffffe0, + .w1c =3D 0x1f, + },{ .name =3D "STATUS_REGISTER", .addr =3D A_STATUS_REGISTER, + .reset =3D 0x1, + .rsvd =3D 0xffffe000, + .ro =3D 0x1fff, + },{ .name =3D "INTERRUPT_STATUS_REGISTER", + .addr =3D A_INTERRUPT_STATUS_REGISTER, + .reset =3D 0x6000, + .rsvd =3D 0xffff8000, + .ro =3D 0x7fff, + },{ .name =3D "INTERRUPT_ENABLE_REGISTER", + .addr =3D A_INTERRUPT_ENABLE_REGISTER, + .rsvd =3D 0xffff8000, + .post_write =3D can_ier_post_write, + },{ .name =3D "INTERRUPT_CLEAR_REGISTER", + .addr =3D A_INTERRUPT_CLEAR_REGISTER, + .rsvd =3D 0xffff8000, + .pre_write =3D can_icr_pre_write, + },{ .name =3D "TIMESTAMP_REGISTER", + .addr =3D A_TIMESTAMP_REGISTER, + .rsvd =3D 0xfffffffe, + .pre_write =3D can_tcr_pre_write, + },{ .name =3D "WIR", .addr =3D A_WIR, + .reset =3D 0x3f3f, + .rsvd =3D 0xffff0000, + },{ .name =3D "TXFIFO_ID", .addr =3D A_TXFIFO_ID, + .post_write =3D can_tx_post_write, + },{ .name =3D "TXFIFO_DLC", .addr =3D A_TXFIFO_DLC, + .rsvd =3D 0xfffffff, + .post_write =3D can_tx_post_write, + },{ .name =3D "TXFIFO_DATA1", .addr =3D A_TXFIFO_DATA1, + .post_write =3D can_tx_post_write, + },{ .name =3D "TXFIFO_DATA2", .addr =3D A_TXFIFO_DATA2, + .post_write =3D can_tx_post_write, + },{ .name =3D "TXHPB_ID", .addr =3D A_TXHPB_ID, + .post_write =3D can_tx_post_write, + },{ .name =3D "TXHPB_DLC", .addr =3D A_TXHPB_DLC, + .rsvd =3D 0xfffffff, + .post_write =3D can_tx_post_write, + },{ .name =3D "TXHPB_DATA1", .addr =3D A_TXHPB_DATA1, + .post_write =3D can_tx_post_write, + },{ .name =3D "TXHPB_DATA2", .addr =3D A_TXHPB_DATA2, + .post_write =3D can_tx_post_write, + },{ .name =3D "RXFIFO_ID", .addr =3D A_RXFIFO_ID, + .ro =3D 0xffffffff, + .post_read =3D can_rxfifo_pre_read, + },{ .name =3D "RXFIFO_DLC", .addr =3D A_RXFIFO_DLC, + .rsvd =3D 0xfff0000, + .post_read =3D can_rxfifo_pre_read, + },{ .name =3D "RXFIFO_DATA1", .addr =3D A_RXFIFO_DATA1, + .post_read =3D can_rxfifo_pre_read, + },{ .name =3D "RXFIFO_DATA2", .addr =3D A_RXFIFO_DATA2, + .post_read =3D can_rxfifo_pre_read, + },{ .name =3D "AFR", .addr =3D A_AFR, + .rsvd =3D 0xfffffff0, + .post_write =3D can_filter_enable_post_write, + },{ .name =3D "AFMR1", .addr =3D A_AFMR1, + .pre_write =3D can_filter_mask_pre_write, + },{ .name =3D "AFIR1", .addr =3D A_AFIR1, + .pre_write =3D can_filter_id_pre_write, + },{ .name =3D "AFMR2", .addr =3D A_AFMR2, + .pre_write =3D can_filter_mask_pre_write, + },{ .name =3D "AFIR2", .addr =3D A_AFIR2, + .pre_write =3D can_filter_id_pre_write, + },{ .name =3D "AFMR3", .addr =3D A_AFMR3, + .pre_write =3D can_filter_mask_pre_write, + },{ .name =3D "AFIR3", .addr =3D A_AFIR3, + .pre_write =3D can_filter_id_pre_write, + },{ .name =3D "AFMR4", .addr =3D A_AFMR4, + .pre_write =3D can_filter_mask_pre_write, + },{ .name =3D "AFIR4", .addr =3D A_AFIR4, + .pre_write =3D can_filter_id_pre_write, + } +}; + +static void xlnx_zynqmp_can_ptimer_cb(void *opaque) +{ + /* No action required on the timer rollover. */ +} + +static const MemoryRegionOps can_ops =3D { + .read =3D register_read_memory, + .write =3D register_write_memory, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +static void xlnx_zynqmp_can_reset_init(Object *obj, ResetType type) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(obj); + unsigned int i; + + for (i =3D R_RXFIFO_ID; i < ARRAY_SIZE(s->reg_info); ++i) { + register_reset(&s->reg_info[i]); + } + + ptimer_transaction_begin(s->can_timer); + ptimer_set_count(s->can_timer, 0); + ptimer_transaction_commit(s->can_timer); +} + +static void xlnx_zynqmp_can_reset_hold(Object *obj) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(obj); + unsigned int i; + + for (i =3D 0; i < R_RXFIFO_ID; ++i) { + register_reset(&s->reg_info[i]); + } + + /* + * Reset FIFOs when CAN model is reset. This will clear the fifo writes + * done by post_write which gets called from register_reset function, + * post_write handle will not be able to trigger tx because CAN will be + * disabled when software_reset_register is cleared first. + */ + fifo32_reset(&s->rx_fifo); + fifo32_reset(&s->tx_fifo); + fifo32_reset(&s->txhpb_fifo); +} + +static bool xlnx_zynqmp_can_can_receive(CanBusClientState *client) +{ + XlnxZynqMPCANState *s =3D container_of(client, XlnxZynqMPCANState, + bus_client); + + if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, SRST)) { + g_autofree char *path =3D object_get_canonical_path(OBJECT(s)); + + qemu_log_mask(LOG_GUEST_ERROR, "%s: Controller is in reset state.\= n", + path); + return false; + } + + if ((ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) =3D=3D 0= ) { + g_autofree char *path =3D object_get_canonical_path(OBJECT(s)); + + qemu_log_mask(LOG_GUEST_ERROR, "%s: Controller is disabled. Incomi= ng" + " messages will be discarded.\n", path); + return false; + } + + return true; +} + +static ssize_t xlnx_zynqmp_can_receive(CanBusClientState *client, + const qemu_can_frame *buf, size_t buf_size)= { + XlnxZynqMPCANState *s =3D container_of(client, XlnxZynqMPCANState, + bus_client); + const qemu_can_frame *frame =3D buf; + + if (buf_size <=3D 0) { + g_autofree char *path =3D object_get_canonical_path(OBJECT(s)); + + qemu_log_mask(LOG_GUEST_ERROR, "%s: Error in the data received.\n", + path); + return 0; + } + + if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SNOOP)) { + /* Snoop Mode: Just keep the data. no response back. */ + update_rx_fifo(s, frame); + } else if ((ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP))) { + /* + * XlnxZynqMPCAN is in sleep mode. Any data on bus will bring it t= o wake + * up state. + */ + can_exit_sleep_mode(s); + update_rx_fifo(s, frame); + } else if ((ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP)) =3D=3D = 0) { + update_rx_fifo(s, frame); + } else { + /* + * XlnxZynqMPCAN will not participate in normal bus communication + * and will not receive any messages transmitted by other CAN node= s. + */ + trace_xlnx_can_rx_discard(s->regs[R_STATUS_REGISTER]); + } + + return 1; +} + +static CanBusClientInfo can_xilinx_bus_client_info =3D { + .can_receive =3D xlnx_zynqmp_can_can_receive, + .receive =3D xlnx_zynqmp_can_receive, +}; + +static int xlnx_zynqmp_can_connect_to_bus(XlnxZynqMPCANState *s, + CanBusState *bus) +{ + s->bus_client.info =3D &can_xilinx_bus_client_info; + + if (can_bus_insert_client(bus, &s->bus_client) < 0) { + return -1; + } + return 0; +} + +static void xlnx_zynqmp_can_realize(DeviceState *dev, Error **errp) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(dev); + + if (s->canbus) { + if (xlnx_zynqmp_can_connect_to_bus(s, s->canbus) < 0) { + g_autofree char *path =3D object_get_canonical_path(OBJECT(s)); + + error_setg(errp, "%s: xlnx_zynqmp_can_connect_to_bus" + " failed.", path); + return; + } + } + + /* Create RX FIFO, TXFIFO, TXHPB storage. */ + fifo32_create(&s->rx_fifo, RXFIFO_SIZE); + fifo32_create(&s->tx_fifo, RXFIFO_SIZE); + fifo32_create(&s->txhpb_fifo, CAN_FRAME_SIZE); + + /* Allocate a new timer. */ + s->can_timer =3D ptimer_init(xlnx_zynqmp_can_ptimer_cb, s, + PTIMER_POLICY_DEFAULT); + + ptimer_transaction_begin(s->can_timer); + + ptimer_set_freq(s->can_timer, s->cfg.ext_clk_freq); + ptimer_set_limit(s->can_timer, CAN_TIMER_MAX, 1); + ptimer_run(s->can_timer, 0); + ptimer_transaction_commit(s->can_timer); +} + +static void xlnx_zynqmp_can_init(Object *obj) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + + RegisterInfoArray *reg_array; + + memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_CAN, + XLNX_ZYNQMP_CAN_R_MAX * 4); + reg_array =3D register_init_block32(DEVICE(obj), can_regs_info, + ARRAY_SIZE(can_regs_info), + s->reg_info, s->regs, + &can_ops, + XLNX_ZYNQMP_CAN_ERR_DEBUG, + XLNX_ZYNQMP_CAN_R_MAX * 4); + + memory_region_add_subregion(&s->iomem, 0x00, ®_array->mem); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); +} + +static const VMStateDescription vmstate_can =3D { + .name =3D TYPE_XLNX_ZYNQMP_CAN, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_FIFO32(rx_fifo, XlnxZynqMPCANState), + VMSTATE_FIFO32(tx_fifo, XlnxZynqMPCANState), + VMSTATE_FIFO32(txhpb_fifo, XlnxZynqMPCANState), + VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPCANState, XLNX_ZYNQMP_CAN_R_M= AX), + VMSTATE_PTIMER(can_timer, XlnxZynqMPCANState), + VMSTATE_END_OF_LIST(), + } +}; + +static Property xlnx_zynqmp_can_properties[] =3D { + DEFINE_PROP_UINT32("ext_clk_freq", XlnxZynqMPCANState, cfg.ext_clk_fre= q, + CAN_DEFAULT_CLOCK), + DEFINE_PROP_LINK("canbus", XlnxZynqMPCANState, canbus, TYPE_CAN_BUS, + CanBusState *), + DEFINE_PROP_END_OF_LIST(), +}; + +static void xlnx_zynqmp_can_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + rc->phases.enter =3D xlnx_zynqmp_can_reset_init; + rc->phases.hold =3D xlnx_zynqmp_can_reset_hold; + dc->realize =3D xlnx_zynqmp_can_realize; + device_class_set_props(dc, xlnx_zynqmp_can_properties); + dc->vmsd =3D &vmstate_can; +} + +static const TypeInfo can_info =3D { + .name =3D TYPE_XLNX_ZYNQMP_CAN, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(XlnxZynqMPCANState), + .class_init =3D xlnx_zynqmp_can_class_init, + .instance_init =3D xlnx_zynqmp_can_init, +}; + +static void can_register_types(void) +{ + type_register_static(&can_info); +} + +type_init(can_register_types) diff --git a/hw/Kconfig b/hw/Kconfig index 4de1797ffda..5ad3c6b5a4b 100644 --- a/hw/Kconfig +++ b/hw/Kconfig @@ -80,3 +80,4 @@ config XILINX_AXI config XLNX_ZYNQMP bool select REGISTER + select CAN_BUS diff --git a/hw/net/can/meson.build b/hw/net/can/meson.build index 714951f375a..8fabbd9ee68 100644 --- a/hw/net/can/meson.build +++ b/hw/net/can/meson.build @@ -4,3 +4,4 @@ softmmu_ss.add(when: 'CONFIG_CAN_PCI', if_true: files('can_= pcm3680_pci.c')) softmmu_ss.add(when: 'CONFIG_CAN_PCI', if_true: files('can_mioe3680_pci.c'= )) softmmu_ss.add(when: 'CONFIG_CAN_CTUCANFD', if_true: files('ctucan_core.c'= )) softmmu_ss.add(when: 'CONFIG_CAN_CTUCANFD_PCI', if_true: files('ctucan_pci= .c')) +softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP', if_true: files('xlnx-zynqmp-can= .c')) diff --git a/hw/net/can/trace-events b/hw/net/can/trace-events new file mode 100644 index 00000000000..8346a98ab5d --- /dev/null +++ b/hw/net/can/trace-events @@ -0,0 +1,9 @@ +# xlnx-zynqmp-can.c +xlnx_can_update_irq(uint32_t isr, uint32_t ier, uint32_t irq) "ISR: 0x%08x= IER: 0x%08x IRQ: 0x%08x" +xlnx_can_reset(uint32_t val) "Resetting controller with value =3D 0x%08x" +xlnx_can_rx_fifo_filter_reject(uint32_t id, uint8_t dlc) "Frame: ID: 0x%08= x DLC: 0x%02x" +xlnx_can_filter_id_pre_write(uint8_t filter_num, uint32_t value) "Filter%d= ID: 0x%08x" +xlnx_can_filter_mask_pre_write(uint8_t filter_num, uint32_t value) "Filter= %d MASK: 0x%08x" +xlnx_can_tx_data(uint32_t id, uint8_t dlc, uint8_t db0, uint8_t db1, uint8= _t db2, uint8_t db3, uint8_t db4, uint8_t db5, uint8_t db6, uint8_t db7) "F= rame: ID: 0x%08x DLC: 0x%02x DATA: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02= x 0x%02x 0x%02x" +xlnx_can_rx_data(uint32_t id, uint32_t dlc, uint8_t db0, uint8_t db1, uint= 8_t db2, uint8_t db3, uint8_t db4, uint8_t db5, uint8_t db6, uint8_t db7) "= Frame: ID: 0x%08x DLC: 0x%02x DATA: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%0= 2x 0x%02x 0x%02x" +xlnx_can_rx_discard(uint32_t status) "Controller is not enabled for bus co= mmunication. Status Register: 0x%08x" --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607601039; cv=none; d=zohomail.com; s=zohoarc; b=Q5d7XUQxXVyLxsX4CRC/JO05aKQto1V4xNajm0xGtWlpUGreQzxWZbcB+vu7+UGxqa4KaZa6Y60o9+Rsrkj2esdCJ5YJAxrgh2+AALTFkqaS8grxgrDS9OfzrupXe+aEk4FvDCYKBG0twGLONK9aIhhbMGikODk1hKbiGsubDNc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607601039; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=W2PjLxacECPQUW4eCpZKhew0wzGcffw3W4zjesTZu74=; b=DONNPBalDFE9KWfpJDt9XcT0Hgh7yn+MshVt4B7PRCQ2D3+F+lClel+I3s3poIqQ6aQym1a4qft56LKLgboqbkULGWCsuoM3sUuIwHXqc9uSJN6hxoqhSadUxopPeveJcjnSh7xdkV9LRo8pe/8b+lZ7+kVZuhgp69SLaPcBk2o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607601038974587.2250042994148; Thu, 10 Dec 2020 03:50:38 -0800 (PST) Received: from localhost ([::1]:36764 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKSz-0002zb-Md for importer@patchew.org; Thu, 10 Dec 2020 06:50:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51040) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKQh-0001If-58 for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:15 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:38378) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKQW-0006yE-GI for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:14 -0500 Received: by mail-wm1-x331.google.com with SMTP id g185so4989288wmf.3 for ; Thu, 10 Dec 2020 03:48:04 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=W2PjLxacECPQUW4eCpZKhew0wzGcffw3W4zjesTZu74=; b=lTHONRYc7x6DtgP3KHAgS7RSjJQmQKFd12HUTSMSwBigpNxbWLh+8tEaygbfhJLDXk kTxtJ7QutF8OGoeaj+7es6ClgtaPQWtwyrWFoVE6zZ5vKDlVasUeNlxnDjpZ1g7H+vdW nYuWL2Ke0wKJ5c+iZehtEvtbWSzAFxgCggu8mTpqthZ+KU18wdExTDs/8CVvKTBLIJPF QZxS2siOPG5uDYchGEb9qOWRLeZTSMIG2u43y35ugr9NQ5gtYsR600E9ykRChl4sTtOS aL8RgHa9diQ+A2sBHDD62Q0ZyQ8EXeHBcUHYTF3rKKT61tTTonAD2ZMfuM8gjwapjSBP 6egw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=W2PjLxacECPQUW4eCpZKhew0wzGcffw3W4zjesTZu74=; b=egYZ3u3YxZ436Um8HR9LW6hhFkABOVbc42TVlWLgt0C1cHzeU0A7G4qkL9GLooMRZu a70G/04n8UtJgWjMz9WYYyXv/pHDf/qm+e3VJ3BaFQQdBmSQv8Yz9NEymL4bqsTinrA5 J1LSTHu8GEi/z9TcAGOibUKr2R/jkSlwYt1CClOzDfIgmjEB6XmtPDRUFeCP03l/YO4l pbDpasXwjguFhPxbrF2rnteO+dh82uzLkonY6fl1cqdjkuN+Ht5YGSOiJkKg4G8Zb4fd 2TozbD9YsrcJj7C1tTXJvIX4gheptVi4Kk6ORzhKQCKjFtsvRIrEwgNyLzl94uVftEu4 BGfw== X-Gm-Message-State: AOAM532fb9mSwpcCurMISo391VBcnTmECzGYh5+39DQz7NHChN08pUpm JwlFuBpK6uk98WGe/fR9Putd07jtSfPbqQ== X-Google-Smtp-Source: ABdhPJz8roiIEqil9sxSi7Sq+49bvAXB0Q4YBxbimBbYYP/HGJP8dxtAVEvJ+YDjB93/YtP4CSLKkg== X-Received: by 2002:a1c:454:: with SMTP id 81mr7767405wme.178.1607600882830; Thu, 10 Dec 2020 03:48:02 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/36] xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllers Date: Thu, 10 Dec 2020 11:47:23 +0000 Message-Id: <20201210114756.16501-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Vikram Garhwal Connect CAN0 and CAN1 on the ZynqMP. Reviewed-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Vikram Garhwal Message-id: 1605728926-352690-3-git-send-email-fnu.vikram@xilinx.com Signed-off-by: Peter Maydell --- include/hw/arm/xlnx-zynqmp.h | 8 ++++++++ hw/arm/xlnx-zcu102.c | 20 ++++++++++++++++++++ hw/arm/xlnx-zynqmp.c | 34 ++++++++++++++++++++++++++++++++++ 3 files changed, 62 insertions(+) diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 567d0dba09b..6f45387a173 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -22,6 +22,7 @@ #include "hw/intc/arm_gic.h" #include "hw/net/cadence_gem.h" #include "hw/char/cadence_uart.h" +#include "hw/net/xlnx-zynqmp-can.h" #include "hw/ide/ahci.h" #include "hw/sd/sdhci.h" #include "hw/ssi/xilinx_spips.h" @@ -33,6 +34,7 @@ #include "hw/cpu/cluster.h" #include "target/arm/cpu.h" #include "qom/object.h" +#include "net/can_emu.h" =20 #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) @@ -41,6 +43,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) #define XLNX_ZYNQMP_NUM_RPU_CPUS 2 #define XLNX_ZYNQMP_NUM_GEMS 4 #define XLNX_ZYNQMP_NUM_UARTS 2 +#define XLNX_ZYNQMP_NUM_CAN 2 +#define XLNX_ZYNQMP_CAN_REF_CLK (24 * 1000 * 1000) #define XLNX_ZYNQMP_NUM_SDHCI 2 #define XLNX_ZYNQMP_NUM_SPIS 2 #define XLNX_ZYNQMP_NUM_GDMA_CH 8 @@ -92,6 +96,7 @@ struct XlnxZynqMPState { =20 CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS]; + XlnxZynqMPCANState can[XLNX_ZYNQMP_NUM_CAN]; SysbusAHCIState sata; SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI]; XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS]; @@ -112,6 +117,9 @@ struct XlnxZynqMPState { bool virt; /* Has the RPU subsystem? */ bool has_rpu; + + /* CAN bus. */ + CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN]; }; =20 #endif diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index ad7fff9697b..4ef0c516bfd 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -25,6 +25,7 @@ #include "sysemu/qtest.h" #include "sysemu/device_tree.h" #include "qom/object.h" +#include "net/can_emu.h" =20 struct XlnxZCU102 { MachineState parent_obj; @@ -34,6 +35,8 @@ struct XlnxZCU102 { bool secure; bool virt; =20 + CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN]; + struct arm_boot_info binfo; }; =20 @@ -125,6 +128,14 @@ static void xlnx_zcu102_init(MachineState *machine) object_property_set_bool(OBJECT(&s->soc), "virtualization", s->virt, &error_fatal); =20 + for (i =3D 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { + gchar *bus_name =3D g_strdup_printf("canbus%d", i); + + object_property_set_link(OBJECT(&s->soc), bus_name, + OBJECT(s->canbus[i]), &error_fatal); + g_free(bus_name); + } + qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); =20 /* Create and plug in the SD cards */ @@ -208,6 +219,15 @@ static void xlnx_zcu102_machine_instance_init(Object *= obj) s->secure =3D false; /* Default to virt (EL2) being disabled */ s->virt =3D false; + object_property_add_link(obj, "xlnx-zcu102.canbus0", TYPE_CAN_BUS, + (Object **)&s->canbus[0], + object_property_allow_set_link, + 0); + + object_property_add_link(obj, "xlnx-zcu102.canbus1", TYPE_CAN_BUS, + (Object **)&s->canbus[1], + object_property_allow_set_link, + 0); } =20 static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 7885bb17745..881847255b4 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -81,6 +81,14 @@ static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] =3D { 21, 22, }; =20 +static const uint64_t can_addr[XLNX_ZYNQMP_NUM_CAN] =3D { + 0xFF060000, 0xFF070000, +}; + +static const int can_intr[XLNX_ZYNQMP_NUM_CAN] =3D { + 23, 24, +}; + static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] =3D { 0xFF160000, 0xFF170000, }; @@ -243,6 +251,11 @@ static void xlnx_zynqmp_init(Object *obj) TYPE_CADENCE_UART); } =20 + for (i =3D 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { + object_initialize_child(obj, "can[*]", &s->can[i], + TYPE_XLNX_ZYNQMP_CAN); + } + object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI); =20 for (i =3D 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { @@ -482,6 +495,23 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Erro= r **errp) gic_spi[uart_intr[i]]); } =20 + for (i =3D 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { + object_property_set_int(OBJECT(&s->can[i]), "ext_clk_freq", + XLNX_ZYNQMP_CAN_REF_CLK, &error_abort); + + object_property_set_link(OBJECT(&s->can[i]), "canbus", + OBJECT(s->canbus[i]), &error_fatal); + + sysbus_realize(SYS_BUS_DEVICE(&s->can[i]), &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->can[i]), 0, can_addr[i]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->can[i]), 0, + gic_spi[can_intr[i]]); + } + object_property_set_int(OBJECT(&s->sata), "num-ports", SATA_NUM_PORTS, &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) { @@ -619,6 +649,10 @@ static Property xlnx_zynqmp_props[] =3D { DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false), DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGI= ON, MemoryRegion *), + DEFINE_PROP_LINK("canbus0", XlnxZynqMPState, canbus[0], TYPE_CAN_BUS, + CanBusState *), + DEFINE_PROP_LINK("canbus1", XlnxZynqMPState, canbus[1], TYPE_CAN_BUS, + CanBusState *), DEFINE_PROP_END_OF_LIST() }; =20 --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607601292; cv=none; d=zohomail.com; s=zohoarc; b=NSV4BMnUHxVA65ssWfM0xUQO3kJ79En4od0GtwlCg+8/lcE6TeQjbGMqwkuWzJaeW7P/0C2+MfcLd9e7FAm4qjpsIAnySuRZnuEyhza9d5L10iQ2bT+WFSq2qS1+7En0Clp3qWkFw3oiQgIRu9sAL2qaB15W86+BtHByiU7Lrz0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607601292; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4Rno6zxO2AJj7yR+plc0//gvJAHj6dsRla/VVrRKHr0=; b=JnRHN4RLWuTreobbMQsVXT+Jw+5lbdu5AB2q4XNH2XgTAjzggnHnkmsNDL75B36amsTPOftejrcLb/dS4fsKd6rAP1ZoKB5j4BTzkxbr3vAfgqxiFaDgZOfPq1vf7oJ1I09VDN5uHsbllQnL2ZyW0Ztt+0M+pug8bOGGrg7Yy6Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607601292361763.9346785064594; Thu, 10 Dec 2020 03:54:52 -0800 (PST) Received: from localhost ([::1]:46668 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKX5-0007E1-3l for importer@patchew.org; Thu, 10 Dec 2020 06:54:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51062) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKQj-0001JJ-2o for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:17 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:53774) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKQX-0006ys-SQ for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:16 -0500 Received: by mail-wm1-x336.google.com with SMTP id k10so4389590wmi.3 for ; Thu, 10 Dec 2020 03:48:05 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=4Rno6zxO2AJj7yR+plc0//gvJAHj6dsRla/VVrRKHr0=; b=oBtQoDgfLRXlLmlLO1+yTy7SZTtHdRde25IiUvkaHdx/lPmaNrHnlIYtMJeIvNNEJx aiJ5aH4uUACvsgbGuXdbClJLUk63djR5HsduqUfopnE64mccxKSMtypDdnmIh/zCS/10 R2eDiCox5EgdW36vWD+fqzZQSxzKdqmhqu/XBuhkdxYVxYB49rouEYh0MUbmrBi2Ob59 OnY2t8KL+PkKLXvL6vB1XX1ApnBQe+VIYS1feRKfmwYxopUmoyYj/RjfbHuSvzoaQeqE DE0Sob2mobaNwtHuNjHZj3a28RIM6L+yz12QAVGsYhscLWZZiEtRjFYpACo0hm1ndnzu mkkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4Rno6zxO2AJj7yR+plc0//gvJAHj6dsRla/VVrRKHr0=; b=llzw3V5oZguiJ6KMoUdxd5dv7tSLQl0sosZ08zl4B3xeIw+ux3XmTOaxiAxAHUGiVR 7Kj0FUzedari4opkf1x6tx7alhSBDNtaVO4dzsG/3r1+92jpr4SgsKiq06FBL5W4yZtK hbq6Vu4NUlIBdfIQ4yKE+nuMrCuCtAPBDEKIJsu5HMTFTUwR1k4I+H388Ord2rHWAGTc cygSkioP6e03FOWunSReIDLT9KeTr/6AmdwebUSovwyw4Y+tepkrbG/yrSv+bGr3+SMC jBkyOvCDTgUvlNN3cwiV2qQsNWiTmDiRxBds2NmXgca4njb+i4G8abHoLJ8pUoovJX0x DDfA== X-Gm-Message-State: AOAM533YKNJ+S9pM0LomhqDgTn+AY5YaCcuW2JWRuXYB9QAfrOgP1IsX BAxq9bQxyE8VHdtX0FwLsJkZV8B9L0kalQ== X-Google-Smtp-Source: ABdhPJwtbCrvF4WkvwRRjnWUhQIri7GAXskwwMy8pHrorhxTr2woHSZZJitx6eCkLG7eWYeeRKNrdQ== X-Received: by 2002:a1c:2c4:: with SMTP id 187mr7920345wmc.187.1607600884026; Thu, 10 Dec 2020 03:48:04 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/36] tests/qtest: Introduce tests for Xilinx ZynqMP CAN controller Date: Thu, 10 Dec 2020 11:47:24 +0000 Message-Id: <20201210114756.16501-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Vikram Garhwal The QTests perform five tests on the Xilinx ZynqMP CAN controller: Tests the CAN controller in loopback, sleep and snoop mode. Tests filtering of incoming CAN messages. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Francisco Iglesias Signed-off-by: Vikram Garhwal Message-id: 1605728926-352690-4-git-send-email-fnu.vikram@xilinx.com Signed-off-by: Peter Maydell --- tests/qtest/xlnx-can-test.c | 360 ++++++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 1 + 2 files changed, 361 insertions(+) create mode 100644 tests/qtest/xlnx-can-test.c diff --git a/tests/qtest/xlnx-can-test.c b/tests/qtest/xlnx-can-test.c new file mode 100644 index 00000000000..3d1120005b6 --- /dev/null +++ b/tests/qtest/xlnx-can-test.c @@ -0,0 +1,360 @@ +/* + * QTests for the Xilinx ZynqMP CAN controller. + * + * Copyright (c) 2020 Xilinx Inc. + * + * Written-by: Vikram Garhwal + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "libqos/libqtest.h" + +/* Base address. */ +#define CAN0_BASE_ADDR 0xFF060000 +#define CAN1_BASE_ADDR 0xFF070000 + +/* Register addresses. */ +#define R_SRR_OFFSET 0x00 +#define R_MSR_OFFSET 0x04 +#define R_SR_OFFSET 0x18 +#define R_ISR_OFFSET 0x1C +#define R_ICR_OFFSET 0x24 +#define R_TXID_OFFSET 0x30 +#define R_TXDLC_OFFSET 0x34 +#define R_TXDATA1_OFFSET 0x38 +#define R_TXDATA2_OFFSET 0x3C +#define R_RXID_OFFSET 0x50 +#define R_RXDLC_OFFSET 0x54 +#define R_RXDATA1_OFFSET 0x58 +#define R_RXDATA2_OFFSET 0x5C +#define R_AFR 0x60 +#define R_AFMR1 0x64 +#define R_AFIR1 0x68 +#define R_AFMR2 0x6C +#define R_AFIR2 0x70 +#define R_AFMR3 0x74 +#define R_AFIR3 0x78 +#define R_AFMR4 0x7C +#define R_AFIR4 0x80 + +/* CAN modes. */ +#define CONFIG_MODE 0x00 +#define NORMAL_MODE 0x00 +#define LOOPBACK_MODE 0x02 +#define SNOOP_MODE 0x04 +#define SLEEP_MODE 0x01 +#define ENABLE_CAN (1 << 1) +#define STATUS_NORMAL_MODE (1 << 3) +#define STATUS_LOOPBACK_MODE (1 << 1) +#define STATUS_SNOOP_MODE (1 << 12) +#define STATUS_SLEEP_MODE (1 << 2) +#define ISR_TXOK (1 << 1) +#define ISR_RXOK (1 << 4) + +static void match_rx_tx_data(const uint32_t *buf_tx, const uint32_t *buf_r= x, + uint8_t can_timestamp) +{ + uint16_t size =3D 0; + uint8_t len =3D 4; + + while (size < len) { + if (R_RXID_OFFSET + 4 * size =3D=3D R_RXDLC_OFFSET) { + g_assert_cmpint(buf_rx[size], =3D=3D, buf_tx[size] + can_times= tamp); + } else { + g_assert_cmpint(buf_rx[size], =3D=3D, buf_tx[size]); + } + + size++; + } +} + +static void read_data(QTestState *qts, uint64_t can_base_addr, uint32_t *b= uf_rx) +{ + uint32_t int_status; + + /* Read the interrupt on CAN rx. */ + int_status =3D qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_RX= OK; + + g_assert_cmpint(int_status, =3D=3D, ISR_RXOK); + + /* Read the RX register data for CAN. */ + buf_rx[0] =3D qtest_readl(qts, can_base_addr + R_RXID_OFFSET); + buf_rx[1] =3D qtest_readl(qts, can_base_addr + R_RXDLC_OFFSET); + buf_rx[2] =3D qtest_readl(qts, can_base_addr + R_RXDATA1_OFFSET); + buf_rx[3] =3D qtest_readl(qts, can_base_addr + R_RXDATA2_OFFSET); + + /* Clear the RX interrupt. */ + qtest_writel(qts, CAN1_BASE_ADDR + R_ICR_OFFSET, ISR_RXOK); +} + +static void send_data(QTestState *qts, uint64_t can_base_addr, + const uint32_t *buf_tx) +{ + uint32_t int_status; + + /* Write the TX register data for CAN. */ + qtest_writel(qts, can_base_addr + R_TXID_OFFSET, buf_tx[0]); + qtest_writel(qts, can_base_addr + R_TXDLC_OFFSET, buf_tx[1]); + qtest_writel(qts, can_base_addr + R_TXDATA1_OFFSET, buf_tx[2]); + qtest_writel(qts, can_base_addr + R_TXDATA2_OFFSET, buf_tx[3]); + + /* Read the interrupt on CAN for tx. */ + int_status =3D qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_TX= OK; + + g_assert_cmpint(int_status, =3D=3D, ISR_TXOK); + + /* Clear the interrupt for tx. */ + qtest_writel(qts, CAN0_BASE_ADDR + R_ICR_OFFSET, ISR_TXOK); +} + +/* + * This test will be transferring data from CAN0 and CAN1 through canbus. = CAN0 + * initiate the data transfer to can-bus, CAN1 receives the data. Test com= pares + * the data sent from CAN0 with received on CAN1. + */ +static void test_can_bus(void) +{ + const uint32_t buf_tx[4] =3D { 0xFF, 0x80000000, 0x12345678, 0x8765432= 1 }; + uint32_t buf_rx[4] =3D { 0x00, 0x00, 0x00, 0x00 }; + uint32_t status =3D 0; + uint8_t can_timestamp =3D 1; + + QTestState *qts =3D qtest_init("-machine xlnx-zcu102" + " -object can-bus,id=3Dcanbus0" + " -machine xlnx-zcu102.canbus0=3Dcanbus0" + " -machine xlnx-zcu102.canbus1=3Dcanbus0" + ); + + /* Configure the CAN0 and CAN1. */ + qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); + qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE); + qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); + qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE); + + /* Check here if CAN0 and CAN1 are in normal mode. */ + status =3D qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET); + g_assert_cmpint(status, =3D=3D, STATUS_NORMAL_MODE); + + status =3D qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET); + g_assert_cmpint(status, =3D=3D, STATUS_NORMAL_MODE); + + send_data(qts, CAN0_BASE_ADDR, buf_tx); + + read_data(qts, CAN1_BASE_ADDR, buf_rx); + match_rx_tx_data(buf_tx, buf_rx, can_timestamp); + + qtest_quit(qts); +} + +/* + * This test is performing loopback mode on CAN0 and CAN1. Data sent from = TX of + * each CAN0 and CAN1 are compared with RX register data for respective CA= N. + */ +static void test_can_loopback(void) +{ + uint32_t buf_tx[4] =3D { 0xFF, 0x80000000, 0x12345678, 0x87654321 }; + uint32_t buf_rx[4] =3D { 0x00, 0x00, 0x00, 0x00 }; + uint32_t status =3D 0; + + QTestState *qts =3D qtest_init("-machine xlnx-zcu102" + " -object can-bus,id=3Dcanbus0" + " -machine xlnx-zcu102.canbus0=3Dcanbus0" + " -machine xlnx-zcu102.canbus1=3Dcanbus0" + ); + + /* Configure the CAN0 in loopback mode. */ + qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE); + qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, LOOPBACK_MODE); + qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); + + /* Check here if CAN0 is set in loopback mode. */ + status =3D qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET); + + g_assert_cmpint(status, =3D=3D, STATUS_LOOPBACK_MODE); + + send_data(qts, CAN0_BASE_ADDR, buf_tx); + read_data(qts, CAN0_BASE_ADDR, buf_rx); + match_rx_tx_data(buf_tx, buf_rx, 0); + + /* Configure the CAN1 in loopback mode. */ + qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE); + qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, LOOPBACK_MODE); + qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); + + /* Check here if CAN1 is set in loopback mode. */ + status =3D qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET); + + g_assert_cmpint(status, =3D=3D, STATUS_LOOPBACK_MODE); + + send_data(qts, CAN1_BASE_ADDR, buf_tx); + read_data(qts, CAN1_BASE_ADDR, buf_rx); + match_rx_tx_data(buf_tx, buf_rx, 0); + + qtest_quit(qts); +} + +/* + * Enable filters for CAN1. This will filter incoming messages with ID. In= this + * test message will pass through filter 2. + */ +static void test_can_filter(void) +{ + uint32_t buf_tx[4] =3D { 0x14, 0x80000000, 0x12345678, 0x87654321 }; + uint32_t buf_rx[4] =3D { 0x00, 0x00, 0x00, 0x00 }; + uint32_t status =3D 0; + uint8_t can_timestamp =3D 1; + + QTestState *qts =3D qtest_init("-machine xlnx-zcu102" + " -object can-bus,id=3Dcanbus0" + " -machine xlnx-zcu102.canbus0=3Dcanbus0" + " -machine xlnx-zcu102.canbus1=3Dcanbus0" + ); + + /* Configure the CAN0 and CAN1. */ + qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); + qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE); + qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); + qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE); + + /* Check here if CAN0 and CAN1 are in normal mode. */ + status =3D qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET); + g_assert_cmpint(status, =3D=3D, STATUS_NORMAL_MODE); + + status =3D qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET); + g_assert_cmpint(status, =3D=3D, STATUS_NORMAL_MODE); + + /* Set filter for CAN1 for incoming messages. */ + qtest_writel(qts, CAN1_BASE_ADDR + R_AFR, 0x0); + qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR1, 0xF7); + qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR1, 0x121F); + qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR2, 0x5431); + qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR2, 0x14); + qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR3, 0x1234); + qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR3, 0x5431); + qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR4, 0xFFF); + qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR4, 0x1234); + + qtest_writel(qts, CAN1_BASE_ADDR + R_AFR, 0xF); + + send_data(qts, CAN0_BASE_ADDR, buf_tx); + + read_data(qts, CAN1_BASE_ADDR, buf_rx); + match_rx_tx_data(buf_tx, buf_rx, can_timestamp); + + qtest_quit(qts); +} + +/* Testing sleep mode on CAN0 while CAN1 is in normal mode. */ +static void test_can_sleepmode(void) +{ + uint32_t buf_tx[4] =3D { 0x14, 0x80000000, 0x12345678, 0x87654321 }; + uint32_t buf_rx[4] =3D { 0x00, 0x00, 0x00, 0x00 }; + uint32_t status =3D 0; + uint8_t can_timestamp =3D 1; + + QTestState *qts =3D qtest_init("-machine xlnx-zcu102" + " -object can-bus,id=3Dcanbus0" + " -machine xlnx-zcu102.canbus0=3Dcanbus0" + " -machine xlnx-zcu102.canbus1=3Dcanbus0" + ); + + /* Configure the CAN0. */ + qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE); + qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, SLEEP_MODE); + qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); + + qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); + qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE); + + /* Check here if CAN0 is in SLEEP mode and CAN1 in normal mode. */ + status =3D qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET); + g_assert_cmpint(status, =3D=3D, STATUS_SLEEP_MODE); + + status =3D qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET); + g_assert_cmpint(status, =3D=3D, STATUS_NORMAL_MODE); + + send_data(qts, CAN1_BASE_ADDR, buf_tx); + + /* + * Once CAN1 sends data on can-bus. CAN0 should exit sleep mode. + * Check the CAN0 status now. It should exit the sleep mode and receiv= e the + * incoming data. + */ + status =3D qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET); + g_assert_cmpint(status, =3D=3D, STATUS_NORMAL_MODE); + + read_data(qts, CAN0_BASE_ADDR, buf_rx); + + match_rx_tx_data(buf_tx, buf_rx, can_timestamp); + + qtest_quit(qts); +} + +/* Testing Snoop mode on CAN0 while CAN1 is in normal mode. */ +static void test_can_snoopmode(void) +{ + uint32_t buf_tx[4] =3D { 0x14, 0x80000000, 0x12345678, 0x87654321 }; + uint32_t buf_rx[4] =3D { 0x00, 0x00, 0x00, 0x00 }; + uint32_t status =3D 0; + uint8_t can_timestamp =3D 1; + + QTestState *qts =3D qtest_init("-machine xlnx-zcu102" + " -object can-bus,id=3Dcanbus0" + " -machine xlnx-zcu102.canbus0=3Dcanbus0" + " -machine xlnx-zcu102.canbus1=3Dcanbus0" + ); + + /* Configure the CAN0. */ + qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE); + qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, SNOOP_MODE); + qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); + + qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); + qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE); + + /* Check here if CAN0 is in SNOOP mode and CAN1 in normal mode. */ + status =3D qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET); + g_assert_cmpint(status, =3D=3D, STATUS_SNOOP_MODE); + + status =3D qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET); + g_assert_cmpint(status, =3D=3D, STATUS_NORMAL_MODE); + + send_data(qts, CAN1_BASE_ADDR, buf_tx); + + read_data(qts, CAN0_BASE_ADDR, buf_rx); + + match_rx_tx_data(buf_tx, buf_rx, can_timestamp); + + qtest_quit(qts); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + qtest_add_func("/net/can/can_bus", test_can_bus); + qtest_add_func("/net/can/can_loopback", test_can_loopback); + qtest_add_func("/net/can/can_filter", test_can_filter); + qtest_add_func("/net/can/can_test_snoopmode", test_can_snoopmode); + qtest_add_func("/net/can/can_test_sleepmode", test_can_sleepmode); + + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index c19f1c85034..4ca83ce6050 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -156,6 +156,7 @@ qtests_aarch64 =3D \ ['arm-cpu-features', 'numa-test', 'boot-serial-test', + 'xlnx-can-test', 'migration-test'] =20 qtests_s390x =3D \ --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607601151; cv=none; d=zohomail.com; s=zohoarc; b=TvYs7d0s8xy2sl2JIvAWvh0viOPiRY3Ko3bsqlECHd8ljjxgHhf+VFfndi5DS+hrAw9FqNKm4Lyu+dtqoazWC2YKLov5Rf9Ve8lGNymSVBkQP3DIBncQglUPGcxXXYfF/YjW7rX38W8GKr63KWwN+s09kqFqRrruDA+hw6RBCRQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607601151; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9tFafGIE7yPElctByswhUwlCG6jiOLsjyVbWG7y68lI=; b=lklWiUoNxpRwjBE1sox3P499X0+f0GzyMmeKA5lQjxx50FfecUyjRVMQbi4szBjLZscLeDH902GprSiDl3bxleEdeyMv4feG3hp2y4Oujavb6cV+WUqIlgwDd3kGs9Ew1yc9isqgpSbZnCOPKt6WdqL9ktJUoUVIKpPSrNv/gX8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 160760115181854.594416597445615; Thu, 10 Dec 2020 03:52:31 -0800 (PST) Received: from localhost ([::1]:41800 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKUo-00059O-MA for importer@patchew.org; Thu, 10 Dec 2020 06:52:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51070) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKQj-0001JT-6y for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:18 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:32926) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKQY-0006zm-Pt for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:16 -0500 Received: by mail-wm1-x329.google.com with SMTP id w206so2616817wma.0 for ; Thu, 10 Dec 2020 03:48:06 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=9tFafGIE7yPElctByswhUwlCG6jiOLsjyVbWG7y68lI=; b=w2a6bXLOynnXplGzwbbdCVezoca1IyI8eliLn+8zdHyXT8ysP68wYZUGWCGu4iSgdn iuCrC10NuRfjGRAvbZElmJbHHHtXOXmm1dlmSbk97wMkIwuNTkSJEHMslrCr31LdfgHL DIPOWrmtdULJutcnsuW26xtpCE0LEl9SgR6T0d2AOFZ7tdr8rEMcqtcA1mxjHQJggFHy x//AzR+iRfWayyCumix8wiu2r84dQiMqycH6Wwq6AavhFKAI3fM6+irJ6mw92DrteL+O /33eMjnQoukuyzgROR8F9XU+qbYwlkXqoyMLBXxAGwanB2ZoQ0LYEyPgkbGS7B/s5De7 po7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9tFafGIE7yPElctByswhUwlCG6jiOLsjyVbWG7y68lI=; b=MNIcCiOWZoNSsDcytdhJk2tMI5skenHCWGkmmPuHIdyhN/S6BAPYjU1YuYkdw7YmKU JvsAM8OATvesNoz3J5MB9UlepYbDkXlOto7G6RaK0vYpnqU8DpSjyr8l1h7QIjb+T++3 0gt4f79qQzze85c1pkUKuV014BkSUvszRbSnxZp+/Ywg/gl3KnpYgMierW8Dxh+WPxT3 ayK6hpl5bhEwFRLn1/ItXi32JpyLC0moXhmJyQ5uxamCg8zncftjdBEO4YljkFw8MWRE RHtZRB90SktxV36Lhp/ceKGAZasiZ9bGLDrqcSiB+lHyMohpteVE7lt1pZ/qz1JQ0Fnu /+uQ== X-Gm-Message-State: AOAM53002sMjmHQnHHuDldncoTdSm9s8zPmO3eAkWibTA/O4ZP6ZpAmA gwSbEDWq2trCjH7fbEP7txjxNh1ttqNcqg== X-Google-Smtp-Source: ABdhPJzJYIVn8bZ7oMRmc6L3O3/hJXHOweh4bRGJogFstzpudeeZpo6SWFqQp8xa9+CmhrbLe6nG+g== X-Received: by 2002:a1c:7f81:: with SMTP id a123mr7871367wmd.6.1607600885404; Thu, 10 Dec 2020 03:48:05 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/36] MAINTAINERS: Add maintainer entry for Xilinx ZynqMP CAN controller Date: Thu, 10 Dec 2020 11:47:25 +0000 Message-Id: <20201210114756.16501-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Vikram Garhwal Reviewed-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Vikram Garhwal Message-id: 1605728926-352690-5-git-send-email-fnu.vikram@xilinx.com Signed-off-by: Peter Maydell --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 68bc160f41b..a83416d54c0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1563,6 +1563,14 @@ F: hw/net/opencores_eth.c =20 Devices ------- +Xilinx CAN +M: Vikram Garhwal +M: Francisco Iglesias +S: Maintained +F: hw/net/can/xlnx-* +F: include/hw/net/xlnx-* +F: tests/qtest/xlnx-can-test* + EDU M: Jiri Slaby S: Maintained --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607601386; cv=none; d=zohomail.com; s=zohoarc; b=dgSywqhRk0uuzsvvZlx5qWXNaridFiuGNMRisHA/AzSUT8Z6m8dexCcAjg64vXgSKkoyL7ZTq5LcooQa0nifRU1Fehg66YlxOQLpFwr4sNVWm7XCRovmTH5XyZZ9bxYtG77zbpcLTwp1Uuv+i4uV7iQke4k7OJndrNG84GnxXc8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607601386; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pxyeVdBMn1RtIRNelqoqiHzeaVL19d3HeWFjF4ofw4A=; b=bP1pezEDKLgpl3Ksv4T7RtfwkPR0yXsli1wj0Ur4fS9hauaMyriv4bRtWmtyiXmjdnIjvOW8TjQImKmIT+43sAGh63DRJxmzVt2UyLb5WCdRqi/pJZjWVUgAebKnJmIT9N9vSffDopXVSll356iMA8WqW8cfCiF6HF5jkiLnH4I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607601386499632.169097878239; Thu, 10 Dec 2020 03:56:26 -0800 (PST) Received: from localhost ([::1]:49870 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKYb-000087-8c for importer@patchew.org; Thu, 10 Dec 2020 06:56:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51118) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKQm-0001M7-O1 for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:22 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:54587) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKQb-00070E-1e for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:20 -0500 Received: by mail-wm1-x336.google.com with SMTP id d3so4379571wmb.4 for ; Thu, 10 Dec 2020 03:48:07 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=pxyeVdBMn1RtIRNelqoqiHzeaVL19d3HeWFjF4ofw4A=; b=oDnfCRToJlhpebEZYC2xhvVZyXvYZKHlsSwPXE5DhVayLKZ4FPW1xtTHA18jxiKAgV 8h4Ku87l6k1uKT6eKKpB0tKJl3d+1Kqxyby4E1J5c7fCuPPP5wz807+ePwFNrNQiIVsH dqDJnAOyReL7rCEyAisCUPoma4aUKSuuwjRBlwf+uLwo0dRBw7XFuHF2bDLEeUWHtw3A aH8TY/VX5bEoAIBYgzq5dCkNE6a6wedXnr2+YgxJ5woZu5ZMelp2hDU6GRIh7q/ssLvE mwirZy4/EqFeyTG/0+6UyZZBtBtCHEojNRs7Qsrcj81jQg91PEyy/5CQrQfr+UZwFpPS 8MkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pxyeVdBMn1RtIRNelqoqiHzeaVL19d3HeWFjF4ofw4A=; b=eo92Wb/8pHg+uBgpLai4I9XQkIOET75VdoXMSwKFnN47KGCHzLWfjTj+paB4w/SGef HtMuULVf/lV6HM13t86lUA966tJa6JqMfpclmW8VuLqEGzyO+BquLfK9ey0DuTG10OGU mGxYuNZhvHACp5jKxNp/9+zr7+qVnK2XsA/X9uBhgwPf1jOZu0u3BlN39bs1hUD7DBvr KGRvi8UL7nLIFSPYv71h2KJS4I7eBxY1Fju2PF2wBhv1uRLoHwvQ4WTnuJ+eMeVQP1a5 0rfvG3tDeRdb09OiNpRoPoSxnNGtRprq8z/JuAVxYMkSYa5B+9XUh8eJuA0Gvo+mrmyx Tkfw== X-Gm-Message-State: AOAM532BXMzUoAeLJHPtwnYw3tx6zCrpXJknVIv1eHjxoJdJQd1jTa4Z t49cPCLmz4SGAaSYQ6J6MOx2UVFaGANpMw== X-Google-Smtp-Source: ABdhPJxmmPy2YIWCBS4pIyzKK5ikie/qQevts4WtGABqo7WgZ1J+CcfVeo4cHJlVNmY86gL6+qchAw== X-Received: by 2002:a7b:c208:: with SMTP id x8mr7766467wmi.179.1607600886559; Thu, 10 Dec 2020 03:48:06 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/36] sbsa-ref: allow to use Cortex-A53/57/72 cpus Date: Thu, 10 Dec 2020 11:47:26 +0000 Message-Id: <20201210114756.16501-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Marcin Juszkiewicz Trusted Firmware now supports A72 on sbsa-ref by default [1] so enable it for QEMU as well. A53 was already enabled there. 1. https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/7117 Signed-off-by: Marcin Juszkiewicz Reviewed-by: Richard Henderson Message-id: 20201120141705.246690-1-marcin.juszkiewicz@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/sbsa-ref.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 7d9e180c0db..4a5ea42938a 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -143,6 +143,24 @@ static const int sbsa_ref_irqmap[] =3D { [SBSA_GWDT] =3D 16, }; =20 +static const char * const valid_cpus[] =3D { + ARM_CPU_TYPE_NAME("cortex-a53"), + ARM_CPU_TYPE_NAME("cortex-a57"), + ARM_CPU_TYPE_NAME("cortex-a72"), +}; + +static bool cpu_type_valid(const char *cpu) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(valid_cpus); i++) { + if (strcmp(cpu, valid_cpus[i]) =3D=3D 0) { + return true; + } + } + return false; +} + static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) { uint8_t clustersz =3D ARM_DEFAULT_CPUS_PER_CLUSTER; @@ -649,9 +667,8 @@ static void sbsa_ref_init(MachineState *machine) const CPUArchIdList *possible_cpus; int n, sbsa_max_cpus; =20 - if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) { - error_report("sbsa-ref: CPU type other than the built-in " - "cortex-a57 not supported"); + if (!cpu_type_valid(machine->cpu_type)) { + error_report("mach-virt: CPU type %s not supported", machine->cpu_= type); exit(1); } =20 --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607601542; cv=none; d=zohomail.com; s=zohoarc; b=nJO/nlqhcV5979u4tAdyVJ6P7jGy7323VnPUlWYlbn+/2MJAo6lH9EoYB+w6JKgmaaMdwes16wMUwExn6Eb6DKBVz3ABbp45+wfRYRWkZSeaEITzzRFUNDA8xrTRKOCu8SCMMwxTWzR/kJe5oXiTGuzsGGF52W/VwMb9VaS1C1c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607601542; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dpThmaMoogi/5GyS9PRoz+06UyOQ4dJ+IrOLxiQU3vE=; b=Uv7SKIG9BppXIN2MBgT7r8MwGH/1PN1RMiKqeJ2fkIGYhPG19qH5BRNCzSOgMdJtBB3rZ9GurLH5aoE9nZRXZ2+QvHjBJiyzkejvAgCIz4/Yd/3poUh2pk/+WyPDqkXq5bZ9gnyjpYiXckfWnwtNTliqRubCA9Fefm2g3FzxG4w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607601542795100.1696787008799; Thu, 10 Dec 2020 03:59:02 -0800 (PST) Received: from localhost ([::1]:58252 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKb7-0003eC-KB for importer@patchew.org; Thu, 10 Dec 2020 06:59:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51170) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKQs-0001PJ-Le for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:28 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:36301) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKQb-00070J-1x for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:25 -0500 Received: by mail-wm1-x333.google.com with SMTP id y23so5005486wmi.1 for ; Thu, 10 Dec 2020 03:48:08 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=dpThmaMoogi/5GyS9PRoz+06UyOQ4dJ+IrOLxiQU3vE=; b=SCH4N21yuypemMdFsIi94E0a4TicFHyCsEYw1Rw+PyzF1LHQJErwFz+yUp0kAjmrdo 7nBkdwBkvJAdJx/NH45hIQSl3zn6G5TUfzQPkOnr32cC31j+MesYNh+HuLf68UInH/9C jxHw9myWX/pE3Uo4o5FUJoamvLmeT6XADyDNz85tG8ywbbJXAwJbdrjaeBLR6Ftea6fX DBuSl0orDHzIZvjeZaBQaiuGY1smGULWRm2Gjkmi3ZxgGvpBRZeklj4j/K8+cfvHF9fu 9YvfgwjyaDHPXwz4DKoGfyc5EYMIsKyKMHMEcyWScBPsGG+qWXtBfyXsvct5rMVIxZhT 4OzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dpThmaMoogi/5GyS9PRoz+06UyOQ4dJ+IrOLxiQU3vE=; b=Px24IdTDSEIKyb8R0zOaR9LzRUIby1YS4M9v7VvAM/pTsIaERGK6nGjJg8mlJSlc6Z wIruFby2mcxMFSg51tvarQDe65Nl8a4EaDHZowm2kzNFZQPFq4j1p85VlsYY+Hc1d7AO toNkuRoPtZ5DtCfdtJwX9E5MnIT+8mpsBewZ3mxsak5Yo5vAUU5XWby9TOgbRd6b7niI c9QP56y1IQ27nt2pS3OzL6YQKwzqhsLoK3V8bcFxbpBpsVlcEU9DcK93nCCtYRuMOsCo sjE4rW7yU8NGwBdHaDCOzaXIj82DYc8/m2043JYsX+ABFn8XnzUS7EZ31mA93FLJbv9J tsKQ== X-Gm-Message-State: AOAM532xPRmI/3KjeGOJkEX1JYdBhjslnvZ4hBmfbqm1CBxtBFc9WTxn J4Ac1DGfQrUqce2NBk1MJAKi5iWqT9ohmg== X-Google-Smtp-Source: ABdhPJzxR7OBEjBtycWt/Pa3ITe4Nm15/USiRjjB7wWQPre7HOsHA9xGepFWKgKSCZdmv9o+/0qSlQ== X-Received: by 2002:a1c:a501:: with SMTP id o1mr7692056wme.44.1607600887601; Thu, 10 Dec 2020 03:48:07 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/36] tests/qtest/npcm7xx_rng-test: dump random data on failure Date: Thu, 10 Dec 2020 11:47:27 +0000 Message-Id: <20201210114756.16501-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Havard Skinnemoen Dump the collected random data after a randomness test failure. Note that this relies on the test having called g_test_set_nonfatal_assertions() so we don't abort immediately on the assertion failure. Signed-off-by: Havard Skinnemoen Reviewed-by: Peter Maydell [PMM: minor commit message tweak] Signed-off-by: Peter Maydell --- tests/qtest/npcm7xx_rng-test.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c index c614968ffcd..797f832e53a 100644 --- a/tests/qtest/npcm7xx_rng-test.c +++ b/tests/qtest/npcm7xx_rng-test.c @@ -20,6 +20,7 @@ =20 #include "libqtest-single.h" #include "qemu/bitops.h" +#include "qemu-common.h" =20 #define RNG_BASE_ADDR 0xf000b000 =20 @@ -36,6 +37,13 @@ /* Number of bits to collect for randomness tests. */ #define TEST_INPUT_BITS (128) =20 +static void dump_buf_if_failed(const uint8_t *buf, size_t size) +{ + if (g_test_failed()) { + qemu_hexdump(stderr, "", buf, size); + } +} + static void rng_writeb(unsigned int offset, uint8_t value) { writeb(RNG_BASE_ADDR + offset, value); @@ -188,6 +196,7 @@ static void test_continuous_monobit(void) } =20 g_assert_cmpfloat(calc_monobit_p(buf, sizeof(buf)), >, 0.01); + dump_buf_if_failed(buf, sizeof(buf)); } =20 /* @@ -209,6 +218,7 @@ static void test_continuous_runs(void) } =20 g_assert_cmpfloat(calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE), >, = 0.01); + dump_buf_if_failed(buf.c, sizeof(buf)); } =20 /* @@ -230,6 +240,7 @@ static void test_first_byte_monobit(void) } =20 g_assert_cmpfloat(calc_monobit_p(buf, sizeof(buf)), >, 0.01); + dump_buf_if_failed(buf, sizeof(buf)); } =20 /* @@ -254,6 +265,7 @@ static void test_first_byte_runs(void) } =20 g_assert_cmpfloat(calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE), >, = 0.01); + dump_buf_if_failed(buf.c, sizeof(buf)); } =20 int main(int argc, char **argv) --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607605153; cv=none; d=zohomail.com; s=zohoarc; b=O7cRFtCZrI/HSg0zKone9R7ldjHK9iAD/58C9I1GeEo6wjSP0DvWxRKpNoKpNYLxTkezMsgnVpmm2tQJGdlRYpVpUYbR2vf/EEkOCxkSM07NYUhesoGUJpktp5L1xfoZ8BquNaKs+q/jGP8PqCFb3n1/VprPXImxZ+HCYmSpexg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607605153; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yQr23rJKjSZ4qtoRCxWVAb/FFzkFzM6tNSyE6y7hzSI=; b=jCrZINRFMBSK8D+Se2HwZ8cqr/tLFnsnirheuHoDVfzNhjFMpAJ4LUDHBIj/PaPeD/rATPJM7XGQm+b0siQniyC2hHKh7X9b7SNUwqxu7ceaQb3Z7u+Pr8/y2tIaBrxh0l4ymwIHlUJ/hXqYoGbsP4TJpIgLMqLSMxU0VipjVAY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607605153554448.3916522883128; Thu, 10 Dec 2020 04:59:13 -0800 (PST) Received: from localhost ([::1]:46452 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKiW-0002Cb-Jx for importer@patchew.org; Thu, 10 Dec 2020 07:06:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51208) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKQu-0001Pr-MK for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:28 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:46664) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKQc-00071L-3v for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:27 -0500 Received: by mail-wr1-x436.google.com with SMTP id l9so5135608wrt.13 for ; Thu, 10 Dec 2020 03:48:09 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=yQr23rJKjSZ4qtoRCxWVAb/FFzkFzM6tNSyE6y7hzSI=; b=Gk1j1m8s93UkA5WkEGnqBCK18ZwyFOArotLYgBA82I0Wg5oNxATSFFTtfjen3nE/H7 Xfw4YclY1+hxZ4LSdKfbVDbfIGnjnYuKaR/BBR14jxje451+BlB+EqMsugn7VIG58DP4 +MU9IuRb1zqhXja+yN8nJITLQObHUoIqRlEs4+WROFvhSGLKbCwgDg4MLQu/bhCfRGne 3jRljLsd1hLERVxNBCB+l6AahrkDTNqO+X8/MRqG+ND+23u1BM6SgSuYPGySVzD9j2Vj xjLuX9G90IJPgchmjlFBwJ0YmZnSF5t0pKzoBTfMNElpvJ4RReju8nZEeY1aZnz2JIia MQLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yQr23rJKjSZ4qtoRCxWVAb/FFzkFzM6tNSyE6y7hzSI=; b=YTjJnslxqLocSglRQleNrBsEfIP/IglppCEf+Y3yQDih613Sc9pYeFoVhT5qVPYsXD euHdevb7vRRPx6p7lepSpIuIpb2do1DBjl9KoAegz3792EjWdpjEbyzeGB3p8n/GR44C QUwfuYK7f1sfmzsbDl8PO+GHDxlQzHD2TMRN56RiC6QYSrp9eZQ8y6Ou/Qs0M/i/kc02 78XAWO5mVxFuUSIAtISDhg888L4FbK+jd28zdhXa5Wv9COEhOe4m5yHzvAQCUVm8nncP vutE9iMs1hh1PXfELR8c0UhAua9Ma7+hAzmnCwOIXsjaDqFH2w8rVxMIDhiGwaWFFQET Qvpw== X-Gm-Message-State: AOAM530ttRhhtjSaiLgIdfZ/9xTqwEzfP3Xv9BqNdSVcBFd5ysqNEy8H wCokSlQGscIjn/a/895H4gFBUxVbtQa4dg== X-Google-Smtp-Source: ABdhPJyqEeO+RJ8igs0eM42HGB1pkVoboLdowVBL0NhC70BhLM36juBa9Kc4Tfs7r2TMo+Kyi1pW7w== X-Received: by 2002:a5d:42cf:: with SMTP id t15mr7721095wrr.267.1607600888659; Thu, 10 Dec 2020 03:48:08 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/36] i.MX25: Fix bad printf format specifiers Date: Thu, 10 Dec 2020 11:47:28 +0000 Message-Id: <20201210114756.16501-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Alex Chen We should use printf format specifier "%u" instead of "%d" for argument of type "unsigned int". Reported-by: Euler Robot Signed-off-by: Alex Chen Message-id: 20201126111109.112238-2-alex.chen@huawei.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/misc/imx25_ccm.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/misc/imx25_ccm.c b/hw/misc/imx25_ccm.c index d3107e5ca29..ff996e2f2ca 100644 --- a/hw/misc/imx25_ccm.c +++ b/hw/misc/imx25_ccm.c @@ -91,7 +91,7 @@ static const char *imx25_ccm_reg_name(uint32_t reg) case IMX25_CCM_LPIMR1_REG: return "lpimr1"; default: - sprintf(unknown, "[%d ?]", reg); + sprintf(unknown, "[%u ?]", reg); return unknown; } } @@ -118,7 +118,7 @@ static uint32_t imx25_ccm_get_mpll_clk(IMXCCMState *dev) freq =3D imx_ccm_calc_pll(s->reg[IMX25_CCM_MPCTL_REG], CKIH_FREQ); } =20 - DPRINTF("freq =3D %d\n", freq); + DPRINTF("freq =3D %u\n", freq); =20 return freq; } @@ -136,7 +136,7 @@ static uint32_t imx25_ccm_get_mcu_clk(IMXCCMState *dev) =20 freq =3D freq / (1 + EXTRACT(s->reg[IMX25_CCM_CCTL_REG], ARM_CLK_DIV)); =20 - DPRINTF("freq =3D %d\n", freq); + DPRINTF("freq =3D %u\n", freq); =20 return freq; } @@ -149,7 +149,7 @@ static uint32_t imx25_ccm_get_ahb_clk(IMXCCMState *dev) freq =3D imx25_ccm_get_mcu_clk(dev) / (1 + EXTRACT(s->reg[IMX25_CCM_CCTL_REG], AHB_CLK_DIV)); =20 - DPRINTF("freq =3D %d\n", freq); + DPRINTF("freq =3D %u\n", freq); =20 return freq; } @@ -160,7 +160,7 @@ static uint32_t imx25_ccm_get_ipg_clk(IMXCCMState *dev) =20 freq =3D imx25_ccm_get_ahb_clk(dev) / 2; =20 - DPRINTF("freq =3D %d\n", freq); + DPRINTF("freq =3D %u\n", freq); =20 return freq; } @@ -186,7 +186,7 @@ static uint32_t imx25_ccm_get_clock_frequency(IMXCCMSta= te *dev, IMXClk clock) break; } =20 - DPRINTF("Clock =3D %d) =3D %d\n", clock, freq); + DPRINTF("Clock =3D %d) =3D %u\n", clock, freq); =20 return freq; } --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607603131; cv=none; d=zohomail.com; s=zohoarc; b=kZ2/RaFNZfhCjK8UKxZ+H63tB0/dqDfnH+ENKXYjY17Vw9NlQCHVaTg5NGOPaxkPJ6fpyxRZEBCg5h+vHkNd5IhQbCtX5mClX2xSz8KsmPI9sj61Ja9A9M+rDB70wTfRtwcLWSDEXMageuLbc4CZW8tE8ZohyayHbbay4/SOvog= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607603131; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=XQsrNMirMBP/WD1WlqfVCpC5aj7zOTNhm+B7VyZuN1Y=; b=mlPkJ7YC5YVNdjaxmiNWo1XHVj3UcuaOulwUtpg0rSTKXKaVi1bI8APADGZuECPntt6wrNvBnecmS0Roku2y0jBbTKVe1rSmuH61kK4warc+XPjpbirxN9c9VMn6nujWPs7L2G+heercV26KwW8FtccCd7x88CVuN3FaWANSUNA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607603131411752.9658026786474; Thu, 10 Dec 2020 04:25:31 -0800 (PST) Received: from localhost ([::1]:38196 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKf3-00079j-M1 for importer@patchew.org; Thu, 10 Dec 2020 07:03:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51210) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKQu-0001QA-N3 for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:28 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:38645) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKQe-00071S-KV for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:28 -0500 Received: by mail-wr1-x432.google.com with SMTP id r7so5150961wrc.5 for ; Thu, 10 Dec 2020 03:48:11 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=XQsrNMirMBP/WD1WlqfVCpC5aj7zOTNhm+B7VyZuN1Y=; b=KR4Yo6FgIvY9YNPabC8wEqMtc95vv0XRLSGfaJVACJo3RpFM37+k14u5fOZ1CxXMpy B5d0y3AmJin04DZzLdoOQU+D7CJtxWpH2+hTVW4EPqUs8rrAypDTL74dmR8s5DSV3KwB Dwg9/tjkjp6V1Fe5EYQ5FfyvxflQAJm7wlYeog4bamQ8pdGV3E5ED/uLpUq9pwm91rtm 6IAtOwKXdlrUo8pkhBeWP2wi+vaVVuFB8d7eWmqUg+z5m7u7g5Fc5GY6HHXNqujAU5Mu QV8TRfp+j+mweZfcqdfnZPnSM3vffe0is7FphuzAtSwfozCKEZsEcblinltJblRS0gmA pMQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XQsrNMirMBP/WD1WlqfVCpC5aj7zOTNhm+B7VyZuN1Y=; b=daFmHUTPlJoZSXHZLbd25AYCmx3tsRJykp7M3LAYC90/COlucCwgK/cVqEhTBQr7Im yddDF8guBak86OWnPbVsTFatiKYDaVm+2JY5ltWVVBkx3/2WoZyUCu283M1CeCeI1A67 7FG+HrdpsPh9hT9mjJatu59fFwxTO1jFDKKXzohw14DS80iFjmPlcxhn+HHq0wI+jCgb FouB0+gPgU5TTAOeDSA4qqujk7hF4t64uZFyHF14pvtqUXGE4imK541NZ09x2/W0ad3q PEL6XlZQn/cAc38sDBrygIIdlR+dePiarYcxWzdu5Tcrw7bHicnV+TEQMDX/cb7nz3J8 xKkg== X-Gm-Message-State: AOAM530HqlL3dlKtdvOss8H1wTRjDEUgp2bYue0rCzprZohI+gzqHTEl VODYdROhb3EzGA8+MOzamsAH7orQ4bNe5g== X-Google-Smtp-Source: ABdhPJyba+nAZ4eYkh5JYRNjdsBedRwi5njhhP0u+O0ThWkTVM/shzkHEDKxPLPFPwODtEc9Ex1B7A== X-Received: by 2002:a5d:6ccb:: with SMTP id c11mr7848188wrc.224.1607600889778; Thu, 10 Dec 2020 03:48:09 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/36] i.MX31: Fix bad printf format specifiers Date: Thu, 10 Dec 2020 11:47:29 +0000 Message-Id: <20201210114756.16501-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Alex Chen We should use printf format specifier "%u" instead of "%d" for argument of type "unsigned int". Reported-by: Euler Robot Signed-off-by: Alex Chen Message-id: 20201126111109.112238-3-alex.chen@huawei.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/misc/imx31_ccm.c | 14 +++++++------- hw/misc/imx_ccm.c | 4 ++-- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/misc/imx31_ccm.c b/hw/misc/imx31_ccm.c index 6e246827ab6..ad30a4b2c0c 100644 --- a/hw/misc/imx31_ccm.c +++ b/hw/misc/imx31_ccm.c @@ -89,7 +89,7 @@ static const char *imx31_ccm_reg_name(uint32_t reg) case IMX31_CCM_PDR2_REG: return "PDR2"; default: - sprintf(unknown, "[%d ?]", reg); + sprintf(unknown, "[%u ?]", reg); return unknown; } } @@ -120,7 +120,7 @@ static uint32_t imx31_ccm_get_pll_ref_clk(IMXCCMState *= dev) freq =3D CKIH_FREQ; } =20 - DPRINTF("freq =3D %d\n", freq); + DPRINTF("freq =3D %u\n", freq); =20 return freq; } @@ -133,7 +133,7 @@ static uint32_t imx31_ccm_get_mpll_clk(IMXCCMState *dev) freq =3D imx_ccm_calc_pll(s->reg[IMX31_CCM_MPCTL_REG], imx31_ccm_get_pll_ref_clk(dev)); =20 - DPRINTF("freq =3D %d\n", freq); + DPRINTF("freq =3D %u\n", freq); =20 return freq; } @@ -150,7 +150,7 @@ static uint32_t imx31_ccm_get_mcu_main_clk(IMXCCMState = *dev) freq =3D imx31_ccm_get_mpll_clk(dev); } =20 - DPRINTF("freq =3D %d\n", freq); + DPRINTF("freq =3D %u\n", freq); =20 return freq; } @@ -163,7 +163,7 @@ static uint32_t imx31_ccm_get_hclk_clk(IMXCCMState *dev) freq =3D imx31_ccm_get_mcu_main_clk(dev) / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], MAX)); =20 - DPRINTF("freq =3D %d\n", freq); + DPRINTF("freq =3D %u\n", freq); =20 return freq; } @@ -176,7 +176,7 @@ static uint32_t imx31_ccm_get_ipg_clk(IMXCCMState *dev) freq =3D imx31_ccm_get_hclk_clk(dev) / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], IPG)); =20 - DPRINTF("freq =3D %d\n", freq); + DPRINTF("freq =3D %u\n", freq); =20 return freq; } @@ -201,7 +201,7 @@ static uint32_t imx31_ccm_get_clock_frequency(IMXCCMSta= te *dev, IMXClk clock) break; } =20 - DPRINTF("Clock =3D %d) =3D %d\n", clock, freq); + DPRINTF("Clock =3D %d) =3D %u\n", clock, freq); =20 return freq; } diff --git a/hw/misc/imx_ccm.c b/hw/misc/imx_ccm.c index 52882071d3b..08a50ee4c8a 100644 --- a/hw/misc/imx_ccm.c +++ b/hw/misc/imx_ccm.c @@ -38,7 +38,7 @@ uint32_t imx_ccm_get_clock_frequency(IMXCCMState *dev, IM= XClk clock) freq =3D klass->get_clock_frequency(dev, clock); } =20 - DPRINTF("(clock =3D %d) =3D %d\n", clock, freq); + DPRINTF("(clock =3D %d) =3D %u\n", clock, freq); =20 return freq; } @@ -65,7 +65,7 @@ uint32_t imx_ccm_calc_pll(uint32_t pllreg, uint32_t base_= freq) freq =3D ((2 * (base_freq >> 10) * (mfi * mfd + mfn)) / (mfd * pd)) << 10; =20 - DPRINTF("(pllreg =3D 0x%08x, base_freq =3D %d) =3D %d\n", pllreg, base= _freq, + DPRINTF("(pllreg =3D 0x%08x, base_freq =3D %u) =3D %d\n", pllreg, base= _freq, freq); =20 return freq; --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607601043; cv=none; d=zohomail.com; s=zohoarc; b=TVRhJlUZ/tlDUWIoFhHsI840bLjWg0HlQEnkK9iMDYZCfIUp1cJVLx6/dVegVeMFwZnxA5DDzXN3RmVMBouplIXu86fYtMcm6tS4Huu+fA8zRwduuggiUGuKx++hmOLa1xf0BEvScRKy9h6CMDYR7DdT/Oe9erwUPqVuWCqCEWA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607601043; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wf1XuqV8Ky+w4DmMBlqPnGd/R9XRzh/8oQR8ynsnFpk=; b=fcdeV72DYXYByUJkpoJTbz2fcxhjhv6dVtmR56O8ZTVS0vD22OHkps95hPzK/noFUr+chMfZYsDPUwbNXnkVxc5Mc5dOARNyFzlWboHzWNwAsk5bGGdaVkZAwf39vw2AhBdxFif6DSthY6FQ7JZyfxgZjdlmcLE68sVTO+MslIs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607601043561698.0989284340995; Thu, 10 Dec 2020 03:50:43 -0800 (PST) Received: from localhost ([::1]:37204 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKT4-0003BS-7u for importer@patchew.org; Thu, 10 Dec 2020 06:50:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51236) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKQw-0001Qz-IL for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:32 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:41479) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKQe-00071X-64 for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:29 -0500 Received: by mail-wr1-x42f.google.com with SMTP id a12so5151938wrv.8 for ; Thu, 10 Dec 2020 03:48:11 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=wf1XuqV8Ky+w4DmMBlqPnGd/R9XRzh/8oQR8ynsnFpk=; b=Ap6Qg2xElTbN205uZ09enxrYZgJRlDu5lB9OVCOssMbklAYUGg/zFVCQZeyZgoaqS9 aJzg/NU3HGxo3mAVXQJh9o67qUZ5hWsNW/5XiL0qqfxOrRo4abazHuu6reBUH/AcArdA xDe5g1XKCwBiko8WXez6v86KKrtrbEqLi9KMEhUMYqLHDNpXzNQEekYENuO6L+vc/BDV 2Ma2cysm4S46b4KEI12/gfq4c97CgRdqYuimb+ltIgj86gjG4XmCG2IBWK2Dl4Ed0k+8 TKSAT9/yXWBGwFml/nuNJr+LMEHaueIbyaoiXTMtAhGjDApaHZ0ge+DJt28MoltXlR9O Z3Kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wf1XuqV8Ky+w4DmMBlqPnGd/R9XRzh/8oQR8ynsnFpk=; b=c1/VFQcj4HElt5zQJtaQS05QezIkWWHZ8Ry68rmf6r8VY5xMCiwHsk29GZnd/bpyEM wsXT9bn6VZ3cEb5wliv/s87A6Mc/z/9Tjzsmbz+kpiAOEoQ708MQZ+OsldqPyXS6ZF8n nLegvTD5YRIjLPCJyVbKBas27QoKWL/e8zmxpLjQEkWSbwShpTSv9ypeTxa1sDYHMiYS +RubvLYOoSGPWgfFUcefMq1gZYMX60fJGy+2tbUaRepJ6wC87ErFjah4UxkXVk1tTtAK B5+nQcBLS69fYpGRO5z/u9f8iSEBPMO1iczGHhaR/lFvNsDycL/h9AvoxPwTot4klxVm Y7Dw== X-Gm-Message-State: AOAM531I8h5eMPhHxdjrHLFZorGVS2YGMv1xtxmi35JLoEfOt9eUVLGa YLH96qbrXWeftLWf0/5vn5YKohKm3+MWOA== X-Google-Smtp-Source: ABdhPJyL3qsX7xi8w7/39g+bDZZ6PMHV4CQhoS9IAWIXGJbVKwJjr5ObImNEK4Tc0u+mZGjMHp+M9g== X-Received: by 2002:adf:e710:: with SMTP id c16mr7846842wrm.295.1607600890646; Thu, 10 Dec 2020 03:48:10 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/36] i.MX6: Fix bad printf format specifiers Date: Thu, 10 Dec 2020 11:47:30 +0000 Message-Id: <20201210114756.16501-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Alex Chen We should use printf format specifier "%u" instead of "%d" for argument of type "unsigned int". Reported-by: Euler Robot Signed-off-by: Alex Chen Message-id: 20201126111109.112238-4-alex.chen@huawei.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/misc/imx6_ccm.c | 20 ++++++++++---------- hw/misc/imx6_src.c | 2 +- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/hw/misc/imx6_ccm.c b/hw/misc/imx6_ccm.c index 7fec8f0a476..cb740427eca 100644 --- a/hw/misc/imx6_ccm.c +++ b/hw/misc/imx6_ccm.c @@ -96,7 +96,7 @@ static const char *imx6_ccm_reg_name(uint32_t reg) case CCM_CMEOR: return "CMEOR"; default: - sprintf(unknown, "%d ?", reg); + sprintf(unknown, "%u ?", reg); return unknown; } } @@ -235,7 +235,7 @@ static const char *imx6_analog_reg_name(uint32_t reg) case USB_ANALOG_DIGPROG: return "USB_ANALOG_DIGPROG"; default: - sprintf(unknown, "%d ?", reg); + sprintf(unknown, "%u ?", reg); return unknown; } } @@ -263,7 +263,7 @@ static uint64_t imx6_analog_get_pll2_clk(IMX6CCMState *= dev) freq *=3D 20; } =20 - DPRINTF("freq =3D %d\n", (uint32_t)freq); + DPRINTF("freq =3D %u\n", (uint32_t)freq); =20 return freq; } @@ -275,7 +275,7 @@ static uint64_t imx6_analog_get_pll2_pfd0_clk(IMX6CCMSt= ate *dev) freq =3D imx6_analog_get_pll2_clk(dev) * 18 / EXTRACT(dev->analog[CCM_ANALOG_PFD_528], PFD0_FRAC); =20 - DPRINTF("freq =3D %d\n", (uint32_t)freq); + DPRINTF("freq =3D %u\n", (uint32_t)freq); =20 return freq; } @@ -287,7 +287,7 @@ static uint64_t imx6_analog_get_pll2_pfd2_clk(IMX6CCMSt= ate *dev) freq =3D imx6_analog_get_pll2_clk(dev) * 18 / EXTRACT(dev->analog[CCM_ANALOG_PFD_528], PFD2_FRAC); =20 - DPRINTF("freq =3D %d\n", (uint32_t)freq); + DPRINTF("freq =3D %u\n", (uint32_t)freq); =20 return freq; } @@ -315,7 +315,7 @@ static uint64_t imx6_analog_get_periph_clk(IMX6CCMState= *dev) break; } =20 - DPRINTF("freq =3D %d\n", (uint32_t)freq); + DPRINTF("freq =3D %u\n", (uint32_t)freq); =20 return freq; } @@ -327,7 +327,7 @@ static uint64_t imx6_ccm_get_ahb_clk(IMX6CCMState *dev) freq =3D imx6_analog_get_periph_clk(dev) / (1 + EXTRACT(dev->ccm[CCM_CBCDR], AHB_PODF)); =20 - DPRINTF("freq =3D %d\n", (uint32_t)freq); + DPRINTF("freq =3D %u\n", (uint32_t)freq); =20 return freq; } @@ -339,7 +339,7 @@ static uint64_t imx6_ccm_get_ipg_clk(IMX6CCMState *dev) freq =3D imx6_ccm_get_ahb_clk(dev) / (1 + EXTRACT(dev->ccm[CCM_CBCDR], IPG_PODF)); =20 - DPRINTF("freq =3D %d\n", (uint32_t)freq); + DPRINTF("freq =3D %u\n", (uint32_t)freq); =20 return freq; } @@ -351,7 +351,7 @@ static uint64_t imx6_ccm_get_per_clk(IMX6CCMState *dev) freq =3D imx6_ccm_get_ipg_clk(dev) / (1 + EXTRACT(dev->ccm[CCM_CSCMR1], PERCLK_PODF)); =20 - DPRINTF("freq =3D %d\n", (uint32_t)freq); + DPRINTF("freq =3D %u\n", (uint32_t)freq); =20 return freq; } @@ -385,7 +385,7 @@ static uint32_t imx6_ccm_get_clock_frequency(IMXCCMStat= e *dev, IMXClk clock) break; } =20 - DPRINTF("Clock =3D %d) =3D %d\n", clock, freq); + DPRINTF("Clock =3D %d) =3D %u\n", clock, freq); =20 return freq; } diff --git a/hw/misc/imx6_src.c b/hw/misc/imx6_src.c index dd99cc7acf0..79f43759113 100644 --- a/hw/misc/imx6_src.c +++ b/hw/misc/imx6_src.c @@ -68,7 +68,7 @@ static const char *imx6_src_reg_name(uint32_t reg) case SRC_GPR10: return "SRC_GPR10"; default: - sprintf(unknown, "%d ?", reg); + sprintf(unknown, "%u ?", reg); return unknown; } } --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607605157; cv=none; d=zohomail.com; s=zohoarc; b=bg4DtQcnP0pI+xIhcsuZ3On66E0FaAY/yNlehc4jIxOOGiVQtGgrm8lqSXzcGcZdg4gx2CG14PkpIc7gwafDLmrq3exEANsDQ/oCUSRCWLtNqSGHkrDi/hv+o44XiRcxQBgW2+yPcuTYi5PKUy9/lYrmV8pq5k9oovJTemGsuG4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607605157; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PnlWOn3wj5epMR6Ukz4GSi3hf0wbVdyWVyWPmQyzxt0=; b=GyV/LggQII7MjTvyCpGqeVwBjytwzCaL/h0NP3iUGqBM/RpbCYmmdqkP745vertKUc0lHxISg9suA26b/BkdKxEUjT+lG/TqcxWvqhGZ9w9PyHGzYsxrAkAKTiSJI/gAgLGUKop9SVvEuahKny7aRH2tJB+GZ4ovU7r9BxdiQOE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607605157137294.6862881017589; Thu, 10 Dec 2020 04:59:17 -0800 (PST) Received: from localhost ([::1]:54900 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKlW-0005gC-UV for importer@patchew.org; Thu, 10 Dec 2020 07:09:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51268) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKQy-0001RZ-IW for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:32 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:52152) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKQf-00072a-6p for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:32 -0500 Received: by mail-wm1-x332.google.com with SMTP id v14so4386590wml.1 for ; Thu, 10 Dec 2020 03:48:12 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=PnlWOn3wj5epMR6Ukz4GSi3hf0wbVdyWVyWPmQyzxt0=; b=NO8hswIonz5L2tq9zhW1tMu+EMfN8DcaDgeKQue78QOwa1ncoN87OG1Bdvz9VB3Vsr LOPMlpLIjdK8tNTa69xOzb1+F9tR2V9Su7gNR2epFywQfO2jYGosppylj/6FQa1pLBfB hF9eZ7R+YFH8guHdLGFfyU09C1PbQrwMCX0V9xM0/v0ArgSZilbLeU0BcTg5Q/m/sgA7 +1Bb20GCLyWljN+Bet/Dml509mHjyoCVzQ0JgKVc2cepVGDFTD0FkaS9coDUg3Bqqzvy /4PKIS0hTYXAu3v0IxD31xCrtjY4ylwW+J/081NhRv9EtV7rKmnnEa0KVhalyX2olswt zWjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PnlWOn3wj5epMR6Ukz4GSi3hf0wbVdyWVyWPmQyzxt0=; b=Rrp0GyFox+5HtfdjXa4aHXH+rXPzZ5RmNLRstw2i/fZeYraiUIYuKVzYLRPTCz7VhG c60vaHSPD7fyBIOWyjPDa5l6fxoBduCpZouozo6nBPJ4doBQCVWuDEDh2mdl2pjmuzY7 Z6xmXT5WRtkqseKjyoFgsgqsLeI25YGHlVaT1Pk9dYlYTJbbrgv3H3cUwvW0smRAWT4v BsAXdt5LQdtf+RTroYbl8ImNFIa3hllrbmvU7wR7QwELBfLMfVH3brT+NtF6/5Z1nbvt YNvbzDtOIK2mJXgiI3wCIFwrGm8XR3FqjgAhG32J1Pf3czVuO9VCN3gq3fSdGFPE/ozd ZLbg== X-Gm-Message-State: AOAM532qvx6g861ke0GrPxJvrYMD2DgUV653n7Uk8bePT+clazlAsVwH tNl57MQx56tggMk0dex+Nkz8uZqDZq7shA== X-Google-Smtp-Source: ABdhPJwLEP6BAUbMbF0roZKx3bRsrGL9WF3DXK1kA+kHenGRs7np5ivONKWUPA8l/M3H7uL+EIRY5A== X-Received: by 2002:a05:600c:cc:: with SMTP id u12mr7951014wmm.42.1607600891635; Thu, 10 Dec 2020 03:48:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/36] i.MX6ul: Fix bad printf format specifiers Date: Thu, 10 Dec 2020 11:47:31 +0000 Message-Id: <20201210114756.16501-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Alex Chen We should use printf format specifier "%u" instead of "%d" for argument of type "unsigned int". Reported-by: Euler Robot Signed-off-by: Alex Chen Message-id: 20201126111109.112238-5-alex.chen@huawei.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/misc/imx6ul_ccm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/misc/imx6ul_ccm.c b/hw/misc/imx6ul_ccm.c index 5e0661dacf7..a65d0314556 100644 --- a/hw/misc/imx6ul_ccm.c +++ b/hw/misc/imx6ul_ccm.c @@ -143,7 +143,7 @@ static const char *imx6ul_ccm_reg_name(uint32_t reg) case CCM_CMEOR: return "CMEOR"; default: - sprintf(unknown, "%d ?", reg); + sprintf(unknown, "%u ?", reg); return unknown; } } @@ -274,7 +274,7 @@ static const char *imx6ul_analog_reg_name(uint32_t reg) case USB_ANALOG_DIGPROG: return "USB_ANALOG_DIGPROG"; default: - sprintf(unknown, "%d ?", reg); + sprintf(unknown, "%u ?", reg); return unknown; } } --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607603856; cv=none; d=zohomail.com; s=zohoarc; b=YchGGd1rQvUYnM2yqkPBccWDcEB3c9MwE2N4L0pmf6aS0sLQjewnPoUkG7b906R3nYZJd2D55xECa2CM7U8qLI8KYhqNcMkOMO6u0hOhPOAvKpNoD3mmN2tw7IKuLPPi5GHFdE9s+56Q6rCx/0O22l3ZSN/ANLaKy/Mspq7sqyk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607603856; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=t3m1K3VFzcJivp35jn7u4hjssugJbQusEvdAPiBN5BU=; b=DQfes150BeZqtTvRC2L2YMuIbmNwcgxR9LKgVg9xxo2weOp27CJskCnTr76hgR+nBpdFhVi2M30tTBzL9o0OcIdhr57PmObeTf+qMbkGkZhV80zQ49TcfiDPIjr0SFPN7AYrqqpda2+whGAAZne14lqwLR9zlddqdLbA14WxW6Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607603856777786.848861004258; Thu, 10 Dec 2020 04:37:36 -0800 (PST) Received: from localhost ([::1]:52360 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKtd-00082D-70 for importer@patchew.org; Thu, 10 Dec 2020 07:18:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51406) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKR4-0001Yd-LN for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:38 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:36300) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKQg-000736-CT for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:38 -0500 Received: by mail-wm1-x331.google.com with SMTP id y23so5005776wmi.1 for ; Thu, 10 Dec 2020 03:48:14 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=t3m1K3VFzcJivp35jn7u4hjssugJbQusEvdAPiBN5BU=; b=RhqxyzYri52+2FTPMz4Ul9e6BUc4BATyJv5HgmTZh2j0OdDgiBhkz/J31N+9mw3GWH i+m+1+8CwoGLkTu7//ndb/VDrtSQuGrXE7UE7dDXml0tXj/08VWgGWZ/H/8INX5Udftz 6maLedWrfPNetMdS2mq686hYzG2yXhebGFRIcq1wctBlvuCeg1f2eDcEL5VKU1fDdrPc Z1mNVbytL+ayDvz9yUO9cMcMOqKbqIfHY1b8EbrczUJV949KSKDrBdon88WWp0EoZgE9 pEwy4BTPINpoRqm7/qJvrmhNqf1HfPziKv/BEF2JEZQGBhd0Ku+tf/dRMJ1NA4tPc4P6 yQqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=t3m1K3VFzcJivp35jn7u4hjssugJbQusEvdAPiBN5BU=; b=qwn3cmQ6k7nFjT0rOOqOMZ/JPw0bFpZx20qn1RzFJUNb777MvXShbK0NuSVwsmvr6x 71yAAvGSG53TOAHUnTM1bg+Y7VU2z0NlssUUjkUOooEpSlepwkupztBLWOBMpPryZjEv 9xCRP2vjTir/wfQPrs4qDCkIsQOgKu/DxbA4g2edRkWw9lbSAFhqIX6YYFbcl+2/x+TD 21JhYtBUKuwewlybvmrqXEunnXLKeVeszVuecVY7WS7UgZT28X8Fm7EL8bnBsO468mwn dTvehg3aRl70WfIuWgdZfVLCKLzxMZxjJkdreIoKiEjDYYhQlt2t41OcpJRTqYtYOlhN cYRA== X-Gm-Message-State: AOAM531YrwKNEHouNTGl3x3wvJZluLSe3GAd6YYh0ey3rix71D90IP0m PJTCYcoxdJYKWgq4ZnDOwhQJs0EPXHaa/Q== X-Google-Smtp-Source: ABdhPJxZY8Z952n2+I2lpLBGSTwJW3YTewYgWSTbGTrr54zOHHWP0zom3F524nu9x+I6EWOa0JwUYg== X-Received: by 2002:a1c:f00a:: with SMTP id a10mr7743721wmb.83.1607600892814; Thu, 10 Dec 2020 03:48:12 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/36] hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault Date: Thu, 10 Dec 2020 11:47:32 +0000 Message-Id: <20201210114756.16501-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" For M-profile CPUs, the range from 0xe0000000 to 0xe00fffff is the Private Peripheral Bus range, which includes all of the memory mapped devices and registers that are part of the CPU itself, including the NVIC, systick timer, and debug and trace components like the Data Watchpoint and Trace unit (DWT). Within this large region, the range 0xe000e000 to 0xe000efff is the System Control Space (NVIC, system registers, systick) and 0xe002e000 to 0exe002efff is its Non-secure alias. The architecture is clear that within the SCS unimplemented registers should be RES0 for privileged accesses and generate BusFault for unprivileged accesses, and we currently implement this. It is less clear about how to handle accesses to unimplemented regions of the wider PPB. Unprivileged accesses should definitely cause BusFaults (R_DQQS), but the behaviour of privileged accesses is not given as a general rule. However, the register definitions of individual registers for components like the DWT all state that they are RES0 if the relevant component is not implemented, so the simplest way to provide that is to provide RAZ/WI for the whole range for privileged accesses. (The v7M Arm ARM does say that reserved registers should be UNK/SBZP.) Expand the container MemoryRegion that the NVIC exposes so that it covers the whole PPB space. This means: * moving the address that the ARMV7M device maps it to down by 0xe000 bytes * moving the off and the offsets within the container of all the subregions forward by 0xe000 bytes * adding a new default MemoryRegion that covers the whole container at a lower priority than anything else and which provides the RAZWI/BusFault behaviour Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-2-peter.maydell@linaro.org --- include/hw/intc/armv7m_nvic.h | 1 + hw/arm/armv7m.c | 2 +- hw/intc/armv7m_nvic.c | 78 ++++++++++++++++++++++++++++++----- 3 files changed, 69 insertions(+), 12 deletions(-) diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index bb087b23c35..33b6d8810c7 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -84,6 +84,7 @@ struct NVICState { MemoryRegion systickmem; MemoryRegion systick_ns_mem; MemoryRegion container; + MemoryRegion defaultmem; =20 uint32_t num_irq; qemu_irq excpout; diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 8113b29f1fd..944f261dd05 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -225,7 +225,7 @@ static void armv7m_realize(DeviceState *dev, Error **er= rp) sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); =20 - memory_region_add_subregion(&s->container, 0xe000e000, + memory_region_add_subregion(&s->container, 0xe0000000, sysbus_mmio_get_region(sbd, 0)); =20 for (i =3D 0; i < ARRAY_SIZE(s->bitband); i++) { diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 42b1ad59e65..9628ce876e0 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2479,6 +2479,43 @@ static const MemoryRegionOps nvic_systick_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 +/* + * Unassigned portions of the PPB space are RAZ/WI for privileged + * accesses, and fault for non-privileged accesses. + */ +static MemTxResult ppb_default_read(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + qemu_log_mask(LOG_UNIMP, "Read of unassigned area of PPB: offset 0x%x\= n", + (uint32_t)addr); + if (attrs.user) { + return MEMTX_ERROR; + } + *data =3D 0; + return MEMTX_OK; +} + +static MemTxResult ppb_default_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, + MemTxAttrs attrs) +{ + qemu_log_mask(LOG_UNIMP, "Write of unassigned area of PPB: offset 0x%x= \n", + (uint32_t)addr); + if (attrs.user) { + return MEMTX_ERROR; + } + return MEMTX_OK; +} + +static const MemoryRegionOps ppb_default_ops =3D { + .read_with_attrs =3D ppb_default_read, + .write_with_attrs =3D ppb_default_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 8, +}; + static int nvic_post_load(void *opaque, int version_id) { NVICState *s =3D opaque; @@ -2675,7 +2712,6 @@ static void nvic_systick_trigger(void *opaque, int n,= int level) static void armv7m_nvic_realize(DeviceState *dev, Error **errp) { NVICState *s =3D NVIC(dev); - int regionlen; =20 /* The armv7m container object will have set our CPU pointer */ if (!s->cpu || !arm_feature(&s->cpu->env, ARM_FEATURE_M)) { @@ -2718,7 +2754,20 @@ static void armv7m_nvic_realize(DeviceState *dev, Er= ror **errp) M_REG_S)); } =20 - /* The NVIC and System Control Space (SCS) starts at 0xe000e000 + /* + * This device provides a single sysbus memory region which + * represents the whole of the "System PPB" space. This is the + * range from 0xe0000000 to 0xe00fffff and includes the NVIC, + * the System Control Space (system registers), the systick timer, + * and for CPUs with the Security extension an NS banked version + * of all of these. + * + * The default behaviour for unimplemented registers/ranges + * (for instance the Data Watchpoint and Trace unit at 0xe0001000) + * is to RAZ/WI for privileged access and BusFault for non-privileged + * access. + * + * The NVIC and System Control Space (SCS) starts at 0xe000e000 * and looks like this: * 0x004 - ICTR * 0x010 - 0xff - systick @@ -2741,32 +2790,39 @@ static void armv7m_nvic_realize(DeviceState *dev, E= rror **errp) * generally code determining which banked register to use should * use attrs.secure; code determining actual behaviour of the system * should use env->v7m.secure. + * + * The container covers the whole PPB space. Within it the priority + * of overlapping regions is: + * - default region (for RAZ/WI and BusFault) : -1 + * - system register regions : 0 + * - systick : 1 + * This is because the systick device is a small block of registers + * in the middle of the other system control registers. */ - regionlen =3D arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? 0x21000 : 0x= 1000; - memory_region_init(&s->container, OBJECT(s), "nvic", regionlen); - /* The system register region goes at the bottom of the priority - * stack as it covers the whole page. - */ + memory_region_init(&s->container, OBJECT(s), "nvic", 0x100000); + memory_region_init_io(&s->defaultmem, OBJECT(s), &ppb_default_ops, s, + "nvic-default", 0x100000); + memory_region_add_subregion_overlap(&s->container, 0, &s->defaultmem, = -1); memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s, "nvic_sysregs", 0x1000); - memory_region_add_subregion(&s->container, 0, &s->sysregmem); + memory_region_add_subregion(&s->container, 0xe000, &s->sysregmem); =20 memory_region_init_io(&s->systickmem, OBJECT(s), &nvic_systick_ops, s, "nvic_systick", 0xe0); =20 - memory_region_add_subregion_overlap(&s->container, 0x10, + memory_region_add_subregion_overlap(&s->container, 0xe010, &s->systickmem, 1); =20 if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s), &nvic_sysreg_ns_ops, &s->sysregmem, "nvic_sysregs_ns", 0x1000); - memory_region_add_subregion(&s->container, 0x20000, &s->sysreg_ns_= mem); + memory_region_add_subregion(&s->container, 0x2e000, &s->sysreg_ns_= mem); memory_region_init_io(&s->systick_ns_mem, OBJECT(s), &nvic_sysreg_ns_ops, &s->systickmem, "nvic_systick_ns", 0xe0); - memory_region_add_subregion_overlap(&s->container, 0x20010, + memory_region_add_subregion_overlap(&s->container, 0x2e010, &s->systick_ns_mem, 1); } =20 --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607601254; cv=none; d=zohomail.com; s=zohoarc; b=HbSTIzOzB9dTLyIRKtmXJ0UUfeYUFGXFr/xM2h2Az/VK6YWHHeOTcOW/PA2LcKB/6SdUbn29Af++vBJGfv4k0iostJZI3yb6wSJwlV3ZQMASMhIBgU5LqAHSp1sQjZERCzhIwerVc0hzstZhBw/zhHd1DubPDg5t8K6q34loz44= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607601254; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BigYO5HdCfFdu3P9A2wjZ5T3N7amcDFj0WcAvdbkd2A=; b=QzOsGbgKABWPU4q2eaCRY8Shb4ZJEP6uklxHOghisvT1ccpMkYzVKO6JLeL4vd1OBdf7ph6XyjFTpgX4IJ2170OG3KDO5kQ5+qHloGKO3UTNRDLtTtyOGWEa7WC0KMPM9mLVVfWkwEHmuGBNneTsghtp4ubjhQ3Nt2AxVzFbyQw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607601254038570.1027771399555; Thu, 10 Dec 2020 03:54:14 -0800 (PST) Received: from localhost ([::1]:45490 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKWS-0006kI-Qa for importer@patchew.org; Thu, 10 Dec 2020 06:54:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51304) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKR0-0001Su-LW for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:34 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:55639) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKQi-00073P-Jc for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:34 -0500 Received: by mail-wm1-x330.google.com with SMTP id x22so4369046wmc.5 for ; Thu, 10 Dec 2020 03:48:15 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=BigYO5HdCfFdu3P9A2wjZ5T3N7amcDFj0WcAvdbkd2A=; b=eyRrEEixygBpgaDIdnrJZG97Jc9ZavHXju/6hziKoq7IqqLYlm85woTYgKFeNzQ+F9 nOGdZIKBhTv1n/cc9fwjk5TblxQrLDbImZDLbYMyGuS50InfcX/VhZgPdV1lbK148VAG XuUSxkYDJBsOQ6ZJ//h5YP8mBRibihHOyas9z5nNxlJ1+5wsZ/u6lHvmTLPP+jrB2v+U IExdM3bPtTEJpqtKK3qIJhBDkN0FbPS26765wAKyWq8TvPnzh2/a6yZRnrrSEci8MxVe Fhx2VgkF3wfkHjnAv+yTnOz0jAQMkFm78WYZy/+IDw/KgZChr6II47dgE8S+9bwn0bW1 0s6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BigYO5HdCfFdu3P9A2wjZ5T3N7amcDFj0WcAvdbkd2A=; b=HZOiZal7GWhOutlcAzAIyUJ2/ys2D7pF8KkZZ60Qhay/Coeye/zWyd+kU0PMjG0+LJ npi7aKzz+x/NKcR+utl7qPTLjDLdQeNxIxpOfp+nTC8BP5IcVlh7w+u7F3DKq2FozHCM Scvr8WL2eYOV8bq1P66UrBISBGJH0FOfCFrVLT60HboIju0J92yJkiOS+s9UraOnFQRS uPot0CqVMPhRY+GdulSmBHq1ccyF9zc8IF6/+zR1ENgJkpSrGMTRS2m00s3tIA0L/Pe6 q1TnPWWj1E5Cf1B+pYyfONSEg08jpaau8Mxp9Ts6Qr2fq+lx0ncICFVvS9MBHlgWnYv+ EcnQ== X-Gm-Message-State: AOAM533TPsEeMoSVhVM6UEoeWyD0ntGVLpIPf7yUL3OjHqi+7xD+KY2W Vx5FH+JhukP/yxMqy9fiAbPtXYwUD5gXWA== X-Google-Smtp-Source: ABdhPJwbVomU9zkiOHe/MqvIuERnCIG1fsSLf6FzJlC904RZpghtK6NGBqRrwoLJ0YjqPc0L/nPOIg== X-Received: by 2002:a1c:df57:: with SMTP id w84mr7726878wmg.37.1607600893995; Thu, 10 Dec 2020 03:48:13 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/36] target/arm: Implement v8.1M PXN extension Date: Thu, 10 Dec 2020 11:47:33 +0000 Message-Id: <20201210114756.16501-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In v8.1M the PXN architecture extension adds a new PXN bit to the MPU_RLAR registers, which forbids execution of code in the region from a privileged mode. This is another feature which is just in the generic "in v8.1M" set and has no ID register field indicating its presence. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-3-peter.maydell@linaro.org --- target/arm/helper.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 38cd35c0492..7b8bcd69030 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11754,6 +11754,11 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t = address, } else { uint32_t ap =3D extract32(env->pmsav8.rbar[secure][matchregion], 1= , 2); uint32_t xn =3D extract32(env->pmsav8.rbar[secure][matchregion], 0= , 1); + bool pxn =3D false; + + if (arm_feature(env, ARM_FEATURE_V8_1M)) { + pxn =3D extract32(env->pmsav8.rlar[secure][matchregion], 4, 1); + } =20 if (m_is_system_region(env, address)) { /* System space is always execute never */ @@ -11761,7 +11766,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t a= ddress, } =20 *prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap); - if (*prot && !xn) { + if (*prot && !xn && !(pxn && !is_user)) { *prot |=3D PAGE_EXEC; } /* We don't need to look the attribute up in the MAIR0/MAIR1 --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607603312; cv=none; d=zohomail.com; s=zohoarc; b=PN5yU0xXluWV9z+j4OmIV+TlaXbHYjKEBuYGG5cGHbYrHxu65ynNisbc1+GISOernOkADSJhBM0/riTcezhaJ42xdlCYsS22oSWpQtHh9NmEGUEaDJRsGSzorBrXa9DCfIVX6os1UW65SxQ5QlVDIOkJE/rTIWVeSfqDOLsonxo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607603312; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=mcv/XrXC4b0o58at+mfsbi4y+Psa/cPzkJdZahv1VmE=; b=IT49RNWAqZIUsrfD4A0WuZ6NnNzs4ez4+JmnN+EQN0TIlXn2YpZy+durdQ3fIWyIpz/v2QT+FWOZHaZzIZ1f8jTrU21akGY822WJfLulT6ItXvpLzD6ZmwAcyo9A83NR8dhhroHoltM8A/MWWPa8ItxzpI5mHm7HK9ixd6tG7nA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607603312159879.5972347280125; Thu, 10 Dec 2020 04:28:32 -0800 (PST) Received: from localhost ([::1]:35308 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKo7-0000qC-Dc for importer@patchew.org; Thu, 10 Dec 2020 07:12:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51324) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKR1-0001UH-Hj for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:35 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:39823) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKQj-00074Q-2L for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:35 -0500 Received: by mail-wr1-x42b.google.com with SMTP id c5so1532583wrp.6 for ; Thu, 10 Dec 2020 03:48:16 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=mcv/XrXC4b0o58at+mfsbi4y+Psa/cPzkJdZahv1VmE=; b=ZsKRt/A8Don/Cr6ShGiYancdWtH3ZUmxbpmzeFUR298iqwqjkOhFHdVTKwdhFn1x5Y gIxHMUxPL/DBp/Pa4k6W7g+IPlUmkv2yqzDrpegp8uE5OZAx3U7y11PWcMIyUGFfLYhA hXSS/uAwl3UiBcgct8ofM5pgYZ84nUbtd/3QIXBekBADCWC+8sJxXhCl+u8fMobjuzTy k1rX6UGOV/cF2bkj/s51OZ61hElrDi0JnkBW2tX0QTmAvlK0dv9Tcqbwdm+h3qPuEhan 4N8CRlTiDnwXzGfv1DfE7DkDFdJRrp4Czxu6tYn9ZtubKrrUFJLhpUonnqEa0tSZshwb ymzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mcv/XrXC4b0o58at+mfsbi4y+Psa/cPzkJdZahv1VmE=; b=TSEkn+FEr6R9eJwgFIY47j+34H+tdy1f/UgEGgHNYMHr3qKVX3qPT/vUgWAwklacSu BnQQNCN3OHn14cl6JIKuOWmA8A/UW29kuYjqiGmy08ZMKBJAdFxYZOxb+JBj8qWjj63o 94U5OfIoOSp2BekPrMYT+LsDE5xvOZTWh6bAMtvuTkHeTbzoagSgIxGLSl/kYRzD0mal F04D+0A1e6hi8jURyurIr9XQrEDrk65cVXQWqO6d7NRA0eXppf9Bga1CnrEHbCk6RNdS bPHsEb+BpYpv+G998Il1HcMPH90rP6i0Q8Ubv0NB+cnttXoJfPXaxmz/G6eYz2bXpySd kPWw== X-Gm-Message-State: AOAM530ns+TBHYNsmEsxKjmJXTESDHNyGuas5/pUp0bOX+cCo6oAIjMr XkuoLezEXgvtRpBzho2sWgUcjv0SujDG2A== X-Google-Smtp-Source: ABdhPJw8D1+VAM8VCOD17Qsx9sH+s9prDOVKWJR+lozgYFREcTdkZWh/Gl0u0v2JFEWmv3qFPmAWzw== X-Received: by 2002:adf:d085:: with SMTP id y5mr2159035wrh.41.1607600895516; Thu, 10 Dec 2020 03:48:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/36] target/arm: Don't clobber ID_PFR1.Security on M-profile cores Date: Thu, 10 Dec 2020 11:47:34 +0000 Message-Id: <20201210114756.16501-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In arm_cpu_realizefn() we check whether the board code disabled EL3 via the has_el3 CPU object property, which we create if the CPU starts with the ARM_FEATURE_EL3 feature bit. If it is disabled, then we turn off ARM_FEATURE_EL3 and also zero out the relevant fields in the ID_PFR1 and ID_AA64PFR0 registers. This codepath was incorrectly being taken for M-profile CPUs, which do not have an EL3 and don't set ARM_FEATURE_EL3, but which may have the M-profile Security extension and so should have non-zero values in the ID_PFR1.Security field. Restrict the handling of the feature flag to A/R-profile cores. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-4-peter.maydell@linaro.org --- target/arm/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 07492e9f9a4..40f3f798b2b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1674,7 +1674,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) } } =20 - if (!cpu->has_el3) { + if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { /* If the has_el3 CPU property is disabled then we need to disable= the * feature. */ --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607603036; cv=none; d=zohomail.com; s=zohoarc; b=RWrs4fEOfXyeX11BH2YFx7NiwTrDpYcCj8koHByUvIKTj0E3jFSzPIaczvGAZYYbRYXDt7by+NjXpqEk7u5MeptPD3KPiMLJRWlLSrORLRViJI9JIT8G/ir4Yt5KizxeV17ZLsIy96BghkAQDobXDH9aA2yy8Asrt6iOLMk1y7c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607603036; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Af8GvxZMcrjzyfwJIHGDTyViExTE+D3Q+RDUgzSTiS0=; b=J1SA2+v0IMgYti33syT/Fs3RO5+1SWHriw8K8NJTp4hVFK9RjdLlPgkJL5fwg3m6IFZ73CCpZKgV/XiyO5h+06vWjnSevk7wBy3L4r/ACxibg3WVWlGOdZFKbHkKzRP/5mbMM1qm6+bSICb2VDSZQYK+kcbJ44IvmlxJglZ4uY8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607603036801901.0373923519691; Thu, 10 Dec 2020 04:23:56 -0800 (PST) Received: from localhost ([::1]:43896 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKqs-0004X6-4A for importer@patchew.org; Thu, 10 Dec 2020 07:15:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51356) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKR2-0001WS-Ri for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:36 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:32929) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKQk-00074f-LD for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:36 -0500 Received: by mail-wm1-x32b.google.com with SMTP id w206so2617060wma.0 for ; Thu, 10 Dec 2020 03:48:17 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Af8GvxZMcrjzyfwJIHGDTyViExTE+D3Q+RDUgzSTiS0=; b=FdBWQVGQCFPIdLiIucg3Xcsl9AZ3wO3Ii+kzi0sO0cZ9zR6pM1hd1XXyDq427N7JJs dnym9q65nHRdrPp1t99KvbO+rCWpas0CYI31q32tG9QCMHJ/Xq2AtMyV7fZMMvr7RUz5 gt46VCutWscwVS6BwtmPODYYJwSYGOfp0PsmyFx4/6LqzA2qXR/ibVWWcIVv5ulX4Br7 E/gFoMkwZxm37o3t0qjK9SL5l0WoGxXi2rDPIc/4uvBGikHd77E+sst8OFFnopZilQmX IeZdTzGe1UpwATRVYYnhQ18YDgByndsD3TPXeLh6h+V/MZYcO8KK0xc7LJkglFz9Mty7 wNmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Af8GvxZMcrjzyfwJIHGDTyViExTE+D3Q+RDUgzSTiS0=; b=T3OduZRzxjjHpvhWKA19Wes+0AfUdRXP+m8xm2D8i9n/YbmfEd8P73d6u5j1wSmys5 qvLqEHwbccVstcQyKV8EeB/0LY5WVTN9/U4EmTz2hUF82mPu6IVPDr938jjv+foFRJFn S6FzW/DgUU6lfqW/8C7/kI5SbYq2v4XEOB0m8eSchKdGgbexUL23dmvrd+yhzuHEAOn6 Jc9ew7W6jL+XgsKGzMqWhXjajbWOQM6E2OjwXLLfZ/qKPtJ0lJW4lUYf+GvxPVsFfgKt A7+Igl4DClFb9rUZY/kGC5P+pnIq3H7Y9p6TtmjMH7dkiG2w1AHm9jEXaRF9nW+bz9Dz Khbw== X-Gm-Message-State: AOAM532t5wDUyyni31NU4py/IfBZ+obNWsW3K/nEjv+ep32RjF07Pjtt 2lD7uVpBBZcNvlEJONJU0HrcY9cI50W5PQ== X-Google-Smtp-Source: ABdhPJwcSbFIjO4VsY/McjCxKPC6D2Kkvc2pjoh94wUfJ5vctcxGlDRWV/kVcc+VFxhVAhoz116Xkw== X-Received: by 2002:a1c:2cc2:: with SMTP id s185mr7585121wms.111.1607600896639; Thu, 10 Dec 2020 03:48:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/36] target/arm: Implement VSCCLRM insn Date: Thu, 10 Dec 2020 11:47:35 +0000 Message-Id: <20201210114756.16501-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the v8.1M VSCCLRM insn, which zeros floating point registers if there is an active floating point context. This requires support in write_neon_element32() for the MO_32 element size, so add it. Because we want to use arm_gen_condlabel(), we need to move the definition of that function up in translate.c so it is before the #include of translate-vfp.c.inc. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-5-peter.maydell@linaro.org --- target/arm/cpu.h | 9 ++++ target/arm/m-nocp.decode | 8 +++- target/arm/translate.c | 21 +++++---- target/arm/translate-vfp.c.inc | 84 ++++++++++++++++++++++++++++++++++ 4 files changed, 111 insertions(+), 11 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e5514c82862..11400a9d248 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3555,6 +3555,15 @@ static inline bool isar_feature_aa32_mprofile(const = ARMISARegisters *id) return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) !=3D 0; } =20 +static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) +{ + /* + * Return true if M-profile state handling insns + * (VSCCLRM, CLRM, FPCTX access insns) are implemented + */ + return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >=3D 3; +} + static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) { /* Sadly this is encoded differently for A-profile and M-profile */ diff --git a/target/arm/m-nocp.decode b/target/arm/m-nocp.decode index 28c8ac6b94c..ccd62e8739a 100644 --- a/target/arm/m-nocp.decode +++ b/target/arm/m-nocp.decode @@ -29,13 +29,17 @@ # If the coprocessor is not present or disabled then we will generate # the NOCP exception; otherwise we let the insn through to the main decode. =20 +%vd_dp 22:1 12:4 +%vd_sp 12:4 22:1 + &nocp cp =20 { # Special cases which do not take an early NOCP: VLLDM and VLSTM VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000 - # TODO: VSCCLRM (new in v8.1M) is similar: - #VSCCLRM 1110 1100 1-01 1111 ---- 1011 ---- ---0 + # VSCCLRM (new in v8.1M) is similar: + VSCCLRM 1110 1100 1.01 1111 .... 1011 imm:7 0 vd=3D%vd_dp size=3D3 + VSCCLRM 1110 1100 1.01 1111 .... 1010 imm:8 vd=3D%vd_sp size=3D2 =20 NOCP 111- 1110 ---- ---- ---- cp:4 ---- ---- &nocp NOCP 111- 110- ---- ---- ---- cp:4 ---- ---- &nocp diff --git a/target/arm/translate.c b/target/arm/translate.c index 6d04ca3a8a0..9f2b6018a21 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -100,6 +100,15 @@ void arm_translate_init(void) a64_translate_init(); } =20 +/* Generate a label used for skipping this instruction */ +static void arm_gen_condlabel(DisasContext *s) +{ + if (!s->condjmp) { + s->condlabel =3D gen_new_label(); + s->condjmp =3D 1; + } +} + /* Flags for the disas_set_da_iss info argument: * lower bits hold the Rt register number, higher bits are flags. */ @@ -1221,6 +1230,9 @@ static void write_neon_element64(TCGv_i64 src, int re= g, int ele, MemOp memop) long off =3D neon_element_offset(reg, ele, memop); =20 switch (memop) { + case MO_32: + tcg_gen_st32_i64(src, cpu_env, off); + break; case MO_64: tcg_gen_st_i64(src, cpu_env, off); break; @@ -5156,15 +5168,6 @@ static void gen_srs(DisasContext *s, s->base.is_jmp =3D DISAS_UPDATE_EXIT; } =20 -/* Generate a label used for skipping this instruction */ -static void arm_gen_condlabel(DisasContext *s) -{ - if (!s->condjmp) { - s->condlabel =3D gen_new_label(); - s->condjmp =3D 1; - } -} - /* Skip this instruction if the ARM condition is false */ static void arm_skip_unless(DisasContext *s, uint32_t cond) { diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 96948f5a2d3..2a67ed0f6e2 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -3406,6 +3406,90 @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_V= LLDM_VLSTM *a) return true; } =20 +static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a) +{ + int btmreg, topreg; + TCGv_i64 zero; + TCGv_i32 aspen, sfpa; + + if (!dc_isar_feature(aa32_m_sec_state, s)) { + /* Before v8.1M, fall through in decode to NOCP check */ + return false; + } + + /* Explicitly UNDEF because this takes precedence over NOCP */ + if (!arm_dc_feature(s, ARM_FEATURE_M_MAIN) || !s->v8m_secure) { + unallocated_encoding(s); + return true; + } + + if (!dc_isar_feature(aa32_vfp_simd, s)) { + /* NOP if we have neither FP nor MVE */ + return true; + } + + /* + * If FPCCR.ASPEN !=3D 0 && CONTROL_S.SFPA =3D=3D 0 then there is no + * active floating point context so we must NOP (without doing + * any lazy state preservation or the NOCP check). + */ + aspen =3D load_cpu_field(v7m.fpccr[M_REG_S]); + sfpa =3D load_cpu_field(v7m.control[M_REG_S]); + tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); + tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); + tcg_gen_andi_i32(sfpa, sfpa, R_V7M_CONTROL_SFPA_MASK); + tcg_gen_or_i32(sfpa, sfpa, aspen); + arm_gen_condlabel(s); + tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel); + + if (s->fp_excp_el !=3D 0) { + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), s->fp_excp_el); + return true; + } + + topreg =3D a->vd + a->imm - 1; + btmreg =3D a->vd; + + /* Convert to Sreg numbers if the insn specified in Dregs */ + if (a->size =3D=3D 3) { + topreg =3D topreg * 2 + 1; + btmreg *=3D 2; + } + + if (topreg > 63 || (topreg > 31 && !(topreg & 1))) { + /* UNPREDICTABLE: we choose to undef */ + unallocated_encoding(s); + return true; + } + + /* Silently ignore requests to clear D16-D31 if they don't exist */ + if (topreg > 31 && !dc_isar_feature(aa32_simd_r32, s)) { + topreg =3D 31; + } + + if (!vfp_access_check(s)) { + return true; + } + + /* Zero the Sregs from btmreg to topreg inclusive. */ + zero =3D tcg_const_i64(0); + if (btmreg & 1) { + write_neon_element64(zero, btmreg >> 1, 1, MO_32); + btmreg++; + } + for (; btmreg + 1 <=3D topreg; btmreg +=3D 2) { + write_neon_element64(zero, btmreg >> 1, 0, MO_64); + } + if (btmreg =3D=3D topreg) { + write_neon_element64(zero, btmreg >> 1, 0, MO_32); + btmreg++; + } + assert(btmreg =3D=3D topreg + 1); + /* TODO: when MVE is implemented, zero VPR here */ + return true; +} + static bool trans_NOCP(DisasContext *s, arg_nocp *a) { /* --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607601468; cv=none; d=zohomail.com; s=zohoarc; b=gpyEJr2uhCU/cP0wey2LiIs0ji+TRGbQIp+UrPavyZqqeSgAvAo/TIJwcA0WZnV/EwPo51Zo7F1KpFY81g5fYDoMtKKuWWe51FntDdIZ3Gu0cjr4yIt0lVyU+9/LnaDUfo/4DKbeSPXLRX1pmvMvDgUazxWGh/2iv5iO0+ciRD8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607601468; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CzFRHLXYHbAS+zng3Ry2pyEty5FizGBShW7cxULP69c=; b=njvvnGmHbjcydUErbb2EGXFz4yNPn3OwZUwTcO04bgglXzBtp8nTJADZ0/noIR75VICUKXYULufL+bO4V6INt8sVKQUFAN1BQmL0/tUaeCoqk2VIxt9quqfqgGN/Qwc26IAhXVecMmEK39W8KlbgeckL8ZlycAAp/O3cNSTtsaM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 160760146858693.71620871269533; Thu, 10 Dec 2020 03:57:48 -0800 (PST) Received: from localhost ([::1]:54184 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKZv-0001xc-FZ for importer@patchew.org; Thu, 10 Dec 2020 06:57:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51332) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKR2-0001Uw-2C for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:36 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:40138) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKQm-00075u-Ft for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:35 -0500 Received: by mail-wm1-x331.google.com with SMTP id a3so4988066wmb.5 for ; Thu, 10 Dec 2020 03:48:18 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=CzFRHLXYHbAS+zng3Ry2pyEty5FizGBShW7cxULP69c=; b=amsbYZGgtpOozFCidXkYouBgpB4n7YFkvp5kJAok4R9Krc9FKtX+t5k3UTZZSh1I1y nZolu+4MGWnC9mG5Vu8axZM8v3eOa2WNy9585ejjTCqr4l3in38CUYpm6YqIU2LhlmRY kObs0Cb+EpvtDrO35x6w1dSDaPRMLzZa1T5yzEnRigjSoks9a/+F0JlXBuAEDJnxGVIn l8bLpA0gd/sre90VABkVxI9rvU6IUtPbfXubKHp32lQvBk3ViAraTc/fRNwkMc3LlaVP XkKcm7hVNNKUyXlzYVYvLE0knP/SqDQoMq9GKi3r9La+96DiuiFWWrvq/dR29Bb5075c RlFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CzFRHLXYHbAS+zng3Ry2pyEty5FizGBShW7cxULP69c=; b=eoqlP0PoW/+YwchOX6qzyyBc1ZpvvkMj+P/Sg72FyhxkAudiqHDeINXgdUAuPqfcHG XyRSUteOmt+2aheZVrdm7FVmBvbKhFfhfXaQaltI8Fm8jo0FGT3SLMsx2RIOYevqPiaF 3wLmx3bqQ1+An/lEob0mnj91FRWVlTVQBtktRf5oTC2EtRTndb9Oh1vJKyr9xTHBXpvg 7GtNzueeGPR7cETjgcnaNRvPfLjuBzOpguggmMbTqhBfE5/Za7eHs6Tjg4bP4JC1cCZ2 mEam8EGTxBEV1oZYxOEBeeSQ4KLhb/lw8wRfS9OnDLrTyCZQBrCT3wZUZhiNDxWm/has rR2Q== X-Gm-Message-State: AOAM532trB2FKS2hBjJ0bxCScRNW3y5u+CXbO+6/J6OvKwYAvaYijssF iJnIVEpk+cHt1M22p2U/62nxpnYvU3GhzQ== X-Google-Smtp-Source: ABdhPJzTw7vKi7FlhTgSjNaDadl6lvdzFQyMRe157fVqKFHdyfJ3ypOuO75M97WSoFA8Tob5B0FVOQ== X-Received: by 2002:a1c:46c5:: with SMTP id t188mr7796849wma.3.1607600897619; Thu, 10 Dec 2020 03:48:17 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/36] target/arm: Implement CLRM instruction Date: Thu, 10 Dec 2020 11:47:36 +0000 Message-Id: <20201210114756.16501-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In v8.1M the new CLRM instruction allows zeroing an arbitrary set of the general-purpose registers and APSR. Implement this. The encoding is a subset of the LDMIA T2 encoding, using what would be Rn=3D0b1111 (which UNDEFs for LDMIA). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-6-peter.maydell@linaro.org --- target/arm/t32.decode | 6 +++++- target/arm/translate.c | 38 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+), 1 deletion(-) diff --git a/target/arm/t32.decode b/target/arm/t32.decode index cfcc71bfb0a..f045eb62c84 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -609,7 +609,11 @@ UXTAB 1111 1010 0101 .... 1111 .... 10.. ..= .. @rrr_rot =20 STM_t32 1110 1000 10.0 .... ................ @ldstm i=3D1= b=3D0 STM_t32 1110 1001 00.0 .... ................ @ldstm i=3D0= b=3D1 -LDM_t32 1110 1000 10.1 .... ................ @ldstm i=3D1= b=3D0 +{ + # Rn=3D15 UNDEFs for LDM; M-profile CLRM uses that encoding + CLRM 1110 1000 1001 1111 list:16 + LDM_t32 1110 1000 10.1 .... ................ @ldstm i=3D1= b=3D0 +} LDM_t32 1110 1001 00.1 .... ................ @ldstm i=3D0= b=3D1 =20 &rfe !extern rn w pu diff --git a/target/arm/translate.c b/target/arm/translate.c index 9f2b6018a21..47a1a5739c8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7968,6 +7968,44 @@ static bool trans_LDM_t16(DisasContext *s, arg_ldst_= block *a) return do_ldm(s, a, 1); } =20 +static bool trans_CLRM(DisasContext *s, arg_CLRM *a) +{ + int i; + TCGv_i32 zero; + + if (!dc_isar_feature(aa32_m_sec_state, s)) { + return false; + } + + if (extract32(a->list, 13, 1)) { + return false; + } + + if (!a->list) { + /* UNPREDICTABLE; we choose to UNDEF */ + return false; + } + + zero =3D tcg_const_i32(0); + for (i =3D 0; i < 15; i++) { + if (extract32(a->list, i, 1)) { + /* Clear R[i] */ + tcg_gen_mov_i32(cpu_R[i], zero); + } + } + if (extract32(a->list, 15, 1)) { + /* + * Clear APSR (by calling the MSR helper with the same argument + * as for "MSR APSR_nzcvqg, Rn": mask =3D 0b1100, SYSM=3D0) + */ + TCGv_i32 maskreg =3D tcg_const_i32(0xc << 8); + gen_helper_v7m_msr(cpu_env, maskreg, zero); + tcg_temp_free_i32(maskreg); + } + tcg_temp_free_i32(zero); + return true; +} + /* * Branch, branch with link */ --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607601456; cv=none; d=zohomail.com; s=zohoarc; b=UsGZUPBes7OpAaAqpCp3laNBwkCFBg7eHYOQbiFYwHFR75Itp1wgJAYmjnNCY3H4bGlN90AZoIdKSzq+sQN5a5Nf467NiHhYWZHSY9dpu63sh4yi1aMny0gHds1CBVkIP1NzAbsACWZ6DoIqcR5NUcfe9jlEpZbxaIItlBG2jCA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607601456; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9ceDHVjskAUjyg+VpK8LBhowzV630zUBK2XJK3tLmPA=; b=CyC10HFYil0EoUy3818mNzBQfoi0zQ2346XLHb4tsQgGPu/GxiK5jc0mIoC6987t5Uyzd/OALe4lxB0EATQglSzFZI34sVb9+mAcBEx5kf96e4ton7jACsp8j1S84NGfHiIcbqLhSAaWfo2uyP/KyKWmqWCBJZErZZQWkjyLJUY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607601456765827.7280203215897; Thu, 10 Dec 2020 03:57:36 -0800 (PST) Received: from localhost ([::1]:53768 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKZj-0001nL-Mb for importer@patchew.org; Thu, 10 Dec 2020 06:57:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51348) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKR2-0001Vc-FB for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:36 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:34856) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKQm-00076V-GQ for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:36 -0500 Received: by mail-wm1-x32e.google.com with SMTP id e25so5000312wme.0 for ; Thu, 10 Dec 2020 03:48:19 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=9ceDHVjskAUjyg+VpK8LBhowzV630zUBK2XJK3tLmPA=; b=BlafwE25/i4HwUcBvX88FA4j0kAxiP7lwxCYRSwgv+LpxE7G2D5Fou7SRb6FbY/J15 jW/bM8CkKY/IbPghfJVpMlptEnTMu1wc4xLgSJhcSVDm/jAo4ELz91sM+7Gmk3B08Ghi 4OepaIucdJvzhrbX1NjV3B70wcALSFkCzlzbahGVVks0dxmy4N9+iqwaAJnJzHyqVf/D jHHXNzI1RSp6u27FOLynbH1TNbPMHeI84i++7BaLGJmw/x6r62PLu8sy6999LNc7XOW8 Dr+SV4k1jwztoqcve4wicpgEZCGbUweNa1AuWnB58Aq3Gw7gd9plZqlnyhj7MjIJFlKP bH6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9ceDHVjskAUjyg+VpK8LBhowzV630zUBK2XJK3tLmPA=; b=MJUxFhmmVB4dso0zMgBD1QK1C91pMdD2CLz3wL88qE3qJKPKfCc4pDRVttS/1CCUzB Y77M8ccGhJaVJ6/4l2ntyfju3a1JeZZqN/W38j8ch/gTi0kJnvT1l69sxvU/8LfeHqg/ LsPzgtIjFDpuWnjLt55AE2TnIrjZdYPpN2rYYMKNO9aCnsZw7tUnaySyEcVe4P4lnTAG Ge3aqf1A4wjr7zHmPo5zssmdCrZ+tutGk8q2kIhvzItBX8NygtbotyexNzGoCrD6LRc4 5Xa2AZxIumeQHMHcmwYKmhoXr4wY3rmTt15id+l/AKfWUiUHYhh2HME8xqoCDycLXxVZ 6JpA== X-Gm-Message-State: AOAM533JcM7AKMOZJbLLQSMCNYj/EH2kaxRHklfE4vuQyhlqrWDUsbNv URZn6f4QPyqziXoGPI9NKegNAGi//Ul+9w== X-Google-Smtp-Source: ABdhPJxMdgh9iNjz/u4zE5Lcct8sLTuqFMmuIwUsesI0tseDYihq9Qo0u5bJvKQMOhZiEFEJFw90Zw== X-Received: by 2002:a1c:741a:: with SMTP id p26mr8012032wmc.47.1607600898584; Thu, 10 Dec 2020 03:48:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/36] target/arm: Enforce M-profile VMRS/VMSR register restrictions Date: Thu, 10 Dec 2020 11:47:37 +0000 Message-Id: <20201210114756.16501-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" For M-profile before v8.1M, the only valid register for VMSR/VMRS is the FPSCR. We have a comment that states this, but the actual logic to forbid accesses for any other register value is missing, so we would end up with A-profile style behaviour. Add the missing check. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-7-peter.maydell@linaro.org --- target/arm/translate-vfp.c.inc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 2a67ed0f6e2..e100182a32c 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -622,7 +622,10 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_= VMRS *a) * Accesses to R15 are UNPREDICTABLE; we choose to undef. * (FPSCR -> r15 is a special case which writes to the PSR flags.) */ - if (a->rt =3D=3D 15 && (!a->l || a->reg !=3D ARM_VFP_FPSCR)) { + if (a->reg !=3D ARM_VFP_FPSCR) { + return false; + } + if (a->rt =3D=3D 15 && !a->l) { return false; } } --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607601667; cv=none; d=zohomail.com; s=zohoarc; b=P1zGVkXo4U2zhiZEuxmwduppz9S5pxpfcPHZ0miasXoTSLkbYEGI04VVVIxNrb3oDA8zZjXTcQYjPv8mVgWgSRnLnJ/nKpkBBGKLx/l1eCGuwrwbOCJlVdIM/E2YmJDhsJuQZzxDKgIVohoiCWYOFbYbDyb5kPVVP6b4VkJPfBQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607601667; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Kf6SvkRVMY6oZcYZ8wg1EY7jkVpy7B/pu1pTCaT3ND4=; b=ZMh9iE6BHy16ebdV7VyBqKI2IMf9JxNkHa8cUUOywx2btmruBIUhIu6XQGz703W3uvfXYbl/YKq89507mk1Dex/RrDJNHbt6IFg3of9qgA0cGUDwrMe43oisrIY2mxGCuYtWwd8Y21O6WAem8dFuawkbcJl4Ir8HQijuF2YFV/U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16076016674491017.4403493966203; Thu, 10 Dec 2020 04:01:07 -0800 (PST) Received: from localhost ([::1]:33930 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKd5-0005Fm-7i for importer@patchew.org; Thu, 10 Dec 2020 07:01:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51382) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKR3-0001Xe-UC for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:37 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:52155) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKQo-00076v-DE for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:37 -0500 Received: by mail-wm1-x334.google.com with SMTP id v14so4386918wml.1 for ; Thu, 10 Dec 2020 03:48:20 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Kf6SvkRVMY6oZcYZ8wg1EY7jkVpy7B/pu1pTCaT3ND4=; b=Bv+cP1u2W7RsEhwXTHdJhMb15PzcFSbUwTCo+iP6L6Xe4NazBtKkM5Ji3d+CXLQQIj kHdvmCTGCC71aZit2LPb9rMZ1YoqNwX+cS0uPMot2XLHRA3WniYcqIAUqSBcV7D0LaNY Tr2NiaVwvEvdYu2tWQ8DIZgu2ofwu/X5MLm5ysDkJ6e6MLNZdzqIq1kbwyCxd2qr+IS+ sQx6811GbgH9XMMvut2GIL0+NgF4/HLYFNF0UhUPXREr5chhZqAvdXyyB7z/zkqbq05c XUoGg7Ul4o1wt8dGyPCbzUdkK8OKlLHv7JaU0sC/ur01QtdDkDktyiJSTna61rX8F63Z 9zSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Kf6SvkRVMY6oZcYZ8wg1EY7jkVpy7B/pu1pTCaT3ND4=; b=IGYcUwJNDo4UbOPp4H22hUaEuW/KsN3mIe7sg2iY2tPs8caGPhG0xxy/1trSRCTNod Jxg+Eg7lCREho+D3v0Qbvo//KPdDlSwwJRVLprg4fAGD27KrOZoULBwjJvoAXgYYsuNH F3TzxvdfA8H7DPB9Gt6S88YkSLL9tenUoWS7J7DvBadA+IkeIUJFX55i/UjUqE0vswJx R2uzHTS4dDAK55qu1nB5efXl4n3RA9oAGJdtBnyobewAV5FSMUbhJq3LNpFYCQGRiSG5 Q8DoGMuDnwMwXD8DEMCEsRSV5MRaaRBAb6Xe7tW/PgGNi81c+KGPzIbzDzcAXaONSr8W CBYQ== X-Gm-Message-State: AOAM530p/f6W0VoudApT5prC8Cpo1C3wFJB7tzzZ1uVfyPHpZuZ830kx Cg16ofInfkupdYwERy7H+/mLnm0ym4y77w== X-Google-Smtp-Source: ABdhPJzeM6QElKzQ90muv8N1rVXqjuh7fGc52F82QWVO7KJe9o4HGmFmvjyC7BdX5re/GghNgS6eVA== X-Received: by 2002:a1c:f002:: with SMTP id a2mr7703264wmb.101.1607600899699; Thu, 10 Dec 2020 03:48:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/36] target/arm: Refactor M-profile VMSR/VMRS handling Date: Thu, 10 Dec 2020 11:47:38 +0000 Message-Id: <20201210114756.16501-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Currently M-profile borrows the A-profile code for VMSR and VMRS (access to the FP system registers), because all it needs to support is the FPSCR. In v8.1M things become significantly more complicated in two ways: * there are several new FP system registers; some have side effects on read, and one (FPCXT_NS) needs to avoid the usual vfp_access_check() and the "only if FPU implemented" check * all sysregs are now accessible both by VMRS/VMSR (which reads/writes a general purpose register) and also by VLDR/VSTR (which reads/writes them directly to memory) Refactor the structure of how we handle VMSR/VMRS to cope with this: * keep the M-profile code entirely separate from the A-profile code * abstract out the "read or write the general purpose register" part of the code into a loadfn or storefn function pointer, so we can reuse it for VLDR/VSTR. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-8-peter.maydell@linaro.org --- target/arm/cpu.h | 3 + target/arm/translate-vfp.c.inc | 182 ++++++++++++++++++++++++++++++--- 2 files changed, 171 insertions(+), 14 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 11400a9d248..ad8b80c667d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1569,6 +1569,9 @@ enum arm_cpu_mode { #define ARM_VFP_FPINST 9 #define ARM_VFP_FPINST2 10 =20 +/* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ +#define QEMU_VFP_FPSCR_NZCV 0xffff + /* iwMMXt coprocessor control registers. */ #define ARM_IWMMXT_wCID 0 #define ARM_IWMMXT_wCon 1 diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index e100182a32c..7a0cbca6640 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -607,27 +607,181 @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a) return true; } =20 +/* + * M-profile provides two different sets of instructions that can + * access floating point system registers: VMSR/VMRS (which move + * to/from a general purpose register) and VLDR/VSTR sysreg (which + * move directly to/from memory). In some cases there are also side + * effects which must happen after any write to memory (which could + * cause an exception). So we implement the common logic for the + * sysreg access in gen_M_fp_sysreg_write() and gen_M_fp_sysreg_read(), + * which take pointers to callback functions which will perform the + * actual "read/write general purpose register" and "read/write + * memory" operations. + */ + +/* + * Emit code to store the sysreg to its final destination; frees the + * TCG temp 'value' it is passed. + */ +typedef void fp_sysreg_storefn(DisasContext *s, void *opaque, TCGv_i32 val= ue); +/* + * Emit code to load the value to be copied to the sysreg; returns + * a new TCG temporary + */ +typedef TCGv_i32 fp_sysreg_loadfn(DisasContext *s, void *opaque); + +/* Common decode/access checks for fp sysreg read/write */ +typedef enum FPSysRegCheckResult { + FPSysRegCheckFailed, /* caller should return false */ + FPSysRegCheckDone, /* caller should return true */ + FPSysRegCheckContinue, /* caller should continue generating code */ +} FPSysRegCheckResult; + +static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno) +{ + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return FPSysRegCheckFailed; + } + + switch (regno) { + case ARM_VFP_FPSCR: + case QEMU_VFP_FPSCR_NZCV: + break; + default: + return FPSysRegCheckFailed; + } + + if (!vfp_access_check(s)) { + return FPSysRegCheckDone; + } + + return FPSysRegCheckContinue; +} + +static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, + + fp_sysreg_loadfn *loadfn, + void *opaque) +{ + /* Do a write to an M-profile floating point system register */ + TCGv_i32 tmp; + + switch (fp_sysreg_checks(s, regno)) { + case FPSysRegCheckFailed: + return false; + case FPSysRegCheckDone: + return true; + case FPSysRegCheckContinue: + break; + } + + switch (regno) { + case ARM_VFP_FPSCR: + tmp =3D loadfn(s, opaque); + gen_helper_vfp_set_fpscr(cpu_env, tmp); + tcg_temp_free_i32(tmp); + gen_lookup_tb(s); + break; + default: + g_assert_not_reached(); + } + return true; +} + +static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, + fp_sysreg_storefn *storefn, + void *opaque) +{ + /* Do a read from an M-profile floating point system register */ + TCGv_i32 tmp; + + switch (fp_sysreg_checks(s, regno)) { + case FPSysRegCheckFailed: + return false; + case FPSysRegCheckDone: + return true; + case FPSysRegCheckContinue: + break; + } + + switch (regno) { + case ARM_VFP_FPSCR: + tmp =3D tcg_temp_new_i32(); + gen_helper_vfp_get_fpscr(tmp, cpu_env); + storefn(s, opaque, tmp); + break; + case QEMU_VFP_FPSCR_NZCV: + /* + * Read just NZCV; this is a special case to avoid the + * helper call for the "VMRS to CPSR.NZCV" insn. + */ + tmp =3D load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); + tcg_gen_andi_i32(tmp, tmp, 0xf0000000); + storefn(s, opaque, tmp); + break; + default: + g_assert_not_reached(); + } + return true; +} + +static void fp_sysreg_to_gpr(DisasContext *s, void *opaque, TCGv_i32 value) +{ + arg_VMSR_VMRS *a =3D opaque; + + if (a->rt =3D=3D 15) { + /* Set the 4 flag bits in the CPSR */ + gen_set_nzcv(value); + tcg_temp_free_i32(value); + } else { + store_reg(s, a->rt, value); + } +} + +static TCGv_i32 gpr_to_fp_sysreg(DisasContext *s, void *opaque) +{ + arg_VMSR_VMRS *a =3D opaque; + + return load_reg(s, a->rt); +} + +static bool gen_M_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) +{ + /* + * Accesses to R15 are UNPREDICTABLE; we choose to undef. + * FPSCR -> r15 is a special case which writes to the PSR flags; + * set a->reg to a special value to tell gen_M_fp_sysreg_read() + * we only care about the top 4 bits of FPSCR there. + */ + if (a->rt =3D=3D 15) { + if (a->l && a->reg =3D=3D ARM_VFP_FPSCR) { + a->reg =3D QEMU_VFP_FPSCR_NZCV; + } else { + return false; + } + } + + if (a->l) { + /* VMRS, move FP system register to gp register */ + return gen_M_fp_sysreg_read(s, a->reg, fp_sysreg_to_gpr, a); + } else { + /* VMSR, move gp register to FP system register */ + return gen_M_fp_sysreg_write(s, a->reg, gpr_to_fp_sysreg, a); + } +} + static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) { TCGv_i32 tmp; bool ignore_vfp_enabled =3D false; =20 - if (!dc_isar_feature(aa32_fpsp_v2, s)) { - return false; + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return gen_M_VMSR_VMRS(s, a); } =20 - if (arm_dc_feature(s, ARM_FEATURE_M)) { - /* - * The only M-profile VFP vmrs/vmsr sysreg is FPSCR. - * Accesses to R15 are UNPREDICTABLE; we choose to undef. - * (FPSCR -> r15 is a special case which writes to the PSR flags.) - */ - if (a->reg !=3D ARM_VFP_FPSCR) { - return false; - } - if (a->rt =3D=3D 15 && !a->l) { - return false; - } + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; } =20 switch (a->reg) { --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607601796; cv=none; d=zohomail.com; s=zohoarc; b=CZAeZPfuq8VQ8Rib6hUmk3hQ20RiqLyn5R6Nqjl7dKLkh4acD3k4h0w1b4b2Dh5DRhNk1f/wMJ2r3mIRf0y53co+LNOHqcR3hfVRfP0P9YUvK/roI67+Q/c2p3ht0mcoSI8PRwc4NRHj2l9YPeLr5/3Dfh0Fp2ZgYx0Ai+i0YAw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607601796; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=px5eFJInHNHQIA7EojQH4T/N5fGZcvKN8m1p9kIe4Dk=; b=OsvWhTdisxGK82fxN5UWRJhsBKRFdt+z3sbenRJIv4OBw9aGQ2F1HFFGO2GYZIVMtP/kfdplTcdBli4fBtQC1snW5JCCdKuLV/g1dvwvvV5LE+F48U3O/EM9dDsrox+JEMooeJ2vBNRvqS511/mR3f/TE8JpsQUQu2Ne5FXyoRo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607601796448702.0665355786869; Thu, 10 Dec 2020 04:03:16 -0800 (PST) Received: from localhost ([::1]:38548 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKfB-0007I8-9v for importer@patchew.org; Thu, 10 Dec 2020 07:03:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51392) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKR4-0001Y4-Eb for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:38 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:34370) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKQo-000776-Di for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:37 -0500 Received: by mail-wm1-x342.google.com with SMTP id g25so2621786wmh.1 for ; Thu, 10 Dec 2020 03:48:21 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=px5eFJInHNHQIA7EojQH4T/N5fGZcvKN8m1p9kIe4Dk=; b=cheLZWft7idakZLRS0l1HryfOeIFL/Hkd5TsRH2WAodjHs+5TEUFZIB5qGXqjlNtnC rQepkS0TheBXuEWGnqkVH0RArfurHzoZNnz2LpQIIrTCfSREx9N1nfiMpiq8LVi6uTdt xPyLFXnP19kJ02D7conlaXxPgvJnqdbcI8njuoZzBm40lLUPHaLxpRPkjjNxUxSGwqn1 dwb6cMfVyXkuVRiBZ2n11RKq+S9yROV3B4bXRgaYtn4Xl3Eew4EU0TFJ9heFR9sayKUd ceeXhTlYmM9SY0gyuqv5/1jWflf33Y1pgMooPQUc9UamzMu5NmGjTXe/5IMbGLFNsdKs M/EA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=px5eFJInHNHQIA7EojQH4T/N5fGZcvKN8m1p9kIe4Dk=; b=t+rTOyua20jiktrGz46Zuytb4WXyiy+SA+A8E+aJFDoxXVa8YQPuR7fesVQLsQSqaX lBK6w8RubhhSYtJQt//Qw1WIBUrDBDfockhwQqrK1icAI3bChBTBLCjuo2cCyXWz1hLq 1bYu1HEBy5DWiNxqcnVPjHHbd14tJxXyNBq+XDh/xbjLeTqEdZCZbL6U5CX7nP+8KJiG xgZ7v51G0NDWK8iAQGnWaxwKZ71tEBRR8rASn/wx1LlHHEuPHurF1nol6xkuu3j+ijFx I7OulVR8jbtzX6DoAAYxOHlLdrg6toKiEFEgqVv5y9JGz+MHnRD7olQKSBw2pB/WUsfs ZEMg== X-Gm-Message-State: AOAM531omQgDlIehVzYvRx47WHjTyfdpee4TY5REr6vHtXAB80+kdDAL sPynWTrChG29XzRXbdrVZG+XrULOCgVxkg== X-Google-Smtp-Source: ABdhPJwXflTk6i0CCdf60YdkiYNERouCILn7UkfCbEgYqWls4Zy6w324EjsRmDuLkOGdZf+Cvacalw== X-Received: by 2002:a7b:c208:: with SMTP id x8mr7767589wmi.179.1607600900774; Thu, 10 Dec 2020 03:48:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/36] target/arm: Move general-use constant expanders up in translate.c Date: Thu, 10 Dec 2020 11:47:39 +0000 Message-Id: <20201210114756.16501-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x342.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The constant-expander functions like negate, plus_2, etc, are generally useful; move them up in translate.c so we can use them in the VFP/Neon decoders as well as in the A32/T32/T16 decoders. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-9-peter.maydell@linaro.org --- target/arm/translate.c | 46 +++++++++++++++++++++++------------------- 1 file changed, 25 insertions(+), 21 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 47a1a5739c8..f5acd32e76a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -109,6 +109,30 @@ static void arm_gen_condlabel(DisasContext *s) } } =20 +/* + * Constant expanders for the decoders. + */ + +static int negate(DisasContext *s, int x) +{ + return -x; +} + +static int plus_2(DisasContext *s, int x) +{ + return x + 2; +} + +static int times_2(DisasContext *s, int x) +{ + return x * 2; +} + +static int times_4(DisasContext *s, int x) +{ + return x * 4; +} + /* Flags for the disas_set_da_iss info argument: * lower bits hold the Rt register number, higher bits are flags. */ @@ -5177,29 +5201,9 @@ static void arm_skip_unless(DisasContext *s, uint32_= t cond) =20 =20 /* - * Constant expanders for the decoders. + * Constant expanders used by T16/T32 decode */ =20 -static int negate(DisasContext *s, int x) -{ - return -x; -} - -static int plus_2(DisasContext *s, int x) -{ - return x + 2; -} - -static int times_2(DisasContext *s, int x) -{ - return x * 2; -} - -static int times_4(DisasContext *s, int x) -{ - return x * 4; -} - /* Return only the rotation part of T32ExpandImm. */ static int t32_expandimm_rot(DisasContext *s, int x) { --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607603479; cv=none; d=zohomail.com; s=zohoarc; b=L3dR7tJ2f8mXRMY5gSt15lA7aIidVsK3Wg/nRNW391T+5EqlhhbeVwF/Mwr7GAkvHjvoh78UusG+V4Qrk5c7Mzt7pR8+a4I3ymJfpXiUuxyNt4vL+51WHniP4YDulxfEV1YFkEm5PNSbgsBJTddHs8Kr7KMhz6bawTlgB1VDw1I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607603479; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=oC9ZADiN58GfuZANtIRVD/N6F8RJXI0Q+vqpyz4GkZU=; b=fe33oRvKVJY9xxKqBMGi6oTdkdzneiP1DMlXtZx9LcJPKCyrdBrm2v5TNRXBPY515RuyHYWv/iDmFViaDSYf2YcbSsp9pLlW7L+KCQGZ5y/7IzutWv08GrE50lpJJbYH8BT93YixmkbOpOS1l6B9zmtc4EP3YyUStInK7ILVUMY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607603478959912.9770910851371; Thu, 10 Dec 2020 04:31:18 -0800 (PST) Received: from localhost ([::1]:46828 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKia-0002Lw-9u for importer@patchew.org; Thu, 10 Dec 2020 07:06:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51442) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKR5-0001am-L8 for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:39 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:43178) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKQs-00077J-FP for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:39 -0500 Received: by mail-wr1-x42e.google.com with SMTP id y17so5133446wrr.10 for ; Thu, 10 Dec 2020 03:48:23 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=oC9ZADiN58GfuZANtIRVD/N6F8RJXI0Q+vqpyz4GkZU=; b=oNPFP7xyz5PUEZYZ1fjrS1ELkDOHNl1yC46n9s70JQ9ul3VeqzWpClOVMQ8q1Crq2z s5w3DoVwEYoagd+A4qFWvlLqVIYt2aFEQE1VxlZ1tFycOu6mGPLaRJhjtpNOOrgjWrsY hztyXb82ZtuYaDrhkRsNAR9d2DP87zWCtHdYEl+yOpfBsCw/aQZuandKN8zbPp3RRkGm av+nxswSMCTEniXaQad2uSnfvZCoZdTxkf921B1wCmU6zCz9vH+A5BgyQ1gcwBqPeI9w dFy092aEg5zW8iFFw57MAtZyAozcoQz5rrV/tVTN9h7sihbhaWdDQk2/JXjuRp6yFHBO QJiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oC9ZADiN58GfuZANtIRVD/N6F8RJXI0Q+vqpyz4GkZU=; b=MZM3+0WImAVlMFwM25GhamuWMOOnt0P6MScoUczEFqJI4br9Nh9nGmsjnw1NSbQbyM 2lxDbllzGHIxhbHW83ceiADpu4IHMEqWsI0hE9vvEdgz5xGPyQvlZYBYZlWQf9NDMDBX 9Tgx108zD8lP0y5eQ2l2qXq1LPurFQagP8cL6A/nE9EsUa+x0jNwwtWscBlM/w5h5UsY sHN1EN4az3mUDgPCHCYPuVqOqshokfyTx9WJqWn9MVFde05cwI0zzf8GyPK3YHUjCOoy CMcuP9PniRZF16+1kU+NQXRPWnsPa1gtl9DIdMQLQxs43FLXFIRQtUgVAsDJ4C0a0kTU L2WA== X-Gm-Message-State: AOAM533m/ggJHaB+Mkae/8jmkPplw8pd35dj6kgcC1fssszEl8e79V/E aaMe+BSy+Q+a1gymcqNbMxQlHVGxHCaL9A== X-Google-Smtp-Source: ABdhPJwaohm8uiXAKpBQRFn6o3s7Y1vs8bTliV1TPORbUaYRWENTqvmDL6YcJK94GoKS0LKsvSYiEA== X-Received: by 2002:adf:f681:: with SMTP id v1mr5711782wrp.133.1607600901984; Thu, 10 Dec 2020 03:48:21 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/36] target/arm: Implement VLDR/VSTR system register Date: Thu, 10 Dec 2020 11:47:40 +0000 Message-Id: <20201210114756.16501-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the new-in-v8.1M VLDR/VSTR variants which directly read or write FP system registers to memory. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-10-peter.maydell@linaro.org --- target/arm/vfp.decode | 14 ++++++ target/arm/translate-vfp.c.inc | 91 ++++++++++++++++++++++++++++++++++ 2 files changed, 105 insertions(+) diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 1300ba045dd..6f7f28f9a46 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -84,6 +84,20 @@ VLDR_VSTR_hp ---- 1101 u:1 .0 l:1 rn:4 .... 1001 imm:8 = vd=3D%vd_sp VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 vd=3D%vd_sp VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 vd=3D%vd_dp =20 +# M-profile VLDR/VSTR to sysreg +%vldr_sysreg 22:1 13:3 +%imm7_0x4 0:7 !function=3Dtimes_4 + +&vldr_sysreg rn reg imm a w p +@vldr_sysreg .... ... . a:1 . . . rn:4 ... . ... .. ....... \ + reg=3D%vldr_sysreg imm=3D%imm7_0x4 &vldr_sysreg + +# P=3D0 W=3D0 is SEE "Related encodings", so split into two patterns +VLDR_sysreg ---- 110 1 . . w:1 1 .... ... 0 111 11 ....... @vldr_sysreg p= =3D1 +VLDR_sysreg ---- 110 0 . . 1 1 .... ... 0 111 11 ....... @vldr_sysreg p= =3D0 w=3D1 +VSTR_sysreg ---- 110 1 . . w:1 0 .... ... 0 111 11 ....... @vldr_sysreg p= =3D1 +VSTR_sysreg ---- 110 0 . . 1 0 .... ... 0 111 11 ....... @vldr_sysreg p= =3D0 w=3D1 + # We split the load/store multiple up into two patterns to avoid # overlap with other insns in the "Advanced SIMD load/store and 64-bit mov= e" # grouping: diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 7a0cbca6640..f884d680a03 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -913,6 +913,97 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_= VMRS *a) return true; } =20 +static void fp_sysreg_to_memory(DisasContext *s, void *opaque, TCGv_i32 va= lue) +{ + arg_vldr_sysreg *a =3D opaque; + uint32_t offset =3D a->imm; + TCGv_i32 addr; + + if (!a->a) { + offset =3D - offset; + } + + addr =3D load_reg(s, a->rn); + if (a->p) { + tcg_gen_addi_i32(addr, addr, offset); + } + + if (s->v8m_stackcheck && a->rn =3D=3D 13 && a->w) { + gen_helper_v8m_stackcheck(cpu_env, addr); + } + + gen_aa32_st_i32(s, value, addr, get_mem_index(s), + MO_UL | MO_ALIGN | s->be_data); + tcg_temp_free_i32(value); + + if (a->w) { + /* writeback */ + if (!a->p) { + tcg_gen_addi_i32(addr, addr, offset); + } + store_reg(s, a->rn, addr); + } else { + tcg_temp_free_i32(addr); + } +} + +static TCGv_i32 memory_to_fp_sysreg(DisasContext *s, void *opaque) +{ + arg_vldr_sysreg *a =3D opaque; + uint32_t offset =3D a->imm; + TCGv_i32 addr; + TCGv_i32 value =3D tcg_temp_new_i32(); + + if (!a->a) { + offset =3D - offset; + } + + addr =3D load_reg(s, a->rn); + if (a->p) { + tcg_gen_addi_i32(addr, addr, offset); + } + + if (s->v8m_stackcheck && a->rn =3D=3D 13 && a->w) { + gen_helper_v8m_stackcheck(cpu_env, addr); + } + + gen_aa32_ld_i32(s, value, addr, get_mem_index(s), + MO_UL | MO_ALIGN | s->be_data); + + if (a->w) { + /* writeback */ + if (!a->p) { + tcg_gen_addi_i32(addr, addr, offset); + } + store_reg(s, a->rn, addr); + } else { + tcg_temp_free_i32(addr); + } + return value; +} + +static bool trans_VLDR_sysreg(DisasContext *s, arg_vldr_sysreg *a) +{ + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { + return false; + } + if (a->rn =3D=3D 15) { + return false; + } + return gen_M_fp_sysreg_write(s, a->reg, memory_to_fp_sysreg, a); +} + +static bool trans_VSTR_sysreg(DisasContext *s, arg_vldr_sysreg *a) +{ + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { + return false; + } + if (a->rn =3D=3D 15) { + return false; + } + return gen_M_fp_sysreg_read(s, a->reg, fp_sysreg_to_memory, a); +} + static bool trans_VMOV_half(DisasContext *s, arg_VMOV_single *a) { TCGv_i32 tmp; --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607603134; cv=none; d=zohomail.com; s=zohoarc; b=DSe2d+XyD+a4dfY4RLqZMdmN6yPAvdz5C5HtkKJYllr/7mHvb63w27MdMB5raebk+QGBqCiWSsyE4ssNPdEtzItx1RgFJQNFs8+ywy+xqsTAfLaxfqS0J4zNUNAQ9earBcv27fMwYLdxpJ1kdWT08YDlzFi+S/YzAkGpEyRue0I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607603134; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/LTSIYlir4ilpKHjcrz/1PwD2k3uNW7FvzrH/uQrWPA=; b=iSOu/mma0L6FYy9BMrTt7EquAm9uUFauwueDfyI1P5cFNWgv/KFlngiOLwtDlZ2pfvRJhbB5ipHzJWoZ4XXBklhl7OdtedyZhbLHgTQd2u0mEvBe5Q+qYWmztB0GqWNP3mIeYH7TWNCa+OFzj+Mz65r9++//YbfffIR29T3Z+20= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607603134625727.7273962254428; Thu, 10 Dec 2020 04:25:34 -0800 (PST) Received: from localhost ([::1]:60946 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKx3-000371-Sr for importer@patchew.org; Thu, 10 Dec 2020 07:21:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51418) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKR5-0001ZX-0r for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:39 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:36843) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKQs-00077W-FG for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:38 -0500 Received: by mail-wr1-x436.google.com with SMTP id t16so5161761wra.3 for ; Thu, 10 Dec 2020 03:48:24 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=/LTSIYlir4ilpKHjcrz/1PwD2k3uNW7FvzrH/uQrWPA=; b=Wk88U7EW87Kdjm9c2zNUA+mfoKUWVfPOpdlGq9n9LkhxyvtZsaxQ6bHhHysrOYkbBg t22BsNdG8eMTZhE1OMrcw9u/4HExjDIdLEulRGVUjT/izSV+2eJjkP8UUtdISCatNPSG AI93GJ0q3Pbv2nbjw0v33iUSgYGkYSIU0RWOKuxMrX48eY3AROjshXB/DgpvCjq+tqzi f9vGyFA2Iuu0/u3FKnt1rIMr6VqJw5x2o3FdCQN+HJvnRzSHEj0sDRmEPYBX4XIR5dGp zdvT/0b+JFXbbqfo0ofmWYJgs4gT8NkSF/6CXKRRlrEFLgUI20zY8TsVEav+Q/MvSfDV QDgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/LTSIYlir4ilpKHjcrz/1PwD2k3uNW7FvzrH/uQrWPA=; b=Kk9/52LDaqUi7kN1SpIP7LT1O+3sy5WC1UuDlOWYoz9hZWHBmzZOJ9ddRJXb/eE1Td jfFSaoO+iv/UjRSyJ2O3Fxe22dkAbHPyi9I5ksnoQTSogfhcTQ9kf8bLfcx4g/kn5OAt ATPNErhn/I7pnw2mA23vida7qlA/4uH305jdaqn9jqFz43gbq84FiMdmaZPs0u3HYKKZ /ARx0mZBr8/QaW+XDrPAw6pBqImf+f6AwJSp0P70gvd6NbtsDOXcNPs+ENx9PeQ4o23M n3EypYGxv1TUDapUI314DSYGysNfMHL2D0PUW2io2eSIuNF9ZO61hkdsfvX4inCP4zdD bfQw== X-Gm-Message-State: AOAM5329ogY61AY274bkVfxaXDrKcnVMnZl/7/Dk9qznhUej4tBXxoBt t5S1xlqq6GFGQBIQeeI3F1bBGUZB5Ig2/w== X-Google-Smtp-Source: ABdhPJxmfHYRatGh5N+ceUOmv6b6GorLa2uh0nlxWtDq2xREpENZn0K2oeltDZu/4iVJ3HKTeInJEA== X-Received: by 2002:a5d:6ccb:: with SMTP id c11mr7849199wrc.224.1607600902975; Thu, 10 Dec 2020 03:48:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/36] target/arm: Implement M-profile FPSCR_nzcvqc Date: Thu, 10 Dec 2020 11:47:41 +0000 Message-Id: <20201210114756.16501-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" v8.1M defines a new FP system register FPSCR_nzcvqc; this behaves like the existing FPSCR, except that it reads and writes only bits [31:27] of the FPSCR (the N, Z, C, V and QC flag bits). (Unlike the FPSCR, the special case for Rt=3D15 of writing the CPSR.NZCV is not permitted.) Implement the register. Since we don't yet implement MVE, we handle the QC bit as RES0, with todo comments for where we will need to add support later. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-11-peter.maydell@linaro.org --- target/arm/cpu.h | 13 +++++++++++++ target/arm/translate-vfp.c.inc | 27 +++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ad8b80c667d..04f6220b2f7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1524,6 +1524,13 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val); #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ #define FPCR_DN (1 << 25) /* Default NaN enable bit */ #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ +#define FPCR_V (1 << 28) /* FP overflow flag */ +#define FPCR_C (1 << 29) /* FP carry flag */ +#define FPCR_Z (1 << 30) /* FP zero flag */ +#define FPCR_N (1 << 31) /* FP negative flag */ + +#define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) +#define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) =20 static inline uint32_t vfp_get_fpsr(CPUARMState *env) { @@ -1568,6 +1575,12 @@ enum arm_cpu_mode { #define ARM_VFP_FPEXC 8 #define ARM_VFP_FPINST 9 #define ARM_VFP_FPINST2 10 +/* These ones are M-profile only */ +#define ARM_VFP_FPSCR_NZCVQC 2 +#define ARM_VFP_VPR 12 +#define ARM_VFP_P0 13 +#define ARM_VFP_FPCXT_NS 14 +#define ARM_VFP_FPCXT_S 15 =20 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ #define QEMU_VFP_FPSCR_NZCV 0xffff diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index f884d680a03..d698f3e1cd1 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -648,6 +648,11 @@ static FPSysRegCheckResult fp_sysreg_checks(DisasConte= xt *s, int regno) case ARM_VFP_FPSCR: case QEMU_VFP_FPSCR_NZCV: break; + case ARM_VFP_FPSCR_NZCVQC: + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { + return false; + } + break; default: return FPSysRegCheckFailed; } @@ -683,6 +688,22 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int= regno, tcg_temp_free_i32(tmp); gen_lookup_tb(s); break; + case ARM_VFP_FPSCR_NZCVQC: + { + TCGv_i32 fpscr; + tmp =3D loadfn(s, opaque); + /* + * TODO: when we implement MVE, write the QC bit. + * For non-MVE, QC is RES0. + */ + tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); + fpscr =3D load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); + tcg_gen_andi_i32(fpscr, fpscr, ~FPCR_NZCV_MASK); + tcg_gen_or_i32(fpscr, fpscr, tmp); + store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]); + tcg_temp_free_i32(tmp); + break; + } default: g_assert_not_reached(); } @@ -711,6 +732,12 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int = regno, gen_helper_vfp_get_fpscr(tmp, cpu_env); storefn(s, opaque, tmp); break; + case ARM_VFP_FPSCR_NZCVQC: + /* + * TODO: MVE has a QC bit, which we probably won't store + * in the xregs[] field. For non-MVE, where QC is RES0, + * we can just fall through to the FPSCR_NZCV case. + */ case QEMU_VFP_FPSCR_NZCV: /* * Read just NZCV; this is a special case to avoid the --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607601903; cv=none; d=zohomail.com; s=zohoarc; b=D7epAUHS8wmQvP+cuMWdjJCeTBfQd9Vf9pt81LTarxLjDOi1IiU/hSr8kRC8rhkmBIxIur4icfhfRNzupuVh2rpLtXcbRfBxup4rZuIQbNLf6Ov/klbPFrMsXiO8MYncscv1wx8rmXMrBq+ZzQJNFQh4bbOuKIB1ro01laSgGWY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607601903; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=XFqW4OUMJKJNIdAWJJrDAuilTkugbK+/iNLz4Uk/fzU=; b=JjfLKsWZsFIwjZvHd8JPH8ldZt/OgNtvoiMqyEO9g8gZBumHlqYNDwRGPayzerl7xnhpXjLyX2g583TO9Y0gxaMt69Lvtx8FeS36krCCr6p+1eA2vfhOtpzz4EbwiSdxOeUEBUj+Ehw91fvwaOr+y7VC24jzPPsTMO05hLsNkzQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607601903153621.2004295724196; Thu, 10 Dec 2020 04:05:03 -0800 (PST) Received: from localhost ([::1]:42134 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKgt-0000LZ-F2 for importer@patchew.org; Thu, 10 Dec 2020 07:04:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51388) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKR4-0001Y1-82 for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:38 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:54428) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKQs-00077e-Bg for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:37 -0500 Received: by mail-wm1-x342.google.com with SMTP id d3so4380302wmb.4 for ; Thu, 10 Dec 2020 03:48:25 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=XFqW4OUMJKJNIdAWJJrDAuilTkugbK+/iNLz4Uk/fzU=; b=MtsDOOPY9T+kXMLa08wM7BzpMM8Bk/5rs/OKQqVV8BKO+CuYWOXp3IS1FEdjw5Nksh yXGCvGMrfuuK8Ko435dSkYkpXSf/sG67FrilzvcBoghejliEPE4WbqNtuISc651e2j+t EPv8PIujH4W6TAbTDezT3wXPxMqV8bQ8OmpUgqQXPNvdVD/c2heWBISQylvJFqyD6ySJ TpB+DemqDtzh+7WfxysU+pYIey4M2iMURQPjPL6EFbYKDebAjQS4OZlh+pa5sOTentJ7 OeejSTN2ce+f6ppsjKoT3kAtTZMAM2Wptu+gc+yxXZQmxttpoZgblsfiTxV3lgEcfOlj uYig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XFqW4OUMJKJNIdAWJJrDAuilTkugbK+/iNLz4Uk/fzU=; b=VMmpQmGXellpWl12FB3B3FOiMnD2a+vtiY1kuUMgURudVJWv1fyHUfK0J4CMRMiziM /wXpZ7SR7g5gCKrKZ5OIdPsAjn9RWxeZBBjf4sy0SYbxRD4CkBjx0gKk/l7rSiQZnn6C Y85PwAPhbkGbKJkA8emk6ydD0Qi4sj1rsbqxByxFsqQinZctE5mKBxaoAQK8jvWJ1Ks+ s49bhJmN7vtKbfszBsyqcgKpmNCJWTceNNO1AIHfKId6HKohBhO8Rx4rAVeozDU2xutd 4ZiFV8y8NSkInD386oQlc/znrqPOGABp0HdsE/IP+38Ys0JsaqVE+xQu0UrIyZthmkc9 Yy+g== X-Gm-Message-State: AOAM53360L4yqCqi4wtzAwn46iBw2kN9D9JQJKGuRlNRE+JSKpz6ZsjY sprZRHPfc3AqoOBr8FgbCa2jf+CodBMklQ== X-Google-Smtp-Source: ABdhPJzhy71pyhIgJ2g88EZxM9mv0i4mzdpRJnWiKUZq4AgWyP3Xt2Lck2RaKdHDexQOtNAU29DsUA== X-Received: by 2002:a1c:4e0a:: with SMTP id g10mr7768906wmh.51.1607600903956; Thu, 10 Dec 2020 03:48:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/36] target/arm: Use new FPCR_NZCV_MASK constant Date: Thu, 10 Dec 2020 11:47:42 +0000 Message-Id: <20201210114756.16501-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x342.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We defined a constant name for the mask of NZCV bits in the FPCR/FPSCR in the previous commit; use it in a couple of places in existing code, where we're masking out everything except NZCV for the "load to Rt=3D15 sets CPSR.NZCV" special case. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-12-peter.maydell@linaro.org --- target/arm/translate-vfp.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index d698f3e1cd1..cd8d5b4f28b 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -744,7 +744,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int r= egno, * helper call for the "VMRS to CPSR.NZCV" insn. */ tmp =3D load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); - tcg_gen_andi_i32(tmp, tmp, 0xf0000000); + tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); storefn(s, opaque, tmp); break; default: @@ -885,7 +885,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_V= MRS *a) case ARM_VFP_FPSCR: if (a->rt =3D=3D 15) { tmp =3D load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); - tcg_gen_andi_i32(tmp, tmp, 0xf0000000); + tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); } else { tmp =3D tcg_temp_new_i32(); gen_helper_vfp_get_fpscr(tmp, cpu_env); --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607601903; cv=none; d=zohomail.com; s=zohoarc; b=K5kFyESEVyuqjKCfbUuQGvE/Mb+LZeijm6hMp++iULULaUcSohLhhuddE3uPPm8pRi2m1fP8cOOxW/EPgWusv0jZNltU57Kr0EYv/E92CD5OJdvEHA2Tux/6uKAte/fJhS9A4qDh9qmBx414Re4dlneOzm38apKl4HBaLrov4qs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607601903; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sQHcIfjNr/dgviDAFuTlog+s/z+W0UmjgTML+ZZcH4k=; b=OiFnaF5kQMWNGrbhFseJMqmympHujSWQcRVE9jdohZTxF5gge+QbaVwSSE0IFQSyjjcmXXMylWyXsJNRwpjbM222Gz+uqpu22z8Pq5/aB1IJeclg9NejSTIrrZl4yPatPhLp+ZlYDF8Jw2N55bTgZjTzhF0Y9ABoI7pWwkMF+sE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607601903558478.4180808814091; Thu, 10 Dec 2020 04:05:03 -0800 (PST) Received: from localhost ([::1]:42420 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKgw-0000Sn-DY for importer@patchew.org; Thu, 10 Dec 2020 07:05:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51492) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKR7-0001dG-37 for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:41 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:46664) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKQu-00077l-3c for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:40 -0500 Received: by mail-wr1-x433.google.com with SMTP id l9so5136504wrt.13 for ; Thu, 10 Dec 2020 03:48:26 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=sQHcIfjNr/dgviDAFuTlog+s/z+W0UmjgTML+ZZcH4k=; b=Sx4nfWSvlGz/kzltCMIQ29PrRN6Be8FKrfQEutu6WY2YB7bXXKsHel9AGytchwXMSN QxU6IvNPlG3RA0/hlv3Yn99T+GET8V3UNVU+4gceQPDxpP3fFlqILJ+LYVb9NV1gmlEa I6rHun8R51afVdihLnxBwft17fgZNst9NGTdG2aCapnOUSW1g8qVCKZB0nwMIh8Eu86h PqY0FzcqsIx+LOnKi+8ug1EHxoek80rmjPkyZLWPgQgTRHP+vKoqhEG00Ta1UnC7oShN Es3tVzH1Ktsqd5JABYm28PTlmpFxuAprm3tTWLjaSymK6lFKcomftEvub6AW4RtXFFj5 fE1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sQHcIfjNr/dgviDAFuTlog+s/z+W0UmjgTML+ZZcH4k=; b=sGoOyNPZLT+fI96hJc/YVqvRiDKM2isq4MdMwfd67WWX9gIPU7Y731DeYgC7UhLo8N Rcp7zoE2KzdpuhG2DFD3GV7K04sKM5zh/TpF6DmgU1IOdHtOmy26E6USM3HyqDm+ULlZ 4TZkxZCDb6XmXIHvjRZKVrdeGUeYQujYuwnINnDOAufmL+a9edIEFnoulmQEV6+rXNxj 5Uvfk4XP3obuMdogsGHKpXgLC0tujvBPO54h46yvVtYFmZlTtZ/CGZ/mEJZve2C6GAgJ Bx+1uslcvCY0+oGM336XBc9NB5gmsnc3ThbLDAROCSw1WCO/zBzxcBUbVCubtzwKL7SJ 5zmA== X-Gm-Message-State: AOAM533/bFoYzWCmGeUbG/UGhVPhc5YMa1HekdzmPZhvq+JQeXNRZWwe y+KSem059wrMK1kN+KgHqj43qQkUo4MfjA== X-Google-Smtp-Source: ABdhPJzpOKGFEODjot4uKYvrlK7pKCYgG2SUEI+wNSmrHzXglfw+0jOTgg6bnvOQj6rkv7l6l78Wzg== X-Received: by 2002:adf:f707:: with SMTP id r7mr8117922wrp.113.1607600905233; Thu, 10 Dec 2020 03:48:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/36] target/arm: Factor out preserve-fp-state from full_vfp_access_check() Date: Thu, 10 Dec 2020 11:47:43 +0000 Message-Id: <20201210114756.16501-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Factor out the code which handles M-profile lazy FP state preservation from full_vfp_access_check(); accesses to the FPCXT_NS register are a special case which need to do just this part (corresponding in the pseudocode to the PreserveFPState() function), and not the full set of actions matching the pseudocode ExecuteFPCheck() which normal FP instructions need to do. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20201119215617.29887-13-peter.maydell@linaro.org --- target/arm/translate-vfp.c.inc | 45 ++++++++++++++++++++-------------- 1 file changed, 27 insertions(+), 18 deletions(-) diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index cd8d5b4f28b..bb1c41413e7 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -83,6 +83,32 @@ static inline long vfp_f16_offset(unsigned reg, bool top) return offs; } =20 +/* + * Generate code for M-profile lazy FP state preservation if needed; + * this corresponds to the pseudocode PreserveFPState() function. + */ +static void gen_preserve_fp_state(DisasContext *s) +{ + if (s->v7m_lspact) { + /* + * Lazy state saving affects external memory and also the NVIC, + * so we must mark it as an IO operation for icount (and cause + * this to be the last insn in the TB). + */ + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + s->base.is_jmp =3D DISAS_UPDATE_EXIT; + gen_io_start(); + } + gen_helper_v7m_preserve_fp_state(cpu_env); + /* + * If the preserve_fp_state helper doesn't throw an exception + * then it will clear LSPACT; we don't need to repeat this for + * any further FP insns in this TB. + */ + s->v7m_lspact =3D false; + } +} + /* * Check that VFP access is enabled. If it is, do the necessary * M-profile lazy-FP handling and then return true. @@ -113,24 +139,7 @@ static bool full_vfp_access_check(DisasContext *s, boo= l ignore_vfp_enabled) /* Handle M-profile lazy FP state mechanics */ =20 /* Trigger lazy-state preservation if necessary */ - if (s->v7m_lspact) { - /* - * Lazy state saving affects external memory and also the NVIC, - * so we must mark it as an IO operation for icount (and cause - * this to be the last insn in the TB). - */ - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - s->base.is_jmp =3D DISAS_UPDATE_EXIT; - gen_io_start(); - } - gen_helper_v7m_preserve_fp_state(cpu_env); - /* - * If the preserve_fp_state helper doesn't throw an exception - * then it will clear LSPACT; we don't need to repeat this for - * any further FP insns in this TB. - */ - s->v7m_lspact =3D false; - } + gen_preserve_fp_state(s); =20 /* Update ownership of FP context: set FPCCR.S to match current st= ate */ if (s->v8m_fpccr_s_wrong) { --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607603126; cv=none; d=zohomail.com; s=zohoarc; b=I2aRv1/djJo9fPQZ+RV+ldo4WIIo+oObAMr8Wpy+5B0LsdNy4xD4KZcPTRk1hGS+votUbNiDoj7xOWViXtCvbdGzg9nHxGv2JDD9irIYW0p11VV3jHJpM0kLFowiTc5IxPKOccn2YdC4b2GViJfycXBVTJhavSmjDQN0Z2jSwnk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607603126; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=a8vaLctK4xh8/h9+I+zTsDJHrnJBsf4D9mh0G81TSRM=; b=WseUmgCySuXJSBDKnz1F8Y2BS2OABhAIE7C+QCy9iuYTUjZLxckaymAA/FUvjJLrWLYmYaMiIn2tRUKUngusURgZeByBJFnxbyPQyxm9veBVKUGanLgUIqiWdOw5nMN5uCMFhNndMoNeEvdEdxOl8M6CiDrYV4uyivoDbevJTEg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 160760312626254.0601392969553; Thu, 10 Dec 2020 04:25:26 -0800 (PST) Received: from localhost ([::1]:41458 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knL0f-0006jl-78 for importer@patchew.org; Thu, 10 Dec 2020 07:25:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51450) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKR6-0001bI-14 for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:40 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:37177) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKQu-000782-DH for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:39 -0500 Received: by mail-wr1-x42f.google.com with SMTP id i9so5163798wrc.4 for ; Thu, 10 Dec 2020 03:48:27 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=a8vaLctK4xh8/h9+I+zTsDJHrnJBsf4D9mh0G81TSRM=; b=kk24dxQbeCzEw0F3Ypof3T2WNXQDc3yk7IcNqUcuSQ3GpqoCTv6xD3MRpon5zIMGS0 TMStgxP9HaULmGodeh9cDaRXuVyYyQ4ENodyX4E83IMPLotc27akbyV/1SMMdiI7SCio N/IZ6KQxnVH4O2cBFeC+lQGbmRD/Cw4+jTpGHtfPQdsuOsZXNmGkIJ3BIbkJqHNRAc+a re5+WfmmCW0bm8ydjzK/Z3STp05tHsuMHYu6sYy5Caxmq17WR02LmxXvKTRLAKH0w6ze 8CFqnQx3Gwt+uN678cwal7HP2pVwSZIVzhXGhRMFfJczK4NCa1bwamR7FxaF/H3AjCc0 pdRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=a8vaLctK4xh8/h9+I+zTsDJHrnJBsf4D9mh0G81TSRM=; b=dAAEcS4Nj+q7ZLq7dXu/cQSt15n7t0gKHUdRpKm0fP4gSNAFzu3X+HzZ+Yoltbwi2K vyDOdtYcpQ4UXiI/uXCBPivzIXllRmhE6dZfH3InFNUksLjQ12j6Ik5eMxrK+NhrAy1P 3btEQEoQoUvFWs1rSG92zgq4YEtukiZYT6pIcvw/xSBF09zVJmjRTEuEwmGVwGL9XbdD fSA717YBVBphbZ5J+7u5BDYwoTp9FNvcQbY2cNN2TayOmmea062f8jdfIjcq2ijVEF+L GF6i9bqzB8L5Dn5OrDyTpBNZYIZUwbQKnNsVRVUlDp5JPgdebibKvEhuKocpoiSZnvMF Ntjw== X-Gm-Message-State: AOAM5319ERrDkWs/g57CE8teOgggEsEg6FKLTNXnDIteQ5nmuKoTY+M3 ZJCv0beEO9YoaPenHmxtJhvUm8yqRuSwHg== X-Google-Smtp-Source: ABdhPJxnmROWTYMpuwy/aF9Y16cLHDkgG9xEK0cdVIj0PkftbUHQOPzWOvv/TicHElrV9+tLwPHbpg== X-Received: by 2002:adf:b194:: with SMTP id q20mr7880994wra.199.1607600906359; Thu, 10 Dec 2020 03:48:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/36] target/arm: Implement FPCXT_S fp system register Date: Thu, 10 Dec 2020 11:47:44 +0000 Message-Id: <20201210114756.16501-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the new-in-v8.1M FPCXT_S floating point system register. This is for saving and restoring the secure floating point context, and it reads and writes bits [27:0] from the FPSCR and the CONTROL.SFPA bit in bit [31]. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-14-peter.maydell@linaro.org --- target/arm/translate-vfp.c.inc | 58 ++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index bb1c41413e7..808b4077054 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -662,6 +662,14 @@ static FPSysRegCheckResult fp_sysreg_checks(DisasConte= xt *s, int regno) return false; } break; + case ARM_VFP_FPCXT_S: + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { + return false; + } + if (!s->v8m_secure) { + return false; + } + break; default: return FPSysRegCheckFailed; } @@ -713,6 +721,26 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int= regno, tcg_temp_free_i32(tmp); break; } + case ARM_VFP_FPCXT_S: + { + TCGv_i32 sfpa, control, fpscr; + /* Set FPSCR[27:0] and CONTROL.SFPA from value */ + tmp =3D loadfn(s, opaque); + sfpa =3D tcg_temp_new_i32(); + tcg_gen_shri_i32(sfpa, tmp, 31); + control =3D load_cpu_field(v7m.control[M_REG_S]); + tcg_gen_deposit_i32(control, control, sfpa, + R_V7M_CONTROL_SFPA_SHIFT, 1); + store_cpu_field(control, v7m.control[M_REG_S]); + fpscr =3D load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); + tcg_gen_andi_i32(fpscr, fpscr, FPCR_NZCV_MASK); + tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK); + tcg_gen_or_i32(fpscr, fpscr, tmp); + store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]); + tcg_temp_free_i32(tmp); + tcg_temp_free_i32(sfpa); + break; + } default: g_assert_not_reached(); } @@ -756,6 +784,36 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int = regno, tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); storefn(s, opaque, tmp); break; + case ARM_VFP_FPCXT_S: + { + TCGv_i32 control, sfpa, fpscr; + /* Bits [27:0] from FPSCR, bit [31] from CONTROL.SFPA */ + tmp =3D tcg_temp_new_i32(); + sfpa =3D tcg_temp_new_i32(); + gen_helper_vfp_get_fpscr(tmp, cpu_env); + tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK); + control =3D load_cpu_field(v7m.control[M_REG_S]); + tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK); + tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT); + tcg_gen_or_i32(tmp, tmp, sfpa); + tcg_temp_free_i32(sfpa); + /* + * Store result before updating FPSCR etc, in case + * it is a memory write which causes an exception. + */ + storefn(s, opaque, tmp); + /* + * Now we must reset FPSCR from FPDSCR_NS, and clear + * CONTROL.SFPA; so we'll end the TB here. + */ + tcg_gen_andi_i32(control, control, ~R_V7M_CONTROL_SFPA_MASK); + store_cpu_field(control, v7m.control[M_REG_S]); + fpscr =3D load_cpu_field(v7m.fpdscr[M_REG_NS]); + gen_helper_vfp_set_fpscr(cpu_env, fpscr); + tcg_temp_free_i32(fpscr); + gen_lookup_tb(s); + break; + } default: g_assert_not_reached(); } --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607603432; cv=none; d=zohomail.com; s=zohoarc; b=Kjg0/HgcS9IWtpYr4KYfRWYoSiD+1QP6v6zWB0fTXDqqXhaP1hMmEhgKEBXc3gmEzqu8AYdV+Lraml3M6/QgnAj4xjgApbKrK1Y4Jn1/k6MoxGdUJxHkvlyz63Ma1YDrQVPl+F030q0Sc1aUMzH/XyWoKqAIgSaIVpRhEDvE/0Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607603432; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=h44TqlrvTwai1qYfMg+SaBdZv0lFo3JpWlTXA4ARCTg=; b=EvDVPVCGWuvh2qdHmSWiMIndVDJ5uJS3CJ2CvUu11gHOsc2Rg5kWftwCnujAo4ud9RZYK4c7P1RECHaPFMopE+bwRZPUpROmF+fZ/ltxBBfUehco/k+WlpIscDyYYuYHeczwy+1jBSbb+4Oddd57V3bYaIlxrukdwk71jFJ6K3c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607603432649274.13480098611547; Thu, 10 Dec 2020 04:30:32 -0800 (PST) Received: from localhost ([::1]:55282 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKlb-0005pj-5T for importer@patchew.org; Thu, 10 Dec 2020 07:09:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51452) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKR6-0001bZ-8u for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:40 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:37181) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKQv-000788-4l for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:39 -0500 Received: by mail-wr1-x433.google.com with SMTP id i9so5163838wrc.4 for ; Thu, 10 Dec 2020 03:48:28 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=h44TqlrvTwai1qYfMg+SaBdZv0lFo3JpWlTXA4ARCTg=; b=OOW27UOyos5fzXhLpgwj3IreNakslFPMKBlkzN9jFp6+7USmCB6w7kyHkAmXcDcnp6 Hk9SfMzfbqSyXC+Za/lsC+vyiHNlaq9rrHTZZF7XscLvhEb2FvevSbzJIwcJZQJZmGio +rFAYKO92By9qvWjxV+3W4ZuvuTxMb+3q35WmrP+hPlRSnV4lheIsNcaNbKR3t5K6MO0 l8KoNI6Nyl7R9EmljwTQrSeGkofnAwX3ISbGy7hqIGsRUF2nvuFaRAk1srLRXdTF/22V IdO5xGNnBhf3ab+Sq1H4K7cUBX9tKawMYWvx6wMrmQPXH4IGugW4Vh15nXfSrOTSkkA9 Wj0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h44TqlrvTwai1qYfMg+SaBdZv0lFo3JpWlTXA4ARCTg=; b=cX3QHDktIIW0dOHPUyO3p6zT+Z6VRzXBT7Ls2JJi2kC3UyQOgohh2pPnp8dayXqMZT O4tNOvDqu8/TZh78qVw2pNLJKaxj1IkMYnab9NJpMUrMDClcP6KP2//03PSBcBC3u0v5 lKfS+T6uUUM8z6SdaGOuD80gbqsdtTXW/r3+5qSjyNs62ztf8gVaj0GVD7ZprYA8dVZe S/tfVIGg96sKdzzpZ+b3lwgkIEVjgCNJeLkZ7EP66i6vcTxXhjSHMOLifbYZ6KrU6sx+ QnB85UN8Zft+I+LIsmPlFuLDSH936SbpbRDyIlIRbFpo5di0I8QGB9us2QLqD0UErUXx RE+g== X-Gm-Message-State: AOAM5329/+JQWuSfpscAYRcamhuuWLOJV99Gz55e7jJaiO0DnDZSrzk8 tDRBotfhrpk1Yu2Ix10qVZrHJYjRnLOHYw== X-Google-Smtp-Source: ABdhPJx8+gxkL8Zse31z1zPB5YhGxGV5SC4LMHHDApPocBNoiSrA7lEZ6CuU1Bp1KHGX+KkyRz1n8A== X-Received: by 2002:adf:fa05:: with SMTP id m5mr7938711wrr.26.1607600907482; Thu, 10 Dec 2020 03:48:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/36] hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M Date: Thu, 10 Dec 2020 11:47:45 +0000 Message-Id: <20201210114756.16501-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The FPDSCR register has a similar layout to the FPSCR. In v8.1M it gains new fields FZ16 (if half-precision floating point is supported) and LTPSIZE (always reads as 4). Update the reset value and the code that handles writes to this register accordingly. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-16-peter.maydell@linaro.org --- target/arm/cpu.h | 5 +++++ hw/intc/armv7m_nvic.c | 9 ++++++++- target/arm/cpu.c | 3 +++ 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 04f6220b2f7..47cb5032ce9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1521,14 +1521,19 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val); #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ +#define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ #define FPCR_DN (1 << 25) /* Default NaN enable bit */ +#define FPCR_AHP (1 << 26) /* Alternative half-precision */ #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ #define FPCR_V (1 << 28) /* FP overflow flag */ #define FPCR_C (1 << 29) /* FP carry flag */ #define FPCR_Z (1 << 30) /* FP zero flag */ #define FPCR_N (1 << 31) /* FP negative flag */ =20 +#define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ +#define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) + #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) =20 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 9628ce876e0..be3bc1f1f45 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2068,7 +2068,14 @@ static void nvic_writel(NVICState *s, uint32_t offse= t, uint32_t value, break; case 0xf3c: /* FPDSCR */ if (cpu_isar_feature(aa32_vfp_simd, cpu)) { - value &=3D 0x07c00000; + uint32_t mask =3D FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE_MA= SK; + if (cpu_isar_feature(any_fp16, cpu)) { + mask |=3D FPCR_FZ16; + } + value &=3D mask; + if (cpu_isar_feature(aa32_lob, cpu)) { + value |=3D 4 << FPCR_LTPSIZE_SHIFT; + } cpu->env.v7m.fpdscr[attrs.secure] =3D value; } break; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 40f3f798b2b..d6188f6566a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -262,6 +262,9 @@ static void arm_cpu_reset(DeviceState *dev) * always reset to 4. */ env->v7m.ltpsize =3D 4; + /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ + env->v7m.fpdscr[M_REG_NS] =3D 4 << FPCR_LTPSIZE_SHIFT; + env->v7m.fpdscr[M_REG_S] =3D 4 << FPCR_LTPSIZE_SHIFT; } =20 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607603233; cv=none; d=zohomail.com; s=zohoarc; b=OUBtl2McQJWxDmBo8+rIbHVqpTlseE7CXBT5QiJ/1xQSFZ5ygfgHfMqPoFZoVJruSZOqO9EpSnYTakckrq4iHykQ95r631UCdGP8OyoIy5rtrge/rJoKa1UxKTYcJ9iK4cF6dy7MJpUnBv4PGVN53oJHrr5Y/8t/AS7NYaL+dbY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607603233; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7GwpflhCK6BEL2dQQRRYORmq+XU3L/lXbqS48LePEFY=; b=BovdLNQvmRnslTv+R5lz6n2uVScBLDIMT/kyZlhMF6H2xQaIJcAyU2Kl7fqTzRdTPL7U4TKttYutDvc5FNIf8VT3IRkOM4dnuxLOquP4TaomHS294uB/gacLfliLgXjddEeeBp0CwRUo/2IcZ/5BcPXDlAVrV0wVgSfENOYcIao= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607603233431154.12558778162213; Thu, 10 Dec 2020 04:27:13 -0800 (PST) Received: from localhost ([::1]:34198 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKdC-0005ME-5q for importer@patchew.org; Thu, 10 Dec 2020 07:01:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51462) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKR6-0001c5-FT for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:40 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:37172) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKQw-00078M-Ax for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:40 -0500 Received: by mail-wr1-x429.google.com with SMTP id i9so5163884wrc.4 for ; Thu, 10 Dec 2020 03:48:29 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=7GwpflhCK6BEL2dQQRRYORmq+XU3L/lXbqS48LePEFY=; b=wKbhhmppBJVEgdRX+LbA4IdSe1Gk3fgge345SnWABNAWWNCwa/2m5F/K8EQHYgQnhf MZ+aSB0tqvc7brja8BtwCj2GmSICAEZm3cWGYHuMOfXhgrDho0ndjPx6OQO5J5dI4E4r vgqQ6GkuRjAtcpaNdSGG8C4p91oPINMQ1QpvCI9xyKOFFr/BEiVRXXOwS7V4/2NNtGkI Yt2M0/36nxya7/Nl7Xhz8oKQQ3t0d3NcULfPmrtNfVmwkPhkhhg3pSH4Tdsi9OZ6FmLk mC6hJ7sMsovzkEdVaIEXNEYGah40o75nOjMRyqms5Bps5IJbGHoA+KiVaPbQA1VF69+h VIRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7GwpflhCK6BEL2dQQRRYORmq+XU3L/lXbqS48LePEFY=; b=HbT+y3rDrgzh//RDGOOxCHj125QN2KX8WFRpR9yMP0TRFT3HhZCmm96GRBKzGcWdeB korkGb+ztIEXRqCPd9jhBZRhoRphYvoju3i4JNFAJh2H8ctjNowyIdx1Vqpd85m9unIy /8EOoNO2rX5647vhd01YXtiF+GxIEkWmNE4MGWGvwm6BkBc2buu40Dm4GazIzH9qmRSv +mFuAfQ6yruE9g8QlLV8p7ZIWT9TXi0qJE9AK7t63h+iwwutIjlF7tGnx5ER6Xj9DMy4 ZgUyyLTGYO4m3vbH2vct8W4k1HNnFfZEu5NFYF4X7ItmLcwHo6AnNijyUrpVAqb/JHco +N8w== X-Gm-Message-State: AOAM531yEIURA+ImB/kdcfHHf91zWHJpwliAD1918UeShxPi8V9+DIsA DKwvYbylWbiF/wAcuY9jYTZ90pob18tOZA== X-Google-Smtp-Source: ABdhPJx05Wm1xI60vWoBlt60l7w1KbtTcglD0ve5Q14OWrV0scGQXS4lO4ds3uK+1/qAE38wseXTlw== X-Received: by 2002:adf:e44d:: with SMTP id t13mr7758771wrm.144.1607600908547; Thu, 10 Dec 2020 03:48:28 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/36] target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry Date: Thu, 10 Dec 2020 11:47:46 +0000 Message-Id: <20201210114756.16501-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In v8.0M, on exception entry the registers R0-R3, R12, APSR and EPSR are zeroed for an exception taken to Non-secure state; for an exception taken to Secure state they become UNKNOWN, and we chose to leave them at their previous values. In v8.1M the behaviour is specified more tightly and these registers are always zeroed regardless of the security state that the exception targets (see rule R_KPZV). Implement this. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-17-peter.maydell@linaro.org --- target/arm/m_helper.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index aad01ea0127..721b4b4896e 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -897,10 +897,12 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t= lr, bool dotailchain, * Clear registers if necessary to prevent non-secure exception * code being able to see register values from secure code. * Where register values become architecturally UNKNOWN we leave - * them with their previous values. + * them with their previous values. v8.1M is tighter than v8.0M + * here and always zeroes the caller-saved registers regardless + * of the security state the exception is targeting. */ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { - if (!targets_secure) { + if (!targets_secure || arm_feature(env, ARM_FEATURE_V8_1M)) { /* * Always clear the caller-saved registers (they have been * pushed to the stack earlier in v7m_push_stack()). @@ -909,10 +911,16 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t= lr, bool dotailchain, * v7m_push_callee_stack()). */ int i; + /* + * r4..r11 are callee-saves, zero only if background + * state was Secure (EXCRET.S =3D=3D 1) and exception + * targets Non-secure state + */ + bool zero_callee_saves =3D !targets_secure && + (lr & R_V7M_EXCRET_S_MASK); =20 for (i =3D 0; i < 13; i++) { - /* r4..r11 are callee-saves, zero only if EXCRET.S =3D= =3D 1 */ - if (i < 4 || i > 11 || (lr & R_V7M_EXCRET_S_MASK)) { + if (i < 4 || i > 11 || zero_callee_saves) { env->regs[i] =3D 0; } } --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607603097; cv=none; d=zohomail.com; s=zohoarc; b=IETvUnw3jvOq1AlK/NxX2CZOybA5ZXb88K9vzP48zKXqH1i+VuJ4QLO429BqUfc2+Guc33EOjd+/NT9S4QgeHPrVOHeZbuNl4eeDl6ZcQfax03D2rCMzA9adIil2YeWqb0U+Z5vHKime/ywYZCO2PIOlX7+yM8jep5mABjEiN58= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607603097; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wcq0GxMvWfold5QlJFLGxctr0lktZC+ze3o2mZSSjxg=; b=XC/nwLVJbmTFymujEE7TfRL0WuYpIPI+v0llIIkyXaGUYj+Q2dP/RRgb2GmjH7oqGmcU6QgVcpgCZx0eaJ40oiUGXzYF3MHG9T01eXBRlZfkPvlAkMEVbOMMHVRlSsFsIT1bTFOj/r3HcWAmWx5E1VXxguAEfSJ3GDvfzDdicIE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607603097560431.6340764006949; Thu, 10 Dec 2020 04:24:57 -0800 (PST) Received: from localhost ([::1]:50386 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKjc-0003q1-Ly for importer@patchew.org; Thu, 10 Dec 2020 07:07:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51496) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKR7-0001dV-EG for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:41 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:38649) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKQy-00078S-9u for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:41 -0500 Received: by mail-wr1-x433.google.com with SMTP id r7so5151908wrc.5 for ; Thu, 10 Dec 2020 03:48:30 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=wcq0GxMvWfold5QlJFLGxctr0lktZC+ze3o2mZSSjxg=; b=CChfZH5igfwtHSgkUjERLSbo05XmIQWY3Uq20NgAH76VUWPTLDEvw8AmdKG5YI+VBG YHFcrOFWjw5WwBRVNgwBJJZEAbEsy5QhJy4iOyO7A88ULvKC4DrA6S6OaFp3WxIkgobW Ip1+PVzXBF/3RnCyO97qQHbMaKM4MLogkGwHthVkrcBEiBf5cU5xvwNfKDkOYe1OLDAV 6y1AnfbIvTtfwaeQusoJ983a1MSD2kLtcmfAGZ7m0s0Rkt3HnTQAhXMUSxehJGSzjrHO P0gKpiIl4EiC3ZZ7+aC4mguz+ts1qISp388I8Lcnr7zHPNmlHMh3K+gXGIv5uqeGNBNX 53Dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wcq0GxMvWfold5QlJFLGxctr0lktZC+ze3o2mZSSjxg=; b=SMZpasgLJpjosVLbnWxqVJkeMJfOfWxim8I5D4ujpJorrvLEBXpQ9N4tRk4UoFG2Uk WU+7ke/EzK91/HmcEmkBcqnYGsxSOILd3F4K9qQkqDOijbX3GUGzbU6ehigK3nyYSHXS 918ItcjVPfpGAqmHJieR3jgiIK4LQxRATLTYXLs5QPDKINNatMpz4Yo5no0QHpw+tWuW JEK4wzJu/GNY4Qyy6JkLRXHnDEbSKzXsE1kxc+i1QyTS1GMpp03F01GilzSToCqAje9p 9bRks3YY5Uap7t/SL6JnAeng10tEXCV9qmdbGoJjn2sq0BPCxdulDcQU2r6B9r2VWFWR D/qQ== X-Gm-Message-State: AOAM532lPqiouDShF7QNH76EfMcvHURtuU5C6j9OvypEqHhwvlAQKMP/ WZ68QkCXqzlKhl8JuCvwaQT5Z+oqAO3ntg== X-Google-Smtp-Source: ABdhPJxIEwM8mHMu3xqVunYPEB5Yv0W61ykcQ42iKBz5EemMalBKcz5kowQX7mG59BWpF8SBJRxA0w== X-Received: by 2002:a5d:6607:: with SMTP id n7mr5146229wru.206.1607600909546; Thu, 10 Dec 2020 03:48:29 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/36] target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failures Date: Thu, 10 Dec 2020 11:47:47 +0000 Message-Id: <20201210114756.16501-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In v8.1M, vector table fetch failures don't set HFSR.FORCED (see rule R_LLRP). (In previous versions of the architecture this was either required or IMPDEF.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-18-peter.maydell@linaro.org --- target/arm/m_helper.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 721b4b4896e..9cdc8a64c29 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -722,11 +722,15 @@ load_fail: * The HardFault is Secure if BFHFNMINS is 0 (meaning that all HFs are * secure); otherwise it targets the same security state as the * underlying exception. + * In v8.1M HardFaults from vector table fetch fails don't set FORCED. */ if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { exc_secure =3D true; } - env->v7m.hfsr |=3D R_V7M_HFSR_VECTTBL_MASK | R_V7M_HFSR_FORCED_MASK; + env->v7m.hfsr |=3D R_V7M_HFSR_VECTTBL_MASK; + if (!arm_feature(env, ARM_FEATURE_V8_1M)) { + env->v7m.hfsr |=3D R_V7M_HFSR_FORCED_MASK; + } armv7m_nvic_set_pending_derived(env->nvic, ARMV7M_EXCP_HARD, exc_secur= e); return false; } --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607604663; cv=none; d=zohomail.com; s=zohoarc; b=Wc4ztiqkeoT4n0aY31+ZJuPubKiw5I8terMaqDWoX9rEhKG0sBgqLkgKRJg2xO87fn0XsFZeIMmW8v6lAanG7fu/vrYIxHiIt1scMx+3pSeCLxNz4dZcVZMyGkFV5zd5bh/rDasIgSb2z2RnUvRd2Pp39FvKdiIj094Jh/iRfMk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607604663; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zv1NQU40j5VwFZuuid1MavRZS4TwKL2icboeKXibbVo=; b=I+wlcLXhFvKno0yZIbc3PR5MF93a5dJxrxy9Q41NDWNYhCKJeSR+gRa8itmSPT+V04V+dq+na5g1Tik1Ayju+ayARx0HnY1x4eKSA99Ly36VHa5PNJfFpxx4/70HGQSGedRL821lm1wHaMG8T+0dyqNPgPY8wQMtxDwaRrJdwaI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607604663752665.6656711252195; Thu, 10 Dec 2020 04:51:03 -0800 (PST) Received: from localhost ([::1]:58782 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKmn-0007H5-6Z for importer@patchew.org; Thu, 10 Dec 2020 07:11:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51500) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKR7-0001dw-KF for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:41 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:46701) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKQy-00078i-AW for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:41 -0500 Received: by mail-wr1-x441.google.com with SMTP id l9so5136780wrt.13 for ; Thu, 10 Dec 2020 03:48:31 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=zv1NQU40j5VwFZuuid1MavRZS4TwKL2icboeKXibbVo=; b=B9TZwJb+BdVvUkuGv2QfccQ/1nE8ODeeG6UR2h1fdtJdN/mO4V8JzdnfiHzqe3CS5I j7UYetmQi98dTIT8Nw2IuUFw3PYloVq2bkEWFAw3eJZ2t/JOiZCPV+C0e2GdpMBOL8lQ IriB8bFwoe1Gq1IzTel8dHgdHMjFXzTd23sMO7yk/HEyaFkpoRvENt0xyhUddfLzpiSE qSt1mrfbAovTs2bwy7e7lJFqguwGeYd84CTxYtjk9T9ovCtGLscSr+ZWq69zUx6wJpqF Ck/NQbHNjmSWu9rn0ZMtXgkpFhWgorQoaYuM6g11eFScwRAJ4knBAMYkd3PhdZlXB5+g oJdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zv1NQU40j5VwFZuuid1MavRZS4TwKL2icboeKXibbVo=; b=qsSwgpLXjCJzXL1p0fhYV5ocoyoDcSoYhqGRuHoEZdwKp3kd9odxbcWHjD+SzCJTvC 09QK6JA5RUfW0SpsogK2lKBpvZys+utRpUh8bboFbXJx4OMDF/1B3lFmexNl/e4XkH+F w36jRAEf2FyVpKwuga3Nyzwi/eGmrK6wf6m0/zVP2P/OVQ2ONeX6r9Mj1Sg10V41cRpg wBYmk4y41ImA8v9ozGhiyvaxu55TRQp5vrpKA3eM5ulsQzoO8ZYPvW7f59u62mEIBCJe l8Lvzp3Drn4bp1yoAUPtpJ9BmlceGx4G01qrCPkIKAo+tUFH/SygX0g9SwZOXwiXpSQs bqUw== X-Gm-Message-State: AOAM533hWD0/mrGKFRiv8yyhSlcOasND42VXShL+qXno8dCN8IvUTt2X OcxRLQNopE99uJfC3xun/u0YlCCwHn6XCA== X-Google-Smtp-Source: ABdhPJzXT5iHubrfZL4KsGnZj7sHAT28bzgbBwQJDD1GE6tzF6MYHcTmEf4FIRhPGstjHJzDOliQNw== X-Received: by 2002:a5d:5146:: with SMTP id u6mr8172163wrt.66.1607600910632; Thu, 10 Dec 2020 03:48:30 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/36] target/arm: Implement v8.1M REVIDR register Date: Thu, 10 Dec 2020 11:47:48 +0000 Message-Id: <20201210114756.16501-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x441.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In v8.1M a REVIDR register is defined, which is at address 0xe00ecfc and is a read-only IMPDEF register providing implementation specific minor revision information, like the v8A REVIDR_EL1. Implement this. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-19-peter.maydell@linaro.org --- hw/intc/armv7m_nvic.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index be3bc1f1f45..effc4a784ca 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1025,6 +1025,11 @@ static uint32_t nvic_readl(NVICState *s, uint32_t of= fset, MemTxAttrs attrs) } return val; } + case 0xcfc: + if (!arm_feature(&cpu->env, ARM_FEATURE_V8_1M)) { + goto bad_offset; + } + return cpu->revidr; case 0xd00: /* CPUID Base. */ return cpu->midr; case 0xd04: /* Interrupt Control State (ICSR) */ --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607603321; cv=none; d=zohomail.com; s=zohoarc; b=KAIAIcgOld0VhjcOEBPGo/jbnmbu5FwyaY4AAOhdrTqMv5mxSMA9RzrYVciI0O+ka31LQNwQhZNuvo6hVdl/pQWp7b3gIh5UWTkeiipHn+rL2JyIN5zrjoMRr1WOmcfJg5Y1TGRZFG5iHL5kBHkTT68fq9a0cM8obLnVR/4Pt5w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607603321; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Z717ki7dYMmiKcMEWYBMDmmyMdFhoLlq4Y+YjRsXmOI=; b=m27TWmGxdMppRpmmX0GTpJ0XD6RjJRr4OnCafDMLUJxerNb9OCGAH1CB6xzdjkarFRhEV4zRwdlx1E5hqhoRudm0Od2jYdRo8VZOb80tldp6znbbSNEXzX27nkpYYD0ZP1ZcN3HztWTvp/l3WxkKeqTBcDImvZOhf+nwE/Umpqw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607603321352466.5325391914271; Thu, 10 Dec 2020 04:28:41 -0800 (PST) Received: from localhost ([::1]:35636 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKoB-0000y8-2T for importer@patchew.org; Thu, 10 Dec 2020 07:12:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51538) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKR8-0001gD-RL for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:42 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:42489) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKR0-00078q-BF for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:42 -0500 Received: by mail-wr1-x42b.google.com with SMTP id m5so5154036wrx.9 for ; Thu, 10 Dec 2020 03:48:32 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Z717ki7dYMmiKcMEWYBMDmmyMdFhoLlq4Y+YjRsXmOI=; b=PyAC70+11+DXDVN0hrYa1h8+gRZ9DGiWRfLqhKqcr1OoyXnL8sA27U+a08j7pa73GO Uloe+h13QJgzFMRLPeVjPPViQkYA2HRfizfvvGzjKPAMF2VKtwmyMJKjjooSiSoT4ujV ZavniwHf1nxKQ6j6oiNK5Lz/vW+QBDzqRNue9KzPvR5hoxU4QBBs4g2c717eiRWu6DBQ v5KQP6Tcd01tuknvnXckZaqWugqC41AOaNbpkX0C02Ezz3tCQTDAK/VCBm/mKdQ1b1by NUUaZENrcHDcVNVSZm1RraNY+zHM9oq0DuJu3XPZpLnEKUj+YUHh5+tJ5KJ9uSBo+fTv Ir7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Z717ki7dYMmiKcMEWYBMDmmyMdFhoLlq4Y+YjRsXmOI=; b=q3z/9yfT7Q4H0Nf/OVnaa+OIIdwShip+tK0qXV6Kzl+KoB6yRtfB4eBVXVJ+CmGx1F boa23tif1Rvte/rJClRAUyOsiLMiVstMfe+CFSkKfNYpfca/MP9dvF/iJcurpacEDPYk Z4F4GeSLjqVsu6BTAulqeopofcUlg1YgHQWq93852y/k5W3e6AHA8TGUc37OmoozxPQn bCc4Gp3Y+L2TqaHfymrfeDA/DS7AQbS3F3+SI04ZKTV8003LQ7WuEKSGMB5+Q/MOB+We YdJNYXYgSIlR421a7/udTX39tcFrziLYgN1B1/QVXd1jnQh7oTsvsvsgB/DupETtiagU j5hA== X-Gm-Message-State: AOAM5311K1XXsTP2HDkL48hN2HByhhuWhCnSBaZ6Z8AynMcniyg6TY5e 7s4udzbt15/3L+CGsrSOT9LHISYug/oQmA== X-Google-Smtp-Source: ABdhPJyonpJk+4S0+TWXrZIqO9iY+rQfz+gm+Z8XU+o6Bvt4+4Ye5Gj4UC44iyLusQBR3XMOgxqrjg== X-Received: by 2002:adf:aad3:: with SMTP id i19mr7638540wrc.119.1607600911732; Thu, 10 Dec 2020 03:48:31 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/36] target/arm: Implement new v8.1M NOCP check for exception return Date: Thu, 10 Dec 2020 11:47:49 +0000 Message-Id: <20201210114756.16501-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In v8.1M a new exception return check is added which may cause a NOCP UsageFault (see rule R_XLTP): before we clear s0..s15 and the FPSCR we must check whether access to CP10 from the Security state of the returning exception is disabled; if it is then we must take a fault. (Note that for our implementation CPPWR is always RAZ/WI and so can never cause CP10 accesses to fail.) The other v8.1M change to this register-clearing code is that if MVE is implemented VPR must also be cleared, so add a TODO comment to that effect. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-20-peter.maydell@linaro.org --- target/arm/m_helper.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 9cdc8a64c29..0bdd3cc10e9 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -1515,7 +1515,27 @@ static void do_v7m_exception_exit(ARMCPU *cpu) v7m_exception_taken(cpu, excret, true, false); return; } else { - /* Clear s0..s15 and FPSCR */ + if (arm_feature(env, ARM_FEATURE_V8_1M)) { + /* v8.1M adds this NOCP check */ + bool nsacr_pass =3D exc_secure || + extract32(env->v7m.nsacr, 10, 1); + bool cpacr_pass =3D v7m_cpacr_pass(env, exc_secure, true); + if (!nsacr_pass) { + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, = true); + env->v7m.cfsr[M_REG_S] |=3D R_V7M_CFSR_NOCP_MASK; + qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on ex= isting " + "stackframe: NSACR prevents clearing FPU registers= \n"); + v7m_exception_taken(cpu, excret, true, false); + } else if (!cpacr_pass) { + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, + exc_secure); + env->v7m.cfsr[exc_secure] |=3D R_V7M_CFSR_NOCP_MASK; + qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on ex= isting " + "stackframe: CPACR prevents clearing FPU registers= \n"); + v7m_exception_taken(cpu, excret, true, false); + } + } + /* Clear s0..s15 and FPSCR; TODO also VPR when MVE is implemen= ted */ int i; =20 for (i =3D 0; i < 16; i +=3D 2) { --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607603070; cv=none; d=zohomail.com; s=zohoarc; b=A2Rbm4uFZ3UzGJvFYUR4WPfFHomXUYMvw7naS6peVz9ptZnXFMPXFebRjqgu+EQ7FYlkBeHBC6l5aS16E7JkVfcQmkRqugkg4cS8PEpSHAw8Pdyy+YvDUWWlpTs1GTIoWmPQvfRFL9LUqGDFCeh13vypj6m2e/bBgN8XQp12OVA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607603070; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=J7TAdII+zoL9ZYUXkFl6fW/f+7IWQ2Rf6gIgGSvs/e8=; b=H906MyH6Kr2av98g99VRJAbPTsCX9mN85cW4TpijnPwm1vjRaGF7hUzAyd6HXcACQdmBbNgkUShE1bTKJpaAml6N6gUgBnQt0h/58zUeWi/11eHGe7NcWy3gYKUJ5r8U77T0kVTVHC1fYsgitftXG4IqXp9yizAea+gHuhzt6X4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607603070961560.2170114789212; Thu, 10 Dec 2020 04:24:30 -0800 (PST) Received: from localhost ([::1]:44092 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKqv-0004bu-QN for importer@patchew.org; Thu, 10 Dec 2020 07:15:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51568) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKR9-0001iJ-Oc for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:43 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:43184) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKR0-000793-Bm for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:43 -0500 Received: by mail-wr1-x433.google.com with SMTP id y17so5133943wrr.10 for ; Thu, 10 Dec 2020 03:48:33 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=J7TAdII+zoL9ZYUXkFl6fW/f+7IWQ2Rf6gIgGSvs/e8=; b=vd01gzaV9SPnOo56IPYIho20N5JDv3X0Ynm4sUsJ7F/SuQVQzxPRdkLIVG3JcDP17D uvMWCjFgTUvFwKFRryt4hV0Ta11QL9mx4MwMTkweGgIyKEb5oMo4QtsguxJxTsfV7eKB fQCauhFO5R4VRm4c5US00EvUl0WTpLKUSNDjvbgp2s6s9uFWBQcyBgWTgkASuv6ZRvr/ SIqt+IZ5NoVUxWSqBEp7BSLpOIahbv2tE/IcVS0etWbxlApvltdq0FoOL2qf4Gfts/Jj 590yAHCaUaD9YuKsiD9voixEZQjEH9UCqc/4/ihgN2JN8DTs6h9dmbMD1SjTLLHWJtOp 188Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=J7TAdII+zoL9ZYUXkFl6fW/f+7IWQ2Rf6gIgGSvs/e8=; b=gtQvANBpAAwTUpYtbwjeBtFjovZx+ssjtEVPgUq/iDFn2868viKyS1nSSY4d2gmZ3p NZ9DPQp9/9IPl/xfNjgSKtH9MrDo6V9GLPIIw5rpPTmqaF6Y3NywUBITsPDucu3FhiGq 66CIamJORVJHU6YuicVtFV57GKfX9VLNVW3Nje2fm+0z8RJ9P//UuPdLBn9aU16OHMWp UL83Zo0IgqzZcEAzx5Auneeo014c5jjp01IqCZkoduU4mrC9B5wZvsjV7m3uF+L973cu Ir6OdnLdf2cyCiVP/PWv8/R2m7j8N466kT56h/o0W2w3/b83/sv6ijc6gJc60G2v7KQl AWTQ== X-Gm-Message-State: AOAM531K8VtWjJfk4DBCLtYL8kygy9Hcji2XcW7sdkEHarH305U4VlQF SXh0mDBPe1KRh1vAp7HWVNEgFmUCxpAvdA== X-Google-Smtp-Source: ABdhPJzqlbevQuvklcHmJifaYvDnE1KTr+YQlKT2fZJh4JyytWP/9CEpNNIWPKDVnpBL4MjJC6F8AQ== X-Received: by 2002:adf:efc5:: with SMTP id i5mr7629530wrp.377.1607600912876; Thu, 10 Dec 2020 03:48:32 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/36] target/arm: Implement new v8.1M VLLDM and VLSTM encodings Date: Thu, 10 Dec 2020 11:47:50 +0000 Message-Id: <20201210114756.16501-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" v8.1M adds new encodings of VLLDM and VLSTM (where bit 7 is set). The only difference is that: * the old T1 encodings UNDEF if the implementation implements 32 Dregs (this is currently architecturally impossible for M-profile) * the new T2 encodings have the implementation-defined option to read from memory (discarding the data) or write UNKNOWN values to memory for the stack slots that would be D16-D31 We choose not to make those accesses, so for us the two instructions behave identically assuming they don't UNDEF. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-21-peter.maydell@linaro.org --- target/arm/m-nocp.decode | 2 +- target/arm/translate-vfp.c.inc | 25 +++++++++++++++++++++++++ 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/target/arm/m-nocp.decode b/target/arm/m-nocp.decode index ccd62e8739a..6699626d7cb 100644 --- a/target/arm/m-nocp.decode +++ b/target/arm/m-nocp.decode @@ -36,7 +36,7 @@ =20 { # Special cases which do not take an early NOCP: VLLDM and VLSTM - VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000 + VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 op:1 000 0000 # VSCCLRM (new in v8.1M) is similar: VSCCLRM 1110 1100 1.01 1111 .... 1011 imm:7 0 vd=3D%vd_dp size=3D3 VSCCLRM 1110 1100 1.01 1111 .... 1010 imm:8 vd=3D%vd_sp size=3D2 diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 808b4077054..0db936084bd 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -3721,6 +3721,31 @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_V= LLDM_VLSTM *a) !arm_dc_feature(s, ARM_FEATURE_V8)) { return false; } + + if (a->op) { + /* + * T2 encoding ({D0-D31} reglist): v8.1M and up. We choose not + * to take the IMPDEF option to make memory accesses to the stack + * slots that correspond to the D16-D31 registers (discarding + * read data and writing UNKNOWN values), so for us the T2 + * encoding behaves identically to the T1 encoding. + */ + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { + return false; + } + } else { + /* + * T1 encoding ({D0-D15} reglist); undef if we have 32 Dregs. + * This is currently architecturally impossible, but we add the + * check to stay in line with the pseudocode. Note that we must + * emit code for the UNDEF so it takes precedence over the NOCP. + */ + if (dc_isar_feature(aa32_simd_r32, s)) { + unallocated_encoding(s); + return true; + } + } + /* * If not secure, UNDEF. We must emit code for this * rather than returning false so that this takes --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607603659; cv=none; d=zohomail.com; s=zohoarc; b=inBoXiwHtk4096YdSQl+HDLLPC6B2YkpFp7ZiWeyWjM0RBxpcREk8hckucqX/u9LHH/Fw9VC+dYtEAJYcrgHXTsnjfna6rzLMA0hUeagzNm83jzxVTfK8qq337/2iFGShRLAX4O4VwCUsCMp7fF0eBXlzQQlTqX2BNs5uuXY5PA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607603659; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=JLPn2HKUKMTiq62Z0j1xU/zunH06nHY3wxhczZYbRZk=; b=SeEb6xOQMHtF9BfDg5Sgq4RpsD3XyjPU0mt8k26QrGZt4j7CliX0v/wDHgqlZlkzJcW5ysFwwLpBV7xg5yacYccmmvCME0xJn6rpIe/qbPnO+qaoD85AhUICs5dVqcSM3h5LHZchjlp3YJhVLaH45g/+6vtdp5MJZHYwDehZIvw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607603659023859.2691685331175; Thu, 10 Dec 2020 04:34:19 -0800 (PST) Received: from localhost ([::1]:50764 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKjl-0003z9-Is for importer@patchew.org; Thu, 10 Dec 2020 07:07:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51548) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKR9-0001gu-4s for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:43 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:35975) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKR1-00079A-8n for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:42 -0500 Received: by mail-wm1-x342.google.com with SMTP id y23so5006930wmi.1 for ; Thu, 10 Dec 2020 03:48:34 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=JLPn2HKUKMTiq62Z0j1xU/zunH06nHY3wxhczZYbRZk=; b=HvI/aA4ysiXIbSouVC8CmPvDjIdu/e1AoLFdkw0XJEz4qqy6LqmOJBbYWdd1oQUoWE CPazyktdS8qjSumAKCgqXnY9vOdwjD/xc6wxjIhjW5krvXyOsNAIjY4TUcqqlPEU+/Ax IifvLkRwPrGaMFN3gueLPSWxlHKtkMul0kDrLFf/uTJB9Hl0xCoABL/wHcohdVlan0UA Ul5OWg2K6o0rFwaIh9TU7x5+L3t6HWK+5AYkhiFdi0uqAqllgdYs34drvJ1fNwd1OCbI kR/Uz4MzsTzMkBRJosvzisxJOjnZHuM3f+NZTksHE2bNev7ehfhDN95pO6Nvo79XQItL P7bA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JLPn2HKUKMTiq62Z0j1xU/zunH06nHY3wxhczZYbRZk=; b=of3vH/Abtksmp8Nd6g/JIaler7eIntSi0uKdnzvH6OFENgINgaQ38CjThwdU4N4EyA qg2a3M+j7fL85gQaDOYxY/S+S+/Y6AztCGsyL0CVxAm8XUV59b9L8qar9eeqAgxoYv+q yNzfl/CKPp1XQ6uk7TVIssgD3d+pVEkYM9mvqOnd5rZd5I2AXXSDoBgrm2WqoMS6fI4Z dowhgnbAoqKD6kn5Az4aumkw21csJt4ic+HhVpFsNmWW5e0716XW7sfXqoDRTNA2FDWF btPrEVZ/rMzJzadp3GvOu7Vy1obokU28z6myKSLj7iQ+2vRpxVeHAKmDzfqlDW4xlJfJ DJ2Q== X-Gm-Message-State: AOAM533rV29O8GcDYSm6p4CLBzyDyAstJ8MISn0rb8y2+o/no4VGZPl0 rUJWBpR9kRFXf4QDxPrfkbg3xYSv1toqtg== X-Google-Smtp-Source: ABdhPJzgb+1Gd1vT1VCvirXXt5t+yc9d/dYT43nKEasyzeAEPO28YufawQEhVFYtaLMMMOfb9Yc/Qw== X-Received: by 2002:a1c:f60b:: with SMTP id w11mr7884732wmc.180.1607600913730; Thu, 10 Dec 2020 03:48:33 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/36] hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit Date: Thu, 10 Dec 2020 11:47:51 +0000 Message-Id: <20201210114756.16501-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x342.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" v8.1M introduces a new TRD flag in the CCR register, which enables checking for stack frame integrity signatures on SG instructions. This bit is not banked, and is always RAZ/WI to Non-secure code. Adjust the code for handling CCR reads and writes to handle this. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-23-peter.maydell@linaro.org --- target/arm/cpu.h | 2 ++ hw/intc/armv7m_nvic.c | 26 ++++++++++++++++++-------- 2 files changed, 20 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 47cb5032ce9..22c55c81933 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1611,6 +1611,8 @@ FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) FIELD(V7M_CCR, DC, 16, 1) FIELD(V7M_CCR, IC, 17, 1) FIELD(V7M_CCR, BP, 18, 1) +FIELD(V7M_CCR, LOB, 19, 1) +FIELD(V7M_CCR, TRD, 20, 1) =20 /* V7M SCR bits */ FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index effc4a784ca..6f94f88a795 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1095,8 +1095,9 @@ static uint32_t nvic_readl(NVICState *s, uint32_t off= set, MemTxAttrs attrs) } return cpu->env.v7m.scr[attrs.secure]; case 0xd14: /* Configuration Control. */ - /* The BFHFNMIGN bit is the only non-banked bit; we - * keep it in the non-secure copy of the register. + /* + * Non-banked bits: BFHFNMIGN (stored in the NS copy of the regist= er) + * and TRD (stored in the S copy of the register) */ val =3D cpu->env.v7m.ccr[attrs.secure]; val |=3D cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK; @@ -1639,17 +1640,25 @@ static void nvic_writel(NVICState *s, uint32_t offs= et, uint32_t value, cpu->env.v7m.scr[attrs.secure] =3D value; break; case 0xd14: /* Configuration Control. */ + { + uint32_t mask; + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } =20 /* Enforce RAZ/WI on reserved and must-RAZ/WI bits */ - value &=3D (R_V7M_CCR_STKALIGN_MASK | - R_V7M_CCR_BFHFNMIGN_MASK | - R_V7M_CCR_DIV_0_TRP_MASK | - R_V7M_CCR_UNALIGN_TRP_MASK | - R_V7M_CCR_USERSETMPEND_MASK | - R_V7M_CCR_NONBASETHRDENA_MASK); + mask =3D R_V7M_CCR_STKALIGN_MASK | + R_V7M_CCR_BFHFNMIGN_MASK | + R_V7M_CCR_DIV_0_TRP_MASK | + R_V7M_CCR_UNALIGN_TRP_MASK | + R_V7M_CCR_USERSETMPEND_MASK | + R_V7M_CCR_NONBASETHRDENA_MASK; + if (arm_feature(&cpu->env, ARM_FEATURE_V8_1M) && attrs.secure) { + /* TRD is always RAZ/WI from NS */ + mask |=3D R_V7M_CCR_TRD_MASK; + } + value &=3D mask; =20 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { /* v8M makes NONBASETHRDENA and STKALIGN be RES1 */ @@ -1666,6 +1675,7 @@ static void nvic_writel(NVICState *s, uint32_t offset= , uint32_t value, =20 cpu->env.v7m.ccr[attrs.secure] =3D value; break; + } case 0xd24: /* System Handler Control and State (SHCSR) */ if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) { goto bad_offset; --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607603623; cv=none; d=zohomail.com; s=zohoarc; b=W3rjVoCzocsX3EBYyrPtgDwJQkuz5xYMsyRHDZJhAmQfyZSXYlpPuk+/6HdayJDlazQ48qpu0Qq7E9MwdnW36P4pM72rxO5dKm5lybmLtnkLFk2p+HPb7rMYJ19NrSdibNjy5Zb+P5lYxDl40eTOVlQFrUMVzYYN5Oa+eXR4Ujc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607603623; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jq/Nxsg8TpCNavQIVD6Yyy7eznP6/KgHKTR5ueVPo7E=; b=OT3f/skSECogcTyRsPThJGFfPqXBVV1vqvXC03Zqn4gjwuzSpXMkRtx/infZKwmo6mPREo/68RYKvWyAGP55jsUp+8u64bfeo3AOc7Pjg8ULLk3s4se/nq/Wge/fyYaZ80b+e/7MdgeqX45vwCJ3OiLiXZ/nWTE9qe0eyTXq7dw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607603623324802.0439731623261; Thu, 10 Dec 2020 04:33:43 -0800 (PST) Received: from localhost ([::1]:38882 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKpY-0002KC-8N for importer@patchew.org; Thu, 10 Dec 2020 07:13:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51586) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKRA-0001kC-P1 for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:44 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:40145) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKR2-00079S-Hu for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:44 -0500 Received: by mail-wm1-x335.google.com with SMTP id a3so4988956wmb.5 for ; Thu, 10 Dec 2020 03:48:36 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=jq/Nxsg8TpCNavQIVD6Yyy7eznP6/KgHKTR5ueVPo7E=; b=AQioI0Kr0Xu0P61rD6yQjFBIATrpSqa+jDmzfWhDT0If4kOrarBeCK4IYmqDKy16eV ojGl8MBT8dTesdJNTaM1V43H5n61z72aCPqOdhXBy+c+81oZT02ogIR0zEOnm1kw4z30 L32p50+WUIsVzCAMv2OPJI64kn4hvsOnNpFDn46TDDyD0+70e+Oqqe/919jqaWgXDa9C luyqQatP1wn0+6gG46pFE67eXOnDvbCUrfZvajfwkgNv0bmbhq6R09YeYl3V6nY2ekBf raXU/51P6TQiJWOeNil3OMPvNfHPeXarvueQSjpl5hUT4zxe/VajF9qTxLcGJGfy4TS4 PIAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jq/Nxsg8TpCNavQIVD6Yyy7eznP6/KgHKTR5ueVPo7E=; b=UITUtO3pxo5NsDNv8G/J0YEpGaKqGNsMR/31bpFN0m1HrXp3wdKdZH4gY7YLqZ4ydJ jTDg6lXGretjf7FEBBqZSo2rKhpDSV+/jD2fYqM84g3d8rUbsch+JQ04qASIf2sFZZU8 Ado65OmNjPDx+4xEyTtE7IznNiMakiQBqPzEDxZrV/14ua2iSBs0V3rykvIUYvqDPSiL JBKGrpZPyhAKLXDjr1OE9FvI+C8YQSJyekjBjqLnuQ5+M+WWvL5oKc4xfe/3jyz8vsB/ pqT0evSFcHDL4zf7Di01seByRWjzKDmpBIlOMXaZh8xRDfZ1oWewX/G35yeA/cYfeKZ2 U+jw== X-Gm-Message-State: AOAM531BuM/Gd04PEss4KWM1FMhdZvCA2LZBBmp27YuicwHbc1AmuoRv zN1KF3qVxavOFu9yW4e308caQCBtBXQ4nA== X-Google-Smtp-Source: ABdhPJyd5c/Ao6C/IBJWtvesqEy7kKOUBZTPGqKG31/P6TfdlOvQY0QXCWbIPtYfXU19Zq0nVQ0D5Q== X-Received: by 2002:a1c:6506:: with SMTP id z6mr7754594wmb.55.1607600914757; Thu, 10 Dec 2020 03:48:34 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/36] target/arm: Implement CCR_S.TRD behaviour for SG insns Date: Thu, 10 Dec 2020 11:47:52 +0000 Message-Id: <20201210114756.16501-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" v8.1M introduces a new TRD flag in the CCR register, which enables checking for stack frame integrity signatures on SG instructions. Add the code in the SG insn implementation for the new behaviour. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-24-peter.maydell@linaro.org --- target/arm/m_helper.c | 86 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 0bdd3cc10e9..643dcafb83d 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -1999,6 +1999,64 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUId= x mmu_idx, return true; } =20 +static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx, + uint32_t addr, uint32_t *spdata) +{ + /* + * Read a word of data from the stack for the SG instruction, + * writing the value into *spdata. If the load succeeds, return + * true; otherwise pend an appropriate exception and return false. + * (We can't use data load helpers here that throw an exception + * because of the context we're called in, which is halfway through + * arm_v7m_cpu_do_interrupt().) + */ + CPUState *cs =3D CPU(cpu); + CPUARMState *env =3D &cpu->env; + MemTxAttrs attrs =3D {}; + MemTxResult txres; + target_ulong page_size; + hwaddr physaddr; + int prot; + ARMMMUFaultInfo fi =3D {}; + ARMCacheAttrs cacheattrs =3D {}; + uint32_t value; + + if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &physaddr, + &attrs, &prot, &page_size, &fi, &cacheattrs)) { + /* MPU/SAU lookup failed */ + if (fi.type =3D=3D ARMFault_QEMU_SFault) { + qemu_log_mask(CPU_LOG_INT, + "...SecureFault during stack word read\n"); + env->v7m.sfsr |=3D R_V7M_SFSR_AUVIOL_MASK | R_V7M_SFSR_SFARVAL= ID_MASK; + env->v7m.sfar =3D addr; + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); + } else { + qemu_log_mask(CPU_LOG_INT, + "...MemManageFault during stack word read\n"); + env->v7m.cfsr[M_REG_S] |=3D R_V7M_CFSR_DACCVIOL_MASK | + R_V7M_CFSR_MMARVALID_MASK; + env->v7m.mmfar[M_REG_S] =3D addr; + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, false); + } + return false; + } + value =3D address_space_ldl(arm_addressspace(cs, attrs), physaddr, + attrs, &txres); + if (txres !=3D MEMTX_OK) { + /* BusFault trying to read the data */ + qemu_log_mask(CPU_LOG_INT, + "...BusFault during stack word read\n"); + env->v7m.cfsr[M_REG_NS] |=3D + (R_V7M_CFSR_PRECISERR_MASK | R_V7M_CFSR_BFARVALID_MASK); + env->v7m.bfar =3D addr; + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false); + return false; + } + + *spdata =3D value; + return true; +} + static bool v7m_handle_execute_nsc(ARMCPU *cpu) { /* @@ -2055,6 +2113,34 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu) */ qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx= 32 ", executing it\n", env->regs[15]); + + if (cpu_isar_feature(aa32_m_sec_state, cpu) && + !arm_v7m_is_handler_mode(env)) { + /* + * v8.1M exception stack frame integrity check. Note that we + * must perform the memory access even if CCR_S.TRD is zero + * and we aren't going to check what the data loaded is. + */ + uint32_t spdata, sp; + + /* + * We know we are currently NS, so the S stack pointers must be + * in other_ss_{psp,msp}, not in regs[13]/other_sp. + */ + sp =3D v7m_using_psp(env) ? env->v7m.other_ss_psp : env->v7m.other= _ss_msp; + if (!v7m_read_sg_stack_word(cpu, mmu_idx, sp, &spdata)) { + /* Stack access failed and an exception has been pended */ + return false; + } + + if (env->v7m.ccr[M_REG_S] & R_V7M_CCR_TRD_MASK) { + if (((spdata & ~1) =3D=3D 0xfefa125a) || + !(env->v7m.control[M_REG_S] & 1)) { + goto gen_invep; + } + } + } + env->regs[14] &=3D ~1; env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_SFPA_MASK; switch_v7m_security_state(env, true); --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607603291; cv=none; d=zohomail.com; s=zohoarc; b=eqSDowvrDzDHWlkipPyB6ugKD/55VKMy6MrcvCQUNiDo4MBNz+cJRuPZE+a6y3XYEkPE8xqqdP67GqGcRASXF6k3wQWiJ4vUQAKS2aVlPSDyOAoEHBmfbg9fooWBbDuTBmPevSa3M0Sluu9dUhtZ7uITa5ix5j6UTkO1iF1IX/U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607603291; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wNSRJGyldygLkHXGOyWkQbluCZKj4TF1SYWL45tCAa8=; b=UqfXNUCyDd98ffeQHzedSYNjDDONvpbCvajBn1zjEeoQX94dXY15zq/Yrwv2Eqjc2MoIxHG+gCQo5yb9o6X13PpW4MmQ8vPc2NOZVCv9t4Xhx49YxGn/IVmEi/Hq7CpFrRlubIexf2rGVU29/utGF1YarXwjPveR9i7RwANxWe0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 160760329111760.65990991321701; Thu, 10 Dec 2020 04:28:11 -0800 (PST) Received: from localhost ([::1]:60996 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKx5-00038h-G6 for importer@patchew.org; Thu, 10 Dec 2020 07:21:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51616) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKRD-0001mG-A7 for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:47 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:34864) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKR3-00079l-Hn for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:45 -0500 Received: by mail-wm1-x334.google.com with SMTP id e25so5001230wme.0 for ; Thu, 10 Dec 2020 03:48:36 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=wNSRJGyldygLkHXGOyWkQbluCZKj4TF1SYWL45tCAa8=; b=CWXB1MuOIxJTsPBYh3s27M6PZntp281ZydzRtKV73+ISQ+OjpxC4uAIe3HuXCPWB+V kCpLBoyky+8pH+FKm3exEuU05q2JcgxH0Y9jfNHe0+2RRZTV0B4mGlrZtX98XCO+11HE 3TnsMRTGAHUi0paWT0g7Tu50rvrxwLxYvU3NSkIybvCFdD7t9vSVfkcZKMd9RLFZEnIe ztgTvcSMB9FGphYsUMeR693sSZH56z2HcTzkhaao86ee0Jrgybo9O/ki2dWoc0Oytt5E TJKvZP9ycdv1ZSmPBrcYGXeZXtd/3cfcV735vcbLHkDJzrpKyhF8qyAUNY1zS6cn/bhu LoZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wNSRJGyldygLkHXGOyWkQbluCZKj4TF1SYWL45tCAa8=; b=Q2Ln7Uwdt8/cooUU/zHLPnkIasD/LvDh0ghVRd7j7AlQyy4w1M/hYgqD6cBOfsmzRw taPqlM0Zz8bcSyyNrCUxxNm46EzLkNXGyoIfyUVJuT9/XNzM1eaEwzF15pahMLxWRmwz tzBHcr17KsMvslpD/eiT/4eGnThZSgYm26Sy3hL7gCM5dyp+oD8xumUAR9EJ+gjRQoha Tvy/q0LIjwxFAwVTuxTCGWasgA6t1LQu/8H6pqCgqZZGobJaKYcyqtdAGTAa+K4cFigr 2RIRbnJDAjt05f0+2FJb31OArsT+zykkrer0byaHa1UzzTFTwVG5yj6mrfg6YJobe+jj 6Wig== X-Gm-Message-State: AOAM532d9v5wBZ4Tau70/4BH4TVrS86GjrtGcjZIj3PtoRjzxtcYvzLp ysX6GtGfUw0D1Q1kS3cULGJkmVpFHtkC+A== X-Google-Smtp-Source: ABdhPJz9h0q4Ex13PqPjspoygjgXZ9iT/v/1kDvgvPQzC65zCHtpkovj2QXAK+KgDHcDJtG7XYbinQ== X-Received: by 2002:a1c:a501:: with SMTP id o1mr7694288wme.44.1607600915950; Thu, 10 Dec 2020 03:48:35 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/36] hw/intc/armv7m_nvic: Fix "return from inactive handler" check Date: Thu, 10 Dec 2020 11:47:53 +0000 Message-Id: <20201210114756.16501-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In commit 077d7449100d824a4 we added code to handle the v8M requirement that returns from NMI or HardFault forcibly deactivate those exceptions regardless of what interrupt the guest is trying to deactivate. Unfortunately this broke the handling of the "illegal exception return because the returning exception number is not active" check for those cases. In the pseudocode this test is done on the exception the guest asks to return from, but because our implementation was doing this in armv7m_nvic_complete_irq() after the new "deactivate NMI/HardFault regardless" code we ended up doing the test on the VecInfo for that exception instead, which usually meant failing to raise the illegal exception return fault. In the case for "configurable exception targeting the opposite security state" we detected the illegal-return case but went ahead and deactivated the VecInfo anyway, which is wrong because that is the VecInfo for the other security state. Rearrange the code so that we first identify the illegal return cases, then see if we really need to deactivate NMI or HardFault instead, and finally do the deactivation. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-25-peter.maydell@linaro.org --- hw/intc/armv7m_nvic.c | 59 +++++++++++++++++++++++-------------------- 1 file changed, 32 insertions(+), 27 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 6f94f88a795..cf233c05616 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -832,10 +832,40 @@ int armv7m_nvic_complete_irq(void *opaque, int irq, b= ool secure) { NVICState *s =3D (NVICState *)opaque; VecInfo *vec =3D NULL; - int ret; + int ret =3D 0; =20 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); =20 + trace_nvic_complete_irq(irq, secure); + + if (secure && exc_is_banked(irq)) { + vec =3D &s->sec_vectors[irq]; + } else { + vec =3D &s->vectors[irq]; + } + + /* + * Identify illegal exception return cases. We can't immediately + * return at this point because we still need to deactivate + * (either this exception or NMI/HardFault) first. + */ + if (!exc_is_banked(irq) && exc_targets_secure(s, irq) !=3D secure) { + /* + * Return from a configurable exception targeting the opposite + * security state from the one we're trying to complete it for. + * Clear vec because it's not really the VecInfo for this + * (irq, secstate) so we mustn't deactivate it. + */ + ret =3D -1; + vec =3D NULL; + } else if (!vec->active) { + /* Return from an inactive interrupt */ + ret =3D -1; + } else { + /* Legal return, we will return the RETTOBASE bit value to the cal= ler */ + ret =3D nvic_rettobase(s); + } + /* * For negative priorities, v8M will forcibly deactivate the appropria= te * NMI or HardFault regardless of what interrupt we're being asked to @@ -865,32 +895,7 @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bo= ol secure) } =20 if (!vec) { - if (secure && exc_is_banked(irq)) { - vec =3D &s->sec_vectors[irq]; - } else { - vec =3D &s->vectors[irq]; - } - } - - trace_nvic_complete_irq(irq, secure); - - if (!vec->active) { - /* Tell the caller this was an illegal exception return */ - return -1; - } - - /* - * If this is a configurable exception and it is currently - * targeting the opposite security state from the one we're trying - * to complete it for, this counts as an illegal exception return. - * We still need to deactivate whatever vector the logic above has - * selected, though, as it might not be the same as the one for the - * requested exception number. - */ - if (!exc_is_banked(irq) && exc_targets_secure(s, irq) !=3D secure) { - ret =3D -1; - } else { - ret =3D nvic_rettobase(s); + return ret; } =20 vec->active =3D 0; --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607603029; cv=none; d=zohomail.com; s=zohoarc; b=P7G8TfYZUki95YmXa9+X2FWJUxQzMn1aYWTh5Qess7u7ueZhxQX/YOXu2kQ5IOSLb7oRllT3qeVewYLuayoIE6gOjVealjQc+utiLvtU+I30v9GEpQxDm97OJsZy7lOWViJ4OyxwK7sEz+KLO+HbkmyVQ8thTfeGFvSc3SZ9L4A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607603029; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lBGDqnODeEZ+VOfjvpLLt/8NFwLRd1+uKDIUVSoKz+4=; b=bS4g1g4ubqZaVyOCG1mMBZ0X3BJMhzsk+0AKL28Fa3C51Ik4uQuJQg4hwcN506o0eLHofOqmJpH4WkWO6OJInaGdsHEixUJd3ow0hvLlRyezyxKN/uEhDgWw13aT6nF/wOdOiIuEmT1VZUZyB9v40aBUCduTkOmYKs771lCI+uQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 160760302915642.194147917840155; Thu, 10 Dec 2020 04:23:49 -0800 (PST) Received: from localhost ([::1]:59438 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKmu-0007cC-JK for importer@patchew.org; Thu, 10 Dec 2020 07:11:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51602) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKRB-0001lZ-Pl for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:45 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:34866) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKR4-0007AS-FT for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:45 -0500 Received: by mail-wm1-x336.google.com with SMTP id e25so5001287wme.0 for ; Thu, 10 Dec 2020 03:48:38 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=lBGDqnODeEZ+VOfjvpLLt/8NFwLRd1+uKDIUVSoKz+4=; b=rMTYk0reR0kbgS23JU29zvjV4J2IX78kAehZ0Oq0N47NjKf9IhLGF5LSVDI7V8UK3V DJxEH5ja4TCzm1v3oSqHMX3HuuNEiCc1Z28UsPz/es2jSMMl69bFwsm6+Hs8uERJ2thv u+8BFXNyQobVPlgpvNq4qwodRiUU8iNJX8bXpkZLQoPAh2WfxYIqrpOcVLQmE5A2hbF6 ORRJjtyYkcOPExiY+I849hfRvOxjw/6G2peljYymTy40IVRNhIlhtDvlc/VIQoMDwY6s L12GcFmdc3IkBUoBuHDwhFqAsJiJNEjdyQE9u84hCRsE7EnXBA8AHxmuZ+PEROIv1U5H Uc7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lBGDqnODeEZ+VOfjvpLLt/8NFwLRd1+uKDIUVSoKz+4=; b=sjhhx4XCJgJkcFiMUY+rGmnzG8swBS0pTv+Cq+6WmH3qjpf5y5v83ewmMBsh/UvC3a vqQPxrKLfTZrToW3ef6Vk6awKcYX6uHspGFlHhq12u4TMUxKimavZwbfdcNyQi16x3y9 wlV63WpfGelMngHtrF/iowXujZITsade4bReT8kFSIxkYIECWNlrA4cI80KGd9kmMjrE 7S3HQQZdW34ep65GJ5u2aTBmAhLR6l9ghL6s8gBOZDmQ3PyGKT2BjSC3rrGhuG4zErKO XObyjbWX7uoPdBi/TZTaF5t8vvexoMNIdB0LxWui/8854BwhLKihqbk/XtZaw6McTY9D OXgA== X-Gm-Message-State: AOAM532BhBOsCPannC6QmdFnLXfYywmev6LU3P9b8kwJJ5Irv4YZ42oK bWsf874eRqMQe2UiEA3yPNKZHjMyxygjZg== X-Google-Smtp-Source: ABdhPJyV+gsSRufd/pHicFiV27GE/lNvZZUDwzinPt/4d6PHXREo4EjeicB9kg6uMhK0uAC1quYvtQ== X-Received: by 2002:a05:600c:cc:: with SMTP id u12mr7952993wmm.42.1607600916913; Thu, 10 Dec 2020 03:48:36 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/36] target/arm: Implement M-profile "minimal RAS implementation" Date: Thu, 10 Dec 2020 11:47:54 +0000 Message-Id: <20201210114756.16501-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" For v8.1M the architecture mandates that CPUs must provide at least the "minimal RAS implementation" from the Reliability, Availability and Serviceability extension. This consists of: * an ESB instruction which is a NOP -- since it is in the HINT space we need only add a comment * an RFSR register which will RAZ/WI * a RAZ/WI AIRCR.IESB bit -- the code which handles writes to AIRCR does not allow setting of RES0 bits, so we already treat this as RAZ/WI; add a comment noting that this is deliberate * minimal implementation of the RAS register block at 0xe0005000 -- this will be in a subsequent commit * setting the ID_PFR0.RAS field to 0b0010 -- we will do this when we add the Cortex-M55 CPU model Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-26-peter.maydell@linaro.org --- target/arm/cpu.h | 14 ++++++++++++++ target/arm/t32.decode | 4 ++++ hw/intc/armv7m_nvic.c | 13 +++++++++++++ 3 files changed, 31 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 22c55c81933..7e6c881a7e2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1827,6 +1827,15 @@ FIELD(ID_MMFR4, LSM, 20, 4) FIELD(ID_MMFR4, CCIDX, 24, 4) FIELD(ID_MMFR4, EVT, 28, 4) =20 +FIELD(ID_PFR0, STATE0, 0, 4) +FIELD(ID_PFR0, STATE1, 4, 4) +FIELD(ID_PFR0, STATE2, 8, 4) +FIELD(ID_PFR0, STATE3, 12, 4) +FIELD(ID_PFR0, CSV2, 16, 4) +FIELD(ID_PFR0, AMU, 20, 4) +FIELD(ID_PFR0, DIT, 24, 4) +FIELD(ID_PFR0, RAS, 28, 4) + FIELD(ID_PFR1, PROGMOD, 0, 4) FIELD(ID_PFR1, SECURITY, 4, 4) FIELD(ID_PFR1, MPROGMOD, 8, 4) @@ -3573,6 +3582,11 @@ static inline bool isar_feature_aa32_predinv(const A= RMISARegisters *id) return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) !=3D 0; } =20 +static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) !=3D 0; +} + static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) { return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) !=3D 0; diff --git a/target/arm/t32.decode b/target/arm/t32.decode index f045eb62c84..8b2c487fa7a 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -307,6 +307,10 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 ..= .. @rdm # SEV 1111 0011 1010 1111 1000 0000 0000 0100 # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 =20 + # For M-profile minimal-RAS ESB can be a NOP, which is the + # default behaviour since it is in the hint space. + # ESB 1111 0011 1010 1111 1000 0000 0001 0000 + # The canonical nop ends in 0000 0000, but the whole rest # of the space is "reserved hint, behaves as nop". NOP 1111 0011 1010 1111 1000 0000 ---- ---- diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index cf233c05616..01e331ab1e4 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1483,6 +1483,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t of= fset, MemTxAttrs attrs) return 0; } return cpu->env.v7m.sfar; + case 0xf04: /* RFSR */ + if (!cpu_isar_feature(aa32_ras, cpu)) { + goto bad_offset; + } + /* We provide minimal-RAS only: RFSR is RAZ/WI */ + return 0; case 0xf34: /* FPCCR */ if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { return 0; @@ -1611,6 +1617,7 @@ static void nvic_writel(NVICState *s, uint32_t offset= , uint32_t value, R_V7M_AIRCR_PRIGROUP_SHIFT, R_V7M_AIRCR_PRIGROUP_LENGTH); } + /* AIRCR.IESB is RAZ/WI because we implement only minimal RAS = */ if (attrs.secure) { /* These bits are only writable by secure */ cpu->env.v7m.aircr =3D value & @@ -2026,6 +2033,12 @@ static void nvic_writel(NVICState *s, uint32_t offse= t, uint32_t value, } break; } + case 0xf04: /* RFSR */ + if (!cpu_isar_feature(aa32_ras, cpu)) { + goto bad_offset; + } + /* We provide minimal-RAS only: RFSR is RAZ/WI */ + break; case 0xf34: /* FPCCR */ if (cpu_isar_feature(aa32_vfp_simd, cpu)) { /* Not all bits here are banked. */ --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607603644; cv=none; d=zohomail.com; s=zohoarc; b=iP0d9L3CWj6+NknnStH7sQG4LIl5w1ZwF9WXABIMMv5yADzm0RQb1jYHUQSDdp/o5pb1lNtl2Ca9JhJco2dPbPFMMli3HQVpREBfjZGricWoz7XMRToBlDIq+z+bcFQ+fqxftcvyvm3x2Jdst5ZmeVWSkp3APIcCq8XVSfJMxpg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607603644; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BT772+aj96371qQWOpWUi9jEw0g+4W5E3EvvBQDFiZI=; b=mPc+XtO7Y642f+bk6zVoCxHTvT/J276gYQx1KWuOfOzW/6+cdhZhk0yQZy0SZlMDU6r3+nfvmKyGH7kCdkIT7ZL7zF4qVmIW/462UHVqeOTtnaZ4JbNI6zatV/m3kRfvTMXHkh/HUQ2Q7xUXB3DwyA2XFegom93GC8DY/wWObg4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607603644213141.79525647378637; Thu, 10 Dec 2020 04:34:04 -0800 (PST) Received: from localhost ([::1]:52514 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knKte-00085l-Pu for importer@patchew.org; Thu, 10 Dec 2020 07:18:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51626) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKRD-0001nJ-AQ for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:47 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:38389) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKR5-0007B2-H8 for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:47 -0500 Received: by mail-wm1-x335.google.com with SMTP id g185so4991211wmf.3 for ; Thu, 10 Dec 2020 03:48:39 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=BT772+aj96371qQWOpWUi9jEw0g+4W5E3EvvBQDFiZI=; b=CS5t5lnyAEeXji26uTeYmh4frOJNwr01ia1QyhsUjVMCeCJGCdv7ZlTtCGPh7W8jfH zzoPrlJJvPr13qKE8isMXqhTZRQfSoVZ107swKJrdeSzo8tbbPfPp4JFqBF4Gb5NtL5c QfHgloj1UUOYdCbj0O1OLbVSP7dbq1KRbcbh4r/Ym2rjtkZ4ANP4gOas56JAFipiIAJq 13ueS90gh7oTK2Z//douUy5FU15TAYMJw+CjwIo2wooPb/ughwRemzNQy+F24nx7i3Ct CuKqcEjmZk2Bp32sqFP6ix+OMYh6S0g6tOK9jE7OBIyTvJRM7ILRpcJ61dyXL8z0DCDb KzvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BT772+aj96371qQWOpWUi9jEw0g+4W5E3EvvBQDFiZI=; b=Wh1nm1ZtP2SmfdpuYWesctyR+x2JFT5GXGjeKQ/NKznCDdo1RuONhrIJo5FC2ZSFmN jwhm+B/ECi92iSe24meYp/z41PbDYA5gYw6B3WTtdbQu3O8KCQ9k3+S4+H9KIeTKTG9t SgoxEqFVFHApbEnpdwMHG1zBjKHD3eiQpgMkwPdZmvYkyRZU6ctSvZQ+UOBasCeebgCa /jzYG2QqDCOA79FU3yPFEVaZhbYltxpBF9L9mv7X/I77WSdc+oZWYM2zqXuhxfU9wFT+ /GL23LhhL8rz/AottKDfo2Se+N5Q5Wop4TXIeIuOyydFlKoJaZyUlijhN+XFOW4j1D+p qC3Q== X-Gm-Message-State: AOAM533ZW+nBJMkllTdTse4t6NKXgLby+GJnFofYGrGWTzy+9KheZ+HF BueZovTQF/vR6bh7bB76woP8WZiW7Y7pjQ== X-Google-Smtp-Source: ABdhPJzgV0sI89+pduqYf3KKy9B9ZbKcIqjEM8LAS82lZc0YBmN+IkuiKoP7/I6CNEoyS9wFRY0Ofg== X-Received: by 2002:a7b:c843:: with SMTP id c3mr7768746wml.100.1607600918010; Thu, 10 Dec 2020 03:48:38 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 35/36] hw/intc/armv7m_nvic: Implement read/write for RAS register block Date: Thu, 10 Dec 2020 11:47:55 +0000 Message-Id: <20201210114756.16501-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The RAS feature has a block of memory-mapped registers at offset 0x5000 within the PPB. For a "minimal RAS" implementation we provide no error records and so the only registers that exist in the block are ERRIIDR and ERRDEVID. The "RAZ/WI for privileged, BusFault for nonprivileged" behaviour of the "nvic-default" region is actually valid for minimal-RAS, so the main benefit of providing an explicit implementation of the register block is more accurate LOG_UNIMP messages, and a framework for where we could add a real RAS implementation later if necessary. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-27-peter.maydell@linaro.org --- include/hw/intc/armv7m_nvic.h | 1 + hw/intc/armv7m_nvic.c | 56 +++++++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+) diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index 33b6d8810c7..39c71e15936 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -83,6 +83,7 @@ struct NVICState { MemoryRegion sysreg_ns_mem; MemoryRegion systickmem; MemoryRegion systick_ns_mem; + MemoryRegion ras_mem; MemoryRegion container; MemoryRegion defaultmem; =20 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 01e331ab1e4..f63aa2d8713 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2519,6 +2519,56 @@ static const MemoryRegionOps nvic_systick_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 + +static MemTxResult ras_read(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + if (attrs.user) { + return MEMTX_ERROR; + } + + switch (addr) { + case 0xe10: /* ERRIIDR */ + /* architect field =3D Arm; product/variant/revision 0 */ + *data =3D 0x43b; + break; + case 0xfc8: /* ERRDEVID */ + /* Minimal RAS: we implement 0 error record indexes */ + *data =3D 0; + break; + default: + qemu_log_mask(LOG_UNIMP, "Read RAS register offset 0x%x\n", + (uint32_t)addr); + *data =3D 0; + break; + } + return MEMTX_OK; +} + +static MemTxResult ras_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, + MemTxAttrs attrs) +{ + if (attrs.user) { + return MEMTX_ERROR; + } + + switch (addr) { + default: + qemu_log_mask(LOG_UNIMP, "Write to RAS register offset 0x%x\n", + (uint32_t)addr); + break; + } + return MEMTX_OK; +} + +static const MemoryRegionOps ras_ops =3D { + .read_with_attrs =3D ras_read, + .write_with_attrs =3D ras_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + /* * Unassigned portions of the PPB space are RAZ/WI for privileged * accesses, and fault for non-privileged accesses. @@ -2866,6 +2916,12 @@ static void armv7m_nvic_realize(DeviceState *dev, Er= ror **errp) &s->systick_ns_mem, 1); } =20 + if (cpu_isar_feature(aa32_ras, s->cpu)) { + memory_region_init_io(&s->ras_mem, OBJECT(s), + &ras_ops, s, "nvic_ras", 0x1000); + memory_region_add_subregion(&s->container, 0x5000, &s->ras_mem); + } + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container); } =20 --=20 2.20.1 From nobody Sat May 18 06:04:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1607603354; cv=none; d=zohomail.com; s=zohoarc; b=R+dFRRdNFXo9iPtzqLtLPFkLTwjkIEuW3N1/jvICKNSdQK9V/3VpFWLzAWgb3exLuRyCWayeiAyQzvMF7uWn8qUyWVvuxm1S17HsKxjMNpsJMGoELHO27x9hD3s+1Qt/Jzdn6eX4VjieohZ4Pf8bD2ViSiOJwYFuIgg+Zk3VP1g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607603354; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ooHjKj5Ndp5pD0CA5cS7KzNA6LKH6qDCEuw8GlWYL/A=; b=dqeifZR9Q3THrF5ojKR47fJgiRs2F0Bj4pE8ibIwagPEbTEoqUiYPjn136OK7Wpth4rbNST97Z3g3YJpRHdW1dQKSymwIKS02Lak9ADesOTj92uB7dnBC9si4oN/43gI+L43p3mFSa0PIM12wxrtjPb4BSUsTLsS5fAJDzE0LtM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607603354285462.33640878063864; Thu, 10 Dec 2020 04:29:14 -0800 (PST) Received: from localhost ([::1]:53370 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1knL4L-0003AE-4N for importer@patchew.org; Thu, 10 Dec 2020 07:29:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51658) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1knKRH-0001oZ-23 for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:57 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:40873) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1knKR6-0007BI-ED for qemu-devel@nongnu.org; Thu, 10 Dec 2020 06:48:50 -0500 Received: by mail-wr1-x444.google.com with SMTP id 91so5148609wrj.7 for ; Thu, 10 Dec 2020 03:48:40 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g192sm9304725wme.48.2020.12.10.03.48.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 03:48:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ooHjKj5Ndp5pD0CA5cS7KzNA6LKH6qDCEuw8GlWYL/A=; b=SRw+VdqPl9s+50dnCp/tdmLxxQewnT8Wj6KGVlnI9rYVP9KJWyOy3MiENjzbBYqD98 EqbJy7pjf2RD30+4m+OHDk4DLTwp8Wpf51vgg0rnAjmhC2Hs46dGo+RP1aWxbDTpiZo6 vW/pMzwI3fgj5Lq+EeWyU4hjk0rHkwviEbxiIexQkO+sgKSprCojQ4VQ142kXtAWzdNl Q4hDmChgxGMVPBDMxdD66xlFZBtaBr6hMwVvHSCqo8Sfs0xQb7rdCUIQ5VbWZy7xAn3C fSb8am5tJP4ToNqhFkPN6e94jdhspoxFKcvXziddi3BRmgMD2BLdxYIs0R3LjuIVVxWf ZcHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ooHjKj5Ndp5pD0CA5cS7KzNA6LKH6qDCEuw8GlWYL/A=; b=uhqY1RCg4mE6P4J6hWcCvYAViScl5wwbw3LIjKBM+3uF3FtuilwHJ1j5DDwaoajh80 +s1ZpxGW8HAAcsOYAPWa2pNHnIrvf/hCujjktVQbNKAK3OBH/RcPtXhk4wl1U/zTI54P 3glvOGanvgx8bVmhGk5G2vSkeibgdSaurr7idWaRkm2lxos/7O0bEBTK7vNu044iRtEf kaG7mAAHGbVXCWZEY8xo6oO8xIgrIi46x4USMYqHEhTUdw+F+OF9u9lna+97puKBsn4N EaGTmsuyCLBvDWcN7t+pGkea/Ve9npSJOMwlrUhcCpzN/6Oq9gmWMNvqbVImm/MOLs7Z Y0Ow== X-Gm-Message-State: AOAM5309U8jnp9eRYHdkOxBBZhslGunS1zAGmUQOnSvsqQjvpJ2rQ8fl Ivo980j4HfGOy6erkaU68LthvBhvlVTN6A== X-Google-Smtp-Source: ABdhPJx5/n8Yu6qGUO///ZN2+TU4A6cvPKusdImx0xq8tUknahl8yx+w3TU9aogHJBA+rBxF1qCppg== X-Received: by 2002:adf:e710:: with SMTP id c16mr7849013wrm.295.1607600918991; Thu, 10 Dec 2020 03:48:38 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/36] hw/arm/armv7m: Correct typo in QOM object name Date: Thu, 10 Dec 2020 11:47:56 +0000 Message-Id: <20201210114756.16501-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org> References: <20201210114756.16501-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x444.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Correct a typo in the name we give the NVIC object. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-28-peter.maydell@linaro.org --- hw/arm/armv7m.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 944f261dd05..8224d4ade9f 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -136,7 +136,7 @@ static void armv7m_instance_init(Object *obj) =20 memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX); =20 - object_initialize_child(obj, "nvnic", &s->nvic, TYPE_NVIC); + object_initialize_child(obj, "nvic", &s->nvic, TYPE_NVIC); object_property_add_alias(obj, "num-irq", OBJECT(&s->nvic), "num-irq"); =20 --=20 2.20.1