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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id x9sm5763368ejd.99.2020.12.08.12.37.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Dec 2020 12:37:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=e1ThRM4curwGL9SR1qu+6oPmIadZWTqw434ldcSwUhY=; b=ZeKuQVoVrFDnIq3klsVf1xGQjVp4L+Wrlg14VoaSMgNckSh70NaHbVliN9pkNF5Eqz MszKDYg8bFNUExuZvzOTq1r3/zinTrDmgcYAZ+tnpR9/BE4A9dpDgS6mJ+tne/GZUlj3 zfcX2sdZeU+un4ycvMrrbHfX73cS1HoWaXcOha3kT3fRuUO4nTyoGDb35yoTzNZSeKsZ gwNusef7Oadk2tV0vzGgAQa53E/P9JXuMI5aCJt7wuTwxIHUMv/MpFpuKujrezc0Qkfz bjyU3bx+AgOQTK0aOiZgtdqWHo9uMPpeI00031F3xRC8GSbVf6qIdw34FX8/J8HD4lqK 3RhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=e1ThRM4curwGL9SR1qu+6oPmIadZWTqw434ldcSwUhY=; b=Wc/LQ6YUkrd23lu63TnqTU0tCdUJETtYCs7ecg1yrZkMqiOTUoM1ihGsJDm2Jfvffz MhMWB3OCTe/b8DBlNxKY+DJioX2aa3CBVUQ5VHs41VgpcclQ5RFIsgZlsMSHs4BZ3ca4 aiB9vxhwqgDK8Rf+VNekHfFhx9cSJDZq8dRe5YI5YA+1ltY8BWhNCM+V7fHUkMS0RQyK wu6k7DNUu4G7tlSHV4AvJ8AosYBcQjuYjdEfXEZMrCFnk/0IZUPts2Nst5c0/sJ8ajrV jo5jUVnYSgfa9WN2LnJaropVOlN+s4OH0vAZSo1yFwUERuwCNn87X/fSQf7KXbg6fzG+ xFMQ== X-Gm-Message-State: AOAM532BOtShRbmY35Z0cReMeTva6nh6TUkMLQ+Ukxi8YALZHX/3oPco damJ7WFPBoNG3R0a0e/jboQ= X-Google-Smtp-Source: ABdhPJyC5gNPf2y9DUmPTpDv8HMoD4+4INUtL0W9fCtf6t9Ru9St5OxobKwoZfSiDbcnRnR3XxjjUw== X-Received: by 2002:a05:6402:1d3b:: with SMTP id dh27mr19429921edb.238.1607459847982; Tue, 08 Dec 2020 12:37:27 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , Richard Henderson Subject: [PATCH 04/13] target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes Date: Tue, 8 Dec 2020 21:36:55 +0100 Message-Id: <20201208203704.243704-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201208203704.243704-1-f4bug@amsat.org> References: <20201208203704.243704-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) LSA and LDSA opcodes are also available with MIPS release 6. Introduce the decodetree config files and call the decode() helpers in the main decode_opc() loop. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.h | 2 ++ target/mips/isa-mips32r6.decode | 17 ++++++++++++++ target/mips/isa-mips64r6.decode | 17 ++++++++++++++ target/mips/isa-mips_rel6_translate.c | 33 +++++++++++++++++++++++++++ target/mips/translate.c | 10 ++++++++ target/mips/meson.build | 3 +++ 6 files changed, 82 insertions(+) create mode 100644 target/mips/isa-mips32r6.decode create mode 100644 target/mips/isa-mips64r6.decode create mode 100644 target/mips/isa-mips_rel6_translate.c diff --git a/target/mips/translate.h b/target/mips/translate.h index 00601232b97..dcd8de602c1 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -96,8 +96,10 @@ extern TCGv bcond; void msa_translate_init(void); =20 /* decodetree generated */ +bool decode_mips32r6(DisasContext *ctx, uint32_t insn); bool decode_msa32(DisasContext *ctx, uint32_t insn); #if defined(TARGET_MIPS64) +bool decode_mips64r6(DisasContext *ctx, uint32_t insn); bool decode_msa64(DisasContext *ctx, uint32_t insn); #endif =20 diff --git a/target/mips/isa-mips32r6.decode b/target/mips/isa-mips32r6.dec= ode new file mode 100644 index 00000000000..027585ee042 --- /dev/null +++ b/target/mips/isa-mips32r6.decode @@ -0,0 +1,17 @@ +# MIPS32 Release 6 instruction set +# +# Copyright (C) 2020 Philippe Mathieu-Daud=C3=A9 +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: +# MIPS Architecture for Programmers Volume II-A +# The MIPS32 Instruction Set Reference Manual, Revision 6.06 +# (Document Number: MD00086-2B-MIPS32BIS-AFP-06.06) +# + +&lsa rd rt rs sa + +@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &lsa + +LSA 000000 ..... ..... ..... 000 .. 000101 @lsa diff --git a/target/mips/isa-mips64r6.decode b/target/mips/isa-mips64r6.dec= ode new file mode 100644 index 00000000000..e812224341e --- /dev/null +++ b/target/mips/isa-mips64r6.decode @@ -0,0 +1,17 @@ +# MIPS64 Release 6 instruction set +# +# Copyright (C) 2020 Philippe Mathieu-Daud=C3=A9 +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: +# MIPS Architecture for Programmers Volume II-A +# The MIPS64 Instruction Set Reference Manual, Revision 6.06 +# (Document Number: MD00087-2B-MIPS64BIS-AFP-6.06) +# + +&lsa rd rt rs sa !extern + +@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &lsa + +DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa diff --git a/target/mips/isa-mips_rel6_translate.c b/target/mips/isa-mips_r= el6_translate.c new file mode 100644 index 00000000000..c77f3ed57e0 --- /dev/null +++ b/target/mips/isa-mips_rel6_translate.c @@ -0,0 +1,33 @@ +/* + * MIPS emulation for QEMU - # Release 6 translation routines + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * Copyright (c) 2006 Marius Groeger (FPU operations) + * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) + * Copyright (c) 2020 Philippe Mathieu-Daud=C3=A9 + * + * This code is licensed under the GNU GPLv2 and later. + */ + +#include "qemu/osdep.h" +#include "tcg/tcg-op.h" +#include "exec/helper-gen.h" +#include "translate.h" + +/* Include the auto-generated decoder. */ +#include "decode-isa-mips32r6.c.inc" +#if defined(TARGET_MIPS64) +#include "decode-isa-mips64r6.c.inc" +#endif /* TARGET_MIPS64 */ + +static bool trans_LSA(DisasContext *ctx, arg_LSA *a) +{ + return gen_LSA(ctx, a->rd, a->rt, a->rs, a->sa); +} + +#if defined(TARGET_MIPS64) +static bool trans_DLSA(DisasContext *ctx, arg_LSA *a) +{ + return gen_DLSA(ctx, a->rd, a->rt, a->rs, a->sa); +} +#endif /* TARGET_MIPS64 */ diff --git a/target/mips/translate.c b/target/mips/translate.c index b3c45d6211a..9b333f97822 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28320,6 +28320,16 @@ static void decode_opc(CPUMIPSState *env, DisasCon= text *ctx) return; } =20 + /* ISA */ +#if defined(TARGET_MIPS64) + if ((ctx->insn_flags & ISA_MIPS64R6) && decode_mips64r6(ctx, ctx->opco= de)) { + return; + } +#endif /* TARGET_MIPS64 */ + if ((ctx->insn_flags & ISA_MIPS32R6) && decode_mips32r6(ctx, ctx->opco= de)) { + return; + } + op =3D MASK_OP_MAJOR(ctx->opcode); rs =3D (ctx->opcode >> 21) & 0x1f; rt =3D (ctx->opcode >> 16) & 0x1f; diff --git a/target/mips/meson.build b/target/mips/meson.build index 124b5f7d49d..a459d0917ee 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -1,7 +1,9 @@ gen =3D [ + decodetree.process('isa-mips32r6.decode', extra_args: [ '--decode=3Ddeco= de_mips32r6' ]), decodetree.process('mod-msa32.decode', extra_args: [ '--decode=3Ddecode_= msa32' ]), ] gen64 =3D [ + decodetree.process('isa-mips64r6.decode', extra_args: [ '--decode=3Ddeco= de_mips64r6' ]), decodetree.process('mod-msa64.decode', extra_args: [ '--decode=3Ddecode_= msa64' ]), ] =20 @@ -13,6 +15,7 @@ 'fpu_helper.c', 'gdbstub.c', 'helper.c', + 'isa-mips_rel6_translate.c', 'lmmi_helper.c', 'op_helper.c', 'mod-msa_helper.c', --=20 2.26.2