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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id x15sm15114272edj.91.2020.12.07.16.37.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 16:37:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3nQ2rq5dw00RN3ISHz847HNPzVTdJvTY+D4+K8lpZUM=; b=O6uCHU2nt9XOgHKby483Y1sNEgW9zJgaE8hSa8WQWYgH66G6t7hlJbK2MH5lk+LFwN o1Qlnt2501GAvmbCTl7B9MwtCzBVK2TpKTFypwDbmjxFe/y30J0jJ28WlsC8JaQSZIxH ocj81ieDaVgREldsWZrOdhUoAA+9W2hnZIHaaMSPktKI0OA9S+CI3vSEmfkGucYVgYJZ eA2PV7Cn4wmwQKMIcKsdsIlIf1s0wkcGBZFrBKkbNITyizVDfx5rGyGy/4HMycsqtXsi lobwTUTDvEGqNjiePtcpkVKjn2hHm7v18PMFCV3r6PwO9oEDKyKPshn/QIGF5RyjO2Dt izow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=3nQ2rq5dw00RN3ISHz847HNPzVTdJvTY+D4+K8lpZUM=; b=THdO/murKq6OKszeqtvJeNrHmWIMffQw147cBQBbvYUk/JNXFaiT5NeY9HpMX74djG vGmIkEwf+11qHIKPucGgBCMNxGgqthRm+cilPG3IY+/VJbQkN5eSbG3WW65AYNKmrMm2 kzLGHV9jNXEKQ6RVUxGGWRYBW7Zh8uIuiWn2qt0MV0kDwAtYM6xIbyKgGKCZiL7BnJ4Z hYfsQPp2+w9so4IklAhq1WS2zRNOH04TrBokCX9lE0HXST82LnAONfKbfntlqM+kUS55 1OSu2fUF+45iMbzDU69wY6lY3XIglhbsqyUUlgEJ2vHv7FqygdVf1HAY3tBgtK6ti9dC klpA== X-Gm-Message-State: AOAM5312ScBvspNc91M4Zh5VXK8IuIX4Bf0qnsH4F6tG0ag0aFqWHKpk hljZXQKkafFqUaztudHPqoc= X-Google-Smtp-Source: ABdhPJxMESd4QPMEdVDiXLWmRmAHveLm75pKdNMT0gidZNPbzqokGnxte7sQEw5ftElnbdGNm96S1Q== X-Received: by 2002:a17:906:a106:: with SMTP id t6mr21575903ejy.63.1607387830419; Mon, 07 Dec 2020 16:37:10 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , kvm@vger.kernel.org, Richard Henderson , Aurelien Jarno , Huacai Chen , Jiaxun Yang Subject: [PATCH 01/17] target/mips: Introduce ase_msa_available() helper Date: Tue, 8 Dec 2020 01:36:46 +0100 Message-Id: <20201208003702.4088927-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201208003702.4088927-1-f4bug@amsat.org> References: <20201208003702.4088927-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Instead of accessing CP0_Config3 directly and checking the 'MSA Present' bit, introduce an explicit helper, making the code easier to read. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/cpu.h | 6 ++++++ target/mips/kvm.c | 12 ++++++------ target/mips/translate.c | 8 +++----- 3 files changed, 15 insertions(+), 11 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 7b3ff2fd6fb..6d4c8d63930 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1296,6 +1296,12 @@ int cpu_mips_signal_handler(int host_signum, void *p= info, void *puc); bool cpu_supports_cps_smp(const char *cpu_type); bool cpu_supports_isa(const char *cpu_type, uint64_t isa); =20 +/* Check presence of MSA implementation */ +static inline bool ase_msa_available(CPUMIPSState *env) +{ + return env->CP0_Config3 & (1 << CP0C3_MSAP); +} + /* Check presence of multi-threading ASE implementation */ static inline bool ase_mt_available(CPUMIPSState *env) { diff --git a/target/mips/kvm.c b/target/mips/kvm.c index 3ca3a0da93f..c511a1303c6 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -82,7 +82,7 @@ int kvm_arch_init_vcpu(CPUState *cs) } } =20 - if (kvm_mips_msa_cap && env->CP0_Config3 & (1 << CP0C3_MSAP)) { + if (kvm_mips_msa_cap && ase_msa_available(env)) { ret =3D kvm_vcpu_enable_cap(cs, KVM_CAP_MIPS_MSA, 0, 0); if (ret < 0) { /* mark unsupported so it gets disabled on reset */ @@ -108,7 +108,7 @@ void kvm_mips_reset_vcpu(MIPSCPU *cpu) warn_report("KVM does not support FPU, disabling"); env->CP0_Config1 &=3D ~(1 << CP0C1_FP); } - if (!kvm_mips_msa_cap && env->CP0_Config3 & (1 << CP0C3_MSAP)) { + if (!kvm_mips_msa_cap && ase_msa_available(env)) { warn_report("KVM does not support MSA, disabling"); env->CP0_Config3 &=3D ~(1 << CP0C3_MSAP); } @@ -621,7 +621,7 @@ static int kvm_mips_put_fpu_registers(CPUState *cs, int= level) * FPU register state is a subset of MSA vector state, so don't pu= t FPU * registers if we're emulating a CPU with MSA. */ - if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) { + if (!ase_msa_available(env)) { /* Floating point registers */ for (i =3D 0; i < 32; ++i) { if (env->CP0_Status & (1 << CP0St_FR)) { @@ -640,7 +640,7 @@ static int kvm_mips_put_fpu_registers(CPUState *cs, int= level) } =20 /* Only put MSA state if we're emulating a CPU with MSA */ - if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { + if (ase_msa_available(env)) { /* MSA Control Registers */ if (level =3D=3D KVM_PUT_FULL_STATE) { err =3D kvm_mips_put_one_reg(cs, KVM_REG_MIPS_MSA_IR, @@ -701,7 +701,7 @@ static int kvm_mips_get_fpu_registers(CPUState *cs) * FPU register state is a subset of MSA vector state, so don't sa= ve FPU * registers if we're emulating a CPU with MSA. */ - if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) { + if (!ase_msa_available(env)) { /* Floating point registers */ for (i =3D 0; i < 32; ++i) { if (env->CP0_Status & (1 << CP0St_FR)) { @@ -720,7 +720,7 @@ static int kvm_mips_get_fpu_registers(CPUState *cs) } =20 /* Only get MSA state if we're emulating a CPU with MSA */ - if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { + if (ase_msa_available(env)) { /* MSA Control Registers */ err =3D kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_IR, &env->msair); diff --git a/target/mips/translate.c b/target/mips/translate.c index 80c9c17819f..cb822e52c4b 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24928,8 +24928,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) gen_trap(ctx, op1, rs, rt, -1); break; case OPC_LSA: /* OPC_PMON */ - if ((ctx->insn_flags & ISA_MIPS32R6) || - (env->CP0_Config3 & (1 << CP0C3_MSAP))) { + if ((ctx->insn_flags & ISA_MIPS32R6) || ase_msa_available(env)) { decode_opc_special_r6(env, ctx); } else { /* Pmon entry point, also R4010 selsl */ @@ -25031,8 +25030,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) } break; case OPC_DLSA: - if ((ctx->insn_flags & ISA_MIPS32R6) || - (env->CP0_Config3 & (1 << CP0C3_MSAP))) { + if ((ctx->insn_flags & ISA_MIPS32R6) || ase_msa_available(env)) { decode_opc_special_r6(env, ctx); } break; @@ -31879,7 +31877,7 @@ void cpu_state_reset(CPUMIPSState *env) } =20 /* MSA */ - if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { + if (ase_msa_available(env)) { msa_reset(env); } =20 --=20 2.26.2