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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id x15sm15114272edj.91.2020.12.07.16.37.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 16:37:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3nQ2rq5dw00RN3ISHz847HNPzVTdJvTY+D4+K8lpZUM=; b=O6uCHU2nt9XOgHKby483Y1sNEgW9zJgaE8hSa8WQWYgH66G6t7hlJbK2MH5lk+LFwN o1Qlnt2501GAvmbCTl7B9MwtCzBVK2TpKTFypwDbmjxFe/y30J0jJ28WlsC8JaQSZIxH ocj81ieDaVgREldsWZrOdhUoAA+9W2hnZIHaaMSPktKI0OA9S+CI3vSEmfkGucYVgYJZ eA2PV7Cn4wmwQKMIcKsdsIlIf1s0wkcGBZFrBKkbNITyizVDfx5rGyGy/4HMycsqtXsi lobwTUTDvEGqNjiePtcpkVKjn2hHm7v18PMFCV3r6PwO9oEDKyKPshn/QIGF5RyjO2Dt izow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=3nQ2rq5dw00RN3ISHz847HNPzVTdJvTY+D4+K8lpZUM=; b=THdO/murKq6OKszeqtvJeNrHmWIMffQw147cBQBbvYUk/JNXFaiT5NeY9HpMX74djG vGmIkEwf+11qHIKPucGgBCMNxGgqthRm+cilPG3IY+/VJbQkN5eSbG3WW65AYNKmrMm2 kzLGHV9jNXEKQ6RVUxGGWRYBW7Zh8uIuiWn2qt0MV0kDwAtYM6xIbyKgGKCZiL7BnJ4Z hYfsQPp2+w9so4IklAhq1WS2zRNOH04TrBokCX9lE0HXST82LnAONfKbfntlqM+kUS55 1OSu2fUF+45iMbzDU69wY6lY3XIglhbsqyUUlgEJ2vHv7FqygdVf1HAY3tBgtK6ti9dC klpA== X-Gm-Message-State: AOAM5312ScBvspNc91M4Zh5VXK8IuIX4Bf0qnsH4F6tG0ag0aFqWHKpk hljZXQKkafFqUaztudHPqoc= X-Google-Smtp-Source: ABdhPJxMESd4QPMEdVDiXLWmRmAHveLm75pKdNMT0gidZNPbzqokGnxte7sQEw5ftElnbdGNm96S1Q== X-Received: by 2002:a17:906:a106:: with SMTP id t6mr21575903ejy.63.1607387830419; Mon, 07 Dec 2020 16:37:10 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , kvm@vger.kernel.org, Richard Henderson , Aurelien Jarno , Huacai Chen , Jiaxun Yang Subject: [PATCH 01/17] target/mips: Introduce ase_msa_available() helper Date: Tue, 8 Dec 2020 01:36:46 +0100 Message-Id: <20201208003702.4088927-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201208003702.4088927-1-f4bug@amsat.org> References: <20201208003702.4088927-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Instead of accessing CP0_Config3 directly and checking the 'MSA Present' bit, introduce an explicit helper, making the code easier to read. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Jiaxun Yang --- target/mips/cpu.h | 6 ++++++ target/mips/kvm.c | 12 ++++++------ target/mips/translate.c | 8 +++----- 3 files changed, 15 insertions(+), 11 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 7b3ff2fd6fb..6d4c8d63930 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1296,6 +1296,12 @@ int cpu_mips_signal_handler(int host_signum, void *p= info, void *puc); bool cpu_supports_cps_smp(const char *cpu_type); bool cpu_supports_isa(const char *cpu_type, uint64_t isa); =20 +/* Check presence of MSA implementation */ +static inline bool ase_msa_available(CPUMIPSState *env) +{ + return env->CP0_Config3 & (1 << CP0C3_MSAP); +} + /* Check presence of multi-threading ASE implementation */ static inline bool ase_mt_available(CPUMIPSState *env) { diff --git a/target/mips/kvm.c b/target/mips/kvm.c index 3ca3a0da93f..c511a1303c6 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -82,7 +82,7 @@ int kvm_arch_init_vcpu(CPUState *cs) } } =20 - if (kvm_mips_msa_cap && env->CP0_Config3 & (1 << CP0C3_MSAP)) { + if (kvm_mips_msa_cap && ase_msa_available(env)) { ret =3D kvm_vcpu_enable_cap(cs, KVM_CAP_MIPS_MSA, 0, 0); if (ret < 0) { /* mark unsupported so it gets disabled on reset */ @@ -108,7 +108,7 @@ void kvm_mips_reset_vcpu(MIPSCPU *cpu) warn_report("KVM does not support FPU, disabling"); env->CP0_Config1 &=3D ~(1 << CP0C1_FP); } - if (!kvm_mips_msa_cap && env->CP0_Config3 & (1 << CP0C3_MSAP)) { + if (!kvm_mips_msa_cap && ase_msa_available(env)) { warn_report("KVM does not support MSA, disabling"); env->CP0_Config3 &=3D ~(1 << CP0C3_MSAP); } @@ -621,7 +621,7 @@ static int kvm_mips_put_fpu_registers(CPUState *cs, int= level) * FPU register state is a subset of MSA vector state, so don't pu= t FPU * registers if we're emulating a CPU with MSA. */ - if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) { + if (!ase_msa_available(env)) { /* Floating point registers */ for (i =3D 0; i < 32; ++i) { if (env->CP0_Status & (1 << CP0St_FR)) { @@ -640,7 +640,7 @@ static int kvm_mips_put_fpu_registers(CPUState *cs, int= level) } =20 /* Only put MSA state if we're emulating a CPU with MSA */ - if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { + if (ase_msa_available(env)) { /* MSA Control Registers */ if (level =3D=3D KVM_PUT_FULL_STATE) { err =3D kvm_mips_put_one_reg(cs, KVM_REG_MIPS_MSA_IR, @@ -701,7 +701,7 @@ static int kvm_mips_get_fpu_registers(CPUState *cs) * FPU register state is a subset of MSA vector state, so don't sa= ve FPU * registers if we're emulating a CPU with MSA. */ - if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) { + if (!ase_msa_available(env)) { /* Floating point registers */ for (i =3D 0; i < 32; ++i) { if (env->CP0_Status & (1 << CP0St_FR)) { @@ -720,7 +720,7 @@ static int kvm_mips_get_fpu_registers(CPUState *cs) } =20 /* Only get MSA state if we're emulating a CPU with MSA */ - if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { + if (ase_msa_available(env)) { /* MSA Control Registers */ err =3D kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_IR, &env->msair); diff --git a/target/mips/translate.c b/target/mips/translate.c index 80c9c17819f..cb822e52c4b 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24928,8 +24928,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) gen_trap(ctx, op1, rs, rt, -1); break; case OPC_LSA: /* OPC_PMON */ - if ((ctx->insn_flags & ISA_MIPS32R6) || - (env->CP0_Config3 & (1 << CP0C3_MSAP))) { + if ((ctx->insn_flags & ISA_MIPS32R6) || ase_msa_available(env)) { decode_opc_special_r6(env, ctx); } else { /* Pmon entry point, also R4010 selsl */ @@ -25031,8 +25030,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) } break; case OPC_DLSA: - if ((ctx->insn_flags & ISA_MIPS32R6) || - (env->CP0_Config3 & (1 << CP0C3_MSAP))) { + if ((ctx->insn_flags & ISA_MIPS32R6) || ase_msa_available(env)) { decode_opc_special_r6(env, ctx); } break; @@ -31879,7 +31877,7 @@ void cpu_state_reset(CPUMIPSState *env) } =20 /* MSA */ - if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { + if (ase_msa_available(env)) { msa_reset(env); } =20 --=20 2.26.2 From nobody Wed May 15 19:53:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.66 as permitted sender) client-ip=209.85.208.66; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f66.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.66 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1607387837; cv=none; d=zohomail.com; s=zohoarc; b=R6DbrcjfhQ2RFVBlIhiGvbct56FzEa8aiJQNDkt7sXimzHzhnwIUKZH8iNDvHXAcpe03Gwhor44bmiuZv3HJS3/0J20/lMGX1Z2YvbaU6YuA9GD31IFN20EKFzxZr9fxik636lB4SipEO/CsXkS1cwGPumfoIObuwizSCMtP3UU= ARC-Message-Signature: i=1; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id c5sm15390194edm.35.2020.12.07.16.37.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 16:37:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cBcAqpVeWvYa5kT7ybzBYVgh68psdEjYqVlt8VyNVPI=; b=EF+mKy3oCXc7rxnqO3XKMyE5cT6yoc49bbljauyDu8Z4h4SwLe3V+8SOQCrOGhM34b OY1WUXROwPnpHjU5K+jvVZEEK3nuKQeMJgUnE/b+cMiD0JaKD68B0XSYqn1vCtaKv059 FKEWGFrVf5rbcdQ0WMCtJt6dtSQXd4rRTdjpg/DqjKi8d1qlXLJ4z1oqIIQoV8fg8+Bg W0uaSc11640bqgGyejQegNrJ3M8Lg/twsTuSmtKA+VI/mgd0eDPA2UzTyhsJ1f/0nOiG NR6vJJKDBeHqXG1iDQXftECja90SlFss0TsGl3GkCc7FyPipxp/aiDgm0p5pPytrzTvY 5jCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=cBcAqpVeWvYa5kT7ybzBYVgh68psdEjYqVlt8VyNVPI=; b=D6nEtQywZdeOixMUiWvqy5FwR3Rc0pOl/Sql+kMYnJQPv4Lckm6labvrAxDkjbQnM7 z4oNBLgCLw5ShsBvgacnkSs/C34BqhU4KQSQj6b/WhmMXBR4ngrh5hhm85fuKQOy3tFD 3JSDRIDIoOpM3xajijmjI6bCk9RWno2lB39r7KrGVKUnrUHOBzp0rozcw/Bhg9pW9g20 o4FHJ5CXMtrANS+nmK99wh+9krBDfBLw67djXjGbJf8HFaR7NPNlsVhgwKkX8Kv8hVXe EqClvrTy5cYpfEQDQGExQqKH7yamk0EckpkbHnV0w0ppRrtQHfHE+CNW7z4MBJMmHd1n ROig== X-Gm-Message-State: AOAM533FWyjWn+PWVE5vWV0molpa4ovwt34I6lKtHTssbI6paG8OskNd YcNKq8qs4EZsDzUv8OOtZ8g= X-Google-Smtp-Source: ABdhPJwYUp7Xv29jcHxIdBN4YcvGvOJHHFZ1ZiLF9SaK7CNzI6qtsm7cRuqA13vmJvwaMSH62iP6GA== X-Received: by 2002:aa7:c749:: with SMTP id c9mr18694617eds.3.1607387835615; Mon, 07 Dec 2020 16:37:15 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , kvm@vger.kernel.org, Richard Henderson , Aurelien Jarno , Huacai Chen , Jiaxun Yang Subject: [PATCH 02/17] target/mips: Simplify msa_reset() Date: Tue, 8 Dec 2020 01:36:47 +0100 Message-Id: <20201208003702.4088927-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201208003702.4088927-1-f4bug@amsat.org> References: <20201208003702.4088927-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Call msa_reset() unconditionally, but only reset the MSA registers if MSA is implemented. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Jiaxun Yang --- target/mips/translate.c | 5 +---- target/mips/translate_init.c.inc | 4 ++++ 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index cb822e52c4b..b20cf1b52d9 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31876,10 +31876,7 @@ void cpu_state_reset(CPUMIPSState *env) env->hflags |=3D MIPS_HFLAG_M16; } =20 - /* MSA */ - if (ase_msa_available(env)) { - msa_reset(env); - } + msa_reset(env); =20 compute_hflags(env); restore_fp_status(env); diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.= c.inc index cac3d241831..3c9ec7e940a 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -1024,6 +1024,10 @@ static void mvp_init(CPUMIPSState *env) =20 static void msa_reset(CPUMIPSState *env) { + if (!ase_msa_available(env)) { + return; + } + #ifdef CONFIG_USER_ONLY /* MSA access enabled */ env->CP0_Config5 |=3D 1 << CP0C5_MSAEn; --=20 2.26.2 From nobody Wed May 15 19:53:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.68 as permitted sender) client-ip=209.85.208.68; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f68.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.68 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1607387842; cv=none; d=zohomail.com; s=zohoarc; b=BtvmSfP0nKqIwQofMsqBJF2uur0SOk0qNYLBEUaDbTcH+rrhSGCBgCODNNRfnp4Is+E8VKC+4pBOw6R/JKuHqIIB0SIVfGGkmVeQW/q+lVjt6LMWFtLO2IruqGyFg8YCF4bSO/bxGGF1jPpbqrOSthZkdLrox/f5KcQ7ZrbEE8Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607387842; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MK8p5/JI65dnw9C1ehTkiB134CDjpILH//LVRSp/y+4=; b=GHf6V8R26OWdjNg9K2JSy8oGZ95l8qa6Ef8LNrzWH9RatQcorpUUgOnIgl0WuSNP8gUTnG3zPsrttI+KdcB62nkytidFD30AAfDdh4yMiHyF1JZtsnkLm3/AzSxQsBs3SH7vzF8Pfd5G8m2JKwOYIbWS6xwiYINj3D/yu2LiJYk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.68 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-ed1-f68.google.com (mail-ed1-f68.google.com [209.85.208.68]) by mx.zohomail.com with SMTPS id 1607387842911434.55699219678775; Mon, 7 Dec 2020 16:37:22 -0800 (PST) Received: by mail-ed1-f68.google.com with SMTP id c7so15768721edv.6 for ; Mon, 07 Dec 2020 16:37:22 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id v18sm15235520edx.30.2020.12.07.16.37.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 16:37:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MK8p5/JI65dnw9C1ehTkiB134CDjpILH//LVRSp/y+4=; b=JQl/Lo9e1zD8sKqZt3xpzQFcocffgbQx0fKnBHhbv6FBOLuLCO9k7lVYKsJTNdKQqF 9htsecuIE89uLySufcQcCJeDYqtqhaCzIL0Vz42GOnr/yHxj9k2ZOEbmGVDlqPepyfYR +oGVjn36ZaHyNmoaKv9jOU28pGlVakxJWXO6rUVJyKMP9PB1nXyCN5TLBWPKnnowyRf7 WoU16EIQcG7jdG+GK09141mtaSlZOy+4Qufd4urUEhybldeYJPIRSE8jlQb3siR3zYPf WRoE2i5jXtmOdKxxBmvslG3lxAdal662tRyBzq08D98AhN+0U+i8dLD6VcH1HzLMJLHb 3uHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=MK8p5/JI65dnw9C1ehTkiB134CDjpILH//LVRSp/y+4=; b=eXHtFgdsXVF7onoHfSLTDx+1FsZsJnEkHCBGU2XJiQc/mFZ2FZtBZxmmXAKwr6P5lX QWhUqYAy4zp7LIifaI1mjTj/RZ9GmVOtnsrGaPff6qzDAXw5odjYUWk8LuxaZmJAKuSf lCpbyO7ycyaN6uioN3fyTFw4MSltiFKRdwi8KqYIdEbMv5al2tsHA5y5kTQR1CaLzC1y RVULD+sBJ0/tFlmU2LthuVg9vuFKxlBedhH/obw2F6hVLyy7Lgse66MFcYq/IIDn+KOi u1yVr+e6WBYzI7J+XHjurwO8fhXaaCKVX1obZTW+D/ejXTVsLNJEkypc5gUa2yv8SlOG YU5A== X-Gm-Message-State: AOAM533cRL2+5Jhc/ETFfbpL3rlulC0/JLtbuHuoTJHKo4WDroti6MFk sD5W2rkJ7OhU9qnTqecVZtk= X-Google-Smtp-Source: ABdhPJy0ccuK5jL3JysApdaWIyvf2n1/KBpbrQZrvbU7b+igqqSrf0FVUEuZq3kXmcBjiOns4mB5ww== X-Received: by 2002:a05:6402:697:: with SMTP id f23mr4216622edy.318.1607387840868; Mon, 07 Dec 2020 16:37:20 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , kvm@vger.kernel.org, Richard Henderson , Aurelien Jarno , Huacai Chen , Jiaxun Yang Subject: [PATCH 03/17] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA Date: Tue, 8 Dec 2020 01:36:48 +0100 Message-Id: <20201208003702.4088927-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201208003702.4088927-1-f4bug@amsat.org> References: <20201208003702.4088927-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) MSA presence is expressed by the MSAP bit of CP0_Config3. We don't need to check anything else. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Jiaxun Yang --- target/mips/internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 6b9d1d4b93b..3bd41239b1d 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -379,7 +379,7 @@ static inline void compute_hflags(CPUMIPSState *env) env->hflags |=3D MIPS_HFLAG_COP1X; } } - if (env->insn_flags & ASE_MSA) { + if (ase_msa_available(env)) { if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) { env->hflags |=3D MIPS_HFLAG_MSA; } --=20 2.26.2 From nobody Wed May 15 19:53:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.65 as permitted sender) client-ip=209.85.208.65; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f65.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.65 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1607387848; cv=none; d=zohomail.com; s=zohoarc; b=RkFNnPdo4WV8elq3eic6ELJ4D7K/SguEcUUtS3t2+jPvuigM+O8mlYniEaOTC91aAnSqgeOmwsxHaYBChYxYzvWzpQmWnSdN/JM64D3zTivtdgJ2sST7XOUru7oRPd7uB30L9h54XVZKO4MiFvcWU0uagHS4VJkDktXW1M+G3/Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607387848; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2EM+VJnj9N5+Eo9D9uZ5ImcarVVv2XQ17VoxaCesAks=; b=YBjCk4pz5ctXWwRFdUrTPBn78RlQ5vlaPeuIu9s5ga1lvTfertq7whqRPtBi/CBFDG+PqjcI1N+lBVpzrN/8xpbs0ybM+2kwdy7ghy03rx5kdjOC9DctTbFssMbizd+0L8y2eN1vxnJaeEia1SDWyDBlToBVrFP2bPznUsy7dLA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.65 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ed1-f65.google.com (mail-ed1-f65.google.com [209.85.208.65]) by mx.zohomail.com with SMTPS id 1607387848167898.3765226128088; Mon, 7 Dec 2020 16:37:28 -0800 (PST) Received: by mail-ed1-f65.google.com with SMTP id v22so15755638edt.9 for ; Mon, 07 Dec 2020 16:37:27 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id b21sm15304035edr.53.2020.12.07.16.37.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 16:37:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2EM+VJnj9N5+Eo9D9uZ5ImcarVVv2XQ17VoxaCesAks=; b=qcON2vRUzK9jDc9B04+NV+rpqvRemQSaXmhQe7iGcQ/CZdr5KMjVd66uY4QlxdnJqj 2D6aWArTGBrgnQTsmXA8xiyCH6lUObZxwX1sW05zgQyNwzApuwNHp7x+LvDzRVhej71V K0FozBgR6tiHwbSRK1yQA0hWa2nb1EGuTLGu/vbFnn6B9wup0H4uAD2L03qsWGykslC+ 60syOPQWPqJ3Aq8f2sdTgSOlFX/4Ereeu8L3eQ407hX0yXk96MK1Ghxqc9upv80c4x7x Tro0Fid6/Y1Wy3ygjnzt9jNtGQcgigQwzpM+5aMMbVKna1YqeORR59HqH4KZIia5P16Z GDtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=2EM+VJnj9N5+Eo9D9uZ5ImcarVVv2XQ17VoxaCesAks=; b=ARuc5BsydyFH2nIV/BVzBPPEz7uVuM5izSQiqe4ESUHFgtRnMnlOBktKoyHArEOand +NErejFEReFpf1Mz2IvFpWhsy3qWBr5ZQOY0681LXTyE1H+WaAy7uY45DCIAcTuq/rNV 4IV7vlYEDSWwWvYHN6MGtBehnj7mIulfk6nWehkTddXtjdWUc2ND4Gw+sInf9Ia/+bZi F90c+v5dHSJ9goXNQfrOY2wp3Np7b70seEjXupCFwkv1d/NPyghGvTVqKshkUmXbubDv B2ixSYMT+q6dtM9GKzVlc13e48D1+EQP3F8fUuv7vufHbwZHDcWi/MSq8M75XawX4Skj Wk+A== X-Gm-Message-State: AOAM5304k1XrT7RoC+1FbgUJc8t/aDZIQxVpf+Y8YYUj5Y5aP/cmVRND sWn97NcAUXynKDsiZmd9bNc= X-Google-Smtp-Source: ABdhPJzTkLxWJ4xhekHbm421HeMQSVtuxyRdyKD/XgMSP91/4CCBemltSQBKeZJy1HJ8wE9Hn9H7Qg== X-Received: by 2002:a05:6402:c83:: with SMTP id cm3mr22139357edb.189.1607387846066; Mon, 07 Dec 2020 16:37:26 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , kvm@vger.kernel.org, Richard Henderson , Aurelien Jarno , Huacai Chen , Jiaxun Yang Subject: [PATCH 04/17] target/mips: Simplify MSA TCG logic Date: Tue, 8 Dec 2020 01:36:49 +0100 Message-Id: <20201208003702.4088927-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201208003702.4088927-1-f4bug@amsat.org> References: <20201208003702.4088927-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Only decode MSA opcodes if MSA is present (implemented). Now than check_msa_access() will only be called if MSA is present, the only way to have MIPS_HFLAG_MSA unset is if MSA is disabled (bit CP0C5_MSAEn cleared, see previous commit). Therefore we can remove the 'reserved instruction' exception. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Jiaxun Yang --- target/mips/translate.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index b20cf1b52d9..da0cb98df09 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28576,13 +28576,8 @@ static inline int check_msa_access(DisasContext *c= tx) } =20 if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) { - if (ctx->insn_flags & ASE_MSA) { - generate_exception_end(ctx, EXCP_MSADIS); - return 0; - } else { - generate_exception_end(ctx, EXCP_RI); - return 0; - } + generate_exception_end(ctx, EXCP_MSADIS); + return 0; } return 1; } @@ -30426,7 +30421,7 @@ static void gen_msa_vec(CPUMIPSState *env, DisasCon= text *ctx) static void gen_msa(CPUMIPSState *env, DisasContext *ctx) { uint32_t opcode =3D ctx->opcode; - check_insn(ctx, ASE_MSA); + check_msa_access(ctx); =20 switch (MASK_MSA_MINOR(opcode)) { @@ -31073,9 +31068,10 @@ static void decode_opc(CPUMIPSState *env, DisasCon= text *ctx) case OPC_BNZ_H: case OPC_BNZ_W: case OPC_BNZ_D: - check_insn(ctx, ASE_MSA); - gen_msa_branch(env, ctx, op1); - break; + if (ase_msa_available(env)) { + gen_msa_branch(env, ctx, op1); + break; + } default: MIPS_INVAL("cp1"); generate_exception_end(ctx, EXCP_RI); @@ -31264,7 +31260,9 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) #endif } else { /* MDMX: Not implemented. */ - gen_msa(env, ctx); + if (ase_msa_available(env)) { + gen_msa(env, ctx); + } } break; case OPC_PCREL: --=20 2.26.2 From nobody Wed May 15 19:53:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.43 as permitted sender) client-ip=209.85.208.43; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f43.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1607387853; cv=none; d=zohomail.com; s=zohoarc; b=I1RxftPfvPZZ/mur+NJWHcTJKXaBXfrleGukXqDQehVNwErYQmvmtfuKUGtExegVGIxVC8uG2wC8xbF46bLaD8gfBKb/zCS9GgSioUen/SJE0CQO2OhL8qP6zuoJwkrLlETmuW0hi/on7xNyNkpA+pZfhair4tIifon2lnfxXdI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607387853; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=p4PZklhHw+Sb6s6FhLRnOXfQjuCQxkl6HaSQzV1xL0k=; b=gHFmBNCIK/VYPZvpbWU85HOU+TTCye5EntQlF2reRfOTiITrxa7nUuYJHUlYWkXzIDq3Tzzv5BfhSnERzYiP9VWncuMLEEyEv1WkwLDYahI4L3084xJjaUo1u4GAeG0Oy2iHphwb5M2FqDvUaswBqre7cucvfQ3xBrUfz8WfPoo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ed1-f43.google.com (mail-ed1-f43.google.com [209.85.208.43]) by mx.zohomail.com with SMTPS id 1607387853083389.4980403363328; Mon, 7 Dec 2020 16:37:33 -0800 (PST) Received: by mail-ed1-f43.google.com with SMTP id cm17so15805364edb.4 for ; Mon, 07 Dec 2020 16:37:32 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id c12sm15438706edw.55.2020.12.07.16.37.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 16:37:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=p4PZklhHw+Sb6s6FhLRnOXfQjuCQxkl6HaSQzV1xL0k=; b=AocFYn/OeGLM5fAC++aIXp7BCu8C9tkHnnrVydtHXjs6E9fqhW56MWeIdDpPSowXnh PV2RQSHQNoMECkD1X3IqwzibgIBqV+DAiBg6Zvx/m9a469QWHABV5DRTGfuSLIzIxBxw 6oYo4MT19IbFUB6nLNTVsDhOkyVhlOpk02GGZe1vSBalHyHsNHtC0HuERHzFR1OcxgKZ Et/5gZ3Ndh5LjkIk1UJF52eeNIglF6cICMxjpI2FhxmOPFRIS9Sxwjmt/vTEIms5IyYi gjNnLCiZwTvYOVfD35TXWZLz5qZttQdB/gh8SfUYZjLomSLZdLKcJfIpW0Q8irzgXpmi n0DQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=p4PZklhHw+Sb6s6FhLRnOXfQjuCQxkl6HaSQzV1xL0k=; b=JC+C2FsslorsVPq3Q8pU2gLT0Ku0XMle2wf0PfyInd9zxRha5Bd/DnlGIlmwnx3rHY Cdc12Q5RinCf7AdfXYoJhKl1PrpzJs8UYxGCRjGAiBWnCYoksWeXCs2OR5jFT+nSXayf IfAXLZNsQAcn3ZLfNbYMqapBTr8QM2OQJOrXPf4Twhf8ghH/KSbBFyAyzXkcvbVBEzQH jpBwbVE37e73zBsvVJ+oLJBb8+1KqhrLBwEis2P39TD0duAN/dIy1iOiNNWP1+afRzE5 lZOoyixpmw7qUs568yK2wx55Kp9bfk+bycdlnCLBcfk/cVtqShwQeU46f7OqpR+YgXPf ABNQ== X-Gm-Message-State: AOAM530zPFSelmTz5Wk4mmRLzJY1KQNEAJwS8oTbUcEKGFcw1J0+cJAC ku9yJrKlGkdyxmj+QopdouU= X-Google-Smtp-Source: ABdhPJwAnXIX7aszxc3Sf9KqxOLgCmeV/WG207FQq1EpZP60tAeQRn9j0oicEGIuDOZQOGynRjz0dw== X-Received: by 2002:aa7:d6c9:: with SMTP id x9mr21868250edr.96.1607387851347; Mon, 07 Dec 2020 16:37:31 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , kvm@vger.kernel.org, Richard Henderson , Aurelien Jarno , Huacai Chen , Jiaxun Yang Subject: [PATCH 05/17] target/mips: Remove now unused ASE_MSA definition Date: Tue, 8 Dec 2020 01:36:50 +0100 Message-Id: <20201208003702.4088927-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201208003702.4088927-1-f4bug@amsat.org> References: <20201208003702.4088927-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We don't use ASE_MSA anymore (replaced by ase_msa_available() checking MSAP bit from CP0_Config3). Remove it. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Jiaxun Yang --- target/mips/mips-defs.h | 1 - target/mips/translate_init.c.inc | 8 ++++---- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index ed6a7a9e545..805034b8956 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -45,7 +45,6 @@ #define ASE_MT 0x0000000040000000ULL #define ASE_SMARTMIPS 0x0000000080000000ULL #define ASE_MICROMIPS 0x0000000100000000ULL -#define ASE_MSA 0x0000000200000000ULL /* * bits 40-51: vendor-specific base instruction sets */ diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.= c.inc index 3c9ec7e940a..f6752d00afe 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -408,7 +408,7 @@ const mips_def_t mips_defs[] =3D .CP1_fcr31_rw_bitmask =3D 0xFF83FFFF, .SEGBITS =3D 32, .PABITS =3D 40, - .insn_flags =3D CPU_MIPS32R5 | ASE_MSA, + .insn_flags =3D CPU_MIPS32R5, .mmu_type =3D MMU_TYPE_R4000, }, { @@ -721,7 +721,7 @@ const mips_def_t mips_defs[] =3D .MSAIR =3D 0x03 << MSAIR_ProcID, .SEGBITS =3D 48, .PABITS =3D 48, - .insn_flags =3D CPU_MIPS64R6 | ASE_MSA, + .insn_flags =3D CPU_MIPS64R6, .mmu_type =3D MMU_TYPE_R4000, }, { @@ -761,7 +761,7 @@ const mips_def_t mips_defs[] =3D .MSAIR =3D 0x03 << MSAIR_ProcID, .SEGBITS =3D 48, .PABITS =3D 48, - .insn_flags =3D CPU_MIPS64R6 | ASE_MSA, + .insn_flags =3D CPU_MIPS64R6, .mmu_type =3D MMU_TYPE_R4000, }, { @@ -887,7 +887,7 @@ const mips_def_t mips_defs[] =3D .CP1_fcr31_rw_bitmask =3D 0xFF83FFFF, .SEGBITS =3D 48, .PABITS =3D 48, - .insn_flags =3D CPU_LOONGSON3A | ASE_MSA, + .insn_flags =3D CPU_LOONGSON3A, .mmu_type =3D MMU_TYPE_R4000, }, { --=20 2.26.2 From nobody Wed May 15 19:53:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.65 as permitted sender) client-ip=209.85.218.65; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-f65.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.65 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1607387858; cv=none; d=zohomail.com; s=zohoarc; b=n/WMReNb1Hzngn4RrLQhEFMok+S5HFrj/m7IRSpqV7tOH2CFKheCPkZaMnN2j1KCoDragOJZaDJV1IyKAQM6VFUrIpmfwEAPOPUUEUGMOfGlz7QAf8wK6iLeuZbjBdAZXArfgSTIrafdi5nYm7lQ6tY/kU+6aRe4qrY5X4GMUOw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607387858; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QCW46ctbFpbEr1flyhvkcp2iVdNnukjjxtvYS//elDE=; b=Dd9LW/afSNrM5Mp5CZLC5dMWLffesRSBwEwD2kIVZpKwQbGmqGjWcecCcT0dnBHnR++QUf42bR18z3OvVF0GLZBXa6dhzqGe532F6cpEmphZJ9q0Un0qUgvu5gorbqyxsBcgi2ZrZ2GwlJEE1o3WOCBqiyjW6zv1JqhD5lQpCC4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.65 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ej1-f65.google.com (mail-ej1-f65.google.com [209.85.218.65]) by mx.zohomail.com with SMTPS id 1607387858391362.60258897711947; Mon, 7 Dec 2020 16:37:38 -0800 (PST) Received: by mail-ej1-f65.google.com with SMTP id qw4so22144509ejb.12 for ; Mon, 07 Dec 2020 16:37:37 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id n16sm15448302edq.62.2020.12.07.16.37.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 16:37:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QCW46ctbFpbEr1flyhvkcp2iVdNnukjjxtvYS//elDE=; b=hRTzVOiwtLffpf/RB7ghUL25ihR0Uvam5D62dW66XbHPy0j5iT/gmx2TYpCtUUV8RV /8RnWh30kChkM+V6dKTLQ0SSo1d2seXpsn91guMlLd92p4TSPrFgA+bz/pynqzI2/MeL tWYAIuZUZZ5BLUpojkZcT6VBLgt2037KKcNenD6inTqK8dpOTn+z8qdti54qIvEdKEcG y/u6tgRwPl28LvACxoLiNg1LN+PAKhGQeyPfKG3+Yoa91TvXsk5Tuu9CXU/HlGiN6FNQ P2YOIYFAQRu6Sia4QBJfqia35WObvqtb0c6/+ncGgPrOGfzgvZXmEbDlE1AIQ0UKdEP4 4kag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=QCW46ctbFpbEr1flyhvkcp2iVdNnukjjxtvYS//elDE=; b=O1fwb7N11CpR0wJmBeYiK6jg8XaqoIToPblt9L09nWiOF21U6ftEWRV/f3nfoDlEI5 zFpFhGfkpHVB2fyWijq/IcwxFVcXDgoqYnWBLIAbVgXwjVlhE+P6Q8F00t1wjk/MRrCJ x8pJrJYLqPTBxxI3xM7icpUo9AfNlcYH2ZAVM/yDrM6Ysphc4sp3WKnjOS87LGmeNh2x kDcg8s8KJuEN7PELgH4GbT469cdRmBwJI8zB9vYMoI9yQpneY3uqKQ2E1c3k87iuTFLT xdgV9wVuX7WPNhYHHkqd2dwzLIEOAJZsaR1geIuEKJgOySDVzRZ3j1lrlnA6JRDQBKCf wsZw== X-Gm-Message-State: AOAM5311oMdTKy23XdBnK8EhRWfwo+m25qGSiIWsxkFz/0/jffm/+hRH 5AO4cXe2DtIOm0ME7C0VueE= X-Google-Smtp-Source: ABdhPJxWDv5KOtm3SwbxMT5bDcGrNzprFe9keLmkkknepOZtlOGbFAoR/ZG9joxns8mGd53tXugD0Q== X-Received: by 2002:a17:906:17d1:: with SMTP id u17mr21748427eje.229.1607387856511; Mon, 07 Dec 2020 16:37:36 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , kvm@vger.kernel.org, Richard Henderson , Aurelien Jarno , Huacai Chen , Jiaxun Yang Subject: [PATCH 06/17] target/mips: Alias MSA vector registers on FPU scalar registers Date: Tue, 8 Dec 2020 01:36:51 +0100 Message-Id: <20201208003702.4088927-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201208003702.4088927-1-f4bug@amsat.org> References: <20201208003702.4088927-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Commits 863f264d10f ("add msa_reset(), global msa register") and cb269f273fd ("fix multiple TCG registers covering same data") removed the FPU scalar registers and replaced them by aliases to the MSA vector registers. While this might be the case for CPU implementing MSA, this makes QEMU code incoherent for CPU not implementing it. It is simpler to inverse the logic and alias the MSA vector registers on the FPU scalar ones. Reviewed-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Jiaxun Yang --- target/mips/translate.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index da0cb98df09..95d07e837c0 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31561,16 +31561,20 @@ void mips_tcg_init(void) offsetof(CPUMIPSState, active_tc.gpr[i]), regnames[i]); - for (i =3D 0; i < 32; i++) { int off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); - msa_wr_d[i * 2] =3D - tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2]); + + fpu_f64[i] =3D tcg_global_mem_new_i64(cpu_env, off, fregnames[i]); + } + /* MSA */ + for (i =3D 0; i < 32; i++) { + int off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); + /* - * The scalar floating-point unit (FPU) registers are mapped on - * the MSA vector registers. + * The MSA vector registers are mapped on the + * scalar floating-point unit (FPU) registers. */ - fpu_f64[i] =3D msa_wr_d[i * 2]; + msa_wr_d[i * 2] =3D fpu_f64[i]; off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); msa_wr_d[i * 2 + 1] =3D tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1= ]); --=20 2.26.2 From nobody Wed May 15 19:53:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.67 as permitted sender) client-ip=209.85.218.67; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-f67.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.67 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1607387863; cv=none; d=zohomail.com; s=zohoarc; b=SFpOZBzJxGnC0ZpjlIrZhxmRoUGI4KcqKXfUd34JIvzLKQtDvxemQZWQx2HasLwRllb/+qHoI3JIi0e7k7FJzXkhBR+Kay55IeDUfR8x5J50OuBtzIGnq2Yd96r+CAt+krxb+eEfev9cCBplP/5b2eGSmNG/VyONGIO0SF7EeZ0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607387863; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wc59UVyyYsG4MSL5Uwdbqv0G30FtyphiU1+yChAdeOE=; b=N/MLMs8mlRDs3JvJ16Fj56dh067qxPVB2oVmg/4ynu+MhAPNybDXUpLBKVsCV5L4eXyOl3XjQMQp2ehpf5NEkzcuOTsbv/No6bbsFkPjsoAt0K83Sfi24EBHRlHghvLQyR1iFxAqpogd+tthhYkU36DQHscUB0ayHkqTwEXSqYo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.67 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ej1-f67.google.com (mail-ej1-f67.google.com [209.85.218.67]) by mx.zohomail.com with SMTPS id 1607387863497649.5706740630266; Mon, 7 Dec 2020 16:37:43 -0800 (PST) Received: by mail-ej1-f67.google.com with SMTP id m19so22125841ejj.11 for ; Mon, 07 Dec 2020 16:37:42 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id s1sm4884009ejx.25.2020.12.07.16.37.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 16:37:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wc59UVyyYsG4MSL5Uwdbqv0G30FtyphiU1+yChAdeOE=; b=rZiiY+p7sDRq/eDiWgYwVWDCXkKtMPzFjFGGoLdXOdzrqEfVv8PjKz5Xy0kjkNoMbc b6VejetpteRzP4glW99fS3Kz5BCZvhUJxYed8wFL6h+LxPfjylJDdrwgMcg+wOS27kau 8L9P7cHbNJNdQHo+vFQwJSF9cTNe/UHvWaoEfRsQgCY2JfRGzo3S1BRv3qOVOeUee26g 1jf0zcrWebfo0iEJcX4qmYcApPpSN/d1DnWS/RuTkLZKsNxX4OKQEfAIkx473874xR8e v8D+w0UM6/hHiyLV7SyUTnL9PCpbzazaq5xHDW5is5rT4z0B1clqV3m3KpmK6YJiBefb 9NoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=wc59UVyyYsG4MSL5Uwdbqv0G30FtyphiU1+yChAdeOE=; b=kYMbxjAzmYI/CdwLQadJdy2GfO8Nb8OtN7CQTxOjQsewhafQDl1z4yDWEr6ajSYbGn TsoxDZjuqdhslkZRDnX8phj4Y+uJa2LLvPoVh1wxWMg4gGl9z93Nihn1wJxvSOn+5bGr YwsC5Wa1fowSkfSUNA4I2WSSeAqVHncZDkjtNrEIVCl03+rZutNKettj96CeoftDXC9f U1vaiT5q+OTE9ae/BWNnqT1iLJ6EFVRCmtUiHfocWRlEIJor0NAg41ZFqybRVFw/Guu+ mUgDSj3aOq/nApSZI0EIa5oKL5QwfDeSzRl579HU7BW059LkNg7ZoZWnT/r2eGuAAVov ZG0A== X-Gm-Message-State: AOAM531vHCzSEa3fDD8FN+54BVowvpM8O+guLfGizYcbo1Vi2iGnuDo7 Is2H6ejd4j1denmQ0uOQgvw= X-Google-Smtp-Source: ABdhPJxOMAspRrPAEACiGM3Yu2xuWZ4PtjwSrLOlfbXYY9wzjsbWryiy+15xQFU3sMB8dF951GraMQ== X-Received: by 2002:a17:906:3883:: with SMTP id q3mr20755205ejd.160.1607387861693; Mon, 07 Dec 2020 16:37:41 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , kvm@vger.kernel.org, Richard Henderson , Aurelien Jarno , Huacai Chen , Jiaxun Yang Subject: [PATCH 07/17] target/mips: Extract msa_translate_init() from mips_tcg_init() Date: Tue, 8 Dec 2020 01:36:52 +0100 Message-Id: <20201208003702.4088927-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201208003702.4088927-1-f4bug@amsat.org> References: <20201208003702.4088927-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Extract the logic initialization of the MSA registers from the generic initialization. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Jiaxun Yang --- target/mips/translate.h | 3 +++ target/mips/translate.c | 33 +++++++++++++++++++-------------- 2 files changed, 22 insertions(+), 14 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index dbf7df7ba6d..765018beeea 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -80,4 +80,7 @@ extern TCGv bcond; } = \ } while (0) =20 +/* MSA */ +void msa_translate_init(void); + #endif diff --git a/target/mips/translate.c b/target/mips/translate.c index 95d07e837c0..bbe06240510 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31551,6 +31551,24 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, in= t flags) } } =20 +static void msa_translate_init(void) +{ + int i; + + for (i =3D 0; i < 32; i++) { + int off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); + + /* + * The MSA vector registers are mapped on the + * scalar floating-point unit (FPU) registers. + */ + msa_wr_d[i * 2] =3D fpu_f64[i]; + off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); + msa_wr_d[i * 2 + 1] =3D + tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1= ]); + } +} + void mips_tcg_init(void) { int i; @@ -31566,20 +31584,7 @@ void mips_tcg_init(void) =20 fpu_f64[i] =3D tcg_global_mem_new_i64(cpu_env, off, fregnames[i]); } - /* MSA */ - for (i =3D 0; i < 32; i++) { - int off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); - - /* - * The MSA vector registers are mapped on the - * scalar floating-point unit (FPU) registers. - */ - msa_wr_d[i * 2] =3D fpu_f64[i]; - off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); - msa_wr_d[i * 2 + 1] =3D - tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1= ]); - } - + msa_translate_init(); cpu_PC =3D tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, active_tc.PC), "PC"= ); for (i =3D 0; i < MIPS_DSP_ACC; i++) { --=20 2.26.2 From nobody Wed May 15 19:53:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.67 as permitted sender) client-ip=209.85.218.67; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-f67.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.67 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1607387868; cv=none; d=zohomail.com; s=zohoarc; b=m1OyW1aebxD+yRcPeHSjS29oZan3edYVPuK0sB1ETZz5c4APEP6hTJNgC0q80i0ftrdwVx/93IqCD0hiEifrX5w1ua8D1fzLvsWzMc/9pnAXai3lpwQAaAvWPsWkOBAfH78g5Kz9Y4zMkcH7uc/8L0VPVV075w8y6ZEqfp60bmQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607387868; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Qd6K0Wd+z678hfI8BXLvKrmGtYY8ZhUxppJGd/aqyEo=; b=HeU+yBgswhWHdt+9Yzcfn9pKbTOGFKyUje4qKW2lfmcfwRelDgU8XAdVepZQkLPeQ20mgGjyenNcKXph33q0fgnMUT5OlHAuDarUva1cWtG3AaIraYVAw+IFyOPcPEq3utsOwraHU7Hh/DRlPe0EqwRju8AekHVwMqccIM7rv1I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.67 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ej1-f67.google.com (mail-ej1-f67.google.com [209.85.218.67]) by mx.zohomail.com with SMTPS id 1607387868775752.0152945704839; Mon, 7 Dec 2020 16:37:48 -0800 (PST) Received: by mail-ej1-f67.google.com with SMTP id bo9so22089046ejb.13 for ; Mon, 07 Dec 2020 16:37:48 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id a13sm15142917edb.76.2020.12.07.16.37.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 16:37:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Qd6K0Wd+z678hfI8BXLvKrmGtYY8ZhUxppJGd/aqyEo=; b=EziROr0WsPcECccUciQUEj3/sGGfm+OD5Gnhq9S6EYdrKfF12dFNq54OMDETSanf9C QxL4xA3hHT7KNsAp9BzSNv61IRfc0HtldtvwpmPTPY1Yl5BxbvPSb3MAo8kwusG4XdeP jmmA2Q6fS5UDuoyZkPwj0psPD06hcTf5DKJnOHnq1init8WKkWyNOA7PVp4dtiHBNmrq /ueODkMruZMt7JNF/anbZvBsfk/PCNUw2aGK5sKTSIl2cQu2hytMGxJMK8EQwy15y9GV YZ4vACJYLdnQ9Ev8gI7YsT12V0T6v9eN9Aq1Ap1SvEQZqt44vx2+c/m2YfYZW2f+FthQ VgiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Qd6K0Wd+z678hfI8BXLvKrmGtYY8ZhUxppJGd/aqyEo=; b=OpxmygFC3zCvmm7zMECJ/pVlcplETOoWPFJRm215KQNdfj7Ii6FSv4f1pgKA3QKyN9 q8jEfTNHKsgppDpNXRP1OYUteX5Jc1/jGuq6Tr3YnLNoAcxKrBAT8R0u2TKCUVfYFRc5 VU3SIfL1tgRi/eP6aY4Bf3p8uGVY9uCT6gRqbkiEwM8Ijz9Hul2KJUUsTgREq143YoCq DMtB/z/tiv3el6G+HG6HHy6U5yRWbQw5alIWzCAGZjahNhxuZNzqEKcV+1gDVe4PBqJA 7+LXH/pEIYAUjaFSjlwFv4aIZfom/pQVHSdrB8xGM2l0/XYVfjv90TiBeDbOtmOmapHR 2x3w== X-Gm-Message-State: AOAM533jWPIaI0hJeTHu0mojJpnEqRkCtfMZySRHcl5qTd+T1cH3FwdV iIWaLf+/0zOQAZeDJlsXOW8= X-Google-Smtp-Source: ABdhPJzKqTZOshd61xQ5Ok/G0rnv4/qMJ+lnXdinCo/Oh8sJDBQNkp7xV28DXIBG+Y3weAzJvgvcdg== X-Received: by 2002:a17:906:4994:: with SMTP id p20mr21073788eju.391.1607387866919; Mon, 07 Dec 2020 16:37:46 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , kvm@vger.kernel.org, Richard Henderson , Aurelien Jarno , Huacai Chen , Jiaxun Yang Subject: [PATCH 08/17] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods Date: Tue, 8 Dec 2020 01:36:53 +0100 Message-Id: <20201208003702.4088927-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201208003702.4088927-1-f4bug@amsat.org> References: <20201208003702.4088927-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The gen_msa*() methods don't use the "CPUMIPSState *env" argument. Remove it to simplify. Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Jiaxun Yang --- target/mips/translate.c | 57 ++++++++++++++++++++--------------------- 1 file changed, 28 insertions(+), 29 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index bbe06240510..5ed7072f275 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28623,7 +28623,7 @@ static void gen_check_zero_element(TCGv tresult, ui= nt8_t df, uint8_t wt) tcg_temp_free_i64(t1); } =20 -static void gen_msa_branch(CPUMIPSState *env, DisasContext *ctx, uint32_t = op1) +static void gen_msa_branch(DisasContext *ctx, uint32_t op1) { uint8_t df =3D (ctx->opcode >> 21) & 0x3; uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; @@ -28668,7 +28668,7 @@ static void gen_msa_branch(CPUMIPSState *env, Disas= Context *ctx, uint32_t op1) ctx->hflags |=3D MIPS_HFLAG_BDS32; } =20 -static void gen_msa_i8(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_i8(DisasContext *ctx) { #define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24))) uint8_t i8 =3D (ctx->opcode >> 16) & 0xff; @@ -28726,7 +28726,7 @@ static void gen_msa_i8(CPUMIPSState *env, DisasCont= ext *ctx) tcg_temp_free_i32(ti8); } =20 -static void gen_msa_i5(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_i5(DisasContext *ctx) { #define MASK_MSA_I5(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) uint8_t df =3D (ctx->opcode >> 21) & 0x3; @@ -28799,7 +28799,7 @@ static void gen_msa_i5(CPUMIPSState *env, DisasCont= ext *ctx) tcg_temp_free_i32(timm); } =20 -static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_bit(DisasContext *ctx) { #define MASK_MSA_BIT(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) uint8_t dfm =3D (ctx->opcode >> 16) & 0x7f; @@ -28883,7 +28883,7 @@ static void gen_msa_bit(CPUMIPSState *env, DisasCon= text *ctx) tcg_temp_free_i32(tws); } =20 -static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_3r(DisasContext *ctx) { #define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) uint8_t df =3D (ctx->opcode >> 21) & 0x3; @@ -29865,7 +29865,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) tcg_temp_free_i32(tdf); } =20 -static void gen_msa_elm_3e(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_elm_3e(DisasContext *ctx) { #define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16))) uint8_t source =3D (ctx->opcode >> 11) & 0x1f; @@ -29897,8 +29897,7 @@ static void gen_msa_elm_3e(CPUMIPSState *env, Disas= Context *ctx) tcg_temp_free_i32(tsr); } =20 -static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t = df, - uint32_t n) +static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n) { #define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; @@ -30008,7 +30007,7 @@ static void gen_msa_elm_df(CPUMIPSState *env, Disas= Context *ctx, uint32_t df, tcg_temp_free_i32(tdf); } =20 -static void gen_msa_elm(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_elm(DisasContext *ctx) { uint8_t dfn =3D (ctx->opcode >> 16) & 0x3f; uint32_t df =3D 0, n =3D 0; @@ -30027,17 +30026,17 @@ static void gen_msa_elm(CPUMIPSState *env, DisasC= ontext *ctx) df =3D DF_DOUBLE; } else if (dfn =3D=3D 0x3E) { /* CTCMSA, CFCMSA, MOVE.V */ - gen_msa_elm_3e(env, ctx); + gen_msa_elm_3e(ctx); return; } else { generate_exception_end(ctx, EXCP_RI); return; } =20 - gen_msa_elm_df(env, ctx, df, n); + gen_msa_elm_df(ctx, df, n); } =20 -static void gen_msa_3rf(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_3rf(DisasContext *ctx) { #define MASK_MSA_3RF(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) uint8_t df =3D (ctx->opcode >> 21) & 0x1; @@ -30195,7 +30194,7 @@ static void gen_msa_3rf(CPUMIPSState *env, DisasCon= text *ctx) tcg_temp_free_i32(tdf); } =20 -static void gen_msa_2r(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_2r(DisasContext *ctx) { #define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \ (op & (0x7 << 18))) @@ -30279,7 +30278,7 @@ static void gen_msa_2r(CPUMIPSState *env, DisasCont= ext *ctx) tcg_temp_free_i32(tdf); } =20 -static void gen_msa_2rf(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_2rf(DisasContext *ctx) { #define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \ (op & (0xf << 17))) @@ -30350,7 +30349,7 @@ static void gen_msa_2rf(CPUMIPSState *env, DisasCon= text *ctx) tcg_temp_free_i32(tdf); } =20 -static void gen_msa_vec_v(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_vec_v(DisasContext *ctx) { #define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21))) uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; @@ -30393,7 +30392,7 @@ static void gen_msa_vec_v(CPUMIPSState *env, DisasC= ontext *ctx) tcg_temp_free_i32(twt); } =20 -static void gen_msa_vec(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa_vec(DisasContext *ctx) { switch (MASK_MSA_VEC(ctx->opcode)) { case OPC_AND_V: @@ -30403,13 +30402,13 @@ static void gen_msa_vec(CPUMIPSState *env, DisasC= ontext *ctx) case OPC_BMNZ_V: case OPC_BMZ_V: case OPC_BSEL_V: - gen_msa_vec_v(env, ctx); + gen_msa_vec_v(ctx); break; case OPC_MSA_2R: - gen_msa_2r(env, ctx); + gen_msa_2r(ctx); break; case OPC_MSA_2RF: - gen_msa_2rf(env, ctx); + gen_msa_2rf(ctx); break; default: MIPS_INVAL("MSA instruction"); @@ -30418,7 +30417,7 @@ static void gen_msa_vec(CPUMIPSState *env, DisasCon= text *ctx) } } =20 -static void gen_msa(CPUMIPSState *env, DisasContext *ctx) +static void gen_msa(DisasContext *ctx) { uint32_t opcode =3D ctx->opcode; =20 @@ -30428,15 +30427,15 @@ static void gen_msa(CPUMIPSState *env, DisasConte= xt *ctx) case OPC_MSA_I8_00: case OPC_MSA_I8_01: case OPC_MSA_I8_02: - gen_msa_i8(env, ctx); + gen_msa_i8(ctx); break; case OPC_MSA_I5_06: case OPC_MSA_I5_07: - gen_msa_i5(env, ctx); + gen_msa_i5(ctx); break; case OPC_MSA_BIT_09: case OPC_MSA_BIT_0A: - gen_msa_bit(env, ctx); + gen_msa_bit(ctx); break; case OPC_MSA_3R_0D: case OPC_MSA_3R_0E: @@ -30447,18 +30446,18 @@ static void gen_msa(CPUMIPSState *env, DisasConte= xt *ctx) case OPC_MSA_3R_13: case OPC_MSA_3R_14: case OPC_MSA_3R_15: - gen_msa_3r(env, ctx); + gen_msa_3r(ctx); break; case OPC_MSA_ELM: - gen_msa_elm(env, ctx); + gen_msa_elm(ctx); break; case OPC_MSA_3RF_1A: case OPC_MSA_3RF_1B: case OPC_MSA_3RF_1C: - gen_msa_3rf(env, ctx); + gen_msa_3rf(ctx); break; case OPC_MSA_VEC: - gen_msa_vec(env, ctx); + gen_msa_vec(ctx); break; case OPC_LD_B: case OPC_LD_H: @@ -31069,7 +31068,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_BNZ_W: case OPC_BNZ_D: if (ase_msa_available(env)) { - gen_msa_branch(env, ctx, op1); + gen_msa_branch(ctx, op1); break; } default: @@ -31261,7 +31260,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) } else { /* MDMX: Not implemented. */ if (ase_msa_available(env)) { - gen_msa(env, ctx); + gen_msa(ctx); } } break; --=20 2.26.2 From nobody Wed May 15 19:53:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.68 as permitted sender) client-ip=209.85.208.68; envelope-from=philippe.mathieu.daude@gmail.com; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id x15sm15115763edj.91.2020.12.07.16.37.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 16:37:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gl3oMtrsjL7vz0QKd+8xonphrNOt4bBvJxiMSG7akXM=; b=TboVAIByVJ0GTYoCjsgx5sycGwMrDlzcODXfxx1jMXGpIEg7kX1aPCXixeLGMNqjaR puKTh4wbzUu/gqFvY/4rcxYBjySKkPB0MGqZwlvXfxZnVGftqffvLmN7w/SfZVbdZ23R DOxLb+qCErNCmK9sqvX/A7G0rvAqHt7M0W4MVaa38YZQ/SxKtS1fHS16h2VAMSNCNY31 DISAu86VbeTJ43Y8lHB1f9AAFf484N1mo04dEbdE6bXg8ZgveyUX1ydm7etkp4JAhnVq hOpGSVLSk08rDviDLLixC6eZ1kzzB6+U0t8G60DvfOMAUJTXN6RFgbwPbs1qkjJe7IHl 00lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=gl3oMtrsjL7vz0QKd+8xonphrNOt4bBvJxiMSG7akXM=; b=JnsexI0SkezzkwXFOTzegTExI/c3EYEqBoTE9wBq9vvLrasnrBoQwl7rc/Ik6agsve SQHNGS916FkHBm2j8qppXDczQS4Sg02jPjN2TcRXimnop8x8X6BvmbPQi/GYoX70UQ9h OGDzd8JSagjVVJIgfLDN5FtPdE6EzEfYTRtCVYuqvvcDUHLMqosnOr1pzp5chEDIhlgd nwzFONTvoft+wSPS/9m+qYBg7V2J85XkMV3OMLGiyG5IH4I6joUFpfcPo62qULY2+uVm 0Gzj6+LR10JDwvhqUe3B/HV+TAtSjLbb5PBJE7qggYGoeZM5hxEl61b1p4oEMHNafnWf PwBQ== X-Gm-Message-State: AOAM533dbOKdGWwlz1SF3e1f6EAkAlrxE0okgncfxsUNUejR6E0RkM48 vg49/tsXiB3zRvIv5OBU/fo= X-Google-Smtp-Source: ABdhPJwM6x9jMd5CtJnJOHif2O47Du+oSBsYQ3wmjaIQ/FnVd6OQJzrokqJhB1bpwUJff2IimmxMqw== X-Received: by 2002:a05:6402:411:: with SMTP id q17mr22633700edv.125.1607387872222; Mon, 07 Dec 2020 16:37:52 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , kvm@vger.kernel.org, Richard Henderson , Aurelien Jarno , Huacai Chen , Jiaxun Yang Subject: [PATCH 09/17] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() Date: Tue, 8 Dec 2020 01:36:54 +0100 Message-Id: <20201208003702.4088927-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201208003702.4088927-1-f4bug@amsat.org> References: <20201208003702.4088927-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) In preparation of using the decodetree script, explode gen_msa_branch() as following: - OPC_BZ_V -> BxZ_V(EQ) - OPC_BNZ_V -> BxZ_V(NE) - OPC_BZ_[BHWD] -> BxZ(false) - OPC_BNZ_[BHWD] -> BxZ(true) Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Jiaxun Yang --- target/mips/translate.c | 71 ++++++++++++++++++++++++++++------------- 1 file changed, 49 insertions(+), 22 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 5ed7072f275..8b1019506fe 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28623,49 +28623,76 @@ static void gen_check_zero_element(TCGv tresult, = uint8_t df, uint8_t wt) tcg_temp_free_i64(t1); } =20 +static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond) +{ + TCGv_i64 t0; + + check_msa_access(ctx); + + if (ctx->hflags & MIPS_HFLAG_BMASK) { + generate_exception_end(ctx, EXCP_RI); + return true; + } + t0 =3D tcg_temp_new_i64(); + tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]); + tcg_gen_setcondi_i64(cond, t0, t0, 0); + tcg_gen_trunc_i64_tl(bcond, t0); + tcg_temp_free_i64(t0); + + ctx->btarget =3D ctx->base.pc_next + (s16 << 2) + 4; + + ctx->hflags |=3D MIPS_HFLAG_BC; + ctx->hflags |=3D MIPS_HFLAG_BDS32; + + return true; +} + +static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool i= f_not) +{ + check_msa_access(ctx); + + if (ctx->hflags & MIPS_HFLAG_BMASK) { + generate_exception_end(ctx, EXCP_RI); + return true; + } + + gen_check_zero_element(bcond, df, wt); + if (if_not) { + tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0); + } + + ctx->btarget =3D ctx->base.pc_next + (s16 << 2) + 4; + ctx->hflags |=3D MIPS_HFLAG_BC; + ctx->hflags |=3D MIPS_HFLAG_BDS32; + + return true; +} + static void gen_msa_branch(DisasContext *ctx, uint32_t op1) { uint8_t df =3D (ctx->opcode >> 21) & 0x3; uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; int64_t s16 =3D (int16_t)ctx->opcode; =20 - check_msa_access(ctx); - - if (ctx->hflags & MIPS_HFLAG_BMASK) { - generate_exception_end(ctx, EXCP_RI); - return; - } switch (op1) { case OPC_BZ_V: case OPC_BNZ_V: - { - TCGv_i64 t0 =3D tcg_temp_new_i64(); - tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]); - tcg_gen_setcondi_i64((op1 =3D=3D OPC_BZ_V) ? - TCG_COND_EQ : TCG_COND_NE, t0, t0, 0); - tcg_gen_trunc_i64_tl(bcond, t0); - tcg_temp_free_i64(t0); - } + gen_msa_BxZ_V(ctx, wt, s16, (op1 =3D=3D OPC_BZ_V) ? + TCG_COND_EQ : TCG_COND_NE); break; case OPC_BZ_B: case OPC_BZ_H: case OPC_BZ_W: case OPC_BZ_D: - gen_check_zero_element(bcond, df, wt); + gen_msa_BxZ(ctx, df, wt, s16, false); break; case OPC_BNZ_B: case OPC_BNZ_H: case OPC_BNZ_W: case OPC_BNZ_D: - gen_check_zero_element(bcond, df, wt); - tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0); + gen_msa_BxZ(ctx, df, wt, s16, true); break; } - - ctx->btarget =3D ctx->base.pc_next + (s16 << 2) + 4; - - ctx->hflags |=3D MIPS_HFLAG_BC; - ctx->hflags |=3D MIPS_HFLAG_BDS32; } =20 static void gen_msa_i8(DisasContext *ctx) --=20 2.26.2 From nobody Wed May 15 19:53:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.68 as permitted sender) client-ip=209.85.218.68; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-f68.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.68 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1607387879; cv=none; d=zohomail.com; s=zohoarc; b=JtSPG07qGmRAkOv64XTaoQpBrfUIGarL0QJafumpP8q9eYQI0YdBT8Z+KrFeYbHhgwzYBLPRjgktTEResHOlMHgfOyuOF4oPDAu4eyyYWU0uduHyg3BB6EELs4OWN2DCDP+yZ5R6dhY1Z7CwrZg0g39XZKYwbMQ12evRmVLmNug= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607387879; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aukrehohMNBj/77mUsP++hcXafJAket0+6KWGIXO0nA=; b=UFVwnDX+poC0C4Y8ItyMq9fi66CjwmT7SlrtVg3KNGJRAjnY5d9bZ7VLGkViuR+g6uRlvssys4xpaLe76afLij5FyMhOzrRY3sSzCflU2RP+wDpa9UGG5QRx9AyGRSubjDXNHglwt5DrUwbvgt3UoseWkPHj1cgUVaqgTkwSyMg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.68 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ej1-f68.google.com (mail-ej1-f68.google.com [209.85.218.68]) by mx.zohomail.com with SMTPS id 1607387879373670.166946687815; Mon, 7 Dec 2020 16:37:59 -0800 (PST) Received: by mail-ej1-f68.google.com with SMTP id b9so11846537ejy.0 for ; Mon, 07 Dec 2020 16:37:58 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id 35sm13972994ede.0.2020.12.07.16.37.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 16:37:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aukrehohMNBj/77mUsP++hcXafJAket0+6KWGIXO0nA=; b=cYJvu8QmCh1iAR1hLkECf/nTF0tRLRFQEqhfJt7gWh0LW/xSxjZT+0CXHzPvis2QXq Rse/iqCWAF2iRQQdSbiJNKGOqrquoZddI6tBLgjgaERU04mpjsN/q2JGWXR0TR/VFlrR U+W2PF7plWveFFlsBr+4d9ZiL8HfXisOAM/MrtDHETwuqDFWpiC5azSjnFBhbiNVAWZ7 E/RBx0FjkgQGiVPZyNdW06WDkk3CK9EwQEOj+CZHLS4zKjtwV1UXjO74mwC4uhqKAYoA darwQKnaXi5KhFBbp0KnkNSWv/OuWdoCO7gjc5CEgyoGF1EKPlnQ8dSnKZ0FOWrGlf6A Limw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=aukrehohMNBj/77mUsP++hcXafJAket0+6KWGIXO0nA=; b=oqcPPsGlG20/vMODicW4P5HCxV0NQOdoARpued8ueBAX87rm8pjhiCIphsCH0RnJDj 8kOVTxV5bv9Ag8ni917ZWcNQ5zJlSwITnggfdK4xCDut+gGQz/c2wE6yzapNY3xvnahm mIgDkn1+Y2fDHg7pEMna8OLjAxRQddLUzregsFXFwGuz28oy6Fv1/FDG2dpNc6bKQKVY 19iGNT+Px2na/JssRsYqvtl3/4DE5BG/U7thk7r80oRbgnYLUhiuy7ItTC8CIPFVfjNX J2nuFeMBVqanyvWHJnkQKsMUHQA6z4LeG+Li/YeuCrDI/uV6NYiEkbxYH5o508SFT26S tp1w== X-Gm-Message-State: AOAM5312AXedtS8F2X01PyH860Co7ZLyP4qX+cRxc/JA9hYt3qT5LLAX 7Cp/lOIpdot231B8VWunEJs= X-Google-Smtp-Source: ABdhPJybqp2BNzaBlaHOIYhqOJWkb3UKa2oTa2o8LX+GbDac5ltWhOZMecS3sI/+6stAs6U7VoBYtQ== X-Received: by 2002:a17:906:38c8:: with SMTP id r8mr21677157ejd.39.1607387877543; Mon, 07 Dec 2020 16:37:57 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , kvm@vger.kernel.org, Richard Henderson , Aurelien Jarno , Huacai Chen , Jiaxun Yang Subject: [PATCH 10/17] target/mips: Rename msa_helper.c as mod-msa_helper.c Date: Tue, 8 Dec 2020 01:36:55 +0100 Message-Id: <20201208003702.4088927-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201208003702.4088927-1-f4bug@amsat.org> References: <20201208003702.4088927-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) MSA means 'MIPS SIMD Architecture' and is defined as a Module by MIPS. To keep the directory sorted, we use the 'mod' prefix for MIPS modules. Rename msa_helper.c as mod-msa_helper.c. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201123204448.3260804-4-f4bug@amsat.org> Tested-by: Jiaxun Yang --- target/mips/{msa_helper.c =3D> mod-msa_helper.c} | 0 target/mips/meson.build | 3 ++- 2 files changed, 2 insertions(+), 1 deletion(-) rename target/mips/{msa_helper.c =3D> mod-msa_helper.c} (100%) diff --git a/target/mips/msa_helper.c b/target/mips/mod-msa_helper.c similarity index 100% rename from target/mips/msa_helper.c rename to target/mips/mod-msa_helper.c diff --git a/target/mips/meson.build b/target/mips/meson.build index 681a5524c0e..35dbbbf6519 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -6,8 +6,9 @@ 'gdbstub.c', 'helper.c', 'lmmi_helper.c', - 'msa_helper.c', 'op_helper.c', + 'mod-msa_helper.c', + 'translate.c', )) mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) --=20 2.26.2 From nobody Wed May 15 19:53:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.68 as permitted sender) client-ip=209.85.208.68; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f68.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.68 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1607387884; cv=none; d=zohomail.com; s=zohoarc; b=HIoSbUfxvovNC/SpvSEwhhJRRp/Rc+nr2y7iyLzpORBPj0jvojpFPb+jDgMbB1QvG31wG2slLyc5IFOrdqyFjz7nwMqYDDeAo2K/Dfv30T2KPhAowmn/Ddpfp0RoZfB2DsjNr2ovsi6QJM0s5St8wrXNmqnSdtQxhY2iqLn4o7E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607387884; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HJfC/h9BxA47xiAn2bX5wMEFeliUIBESbbbnkjnhevs=; b=BkDEG7HajjTIg18bU6i5/3x9vwRLIcwY1Yd13ki2JgWUe04aaWGd90yGvCfwmlqCNVappGNgx5PoLQJXY4goTE80NPoOiBxaL7DYS3gw7gMCZDC0OM9l1HyFPXToLxhJ+xY3kZA3HkXEHVVAAejrA+f6NelLmLSqdM6eE56prBo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.68 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ed1-f68.google.com (mail-ed1-f68.google.com [209.85.208.68]) by mx.zohomail.com with SMTPS id 1607387884735640.5522396354304; Mon, 7 Dec 2020 16:38:04 -0800 (PST) Received: by mail-ed1-f68.google.com with SMTP id c7so15770056edv.6 for ; Mon, 07 Dec 2020 16:38:04 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id cb14sm13977041ejb.105.2020.12.07.16.38.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 16:38:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HJfC/h9BxA47xiAn2bX5wMEFeliUIBESbbbnkjnhevs=; b=eKoyJyPo4jM7ONO8s65eXNGeIdy/J0u0dvc7qFl+zwSrKcgtsv1CyYoetFAl4oxqga rjKkh09MKAAgAb9y9TvqJVSX62Gns09fezDlJjNAQ250m/yZgovS8fD1OgAKgMo4396N eQnIY+fqpdHcsxjsNDixxQB2DYx3NpsN6Ds4tNqgvNC8jbSIUYhnU0jC0u7eeyNhRue3 g9NZAmQdUdekBT9YKQJDlUHdYCN9/Lmdaoik3Ga+GKh3eyQKbFsMccHwpycSNwlRdl0f GqCCPydPYccc3dOtbgGiuUSb3DFycMO1kCtTbRnQboGXAlKN3AKngA98Ncv+Sv+lzwAS /4ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=HJfC/h9BxA47xiAn2bX5wMEFeliUIBESbbbnkjnhevs=; b=W9lEguwgc2uEol+Zoy4bYmQFYp+BDsanJb/VyGWYSyMMNmxkBiXpdgQqcVq4wYeiQY fVYqBIPr3885Od2x+53d7/sMjB82fS+hfWy2HaDJWzUIXY5etWo++0ptIDTA4HCVzdfq hDbGJ7mC8B8orkbZ+wcxrq7Y06FNXycMOwvWJks8ysXOSI8Kur8GldmAn5ytIzsNla+Q ASHSxN5itK5vuBoKLoOLS9Qv3G+HjuyaKbB17IHOS9TZBP/45+kvWll0QpTgS0mST6wk wGhm8x0JL7kmSz3naPQoiq2DrAVmF7ClSYDM1VCrZYIMNG9NgpPwiAso7rbUQkHsZwfo uBWw== X-Gm-Message-State: AOAM530gLhuVqyorLFe8qZG3mh2yX3iFVkWAchNMjo6KrxaAmTWQCjxH kL1sxXHQ20zFXl1pxXTk9rs= X-Google-Smtp-Source: ABdhPJxkiRvPIJh42/zO15MexanV2Iy2soVWu7CEZ0SXqdozNkWFmgT9/GcL7BMOFXuDT6E2+NgCRA== X-Received: by 2002:a50:e715:: with SMTP id a21mr22536767edn.285.1607387882785; Mon, 07 Dec 2020 16:38:02 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , kvm@vger.kernel.org, Richard Henderson , Aurelien Jarno , Huacai Chen , Jiaxun Yang Subject: [PATCH 11/17] target/mips: Move msa_reset() to mod-msa_helper.c Date: Tue, 8 Dec 2020 01:36:56 +0100 Message-Id: <20201208003702.4088927-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201208003702.4088927-1-f4bug@amsat.org> References: <20201208003702.4088927-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) translate_init.c.inc mostly contains CPU definitions. msa_reset() doesn't belong here, move it with the MSA helpers. One comment style is updated to avoid checkpatch.pl warning. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Jiaxun Yang --- target/mips/internal.h | 2 ++ target/mips/mod-msa_helper.c | 36 ++++++++++++++++++++++++++++++++ target/mips/translate_init.c.inc | 34 ------------------------------ 3 files changed, 38 insertions(+), 34 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 3bd41239b1d..7813eb224c9 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -201,6 +201,8 @@ void mips_tcg_init(void); void cpu_state_reset(CPUMIPSState *s); void cpu_mips_realize_env(CPUMIPSState *env); =20 +void msa_reset(CPUMIPSState *env); + /* cp0_timer.c */ uint32_t cpu_mips_get_count(CPUMIPSState *env); void cpu_mips_store_count(CPUMIPSState *env, uint32_t value); diff --git a/target/mips/mod-msa_helper.c b/target/mips/mod-msa_helper.c index b89b4c44902..f0d728c03f0 100644 --- a/target/mips/mod-msa_helper.c +++ b/target/mips/mod-msa_helper.c @@ -8201,3 +8201,39 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32= _t df, uint32_t wd, =20 msa_move_v(pwd, pwx); } + +void msa_reset(CPUMIPSState *env) +{ + if (!ase_msa_available(env)) { + return; + } + +#ifdef CONFIG_USER_ONLY + /* MSA access enabled */ + env->CP0_Config5 |=3D 1 << CP0C5_MSAEn; + env->CP0_Status |=3D (1 << CP0St_CU1) | (1 << CP0St_FR); +#endif + + /* + * MSA CSR: + * - non-signaling floating point exception mode off (NX bit is 0) + * - Cause, Enables, and Flags are all 0 + * - round to nearest / ties to even (RM bits are 0) + */ + env->active_tc.msacsr =3D 0; + + restore_msa_fp_status(env); + + /* tininess detected after rounding.*/ + set_float_detect_tininess(float_tininess_after_rounding, + &env->active_tc.msa_fp_status); + + /* clear float_status exception flags */ + set_float_exception_flags(0, &env->active_tc.msa_fp_status); + + /* clear float_status nan mode */ + set_default_nan_mode(0, &env->active_tc.msa_fp_status); + + /* set proper signanling bit meaning ("1" means "quiet") */ + set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); +} diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.= c.inc index f6752d00afe..4856f4c5a4a 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -1021,37 +1021,3 @@ static void mvp_init(CPUMIPSState *env) (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2= ) | (0x1 << CP0MVPC1_PCP1); } - -static void msa_reset(CPUMIPSState *env) -{ - if (!ase_msa_available(env)) { - return; - } - -#ifdef CONFIG_USER_ONLY - /* MSA access enabled */ - env->CP0_Config5 |=3D 1 << CP0C5_MSAEn; - env->CP0_Status |=3D (1 << CP0St_CU1) | (1 << CP0St_FR); -#endif - - /* MSA CSR: - - non-signaling floating point exception mode off (NX bit is 0) - - Cause, Enables, and Flags are all 0 - - round to nearest / ties to even (RM bits are 0) */ - env->active_tc.msacsr =3D 0; - - restore_msa_fp_status(env); - - /* tininess detected after rounding.*/ - set_float_detect_tininess(float_tininess_after_rounding, - &env->active_tc.msa_fp_status); - - /* clear float_status exception flags */ - set_float_exception_flags(0, &env->active_tc.msa_fp_status); - - /* clear float_status nan mode */ - set_default_nan_mode(0, &env->active_tc.msa_fp_status); - - /* set proper signanling bit meaning ("1" means "quiet") */ - set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); -} --=20 2.26.2 From nobody Wed May 15 19:53:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.53 as permitted sender) client-ip=209.85.208.53; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id 91sm16992226edy.45.2020.12.07.16.38.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 16:38:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iM3H2Ta4pn+TmsQ3aEW4N1rY8+vva4THxsw5TVI8MU4=; b=WBhLs8SQ3OiYTnyt2aaYUXwJxbKWB9tbGUaTQjwo9ky5q00QzXjBwHt96gtuiNg8Ep lBrHzRZO9USx6sLY69s3YpGQNAzgsEkW8VM+PAB2xKXIpPHM3mzKMFBhmHDdWqSq5UKJ KZa5Ktw7/pfEgBWTWA3FOHj9ceBEYUBVe8HlR3G+T4TIiKnI8x/gLvWe8dcyIGjLo/oV AkxvpOz6N05DrH0qH8M1cxHOAZwqAQcAaFcz7ig60xQDEUu+5GDMPHrNkyu4td+RLXqn BeNz93+QNJqyM6Ov/kZ1RTFhgk2EQM7iIww9o4kl2YDg45a7MOsmWu23F8VkSkqlJo3b MbGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=iM3H2Ta4pn+TmsQ3aEW4N1rY8+vva4THxsw5TVI8MU4=; b=rg4sS75RXaIE6XKp9gXloNuMfFbgJ/+70GK+FCTrhuSwW0ITjeiV0HgLfqD6V0+PhY 7iMzoWi70er7Z+xkki0S0AYHDJIGpU1q+DSPMSYsvkfIslo+oeQAI7tTMllY9FbJkTkD 3xrGAlAYlNz0iWFx8cy2CE1nVDPWXHvus4F3m9tfWNCubRUhpsrahGgjAh+OtVhjNouV fmZTJWzzQockHBLzNhInGF/UfpDjhKBTZGvv0nRo0mhIGZ4VhpBb/UWmF361wpvNrajr TD8r6ldHWol3MBznjvB6Zeh9yUk1Gz16Lyae5CkGUkzFG6DBUxjCBHoknkzbJ/igZ+h2 Ivmg== X-Gm-Message-State: AOAM531Pf3xkiNYAgFEuEp3Gi6sEiW1fHTJ4JK5ZWElqnyuN9Fltbnz4 N+M5w0Cf0y3aLSCOH4VD6ek= X-Google-Smtp-Source: ABdhPJz/T2RNYjSwREIDjK1dctOdOKN3qyCsHMkk+yLzLx6y2hi96E/f502UEpHiYX22T+V0xS8MOQ== X-Received: by 2002:aa7:d915:: with SMTP id a21mr22114267edr.251.1607387888253; Mon, 07 Dec 2020 16:38:08 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , kvm@vger.kernel.org, Richard Henderson , Aurelien Jarno , Huacai Chen , Jiaxun Yang Subject: [PATCH 12/17] target/mips: Extract MSA helpers from op_helper.c Date: Tue, 8 Dec 2020 01:36:57 +0100 Message-Id: <20201208003702.4088927-13-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201208003702.4088927-1-f4bug@amsat.org> References: <20201208003702.4088927-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) We have ~400 lines of MSA helpers in the generic op_helper.c, move them with the other helpers in 'mod-msa_helper.c'. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201123204448.3260804-5-f4bug@amsat.org> Tested-by: Jiaxun Yang --- target/mips/mod-msa_helper.c | 393 ++++++++++++++++++++++++++++++++++ target/mips/op_helper.c | 394 ----------------------------------- 2 files changed, 393 insertions(+), 394 deletions(-) diff --git a/target/mips/mod-msa_helper.c b/target/mips/mod-msa_helper.c index f0d728c03f0..1298a1917ce 100644 --- a/target/mips/mod-msa_helper.c +++ b/target/mips/mod-msa_helper.c @@ -22,6 +22,7 @@ #include "internal.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" +#include "exec/memop.h" #include "fpu/softfloat.h" #include "fpu_helper.h" =20 @@ -8202,6 +8203,398 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint3= 2_t df, uint32_t wd, msa_move_v(pwd, pwx); } =20 +/* Data format min and max values */ +#define DF_BITS(df) (1 << ((df) + 3)) + +/* Element-by-element access macros */ +#define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df)) + +#if !defined(CONFIG_USER_ONLY) +#define MEMOP_IDX(DF) \ + TCGMemOpIdx oi =3D make_memop_idx(MO_TE | DF | MO_UNALN, \ + cpu_mmu_index(env, false)); +#else +#define MEMOP_IDX(DF) +#endif + +void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + MEMOP_IDX(DF_BYTE) +#if !defined(CONFIG_USER_ONLY) +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->b[0] =3D helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GE= TPC()); + pwd->b[1] =3D helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GE= TPC()); + pwd->b[2] =3D helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GE= TPC()); + pwd->b[3] =3D helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GE= TPC()); + pwd->b[4] =3D helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GE= TPC()); + pwd->b[5] =3D helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GE= TPC()); + pwd->b[6] =3D helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GE= TPC()); + pwd->b[7] =3D helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GE= TPC()); + pwd->b[8] =3D helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GE= TPC()); + pwd->b[9] =3D helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GE= TPC()); + pwd->b[10] =3D helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GE= TPC()); + pwd->b[11] =3D helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GE= TPC()); + pwd->b[12] =3D helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GE= TPC()); + pwd->b[13] =3D helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GE= TPC()); + pwd->b[14] =3D helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GE= TPC()); + pwd->b[15] =3D helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GE= TPC()); +#else + pwd->b[0] =3D helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GE= TPC()); + pwd->b[1] =3D helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GE= TPC()); + pwd->b[2] =3D helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GE= TPC()); + pwd->b[3] =3D helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GE= TPC()); + pwd->b[4] =3D helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GE= TPC()); + pwd->b[5] =3D helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GE= TPC()); + pwd->b[6] =3D helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GE= TPC()); + pwd->b[7] =3D helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GE= TPC()); + pwd->b[8] =3D helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GE= TPC()); + pwd->b[9] =3D helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GE= TPC()); + pwd->b[10] =3D helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GE= TPC()); + pwd->b[11] =3D helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GE= TPC()); + pwd->b[12] =3D helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GE= TPC()); + pwd->b[13] =3D helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GE= TPC()); + pwd->b[14] =3D helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GE= TPC()); + pwd->b[15] =3D helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GE= TPC()); +#endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->b[0] =3D cpu_ldub_data(env, addr + (0 << DF_BYTE)); + pwd->b[1] =3D cpu_ldub_data(env, addr + (1 << DF_BYTE)); + pwd->b[2] =3D cpu_ldub_data(env, addr + (2 << DF_BYTE)); + pwd->b[3] =3D cpu_ldub_data(env, addr + (3 << DF_BYTE)); + pwd->b[4] =3D cpu_ldub_data(env, addr + (4 << DF_BYTE)); + pwd->b[5] =3D cpu_ldub_data(env, addr + (5 << DF_BYTE)); + pwd->b[6] =3D cpu_ldub_data(env, addr + (6 << DF_BYTE)); + pwd->b[7] =3D cpu_ldub_data(env, addr + (7 << DF_BYTE)); + pwd->b[8] =3D cpu_ldub_data(env, addr + (8 << DF_BYTE)); + pwd->b[9] =3D cpu_ldub_data(env, addr + (9 << DF_BYTE)); + pwd->b[10] =3D cpu_ldub_data(env, addr + (10 << DF_BYTE)); + pwd->b[11] =3D cpu_ldub_data(env, addr + (11 << DF_BYTE)); + pwd->b[12] =3D cpu_ldub_data(env, addr + (12 << DF_BYTE)); + pwd->b[13] =3D cpu_ldub_data(env, addr + (13 << DF_BYTE)); + pwd->b[14] =3D cpu_ldub_data(env, addr + (14 << DF_BYTE)); + pwd->b[15] =3D cpu_ldub_data(env, addr + (15 << DF_BYTE)); +#else + pwd->b[0] =3D cpu_ldub_data(env, addr + (7 << DF_BYTE)); + pwd->b[1] =3D cpu_ldub_data(env, addr + (6 << DF_BYTE)); + pwd->b[2] =3D cpu_ldub_data(env, addr + (5 << DF_BYTE)); + pwd->b[3] =3D cpu_ldub_data(env, addr + (4 << DF_BYTE)); + pwd->b[4] =3D cpu_ldub_data(env, addr + (3 << DF_BYTE)); + pwd->b[5] =3D cpu_ldub_data(env, addr + (2 << DF_BYTE)); + pwd->b[6] =3D cpu_ldub_data(env, addr + (1 << DF_BYTE)); + pwd->b[7] =3D cpu_ldub_data(env, addr + (0 << DF_BYTE)); + pwd->b[8] =3D cpu_ldub_data(env, addr + (15 << DF_BYTE)); + pwd->b[9] =3D cpu_ldub_data(env, addr + (14 << DF_BYTE)); + pwd->b[10] =3D cpu_ldub_data(env, addr + (13 << DF_BYTE)); + pwd->b[11] =3D cpu_ldub_data(env, addr + (12 << DF_BYTE)); + pwd->b[12] =3D cpu_ldub_data(env, addr + (11 << DF_BYTE)); + pwd->b[13] =3D cpu_ldub_data(env, addr + (10 << DF_BYTE)); + pwd->b[14] =3D cpu_ldub_data(env, addr + (9 << DF_BYTE)); + pwd->b[15] =3D cpu_ldub_data(env, addr + (8 << DF_BYTE)); +#endif +#endif +} + +void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + MEMOP_IDX(DF_HALF) +#if !defined(CONFIG_USER_ONLY) +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->h[0] =3D helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETP= C()); + pwd->h[1] =3D helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETP= C()); + pwd->h[2] =3D helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETP= C()); + pwd->h[3] =3D helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETP= C()); + pwd->h[4] =3D helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETP= C()); + pwd->h[5] =3D helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETP= C()); + pwd->h[6] =3D helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETP= C()); + pwd->h[7] =3D helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETP= C()); +#else + pwd->h[0] =3D helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETP= C()); + pwd->h[1] =3D helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETP= C()); + pwd->h[2] =3D helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETP= C()); + pwd->h[3] =3D helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETP= C()); + pwd->h[4] =3D helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETP= C()); + pwd->h[5] =3D helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETP= C()); + pwd->h[6] =3D helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETP= C()); + pwd->h[7] =3D helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETP= C()); +#endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->h[0] =3D cpu_lduw_data(env, addr + (0 << DF_HALF)); + pwd->h[1] =3D cpu_lduw_data(env, addr + (1 << DF_HALF)); + pwd->h[2] =3D cpu_lduw_data(env, addr + (2 << DF_HALF)); + pwd->h[3] =3D cpu_lduw_data(env, addr + (3 << DF_HALF)); + pwd->h[4] =3D cpu_lduw_data(env, addr + (4 << DF_HALF)); + pwd->h[5] =3D cpu_lduw_data(env, addr + (5 << DF_HALF)); + pwd->h[6] =3D cpu_lduw_data(env, addr + (6 << DF_HALF)); + pwd->h[7] =3D cpu_lduw_data(env, addr + (7 << DF_HALF)); +#else + pwd->h[0] =3D cpu_lduw_data(env, addr + (3 << DF_HALF)); + pwd->h[1] =3D cpu_lduw_data(env, addr + (2 << DF_HALF)); + pwd->h[2] =3D cpu_lduw_data(env, addr + (1 << DF_HALF)); + pwd->h[3] =3D cpu_lduw_data(env, addr + (0 << DF_HALF)); + pwd->h[4] =3D cpu_lduw_data(env, addr + (7 << DF_HALF)); + pwd->h[5] =3D cpu_lduw_data(env, addr + (6 << DF_HALF)); + pwd->h[6] =3D cpu_lduw_data(env, addr + (5 << DF_HALF)); + pwd->h[7] =3D cpu_lduw_data(env, addr + (4 << DF_HALF)); +#endif +#endif +} + +void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + MEMOP_IDX(DF_WORD) +#if !defined(CONFIG_USER_ONLY) +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->w[0] =3D helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETP= C()); + pwd->w[1] =3D helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETP= C()); + pwd->w[2] =3D helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETP= C()); + pwd->w[3] =3D helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETP= C()); +#else + pwd->w[0] =3D helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETP= C()); + pwd->w[1] =3D helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETP= C()); + pwd->w[2] =3D helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETP= C()); + pwd->w[3] =3D helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETP= C()); +#endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + pwd->w[0] =3D cpu_ldl_data(env, addr + (0 << DF_WORD)); + pwd->w[1] =3D cpu_ldl_data(env, addr + (1 << DF_WORD)); + pwd->w[2] =3D cpu_ldl_data(env, addr + (2 << DF_WORD)); + pwd->w[3] =3D cpu_ldl_data(env, addr + (3 << DF_WORD)); +#else + pwd->w[0] =3D cpu_ldl_data(env, addr + (1 << DF_WORD)); + pwd->w[1] =3D cpu_ldl_data(env, addr + (0 << DF_WORD)); + pwd->w[2] =3D cpu_ldl_data(env, addr + (3 << DF_WORD)); + pwd->w[3] =3D cpu_ldl_data(env, addr + (2 << DF_WORD)); +#endif +#endif +} + +void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + MEMOP_IDX(DF_DOUBLE) +#if !defined(CONFIG_USER_ONLY) + pwd->d[0] =3D helper_ret_ldq_mmu(env, addr + (0 << DF_DOUBLE), oi, GET= PC()); + pwd->d[1] =3D helper_ret_ldq_mmu(env, addr + (1 << DF_DOUBLE), oi, GET= PC()); +#else + pwd->d[0] =3D cpu_ldq_data(env, addr + (0 << DF_DOUBLE)); + pwd->d[1] =3D cpu_ldq_data(env, addr + (1 << DF_DOUBLE)); +#endif +} + +#define MSA_PAGESPAN(x) \ + ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN / 8 - 1) >=3D TARGET_PAGE_= SIZE) + +static inline void ensure_writable_pages(CPUMIPSState *env, + target_ulong addr, + int mmu_idx, + uintptr_t retaddr) +{ + /* FIXME: Probe the actual accesses (pass and use a size) */ + if (unlikely(MSA_PAGESPAN(addr))) { + /* first page */ + probe_write(env, addr, 0, mmu_idx, retaddr); + /* second page */ + addr =3D (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; + probe_write(env, addr, 0, mmu_idx, retaddr); + } +} + +void helper_msa_st_b(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + int mmu_idx =3D cpu_mmu_index(env, false); + + MEMOP_IDX(DF_BYTE) + ensure_writable_pages(env, addr, mmu_idx, GETPC()); +#if !defined(CONFIG_USER_ONLY) +#if !defined(HOST_WORDS_BIGENDIAN) + helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[0], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[1], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[2], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[3], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[4], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[5], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[6], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[7], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[8], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[9], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[10], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[11], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[12], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[13], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[14], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[15], oi, GETPC(= )); +#else + helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[0], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[1], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[2], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[3], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[4], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[5], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[6], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[7], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[8], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[9], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[10], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[11], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[12], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[13], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[14], oi, GETPC(= )); + helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[15], oi, GETPC(= )); +#endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[0]); + cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[1]); + cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[2]); + cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[3]); + cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[4]); + cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[5]); + cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[6]); + cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[7]); + cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[8]); + cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[9]); + cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[10]); + cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[11]); + cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[12]); + cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[13]); + cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[14]); + cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[15]); +#else + cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[0]); + cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[1]); + cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[2]); + cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[3]); + cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[4]); + cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[5]); + cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[6]); + cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[7]); + cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[8]); + cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[9]); + cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[10]); + cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[11]); + cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[12]); + cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[13]); + cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[14]); + cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[15]); +#endif +#endif +} + +void helper_msa_st_h(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + int mmu_idx =3D cpu_mmu_index(env, false); + + MEMOP_IDX(DF_HALF) + ensure_writable_pages(env, addr, mmu_idx, GETPC()); +#if !defined(CONFIG_USER_ONLY) +#if !defined(HOST_WORDS_BIGENDIAN) + helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[0], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[1], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[2], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[3], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[4], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[5], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[6], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[7], oi, GETPC()); +#else + helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[0], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[1], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[2], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[3], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[4], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[5], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[6], oi, GETPC()); + helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[7], oi, GETPC()); +#endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[0]); + cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[1]); + cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[2]); + cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[3]); + cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[4]); + cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[5]); + cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[6]); + cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[7]); +#else + cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[0]); + cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[1]); + cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[2]); + cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[3]); + cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[4]); + cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[5]); + cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[6]); + cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[7]); +#endif +#endif +} + +void helper_msa_st_w(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + int mmu_idx =3D cpu_mmu_index(env, false); + + MEMOP_IDX(DF_WORD) + ensure_writable_pages(env, addr, mmu_idx, GETPC()); +#if !defined(CONFIG_USER_ONLY) +#if !defined(HOST_WORDS_BIGENDIAN) + helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[0], oi, GETPC()); + helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[1], oi, GETPC()); + helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[2], oi, GETPC()); + helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[3], oi, GETPC()); +#else + helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[0], oi, GETPC()); + helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[1], oi, GETPC()); + helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[2], oi, GETPC()); + helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[3], oi, GETPC()); +#endif +#else +#if !defined(HOST_WORDS_BIGENDIAN) + cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[0]); + cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[1]); + cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[2]); + cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[3]); +#else + cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[0]); + cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[1]); + cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[2]); + cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[3]); +#endif +#endif +} + +void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, + target_ulong addr) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + int mmu_idx =3D cpu_mmu_index(env, false); + + MEMOP_IDX(DF_DOUBLE) + ensure_writable_pages(env, addr, mmu_idx, GETPC()); +#if !defined(CONFIG_USER_ONLY) + helper_ret_stq_mmu(env, addr + (0 << DF_DOUBLE), pwd->d[0], oi, GETPC(= )); + helper_ret_stq_mmu(env, addr + (1 << DF_DOUBLE), pwd->d[1], oi, GETPC(= )); +#else + cpu_stq_data(env, addr + (0 << DF_DOUBLE), pwd->d[0]); + cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]); +#endif +} + void msa_reset(CPUMIPSState *env) { if (!ase_msa_available(env)) { diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 72613706188..dd09a4c714a 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -28,7 +28,6 @@ #include "exec/cpu_ldst.h" #include "exec/memop.h" #include "sysemu/kvm.h" -#include "fpu_helper.h" =20 =20 /*************************************************************************= ****/ @@ -1179,399 +1178,6 @@ void mips_cpu_do_transaction_failed(CPUState *cs, h= waddr physaddr, #endif /* !CONFIG_USER_ONLY */ =20 =20 -/* MSA */ -/* Data format min and max values */ -#define DF_BITS(df) (1 << ((df) + 3)) - -/* Element-by-element access macros */ -#define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df)) - -#if !defined(CONFIG_USER_ONLY) -#define MEMOP_IDX(DF) \ - TCGMemOpIdx oi =3D make_memop_idx(MO_TE | DF | MO_UNALN, \ - cpu_mmu_index(env, false)); -#else -#define MEMOP_IDX(DF) -#endif - -void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - MEMOP_IDX(DF_BYTE) -#if !defined(CONFIG_USER_ONLY) -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->b[0] =3D helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GE= TPC()); - pwd->b[1] =3D helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GE= TPC()); - pwd->b[2] =3D helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GE= TPC()); - pwd->b[3] =3D helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GE= TPC()); - pwd->b[4] =3D helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GE= TPC()); - pwd->b[5] =3D helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GE= TPC()); - pwd->b[6] =3D helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GE= TPC()); - pwd->b[7] =3D helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GE= TPC()); - pwd->b[8] =3D helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GE= TPC()); - pwd->b[9] =3D helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GE= TPC()); - pwd->b[10] =3D helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GE= TPC()); - pwd->b[11] =3D helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GE= TPC()); - pwd->b[12] =3D helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GE= TPC()); - pwd->b[13] =3D helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GE= TPC()); - pwd->b[14] =3D helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GE= TPC()); - pwd->b[15] =3D helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GE= TPC()); -#else - pwd->b[0] =3D helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GE= TPC()); - pwd->b[1] =3D helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GE= TPC()); - pwd->b[2] =3D helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GE= TPC()); - pwd->b[3] =3D helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GE= TPC()); - pwd->b[4] =3D helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GE= TPC()); - pwd->b[5] =3D helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GE= TPC()); - pwd->b[6] =3D helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GE= TPC()); - pwd->b[7] =3D helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GE= TPC()); - pwd->b[8] =3D helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GE= TPC()); - pwd->b[9] =3D helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GE= TPC()); - pwd->b[10] =3D helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GE= TPC()); - pwd->b[11] =3D helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GE= TPC()); - pwd->b[12] =3D helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GE= TPC()); - pwd->b[13] =3D helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GE= TPC()); - pwd->b[14] =3D helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GE= TPC()); - pwd->b[15] =3D helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GE= TPC()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->b[0] =3D cpu_ldub_data(env, addr + (0 << DF_BYTE)); - pwd->b[1] =3D cpu_ldub_data(env, addr + (1 << DF_BYTE)); - pwd->b[2] =3D cpu_ldub_data(env, addr + (2 << DF_BYTE)); - pwd->b[3] =3D cpu_ldub_data(env, addr + (3 << DF_BYTE)); - pwd->b[4] =3D cpu_ldub_data(env, addr + (4 << DF_BYTE)); - pwd->b[5] =3D cpu_ldub_data(env, addr + (5 << DF_BYTE)); - pwd->b[6] =3D cpu_ldub_data(env, addr + (6 << DF_BYTE)); - pwd->b[7] =3D cpu_ldub_data(env, addr + (7 << DF_BYTE)); - pwd->b[8] =3D cpu_ldub_data(env, addr + (8 << DF_BYTE)); - pwd->b[9] =3D cpu_ldub_data(env, addr + (9 << DF_BYTE)); - pwd->b[10] =3D cpu_ldub_data(env, addr + (10 << DF_BYTE)); - pwd->b[11] =3D cpu_ldub_data(env, addr + (11 << DF_BYTE)); - pwd->b[12] =3D cpu_ldub_data(env, addr + (12 << DF_BYTE)); - pwd->b[13] =3D cpu_ldub_data(env, addr + (13 << DF_BYTE)); - pwd->b[14] =3D cpu_ldub_data(env, addr + (14 << DF_BYTE)); - pwd->b[15] =3D cpu_ldub_data(env, addr + (15 << DF_BYTE)); -#else - pwd->b[0] =3D cpu_ldub_data(env, addr + (7 << DF_BYTE)); - pwd->b[1] =3D cpu_ldub_data(env, addr + (6 << DF_BYTE)); - pwd->b[2] =3D cpu_ldub_data(env, addr + (5 << DF_BYTE)); - pwd->b[3] =3D cpu_ldub_data(env, addr + (4 << DF_BYTE)); - pwd->b[4] =3D cpu_ldub_data(env, addr + (3 << DF_BYTE)); - pwd->b[5] =3D cpu_ldub_data(env, addr + (2 << DF_BYTE)); - pwd->b[6] =3D cpu_ldub_data(env, addr + (1 << DF_BYTE)); - pwd->b[7] =3D cpu_ldub_data(env, addr + (0 << DF_BYTE)); - pwd->b[8] =3D cpu_ldub_data(env, addr + (15 << DF_BYTE)); - pwd->b[9] =3D cpu_ldub_data(env, addr + (14 << DF_BYTE)); - pwd->b[10] =3D cpu_ldub_data(env, addr + (13 << DF_BYTE)); - pwd->b[11] =3D cpu_ldub_data(env, addr + (12 << DF_BYTE)); - pwd->b[12] =3D cpu_ldub_data(env, addr + (11 << DF_BYTE)); - pwd->b[13] =3D cpu_ldub_data(env, addr + (10 << DF_BYTE)); - pwd->b[14] =3D cpu_ldub_data(env, addr + (9 << DF_BYTE)); - pwd->b[15] =3D cpu_ldub_data(env, addr + (8 << DF_BYTE)); -#endif -#endif -} - -void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - MEMOP_IDX(DF_HALF) -#if !defined(CONFIG_USER_ONLY) -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->h[0] =3D helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETP= C()); - pwd->h[1] =3D helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETP= C()); - pwd->h[2] =3D helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETP= C()); - pwd->h[3] =3D helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETP= C()); - pwd->h[4] =3D helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETP= C()); - pwd->h[5] =3D helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETP= C()); - pwd->h[6] =3D helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETP= C()); - pwd->h[7] =3D helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETP= C()); -#else - pwd->h[0] =3D helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETP= C()); - pwd->h[1] =3D helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETP= C()); - pwd->h[2] =3D helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETP= C()); - pwd->h[3] =3D helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETP= C()); - pwd->h[4] =3D helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETP= C()); - pwd->h[5] =3D helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETP= C()); - pwd->h[6] =3D helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETP= C()); - pwd->h[7] =3D helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETP= C()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->h[0] =3D cpu_lduw_data(env, addr + (0 << DF_HALF)); - pwd->h[1] =3D cpu_lduw_data(env, addr + (1 << DF_HALF)); - pwd->h[2] =3D cpu_lduw_data(env, addr + (2 << DF_HALF)); - pwd->h[3] =3D cpu_lduw_data(env, addr + (3 << DF_HALF)); - pwd->h[4] =3D cpu_lduw_data(env, addr + (4 << DF_HALF)); - pwd->h[5] =3D cpu_lduw_data(env, addr + (5 << DF_HALF)); - pwd->h[6] =3D cpu_lduw_data(env, addr + (6 << DF_HALF)); - pwd->h[7] =3D cpu_lduw_data(env, addr + (7 << DF_HALF)); -#else - pwd->h[0] =3D cpu_lduw_data(env, addr + (3 << DF_HALF)); - pwd->h[1] =3D cpu_lduw_data(env, addr + (2 << DF_HALF)); - pwd->h[2] =3D cpu_lduw_data(env, addr + (1 << DF_HALF)); - pwd->h[3] =3D cpu_lduw_data(env, addr + (0 << DF_HALF)); - pwd->h[4] =3D cpu_lduw_data(env, addr + (7 << DF_HALF)); - pwd->h[5] =3D cpu_lduw_data(env, addr + (6 << DF_HALF)); - pwd->h[6] =3D cpu_lduw_data(env, addr + (5 << DF_HALF)); - pwd->h[7] =3D cpu_lduw_data(env, addr + (4 << DF_HALF)); -#endif -#endif -} - -void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - MEMOP_IDX(DF_WORD) -#if !defined(CONFIG_USER_ONLY) -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->w[0] =3D helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETP= C()); - pwd->w[1] =3D helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETP= C()); - pwd->w[2] =3D helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETP= C()); - pwd->w[3] =3D helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETP= C()); -#else - pwd->w[0] =3D helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETP= C()); - pwd->w[1] =3D helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETP= C()); - pwd->w[2] =3D helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETP= C()); - pwd->w[3] =3D helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETP= C()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - pwd->w[0] =3D cpu_ldl_data(env, addr + (0 << DF_WORD)); - pwd->w[1] =3D cpu_ldl_data(env, addr + (1 << DF_WORD)); - pwd->w[2] =3D cpu_ldl_data(env, addr + (2 << DF_WORD)); - pwd->w[3] =3D cpu_ldl_data(env, addr + (3 << DF_WORD)); -#else - pwd->w[0] =3D cpu_ldl_data(env, addr + (1 << DF_WORD)); - pwd->w[1] =3D cpu_ldl_data(env, addr + (0 << DF_WORD)); - pwd->w[2] =3D cpu_ldl_data(env, addr + (3 << DF_WORD)); - pwd->w[3] =3D cpu_ldl_data(env, addr + (2 << DF_WORD)); -#endif -#endif -} - -void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - MEMOP_IDX(DF_DOUBLE) -#if !defined(CONFIG_USER_ONLY) - pwd->d[0] =3D helper_ret_ldq_mmu(env, addr + (0 << DF_DOUBLE), oi, GET= PC()); - pwd->d[1] =3D helper_ret_ldq_mmu(env, addr + (1 << DF_DOUBLE), oi, GET= PC()); -#else - pwd->d[0] =3D cpu_ldq_data(env, addr + (0 << DF_DOUBLE)); - pwd->d[1] =3D cpu_ldq_data(env, addr + (1 << DF_DOUBLE)); -#endif -} - -#define MSA_PAGESPAN(x) \ - ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN / 8 - 1) >=3D TARGET_PAGE_= SIZE) - -static inline void ensure_writable_pages(CPUMIPSState *env, - target_ulong addr, - int mmu_idx, - uintptr_t retaddr) -{ - /* FIXME: Probe the actual accesses (pass and use a size) */ - if (unlikely(MSA_PAGESPAN(addr))) { - /* first page */ - probe_write(env, addr, 0, mmu_idx, retaddr); - /* second page */ - addr =3D (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; - probe_write(env, addr, 0, mmu_idx, retaddr); - } -} - -void helper_msa_st_b(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - int mmu_idx =3D cpu_mmu_index(env, false); - - MEMOP_IDX(DF_BYTE) - ensure_writable_pages(env, addr, mmu_idx, GETPC()); -#if !defined(CONFIG_USER_ONLY) -#if !defined(HOST_WORDS_BIGENDIAN) - helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[0], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[1], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[2], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[3], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[4], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[5], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[6], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[7], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[8], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[9], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[10], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[11], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[12], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[13], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[14], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[15], oi, GETPC(= )); -#else - helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[0], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[1], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[2], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[3], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[4], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[5], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[6], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[7], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[8], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[9], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[10], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[11], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[12], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[13], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[14], oi, GETPC(= )); - helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[15], oi, GETPC(= )); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[0]); - cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[1]); - cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[2]); - cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[3]); - cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[4]); - cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[5]); - cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[6]); - cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[7]); - cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[8]); - cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[9]); - cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[10]); - cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[11]); - cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[12]); - cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[13]); - cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[14]); - cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[15]); -#else - cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[0]); - cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[1]); - cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[2]); - cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[3]); - cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[4]); - cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[5]); - cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[6]); - cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[7]); - cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[8]); - cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[9]); - cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[10]); - cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[11]); - cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[12]); - cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[13]); - cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[14]); - cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[15]); -#endif -#endif -} - -void helper_msa_st_h(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - int mmu_idx =3D cpu_mmu_index(env, false); - - MEMOP_IDX(DF_HALF) - ensure_writable_pages(env, addr, mmu_idx, GETPC()); -#if !defined(CONFIG_USER_ONLY) -#if !defined(HOST_WORDS_BIGENDIAN) - helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[0], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[1], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[2], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[3], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[4], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[5], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[6], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[7], oi, GETPC()); -#else - helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[0], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[1], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[2], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[3], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[4], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[5], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[6], oi, GETPC()); - helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[7], oi, GETPC()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[0]); - cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[1]); - cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[2]); - cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[3]); - cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[4]); - cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[5]); - cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[6]); - cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[7]); -#else - cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[0]); - cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[1]); - cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[2]); - cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[3]); - cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[4]); - cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[5]); - cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[6]); - cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[7]); -#endif -#endif -} - -void helper_msa_st_w(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - int mmu_idx =3D cpu_mmu_index(env, false); - - MEMOP_IDX(DF_WORD) - ensure_writable_pages(env, addr, mmu_idx, GETPC()); -#if !defined(CONFIG_USER_ONLY) -#if !defined(HOST_WORDS_BIGENDIAN) - helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[0], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[1], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[2], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[3], oi, GETPC()); -#else - helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[0], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[1], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[2], oi, GETPC()); - helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[3], oi, GETPC()); -#endif -#else -#if !defined(HOST_WORDS_BIGENDIAN) - cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[0]); - cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[1]); - cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[2]); - cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[3]); -#else - cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[0]); - cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[1]); - cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[2]); - cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[3]); -#endif -#endif -} - -void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, - target_ulong addr) -{ - wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); - int mmu_idx =3D cpu_mmu_index(env, false); - - MEMOP_IDX(DF_DOUBLE) - ensure_writable_pages(env, addr, mmu_idx, GETPC()); -#if !defined(CONFIG_USER_ONLY) - helper_ret_stq_mmu(env, addr + (0 << DF_DOUBLE), pwd->d[0], oi, GETPC(= )); - helper_ret_stq_mmu(env, addr + (1 << DF_DOUBLE), pwd->d[1], oi, GETPC(= )); -#else - cpu_stq_data(env, addr + (0 << DF_DOUBLE), pwd->d[0]); - cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]); -#endif -} - void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op) { #ifndef CONFIG_USER_ONLY --=20 2.26.2 From nobody Wed May 15 19:53:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.46 as permitted sender) client-ip=209.85.208.46; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id t15sm11956602ejx.88.2020.12.07.16.38.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 16:38:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4LRz+2kXa1G+kvmW7hNaI1eqoy4+tVkf4TaV4Xk9Z+E=; b=rKYlg8VVU303Q8fTYU9IRyIoA9EHSugVE17S9JoxMaGUkRpKnyxGGjBEGdojwp6SGv r6mexaijbwIVvKizsB3I3hMXxOBUwpGTCTZn/omBf6rhldPQ9uA9z+BPcqsyW41inEHn 82t54Q9nQEYv/ZDNBLDiRJSjRiJ0VEULPNiE2Qs2tzz8ZzgP8cefVTbz9IqkLw90dpM1 7brBqPkq2q9WQx7UHtbC3MB095TWChEHhlszqVUD5SXdXLkGRiYi3AcVwfx9MJUeHoYX 0DvmQi6KdPjXphpMDxzw8+QovEskAJ3+1SOekPAwRcPidKgc7GphfTLR29+VBWMi+eqP NouA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=4LRz+2kXa1G+kvmW7hNaI1eqoy4+tVkf4TaV4Xk9Z+E=; b=SeXAOPx94DKWO5B5Mi6rXhZ2b3DOwdaxE4hy103eneEgMesRRW6IvHKQjoGtBcKjtk 9ljec6VLbGYYjUXZHANLg4cXg/lLsPI36Mi6TGnQw9QGMDD2i9lXc0K694nML9k425xV C1LjF5/iWHYPbv9jxQvHdxESrBFfLYd3wDKPoLM+mLpGTCMM7PVt5XUHVmgRkBNhDa+3 aRpEdaT+Y9wYh4uehdVt/TLUf4tPE/lnx/wzxie2RKYtNHc4rhOvvJUi6l7iImkgy4uo uUXAAXANlwg7ON2v0DuGWT1YwG8sAqAm+DpxTzoJMw+TPgL+FTGiXcyYvRfoR6TLI0FF Oluw== X-Gm-Message-State: AOAM531+O4XvPZFgFs5tr8oOeojot1NxNarkSXiHYGjSuXE5tAw7pCL/ 4B2El1zeKyAo2S6xRc5a+Ak= X-Google-Smtp-Source: ABdhPJy8OSVdsw2f443NkY2BcKObeSrejkfkAjii2ISzvPXd+rZwev03jy17bPn+o55PqG7EvXBGow== X-Received: by 2002:a50:e78b:: with SMTP id b11mr12577580edn.165.1607387893640; Mon, 07 Dec 2020 16:38:13 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , kvm@vger.kernel.org, Richard Henderson , Aurelien Jarno , Huacai Chen , Jiaxun Yang Subject: [PATCH 13/17] target/mips: Extract MSA helper definitions Date: Tue, 8 Dec 2020 01:36:58 +0100 Message-Id: <20201208003702.4088927-14-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201208003702.4088927-1-f4bug@amsat.org> References: <20201208003702.4088927-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Keep all MSA-related code altogether. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20201120210844.2625602-4-f4bug@amsat.org> Tested-by: Jiaxun Yang --- target/mips/helper.h | 436 +----------------------------- target/mips/mod-msa_helper.h.inc | 443 +++++++++++++++++++++++++++++++ 2 files changed, 445 insertions(+), 434 deletions(-) create mode 100644 target/mips/mod-msa_helper.h.inc diff --git a/target/mips/helper.h b/target/mips/helper.h index e97655dc0eb..80eb675fa64 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -781,438 +781,6 @@ DEF_HELPER_FLAGS_3(dmthlip, 0, void, tl, tl, env) DEF_HELPER_FLAGS_3(wrdsp, 0, void, tl, tl, env) DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env) =20 -/* MIPS SIMD Architecture */ - -DEF_HELPER_3(msa_nloc_b, void, env, i32, i32) -DEF_HELPER_3(msa_nloc_h, void, env, i32, i32) -DEF_HELPER_3(msa_nloc_w, void, env, i32, i32) -DEF_HELPER_3(msa_nloc_d, void, env, i32, i32) - -DEF_HELPER_3(msa_nlzc_b, void, env, i32, i32) -DEF_HELPER_3(msa_nlzc_h, void, env, i32, i32) -DEF_HELPER_3(msa_nlzc_w, void, env, i32, i32) -DEF_HELPER_3(msa_nlzc_d, void, env, i32, i32) - -DEF_HELPER_3(msa_pcnt_b, void, env, i32, i32) -DEF_HELPER_3(msa_pcnt_h, void, env, i32, i32) -DEF_HELPER_3(msa_pcnt_w, void, env, i32, i32) -DEF_HELPER_3(msa_pcnt_d, void, env, i32, i32) - -DEF_HELPER_4(msa_binsl_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_binsl_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_binsl_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_binsl_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_binsr_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_binsr_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_binsr_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_binsr_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_bmnz_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_bclr_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bclr_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bclr_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bclr_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_bneg_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bneg_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bneg_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bneg_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_bset_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bset_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bset_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bset_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_add_a_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_add_a_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_add_a_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_add_a_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_adds_a_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_adds_a_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_adds_a_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_adds_a_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_adds_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_adds_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_adds_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_adds_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_adds_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_adds_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_adds_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_adds_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_addv_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_addv_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_addv_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_addv_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_hadd_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_hadd_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_hadd_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_hadd_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_hadd_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_hadd_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_ave_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ave_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ave_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ave_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_ave_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ave_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ave_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ave_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_aver_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_aver_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_aver_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_aver_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_aver_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_aver_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_aver_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_aver_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_ceq_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ceq_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ceq_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ceq_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_cle_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_cle_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_cle_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_cle_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_cle_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_cle_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_cle_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_cle_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_clt_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_clt_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_clt_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_clt_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_clt_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_clt_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_clt_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_clt_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_div_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_div_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_div_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_div_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_div_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_div_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_div_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_div_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_max_a_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_a_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_a_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_a_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_s_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_max_u_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_a_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_a_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_a_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_a_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_s_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_min_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_mod_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_mod_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_mod_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_mod_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_mod_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_mod_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_mod_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_mod_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_maddv_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_maddv_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_maddv_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_maddv_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_msubv_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_msubv_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_msubv_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_msubv_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_mulv_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_mulv_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_mulv_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_mulv_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_asub_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_asub_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_asub_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_asub_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_asub_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_asub_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_asub_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_asub_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_hsub_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_hsub_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_hsub_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_hsub_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_hsub_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_hsub_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_subs_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subs_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subs_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subs_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_subs_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subs_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subs_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subs_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_subsus_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subsus_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subsus_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subsus_u_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_subsuu_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subsuu_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subsuu_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subsuu_s_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_subv_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subv_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subv_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_subv_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_ilvev_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvev_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvev_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvev_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvod_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvod_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvod_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvod_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvl_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvl_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvl_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvl_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvr_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvr_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvr_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ilvr_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_and_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32) -DEF_HELPER_4(msa_xor_v, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_pckev_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_pckev_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_pckev_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_pckev_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_pckod_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_pckod_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_pckod_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_pckod_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_sll_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_sll_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_sll_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_sll_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_sra_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_sra_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_sra_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_sra_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_srar_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_srar_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_srar_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_srar_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_srl_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_srl_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_srl_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_srl_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_srlr_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_srlr_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_srlr_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_srlr_d, void, env, i32, i32, i32) - -DEF_HELPER_3(msa_move_v, void, env, i32, i32) - -DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_nori_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_xori_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bmnzi_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bmzi_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_bseli_b, void, env, i32, i32, i32) -DEF_HELPER_5(msa_shf_df, void, env, i32, i32, i32, i32) - -DEF_HELPER_5(msa_addvi_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_subvi_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_maxi_s_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_maxi_u_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_mini_s_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_mini_u_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_ceqi_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_clti_s_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_clti_u_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_clei_s_df, void, env, i32, i32, i32, s32) -DEF_HELPER_5(msa_clei_u_df, void, env, i32, i32, i32, s32) -DEF_HELPER_4(msa_ldi_df, void, env, i32, i32, s32) - -DEF_HELPER_5(msa_slli_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_srai_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_srli_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_bclri_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_bseti_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_bnegi_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_binsli_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_binsri_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_sat_s_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_sat_u_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_srari_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_srlri_df, void, env, i32, i32, i32, i32) - -DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32) - -DEF_HELPER_4(msa_dotp_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dotp_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dotp_s_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dotp_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dotp_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dotp_u_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpadd_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpadd_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpadd_s_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpadd_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpadd_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpadd_u_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpsub_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpsub_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpsub_s_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpsub_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpsub_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_dpsub_u_d, void, env, i32, i32, i32) -DEF_HELPER_5(msa_sld_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_splat_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32) - -DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32) - -DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32) -DEF_HELPER_3(msa_ctcmsa, void, env, tl, i32) -DEF_HELPER_2(msa_cfcmsa, tl, env, i32) - -DEF_HELPER_5(msa_fcaf_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fcun_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fceq_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fcueq_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fclt_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fcult_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fcle_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fcule_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsaf_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsun_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fseq_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsueq_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fslt_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsult_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsle_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsule_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fadd_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsub_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fmul_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fdiv_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fmadd_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fmsub_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fexp2_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fexdo_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_ftq_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fmin_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fmin_a_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fmax_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fmax_a_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fcor_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fcune_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fcne_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_mul_q_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_madd_q_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_msub_q_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsor_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsune_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_fsne_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_mulr_q_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_maddr_q_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_msubr_q_df, void, env, i32, i32, i32, i32) - -DEF_HELPER_4(msa_fill_df, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_copy_s_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_copy_s_d, void, env, i32, i32, i32) -DEF_HELPER_4(msa_copy_u_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_copy_u_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_copy_u_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_insert_b, void, env, i32, i32, i32) -DEF_HELPER_4(msa_insert_h, void, env, i32, i32, i32) -DEF_HELPER_4(msa_insert_w, void, env, i32, i32, i32) -DEF_HELPER_4(msa_insert_d, void, env, i32, i32, i32) - -DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ftrunc_u_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_fsqrt_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_frsqrt_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_frcp_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_frint_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_flog2_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_fexupl_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_fexupr_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ffql_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ffqr_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ftint_s_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ftint_u_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ffint_s_df, void, env, i32, i32, i32) -DEF_HELPER_4(msa_ffint_u_df, void, env, i32, i32, i32) - -#define MSALDST_PROTO(type) \ -DEF_HELPER_3(msa_ld_ ## type, void, env, i32, tl) \ -DEF_HELPER_3(msa_st_ ## type, void, env, i32, tl) -MSALDST_PROTO(b) -MSALDST_PROTO(h) -MSALDST_PROTO(w) -MSALDST_PROTO(d) -#undef MSALDST_PROTO - DEF_HELPER_3(cache, void, env, tl, i32) + +#include "mod-msa_helper.h.inc" diff --git a/target/mips/mod-msa_helper.h.inc b/target/mips/mod-msa_helper.= h.inc new file mode 100644 index 00000000000..4963d1553a0 --- /dev/null +++ b/target/mips/mod-msa_helper.h.inc @@ -0,0 +1,443 @@ +/* + * MIPS SIMD Architecture Module (MSA) helpers for QEMU. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * Copyright (c) 2006 Marius Groeger (FPU operations) + * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) + * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) + * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support) + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +DEF_HELPER_3(msa_nloc_b, void, env, i32, i32) +DEF_HELPER_3(msa_nloc_h, void, env, i32, i32) +DEF_HELPER_3(msa_nloc_w, void, env, i32, i32) +DEF_HELPER_3(msa_nloc_d, void, env, i32, i32) + +DEF_HELPER_3(msa_nlzc_b, void, env, i32, i32) +DEF_HELPER_3(msa_nlzc_h, void, env, i32, i32) +DEF_HELPER_3(msa_nlzc_w, void, env, i32, i32) +DEF_HELPER_3(msa_nlzc_d, void, env, i32, i32) + +DEF_HELPER_3(msa_pcnt_b, void, env, i32, i32) +DEF_HELPER_3(msa_pcnt_h, void, env, i32, i32) +DEF_HELPER_3(msa_pcnt_w, void, env, i32, i32) +DEF_HELPER_3(msa_pcnt_d, void, env, i32, i32) + +DEF_HELPER_4(msa_binsl_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsl_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsl_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsl_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_binsr_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsr_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsr_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_binsr_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_bmnz_v, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_bclr_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bclr_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bclr_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bclr_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_bneg_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bneg_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bneg_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bneg_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_bset_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bset_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bset_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bset_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_add_a_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_add_a_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_add_a_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_add_a_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_adds_a_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_a_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_a_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_a_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_adds_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_adds_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_adds_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_addv_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_addv_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_addv_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_addv_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_hadd_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hadd_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hadd_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_hadd_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hadd_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hadd_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_ave_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ave_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ave_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ave_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_ave_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ave_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ave_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ave_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_aver_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_aver_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_aver_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_ceq_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ceq_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ceq_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ceq_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_cle_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_cle_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_cle_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_cle_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_cle_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_cle_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_cle_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_cle_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_clt_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_clt_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_clt_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_div_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_div_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_div_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_div_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_div_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_div_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_div_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_div_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_max_a_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_a_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_a_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_a_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_s_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_max_u_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_a_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_a_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_a_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_a_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_s_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_min_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_mod_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_mod_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mod_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_maddv_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_maddv_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_maddv_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_maddv_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_msubv_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_msubv_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_msubv_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_msubv_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_mulv_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mulv_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mulv_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_mulv_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_asub_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_asub_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_asub_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_asub_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_asub_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_asub_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_asub_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_asub_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_hsub_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hsub_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hsub_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_hsub_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hsub_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_hsub_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_subs_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subs_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subs_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subs_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_subs_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subs_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subs_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subs_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_subsus_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subsus_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subsus_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subsus_u_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_subsuu_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subsuu_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subsuu_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subsuu_s_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_subv_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subv_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subv_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_subv_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_ilvev_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvev_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvev_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvev_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvod_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvod_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvod_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvod_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvl_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvl_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvl_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvl_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvr_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvr_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvr_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ilvr_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_and_v, void, env, i32, i32, i32) +DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32) +DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32) +DEF_HELPER_4(msa_xor_v, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_pckev_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckev_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckev_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckev_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckod_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckod_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckod_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_pckod_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_sll_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_sll_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_sll_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_sll_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_sra_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_sra_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_sra_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_sra_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_srar_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srar_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srar_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srar_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_srl_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srl_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srl_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srl_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_srlr_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srlr_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srlr_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_srlr_d, void, env, i32, i32, i32) + +DEF_HELPER_3(msa_move_v, void, env, i32, i32) + +DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_nori_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_xori_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bmnzi_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bmzi_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_bseli_b, void, env, i32, i32, i32) +DEF_HELPER_5(msa_shf_df, void, env, i32, i32, i32, i32) + +DEF_HELPER_5(msa_addvi_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_subvi_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_maxi_s_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_maxi_u_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_mini_s_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_mini_u_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_ceqi_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_clti_s_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_clti_u_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_clei_s_df, void, env, i32, i32, i32, s32) +DEF_HELPER_5(msa_clei_u_df, void, env, i32, i32, i32, s32) +DEF_HELPER_4(msa_ldi_df, void, env, i32, i32, s32) + +DEF_HELPER_5(msa_slli_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_srai_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_srli_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_bclri_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_bseti_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_bnegi_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_binsli_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_binsri_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_sat_s_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_sat_u_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_srari_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_srlri_df, void, env, i32, i32, i32, i32) + +DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32) + +DEF_HELPER_4(msa_dotp_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dotp_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dotp_s_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dotp_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dotp_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dotp_u_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpadd_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpadd_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpadd_s_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpadd_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpadd_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpadd_u_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpsub_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpsub_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpsub_s_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpsub_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpsub_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_dpsub_u_d, void, env, i32, i32, i32) +DEF_HELPER_5(msa_sld_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_splat_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32) + +DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32) + +DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32) +DEF_HELPER_3(msa_ctcmsa, void, env, tl, i32) +DEF_HELPER_2(msa_cfcmsa, tl, env, i32) + +DEF_HELPER_5(msa_fcaf_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fcun_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fceq_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fcueq_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fclt_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fcult_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fcle_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fcule_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsaf_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsun_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fseq_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsueq_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fslt_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsult_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsle_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsule_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fadd_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsub_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fmul_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fdiv_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fmadd_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fmsub_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fexp2_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fexdo_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_ftq_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fmin_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fmin_a_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fmax_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fmax_a_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fcor_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fcune_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fcne_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_mul_q_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_madd_q_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_msub_q_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsor_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsune_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_fsne_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_mulr_q_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_maddr_q_df, void, env, i32, i32, i32, i32) +DEF_HELPER_5(msa_msubr_q_df, void, env, i32, i32, i32, i32) + +DEF_HELPER_4(msa_fill_df, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_s_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_s_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_u_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_insert_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_insert_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_insert_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_insert_d, void, env, i32, i32, i32) + +DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ftrunc_u_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_fsqrt_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_frsqrt_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_frcp_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_frint_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_flog2_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_fexupl_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_fexupr_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ffql_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ffqr_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ftint_s_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ftint_u_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ffint_s_df, void, env, i32, i32, i32) +DEF_HELPER_4(msa_ffint_u_df, void, env, i32, i32, i32) + +#define MSALDST_PROTO(type) \ +DEF_HELPER_3(msa_ld_ ## type, void, env, i32, tl) \ +DEF_HELPER_3(msa_st_ ## type, void, env, i32, tl) +MSALDST_PROTO(b) +MSALDST_PROTO(h) +MSALDST_PROTO(w) +MSALDST_PROTO(d) +#undef MSALDST_PROTO --=20 2.26.2 From nobody Wed May 15 19:53:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.65 as permitted sender) client-ip=209.85.218.65; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-f65.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.65 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1607387901; cv=none; d=zohomail.com; s=zohoarc; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id q4sm11590147ejc.78.2020.12.07.16.38.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 16:38:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VlrFjWtMkM6uUa/WdAt5ZGBwVseuDv9UZLscN2Lc6YE=; b=BTbC8sfgwcLErcE9Hgftpej+TdCf0CU7Xd+fKx9k+aNXF/+eqfoMap7579RGKkP+6P Vi3Ejna5DpRoseSrKcFya/SmRPRfHKMUuG5U01E+MYE8usNGlpOLXv8sQ/bhgsEnaB1I MW+j7dnMN8/03LrWNA1vUK0PIMc4qgBi9W3coF1Hw1kzDd3/eD/KzhyUOGeXnvCMMGSa OvIZWgd74s9I3/ckLr3Yzxh15nG6ES77Jqj+iJ/60piaGA3Hps8MoMTJqoCGjV43qju/ 8dHbcHyah3i5XdY6NTUbqRIqdOzMNt+dUs1HNowb1TV8/God8Fe3npTyqBbmh6ZkJwkN 66kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=VlrFjWtMkM6uUa/WdAt5ZGBwVseuDv9UZLscN2Lc6YE=; b=nFoJvDZhjhS33kpZErVDdo9s41tOdkpZK6J6m9V677GBqYki/Vajjx52n5TasR4N1O obO9Lq5XrlL+g6BByGvZ5jivqaH35k5Ym5CL9G3AvzOUMmBY/hllGRKyl+2XfOdZTeDj fmBEA7kyNZ8ghWTUK85t8TGRPSMIjbTSY2woyjAsbRQ9DhXw9o+bCgOJUoAkBm+mTYHJ hRHzxj8+m9JfuwuzpCC6f7Xqt60gn5aPiLn/h0VSP+4YD8EeYm37l63J5RTfRow5ZJPv h/YJArakhrFEpBhO9nXIcIDcxo1TvV5o/Nhhxe5cI8Jd27XC3hJSSaFlgL8dnQtuIMxO uQhQ== X-Gm-Message-State: AOAM531yatfNwvniyDYqStmaiONHv/f0AzKYjyUrIQNcSJIYn1qVWX6U dJrVtvLHH0JytE6LyFeFFUw= X-Google-Smtp-Source: ABdhPJwCIJGZcoYl8+1xDZoULgzVXnjluO077d61/nE3jbLEV0gRpRVHtJ8udlI5N1u2qZkBLWuhrw== X-Received: by 2002:a17:906:c244:: with SMTP id bl4mr20250819ejb.430.1607387898842; Mon, 07 Dec 2020 16:38:18 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , kvm@vger.kernel.org, Richard Henderson , Aurelien Jarno , Huacai Chen , Jiaxun Yang Subject: [PATCH 14/17] target/mips: Declare gen_msa/_branch() in 'translate.h' Date: Tue, 8 Dec 2020 01:36:59 +0100 Message-Id: <20201208003702.4088927-15-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201208003702.4088927-1-f4bug@amsat.org> References: <20201208003702.4088927-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Make gen_msa() and gen_msa_branch() public declarations so we can keep calling them once extracted from the big translate.c in the next commit. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Jiaxun Yang --- target/mips/translate.h | 2 ++ target/mips/translate.c | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index 765018beeea..c26b0d9155d 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -82,5 +82,7 @@ extern TCGv bcond; =20 /* MSA */ void msa_translate_init(void); +void gen_msa(DisasContext *ctx); +void gen_msa_branch(DisasContext *ctx, uint32_t op1); =20 #endif diff --git a/target/mips/translate.c b/target/mips/translate.c index 8b1019506fe..d8553c626f3 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28668,7 +28668,7 @@ static bool gen_msa_BxZ(DisasContext *ctx, int df, = int wt, int s16, bool if_not) return true; } =20 -static void gen_msa_branch(DisasContext *ctx, uint32_t op1) +void gen_msa_branch(DisasContext *ctx, uint32_t op1) { uint8_t df =3D (ctx->opcode >> 21) & 0x3; uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; @@ -30444,7 +30444,7 @@ static void gen_msa_vec(DisasContext *ctx) } } =20 -static void gen_msa(DisasContext *ctx) +void gen_msa(DisasContext *ctx) { uint32_t opcode =3D ctx->opcode; =20 --=20 2.26.2 From nobody Wed May 15 19:53:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.47 as permitted sender) client-ip=209.85.208.47; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f47.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1607387909; cv=none; d=zohomail.com; s=zohoarc; b=BKJyo+376mfu6CiRdclEvxlPrdYE/pUxSPYZxwSiodWXlfk84LDCXkm3vsjxCeIq3h2EeMd4JdKfkLR8cSzAn7Kftxx67tKrBWGmB9MzZnBsit0oiOJlQbVrkEVFb5H2AoXsYbjQILA/RVHAxNiRzTt0wUpb8LJmMQgVL9p/F7c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607387909; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=E4vavFlI7roo0hGflFp6QI2DM9XE9koaTi2F622nZe4=; b=CPWUwRwQpM5VGtC9zKjx53i7BfnYUvz33T6gVEx+RMOOObmK3/HS7MIMWjaDURXG7t+qs3upXSAs+5NY49aCc96ahkVgQpYOBLQQvVvDZ8XpuQYzWesOonBydOCZvjNWzb1Ffdkr+0eLCA8tWQW24/m3hppiDGajrTTqtKkRnYE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ed1-f47.google.com (mail-ed1-f47.google.com [209.85.208.47]) by mx.zohomail.com with SMTPS id 1607387909489872.4835539941449; Mon, 7 Dec 2020 16:38:29 -0800 (PST) Received: by mail-ed1-f47.google.com with SMTP id b2so15790870edm.3 for ; Mon, 07 Dec 2020 16:38:26 -0800 (PST) Return-Path: Return-Path: Received: from x1w.redhat.com (101.red-88-21-206.staticip.rima-tde.net. [88.21.206.101]) by smtp.gmail.com with ESMTPSA id u9sm11591420edd.54.2020.12.07.16.38.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 16:38:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E4vavFlI7roo0hGflFp6QI2DM9XE9koaTi2F622nZe4=; b=MpEcLXoG0gH/Hr2wFRLc1wIU8Fl5wMsSFELK2wU945946n2O/wZwGK8fu5rwfgrgDc iTW6kAMIjwX/r+aAyRYNAOo6lgom4a/oejvbM8lc6bAmmfuVbUXwvLwTiV+ivN2KA4k0 jhk7cZ/vo04/DREO8JBW69nSm01YxLqZ38IgLb8p+UA1nUM6mkIMNvpv0wV7Fdmg5u/x GlA2fMInp+ChR97Oo6HJo3SSHbaYnJR/B5SfMmTyXOR5PqMbdW8UOtTlzVuniP3upj3r k/P3rEcM9pSJt+iMoMkXwTp1DBK2kspNReqXoQVAThqLdDycv1bQ1gtlO5p1p0L0Ahn/ nKvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=E4vavFlI7roo0hGflFp6QI2DM9XE9koaTi2F622nZe4=; b=OS/qjg1zm3yOFCIA0UcGv8ZQQRFMA5fH0QCu4AB/oow3JYWnBNr1vGR82/n4FB4l/N wGUWGgv86t2V2gWDrfWSKTb9/1Pq6KIpeisn1vxeRypStVegxHNEJcm0Ag7sxQKbFbkN tBKuvgLLVYXoKCdUf3sE/XU9519MrVbf+kV1MVAndE2Bx7XEXcvaycMSt+6DtDnSTRkz MAGdC2uwx5AcUp46i1tJVgfpPIDpFlM1kjooeFqwLg2m/XZL96j+wgriISFiPGcvtXws 1vO9+7K2ukKzSi2zOUbUcKdrCG6nE49olez69XzhVy/7T8obnzLjCOFeQyG4Lhk2m+iE K2Ng== X-Gm-Message-State: AOAM53232UcHwKBzxjeR4Bgs8+doMN/DHCZm63t0y2K3WJBoiy6wZ2DD RcJbWt5aviSkjCITYuFzKfI= X-Google-Smtp-Source: ABdhPJz93Hn4Fg9qfomTKpaGMjm0jVtnKZm9h9tupFSSAqfR6DMPjKBWiKjIAEvxCGVBuWqv4fWSIw== X-Received: by 2002:a50:d757:: with SMTP id i23mr22687695edj.116.1607387904684; Mon, 07 Dec 2020 16:38:24 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , kvm@vger.kernel.org, Richard Henderson , Aurelien Jarno , Huacai Chen , Jiaxun Yang Subject: [PATCH 15/17] target/mips: Extract MSA translation routines Date: Tue, 8 Dec 2020 01:37:00 +0100 Message-Id: <20201208003702.4088927-16-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201208003702.4088927-1-f4bug@amsat.org> References: <20201208003702.4088927-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Extract 2200 lines from the huge translate.c to a new file, 'mod-msa_translate.c'. As there are too many inter-dependencies we don't compile it as another object yet, but keep including it in the big translate.o. We gain in code maintainability. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201120210844.2625602-5-f4bug@amsat.org> Tested-by: Jiaxun Yang --- target/mips/mod-msa_translate.c | 2266 +++++++++++++++++++++++++++++++ target/mips/translate.c | 2249 ------------------------------ target/mips/meson.build | 1 + 3 files changed, 2267 insertions(+), 2249 deletions(-) create mode 100644 target/mips/mod-msa_translate.c diff --git a/target/mips/mod-msa_translate.c b/target/mips/mod-msa_translat= e.c new file mode 100644 index 00000000000..55c2a2f1acc --- /dev/null +++ b/target/mips/mod-msa_translate.c @@ -0,0 +1,2266 @@ +/* + * MIPS SIMD Architecture Module (MSA) translation routines + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * Copyright (c) 2006 Marius Groeger (FPU operations) + * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) + * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) + * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support) + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#include "qemu/osdep.h" +#include "tcg/tcg-op.h" +#include "exec/helper-gen.h" +#include "translate.h" +#include "fpu_translate.h" +#include "fpu_helper.h" +#include "internal.h" + +#define OPC_MSA (0x1E << 26) + +#define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) +enum { + OPC_MSA_I8_00 =3D 0x00 | OPC_MSA, + OPC_MSA_I8_01 =3D 0x01 | OPC_MSA, + OPC_MSA_I8_02 =3D 0x02 | OPC_MSA, + OPC_MSA_I5_06 =3D 0x06 | OPC_MSA, + OPC_MSA_I5_07 =3D 0x07 | OPC_MSA, + OPC_MSA_BIT_09 =3D 0x09 | OPC_MSA, + OPC_MSA_BIT_0A =3D 0x0A | OPC_MSA, + OPC_MSA_3R_0D =3D 0x0D | OPC_MSA, + OPC_MSA_3R_0E =3D 0x0E | OPC_MSA, + OPC_MSA_3R_0F =3D 0x0F | OPC_MSA, + OPC_MSA_3R_10 =3D 0x10 | OPC_MSA, + OPC_MSA_3R_11 =3D 0x11 | OPC_MSA, + OPC_MSA_3R_12 =3D 0x12 | OPC_MSA, + OPC_MSA_3R_13 =3D 0x13 | OPC_MSA, + OPC_MSA_3R_14 =3D 0x14 | OPC_MSA, + OPC_MSA_3R_15 =3D 0x15 | OPC_MSA, + OPC_MSA_ELM =3D 0x19 | OPC_MSA, + OPC_MSA_3RF_1A =3D 0x1A | OPC_MSA, + OPC_MSA_3RF_1B =3D 0x1B | OPC_MSA, + OPC_MSA_3RF_1C =3D 0x1C | OPC_MSA, + OPC_MSA_VEC =3D 0x1E | OPC_MSA, + + /* MI10 instruction */ + OPC_LD_B =3D (0x20) | OPC_MSA, + OPC_LD_H =3D (0x21) | OPC_MSA, + OPC_LD_W =3D (0x22) | OPC_MSA, + OPC_LD_D =3D (0x23) | OPC_MSA, + OPC_ST_B =3D (0x24) | OPC_MSA, + OPC_ST_H =3D (0x25) | OPC_MSA, + OPC_ST_W =3D (0x26) | OPC_MSA, + OPC_ST_D =3D (0x27) | OPC_MSA, +}; + +enum { + /* I5 instruction df(bits 22..21) =3D _b, _h, _w, _d */ + OPC_ADDVI_df =3D (0x0 << 23) | OPC_MSA_I5_06, + OPC_CEQI_df =3D (0x0 << 23) | OPC_MSA_I5_07, + OPC_SUBVI_df =3D (0x1 << 23) | OPC_MSA_I5_06, + OPC_MAXI_S_df =3D (0x2 << 23) | OPC_MSA_I5_06, + OPC_CLTI_S_df =3D (0x2 << 23) | OPC_MSA_I5_07, + OPC_MAXI_U_df =3D (0x3 << 23) | OPC_MSA_I5_06, + OPC_CLTI_U_df =3D (0x3 << 23) | OPC_MSA_I5_07, + OPC_MINI_S_df =3D (0x4 << 23) | OPC_MSA_I5_06, + OPC_CLEI_S_df =3D (0x4 << 23) | OPC_MSA_I5_07, + OPC_MINI_U_df =3D (0x5 << 23) | OPC_MSA_I5_06, + OPC_CLEI_U_df =3D (0x5 << 23) | OPC_MSA_I5_07, + OPC_LDI_df =3D (0x6 << 23) | OPC_MSA_I5_07, + + /* I8 instruction */ + OPC_ANDI_B =3D (0x0 << 24) | OPC_MSA_I8_00, + OPC_BMNZI_B =3D (0x0 << 24) | OPC_MSA_I8_01, + OPC_SHF_B =3D (0x0 << 24) | OPC_MSA_I8_02, + OPC_ORI_B =3D (0x1 << 24) | OPC_MSA_I8_00, + OPC_BMZI_B =3D (0x1 << 24) | OPC_MSA_I8_01, + OPC_SHF_H =3D (0x1 << 24) | OPC_MSA_I8_02, + OPC_NORI_B =3D (0x2 << 24) | OPC_MSA_I8_00, + OPC_BSELI_B =3D (0x2 << 24) | OPC_MSA_I8_01, + OPC_SHF_W =3D (0x2 << 24) | OPC_MSA_I8_02, + OPC_XORI_B =3D (0x3 << 24) | OPC_MSA_I8_00, + + /* VEC/2R/2RF instruction */ + OPC_AND_V =3D (0x00 << 21) | OPC_MSA_VEC, + OPC_OR_V =3D (0x01 << 21) | OPC_MSA_VEC, + OPC_NOR_V =3D (0x02 << 21) | OPC_MSA_VEC, + OPC_XOR_V =3D (0x03 << 21) | OPC_MSA_VEC, + OPC_BMNZ_V =3D (0x04 << 21) | OPC_MSA_VEC, + OPC_BMZ_V =3D (0x05 << 21) | OPC_MSA_VEC, + OPC_BSEL_V =3D (0x06 << 21) | OPC_MSA_VEC, + + OPC_MSA_2R =3D (0x18 << 21) | OPC_MSA_VEC, + OPC_MSA_2RF =3D (0x19 << 21) | OPC_MSA_VEC, + + /* 2R instruction df(bits 17..16) =3D _b, _h, _w, _d */ + OPC_FILL_df =3D (0x00 << 18) | OPC_MSA_2R, + OPC_PCNT_df =3D (0x01 << 18) | OPC_MSA_2R, + OPC_NLOC_df =3D (0x02 << 18) | OPC_MSA_2R, + OPC_NLZC_df =3D (0x03 << 18) | OPC_MSA_2R, + + /* 2RF instruction df(bit 16) =3D _w, _d */ + OPC_FCLASS_df =3D (0x00 << 17) | OPC_MSA_2RF, + OPC_FTRUNC_S_df =3D (0x01 << 17) | OPC_MSA_2RF, + OPC_FTRUNC_U_df =3D (0x02 << 17) | OPC_MSA_2RF, + OPC_FSQRT_df =3D (0x03 << 17) | OPC_MSA_2RF, + OPC_FRSQRT_df =3D (0x04 << 17) | OPC_MSA_2RF, + OPC_FRCP_df =3D (0x05 << 17) | OPC_MSA_2RF, + OPC_FRINT_df =3D (0x06 << 17) | OPC_MSA_2RF, + OPC_FLOG2_df =3D (0x07 << 17) | OPC_MSA_2RF, + OPC_FEXUPL_df =3D (0x08 << 17) | OPC_MSA_2RF, + OPC_FEXUPR_df =3D (0x09 << 17) | OPC_MSA_2RF, + OPC_FFQL_df =3D (0x0A << 17) | OPC_MSA_2RF, + OPC_FFQR_df =3D (0x0B << 17) | OPC_MSA_2RF, + OPC_FTINT_S_df =3D (0x0C << 17) | OPC_MSA_2RF, + OPC_FTINT_U_df =3D (0x0D << 17) | OPC_MSA_2RF, + OPC_FFINT_S_df =3D (0x0E << 17) | OPC_MSA_2RF, + OPC_FFINT_U_df =3D (0x0F << 17) | OPC_MSA_2RF, + + /* 3R instruction df(bits 22..21) =3D _b, _h, _w, d */ + OPC_SLL_df =3D (0x0 << 23) | OPC_MSA_3R_0D, + OPC_ADDV_df =3D (0x0 << 23) | OPC_MSA_3R_0E, + OPC_CEQ_df =3D (0x0 << 23) | OPC_MSA_3R_0F, + OPC_ADD_A_df =3D (0x0 << 23) | OPC_MSA_3R_10, + OPC_SUBS_S_df =3D (0x0 << 23) | OPC_MSA_3R_11, + OPC_MULV_df =3D (0x0 << 23) | OPC_MSA_3R_12, + OPC_DOTP_S_df =3D (0x0 << 23) | OPC_MSA_3R_13, + OPC_SLD_df =3D (0x0 << 23) | OPC_MSA_3R_14, + OPC_VSHF_df =3D (0x0 << 23) | OPC_MSA_3R_15, + OPC_SRA_df =3D (0x1 << 23) | OPC_MSA_3R_0D, + OPC_SUBV_df =3D (0x1 << 23) | OPC_MSA_3R_0E, + OPC_ADDS_A_df =3D (0x1 << 23) | OPC_MSA_3R_10, + OPC_SUBS_U_df =3D (0x1 << 23) | OPC_MSA_3R_11, + OPC_MADDV_df =3D (0x1 << 23) | OPC_MSA_3R_12, + OPC_DOTP_U_df =3D (0x1 << 23) | OPC_MSA_3R_13, + OPC_SPLAT_df =3D (0x1 << 23) | OPC_MSA_3R_14, + OPC_SRAR_df =3D (0x1 << 23) | OPC_MSA_3R_15, + OPC_SRL_df =3D (0x2 << 23) | OPC_MSA_3R_0D, + OPC_MAX_S_df =3D (0x2 << 23) | OPC_MSA_3R_0E, + OPC_CLT_S_df =3D (0x2 << 23) | OPC_MSA_3R_0F, + OPC_ADDS_S_df =3D (0x2 << 23) | OPC_MSA_3R_10, + OPC_SUBSUS_U_df =3D (0x2 << 23) | OPC_MSA_3R_11, + OPC_MSUBV_df =3D (0x2 << 23) | OPC_MSA_3R_12, + OPC_DPADD_S_df =3D (0x2 << 23) | OPC_MSA_3R_13, + OPC_PCKEV_df =3D (0x2 << 23) | OPC_MSA_3R_14, + OPC_SRLR_df =3D (0x2 << 23) | OPC_MSA_3R_15, + OPC_BCLR_df =3D (0x3 << 23) | OPC_MSA_3R_0D, + OPC_MAX_U_df =3D (0x3 << 23) | OPC_MSA_3R_0E, + OPC_CLT_U_df =3D (0x3 << 23) | OPC_MSA_3R_0F, + OPC_ADDS_U_df =3D (0x3 << 23) | OPC_MSA_3R_10, + OPC_SUBSUU_S_df =3D (0x3 << 23) | OPC_MSA_3R_11, + OPC_DPADD_U_df =3D (0x3 << 23) | OPC_MSA_3R_13, + OPC_PCKOD_df =3D (0x3 << 23) | OPC_MSA_3R_14, + OPC_BSET_df =3D (0x4 << 23) | OPC_MSA_3R_0D, + OPC_MIN_S_df =3D (0x4 << 23) | OPC_MSA_3R_0E, + OPC_CLE_S_df =3D (0x4 << 23) | OPC_MSA_3R_0F, + OPC_AVE_S_df =3D (0x4 << 23) | OPC_MSA_3R_10, + OPC_ASUB_S_df =3D (0x4 << 23) | OPC_MSA_3R_11, + OPC_DIV_S_df =3D (0x4 << 23) | OPC_MSA_3R_12, + OPC_DPSUB_S_df =3D (0x4 << 23) | OPC_MSA_3R_13, + OPC_ILVL_df =3D (0x4 << 23) | OPC_MSA_3R_14, + OPC_HADD_S_df =3D (0x4 << 23) | OPC_MSA_3R_15, + OPC_BNEG_df =3D (0x5 << 23) | OPC_MSA_3R_0D, + OPC_MIN_U_df =3D (0x5 << 23) | OPC_MSA_3R_0E, + OPC_CLE_U_df =3D (0x5 << 23) | OPC_MSA_3R_0F, + OPC_AVE_U_df =3D (0x5 << 23) | OPC_MSA_3R_10, + OPC_ASUB_U_df =3D (0x5 << 23) | OPC_MSA_3R_11, + OPC_DIV_U_df =3D (0x5 << 23) | OPC_MSA_3R_12, + OPC_DPSUB_U_df =3D (0x5 << 23) | OPC_MSA_3R_13, + OPC_ILVR_df =3D (0x5 << 23) | OPC_MSA_3R_14, + OPC_HADD_U_df =3D (0x5 << 23) | OPC_MSA_3R_15, + OPC_BINSL_df =3D (0x6 << 23) | OPC_MSA_3R_0D, + OPC_MAX_A_df =3D (0x6 << 23) | OPC_MSA_3R_0E, + OPC_AVER_S_df =3D (0x6 << 23) | OPC_MSA_3R_10, + OPC_MOD_S_df =3D (0x6 << 23) | OPC_MSA_3R_12, + OPC_ILVEV_df =3D (0x6 << 23) | OPC_MSA_3R_14, + OPC_HSUB_S_df =3D (0x6 << 23) | OPC_MSA_3R_15, + OPC_BINSR_df =3D (0x7 << 23) | OPC_MSA_3R_0D, + OPC_MIN_A_df =3D (0x7 << 23) | OPC_MSA_3R_0E, + OPC_AVER_U_df =3D (0x7 << 23) | OPC_MSA_3R_10, + OPC_MOD_U_df =3D (0x7 << 23) | OPC_MSA_3R_12, + OPC_ILVOD_df =3D (0x7 << 23) | OPC_MSA_3R_14, + OPC_HSUB_U_df =3D (0x7 << 23) | OPC_MSA_3R_15, + + /* ELM instructions df(bits 21..16) =3D _b, _h, _w, _d */ + OPC_SLDI_df =3D (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM, + OPC_CTCMSA =3D (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM, + OPC_SPLATI_df =3D (0x1 << 22) | (0x00 << 16) | OPC_MSA_ELM, + OPC_CFCMSA =3D (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM, + OPC_COPY_S_df =3D (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM, + OPC_MOVE_V =3D (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM, + OPC_COPY_U_df =3D (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM, + OPC_INSERT_df =3D (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM, + OPC_INSVE_df =3D (0x5 << 22) | (0x00 << 16) | OPC_MSA_ELM, + + /* 3RF instruction _df(bit 21) =3D _w, _d */ + OPC_FCAF_df =3D (0x0 << 22) | OPC_MSA_3RF_1A, + OPC_FADD_df =3D (0x0 << 22) | OPC_MSA_3RF_1B, + OPC_FCUN_df =3D (0x1 << 22) | OPC_MSA_3RF_1A, + OPC_FSUB_df =3D (0x1 << 22) | OPC_MSA_3RF_1B, + OPC_FCOR_df =3D (0x1 << 22) | OPC_MSA_3RF_1C, + OPC_FCEQ_df =3D (0x2 << 22) | OPC_MSA_3RF_1A, + OPC_FMUL_df =3D (0x2 << 22) | OPC_MSA_3RF_1B, + OPC_FCUNE_df =3D (0x2 << 22) | OPC_MSA_3RF_1C, + OPC_FCUEQ_df =3D (0x3 << 22) | OPC_MSA_3RF_1A, + OPC_FDIV_df =3D (0x3 << 22) | OPC_MSA_3RF_1B, + OPC_FCNE_df =3D (0x3 << 22) | OPC_MSA_3RF_1C, + OPC_FCLT_df =3D (0x4 << 22) | OPC_MSA_3RF_1A, + OPC_FMADD_df =3D (0x4 << 22) | OPC_MSA_3RF_1B, + OPC_MUL_Q_df =3D (0x4 << 22) | OPC_MSA_3RF_1C, + OPC_FCULT_df =3D (0x5 << 22) | OPC_MSA_3RF_1A, + OPC_FMSUB_df =3D (0x5 << 22) | OPC_MSA_3RF_1B, + OPC_MADD_Q_df =3D (0x5 << 22) | OPC_MSA_3RF_1C, + OPC_FCLE_df =3D (0x6 << 22) | OPC_MSA_3RF_1A, + OPC_MSUB_Q_df =3D (0x6 << 22) | OPC_MSA_3RF_1C, + OPC_FCULE_df =3D (0x7 << 22) | OPC_MSA_3RF_1A, + OPC_FEXP2_df =3D (0x7 << 22) | OPC_MSA_3RF_1B, + OPC_FSAF_df =3D (0x8 << 22) | OPC_MSA_3RF_1A, + OPC_FEXDO_df =3D (0x8 << 22) | OPC_MSA_3RF_1B, + OPC_FSUN_df =3D (0x9 << 22) | OPC_MSA_3RF_1A, + OPC_FSOR_df =3D (0x9 << 22) | OPC_MSA_3RF_1C, + OPC_FSEQ_df =3D (0xA << 22) | OPC_MSA_3RF_1A, + OPC_FTQ_df =3D (0xA << 22) | OPC_MSA_3RF_1B, + OPC_FSUNE_df =3D (0xA << 22) | OPC_MSA_3RF_1C, + OPC_FSUEQ_df =3D (0xB << 22) | OPC_MSA_3RF_1A, + OPC_FSNE_df =3D (0xB << 22) | OPC_MSA_3RF_1C, + OPC_FSLT_df =3D (0xC << 22) | OPC_MSA_3RF_1A, + OPC_FMIN_df =3D (0xC << 22) | OPC_MSA_3RF_1B, + OPC_MULR_Q_df =3D (0xC << 22) | OPC_MSA_3RF_1C, + OPC_FSULT_df =3D (0xD << 22) | OPC_MSA_3RF_1A, + OPC_FMIN_A_df =3D (0xD << 22) | OPC_MSA_3RF_1B, + OPC_MADDR_Q_df =3D (0xD << 22) | OPC_MSA_3RF_1C, + OPC_FSLE_df =3D (0xE << 22) | OPC_MSA_3RF_1A, + OPC_FMAX_df =3D (0xE << 22) | OPC_MSA_3RF_1B, + OPC_MSUBR_Q_df =3D (0xE << 22) | OPC_MSA_3RF_1C, + OPC_FSULE_df =3D (0xF << 22) | OPC_MSA_3RF_1A, + OPC_FMAX_A_df =3D (0xF << 22) | OPC_MSA_3RF_1B, + + /* BIT instruction df(bits 22..16) =3D _B _H _W _D */ + OPC_SLLI_df =3D (0x0 << 23) | OPC_MSA_BIT_09, + OPC_SAT_S_df =3D (0x0 << 23) | OPC_MSA_BIT_0A, + OPC_SRAI_df =3D (0x1 << 23) | OPC_MSA_BIT_09, + OPC_SAT_U_df =3D (0x1 << 23) | OPC_MSA_BIT_0A, + OPC_SRLI_df =3D (0x2 << 23) | OPC_MSA_BIT_09, + OPC_SRARI_df =3D (0x2 << 23) | OPC_MSA_BIT_0A, + OPC_BCLRI_df =3D (0x3 << 23) | OPC_MSA_BIT_09, + OPC_SRLRI_df =3D (0x3 << 23) | OPC_MSA_BIT_0A, + OPC_BSETI_df =3D (0x4 << 23) | OPC_MSA_BIT_09, + OPC_BNEGI_df =3D (0x5 << 23) | OPC_MSA_BIT_09, + OPC_BINSLI_df =3D (0x6 << 23) | OPC_MSA_BIT_09, + OPC_BINSRI_df =3D (0x7 << 23) | OPC_MSA_BIT_09, +}; + +static const char * const msaregnames[] =3D { + "w0.d0", "w0.d1", "w1.d0", "w1.d1", + "w2.d0", "w2.d1", "w3.d0", "w3.d1", + "w4.d0", "w4.d1", "w5.d0", "w5.d1", + "w6.d0", "w6.d1", "w7.d0", "w7.d1", + "w8.d0", "w8.d1", "w9.d0", "w9.d1", + "w10.d0", "w10.d1", "w11.d0", "w11.d1", + "w12.d0", "w12.d1", "w13.d0", "w13.d1", + "w14.d0", "w14.d1", "w15.d0", "w15.d1", + "w16.d0", "w16.d1", "w17.d0", "w17.d1", + "w18.d0", "w18.d1", "w19.d0", "w19.d1", + "w20.d0", "w20.d1", "w21.d0", "w21.d1", + "w22.d0", "w22.d1", "w23.d0", "w23.d1", + "w24.d0", "w24.d1", "w25.d0", "w25.d1", + "w26.d0", "w26.d1", "w27.d0", "w27.d1", + "w28.d0", "w28.d1", "w29.d0", "w29.d1", + "w30.d0", "w30.d1", "w31.d0", "w31.d1", +}; + +static TCGv_i64 msa_wr_d[64]; + +void msa_translate_init(void) +{ + int i, off; + + for (i =3D 0; i < 32; i++) { + /* + * The MSA vector registers are mapped on the + * scalar floating-point unit (FPU) registers. + */ + off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); + msa_wr_d[i * 2] =3D fpu_f64[i]; + + off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); + msa_wr_d[i * 2 + 1] =3D tcg_global_mem_new_i64(cpu_env, off, + msaregnames[i * 2 + 1= ]); + } +} + +static inline int check_msa_access(DisasContext *ctx) +{ + if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) && + !(ctx->hflags & MIPS_HFLAG_F64))) { + generate_exception_end(ctx, EXCP_RI); + return 0; + } + + if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) { + generate_exception_end(ctx, EXCP_MSADIS); + return 0; + } + return 1; +} + +static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt) +{ + /* generates tcg ops to check if any element is 0 */ + /* Note this function only works with MSA_WRLEN =3D 128 */ + uint64_t eval_zero_or_big =3D 0; + uint64_t eval_big =3D 0; + TCGv_i64 t0 =3D tcg_temp_new_i64(); + TCGv_i64 t1 =3D tcg_temp_new_i64(); + switch (df) { + case DF_BYTE: + eval_zero_or_big =3D 0x0101010101010101ULL; + eval_big =3D 0x8080808080808080ULL; + break; + case DF_HALF: + eval_zero_or_big =3D 0x0001000100010001ULL; + eval_big =3D 0x8000800080008000ULL; + break; + case DF_WORD: + eval_zero_or_big =3D 0x0000000100000001ULL; + eval_big =3D 0x8000000080000000ULL; + break; + case DF_DOUBLE: + eval_zero_or_big =3D 0x0000000000000001ULL; + eval_big =3D 0x8000000000000000ULL; + break; + } + tcg_gen_subi_i64(t0, msa_wr_d[wt << 1], eval_zero_or_big); + tcg_gen_andc_i64(t0, t0, msa_wr_d[wt << 1]); + tcg_gen_andi_i64(t0, t0, eval_big); + tcg_gen_subi_i64(t1, msa_wr_d[(wt << 1) + 1], eval_zero_or_big); + tcg_gen_andc_i64(t1, t1, msa_wr_d[(wt << 1) + 1]); + tcg_gen_andi_i64(t1, t1, eval_big); + tcg_gen_or_i64(t0, t0, t1); + /* if all bits are zero then all elements are not zero */ + /* if some bit is non-zero then some element is zero */ + tcg_gen_setcondi_i64(TCG_COND_NE, t0, t0, 0); + tcg_gen_trunc_i64_tl(tresult, t0); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); +} + +static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond) +{ + TCGv_i64 t0; + + check_msa_access(ctx); + + if (ctx->hflags & MIPS_HFLAG_BMASK) { + generate_exception_end(ctx, EXCP_RI); + return true; + } + t0 =3D tcg_temp_new_i64(); + tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]); + tcg_gen_setcondi_i64(cond, t0, t0, 0); + tcg_gen_trunc_i64_tl(bcond, t0); + tcg_temp_free_i64(t0); + + ctx->btarget =3D ctx->base.pc_next + (s16 << 2) + 4; + + ctx->hflags |=3D MIPS_HFLAG_BC; + ctx->hflags |=3D MIPS_HFLAG_BDS32; + + return true; +} + +static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool i= f_not) +{ + check_msa_access(ctx); + + if (ctx->hflags & MIPS_HFLAG_BMASK) { + generate_exception_end(ctx, EXCP_RI); + return true; + } + + gen_check_zero_element(bcond, df, wt); + if (if_not) { + tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0); + } + + ctx->btarget =3D ctx->base.pc_next + (s16 << 2) + 4; + ctx->hflags |=3D MIPS_HFLAG_BC; + ctx->hflags |=3D MIPS_HFLAG_BDS32; + + return true; +} + +void gen_msa_branch(DisasContext *ctx, uint32_t op1) +{ + uint8_t df =3D (ctx->opcode >> 21) & 0x3; + uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; + int64_t s16 =3D (int16_t)ctx->opcode; + + switch (op1) { + case OPC_BZ_V: + case OPC_BNZ_V: + gen_msa_BxZ_V(ctx, wt, s16, (op1 =3D=3D OPC_BZ_V) ? + TCG_COND_EQ : TCG_COND_NE); + break; + case OPC_BZ_B: + case OPC_BZ_H: + case OPC_BZ_W: + case OPC_BZ_D: + gen_msa_BxZ(ctx, df, wt, s16, false); + break; + case OPC_BNZ_B: + case OPC_BNZ_H: + case OPC_BNZ_W: + case OPC_BNZ_D: + gen_msa_BxZ(ctx, df, wt, s16, true); + break; + } +} + +static void gen_msa_i8(DisasContext *ctx) +{ +#define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24))) + uint8_t i8 =3D (ctx->opcode >> 16) & 0xff; + uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + + TCGv_i32 twd =3D tcg_const_i32(wd); + TCGv_i32 tws =3D tcg_const_i32(ws); + TCGv_i32 ti8 =3D tcg_const_i32(i8); + + switch (MASK_MSA_I8(ctx->opcode)) { + case OPC_ANDI_B: + gen_helper_msa_andi_b(cpu_env, twd, tws, ti8); + break; + case OPC_ORI_B: + gen_helper_msa_ori_b(cpu_env, twd, tws, ti8); + break; + case OPC_NORI_B: + gen_helper_msa_nori_b(cpu_env, twd, tws, ti8); + break; + case OPC_XORI_B: + gen_helper_msa_xori_b(cpu_env, twd, tws, ti8); + break; + case OPC_BMNZI_B: + gen_helper_msa_bmnzi_b(cpu_env, twd, tws, ti8); + break; + case OPC_BMZI_B: + gen_helper_msa_bmzi_b(cpu_env, twd, tws, ti8); + break; + case OPC_BSELI_B: + gen_helper_msa_bseli_b(cpu_env, twd, tws, ti8); + break; + case OPC_SHF_B: + case OPC_SHF_H: + case OPC_SHF_W: + { + uint8_t df =3D (ctx->opcode >> 24) & 0x3; + if (df =3D=3D DF_DOUBLE) { + generate_exception_end(ctx, EXCP_RI); + } else { + TCGv_i32 tdf =3D tcg_const_i32(df); + gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, ti8); + tcg_temp_free_i32(tdf); + } + } + break; + default: + MIPS_INVAL("MSA instruction"); + generate_exception_end(ctx, EXCP_RI); + break; + } + + tcg_temp_free_i32(twd); + tcg_temp_free_i32(tws); + tcg_temp_free_i32(ti8); +} + +static void gen_msa_i5(DisasContext *ctx) +{ +#define MASK_MSA_I5(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) + uint8_t df =3D (ctx->opcode >> 21) & 0x3; + int8_t s5 =3D (int8_t) sextract32(ctx->opcode, 16, 5); + uint8_t u5 =3D (ctx->opcode >> 16) & 0x1f; + uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + + TCGv_i32 tdf =3D tcg_const_i32(df); + TCGv_i32 twd =3D tcg_const_i32(wd); + TCGv_i32 tws =3D tcg_const_i32(ws); + TCGv_i32 timm =3D tcg_temp_new_i32(); + tcg_gen_movi_i32(timm, u5); + + switch (MASK_MSA_I5(ctx->opcode)) { + case OPC_ADDVI_df: + gen_helper_msa_addvi_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_SUBVI_df: + gen_helper_msa_subvi_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_MAXI_S_df: + tcg_gen_movi_i32(timm, s5); + gen_helper_msa_maxi_s_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_MAXI_U_df: + gen_helper_msa_maxi_u_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_MINI_S_df: + tcg_gen_movi_i32(timm, s5); + gen_helper_msa_mini_s_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_MINI_U_df: + gen_helper_msa_mini_u_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_CEQI_df: + tcg_gen_movi_i32(timm, s5); + gen_helper_msa_ceqi_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_CLTI_S_df: + tcg_gen_movi_i32(timm, s5); + gen_helper_msa_clti_s_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_CLTI_U_df: + gen_helper_msa_clti_u_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_CLEI_S_df: + tcg_gen_movi_i32(timm, s5); + gen_helper_msa_clei_s_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_CLEI_U_df: + gen_helper_msa_clei_u_df(cpu_env, tdf, twd, tws, timm); + break; + case OPC_LDI_df: + { + int32_t s10 =3D sextract32(ctx->opcode, 11, 10); + tcg_gen_movi_i32(timm, s10); + gen_helper_msa_ldi_df(cpu_env, tdf, twd, timm); + } + break; + default: + MIPS_INVAL("MSA instruction"); + generate_exception_end(ctx, EXCP_RI); + break; + } + + tcg_temp_free_i32(tdf); + tcg_temp_free_i32(twd); + tcg_temp_free_i32(tws); + tcg_temp_free_i32(timm); +} + +static void gen_msa_bit(DisasContext *ctx) +{ +#define MASK_MSA_BIT(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) + uint8_t dfm =3D (ctx->opcode >> 16) & 0x7f; + uint32_t df =3D 0, m =3D 0; + uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + + TCGv_i32 tdf; + TCGv_i32 tm; + TCGv_i32 twd; + TCGv_i32 tws; + + if ((dfm & 0x40) =3D=3D 0x00) { + m =3D dfm & 0x3f; + df =3D DF_DOUBLE; + } else if ((dfm & 0x60) =3D=3D 0x40) { + m =3D dfm & 0x1f; + df =3D DF_WORD; + } else if ((dfm & 0x70) =3D=3D 0x60) { + m =3D dfm & 0x0f; + df =3D DF_HALF; + } else if ((dfm & 0x78) =3D=3D 0x70) { + m =3D dfm & 0x7; + df =3D DF_BYTE; + } else { + generate_exception_end(ctx, EXCP_RI); + return; + } + + tdf =3D tcg_const_i32(df); + tm =3D tcg_const_i32(m); + twd =3D tcg_const_i32(wd); + tws =3D tcg_const_i32(ws); + + switch (MASK_MSA_BIT(ctx->opcode)) { + case OPC_SLLI_df: + gen_helper_msa_slli_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_SRAI_df: + gen_helper_msa_srai_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_SRLI_df: + gen_helper_msa_srli_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_BCLRI_df: + gen_helper_msa_bclri_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_BSETI_df: + gen_helper_msa_bseti_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_BNEGI_df: + gen_helper_msa_bnegi_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_BINSLI_df: + gen_helper_msa_binsli_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_BINSRI_df: + gen_helper_msa_binsri_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_SAT_S_df: + gen_helper_msa_sat_s_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_SAT_U_df: + gen_helper_msa_sat_u_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_SRARI_df: + gen_helper_msa_srari_df(cpu_env, tdf, twd, tws, tm); + break; + case OPC_SRLRI_df: + gen_helper_msa_srlri_df(cpu_env, tdf, twd, tws, tm); + break; + default: + MIPS_INVAL("MSA instruction"); + generate_exception_end(ctx, EXCP_RI); + break; + } + + tcg_temp_free_i32(tdf); + tcg_temp_free_i32(tm); + tcg_temp_free_i32(twd); + tcg_temp_free_i32(tws); +} + +static void gen_msa_3r(DisasContext *ctx) +{ +#define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) + uint8_t df =3D (ctx->opcode >> 21) & 0x3; + uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; + uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + + TCGv_i32 tdf =3D tcg_const_i32(df); + TCGv_i32 twd =3D tcg_const_i32(wd); + TCGv_i32 tws =3D tcg_const_i32(ws); + TCGv_i32 twt =3D tcg_const_i32(wt); + + switch (MASK_MSA_3R(ctx->opcode)) { + case OPC_BINSL_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_binsl_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_binsl_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_binsl_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_binsl_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_BINSR_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_binsr_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_binsr_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_binsr_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_binsr_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_BCLR_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_bclr_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_bclr_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_bclr_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_bclr_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_BNEG_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_bneg_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_bneg_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_bneg_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_bneg_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_BSET_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_bset_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_bset_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_bset_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_bset_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ADD_A_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_add_a_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_add_a_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_add_a_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_add_a_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ADDS_A_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_adds_a_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_adds_a_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_adds_a_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_adds_a_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ADDS_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_adds_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_adds_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_adds_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_adds_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ADDS_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_adds_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_adds_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_adds_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_adds_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ADDV_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_addv_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_addv_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_addv_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_addv_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_AVE_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ave_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ave_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ave_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ave_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_AVE_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ave_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ave_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ave_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ave_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_AVER_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_aver_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_aver_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_aver_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_aver_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_AVER_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_aver_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_aver_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_aver_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_aver_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_CEQ_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ceq_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ceq_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ceq_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ceq_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_CLE_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_cle_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_cle_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_cle_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_cle_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_CLE_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_cle_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_cle_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_cle_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_cle_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_CLT_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_clt_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_clt_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_clt_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_clt_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_CLT_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_clt_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_clt_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_clt_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_clt_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_DIV_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_div_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_div_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_div_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_div_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_DIV_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_div_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_div_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_div_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_div_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MAX_A_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_max_a_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_max_a_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_max_a_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_max_a_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MAX_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_max_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_max_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_max_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_max_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MAX_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_max_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_max_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_max_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_max_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MIN_A_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_min_a_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_min_a_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_min_a_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_min_a_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MIN_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_min_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_min_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_min_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_min_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MIN_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_min_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_min_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_min_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_min_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MOD_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_mod_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_mod_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_mod_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_mod_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MOD_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_mod_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_mod_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_mod_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_mod_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MADDV_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_maddv_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_maddv_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_maddv_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_maddv_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MSUBV_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_msubv_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_msubv_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_msubv_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_msubv_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ASUB_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_asub_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_asub_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_asub_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_asub_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ASUB_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_asub_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_asub_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_asub_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_asub_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ILVEV_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ilvev_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ilvev_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ilvev_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ilvev_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ILVOD_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ilvod_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ilvod_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ilvod_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ilvod_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ILVL_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ilvl_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ilvl_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ilvl_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ilvl_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_ILVR_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_ilvr_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_ilvr_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_ilvr_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_ilvr_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_PCKEV_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_pckev_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_pckev_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_pckev_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_pckev_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_PCKOD_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_pckod_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_pckod_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_pckod_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_pckod_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SLL_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_sll_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_sll_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_sll_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_sll_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SRA_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_sra_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_sra_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_sra_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_sra_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SRAR_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_srar_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_srar_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_srar_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_srar_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SRL_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_srl_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_srl_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_srl_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_srl_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SRLR_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_srlr_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_srlr_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_srlr_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_srlr_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SUBS_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_subs_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_subs_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_subs_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_subs_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_MULV_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_mulv_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_mulv_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_mulv_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_mulv_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SLD_df: + gen_helper_msa_sld_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_VSHF_df: + gen_helper_msa_vshf_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_SUBV_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_subv_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_subv_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_subv_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_subv_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SUBS_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_subs_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_subs_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_subs_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_subs_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SPLAT_df: + gen_helper_msa_splat_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_SUBSUS_U_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_subsus_u_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_subsus_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_subsus_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_subsus_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_SUBSUU_S_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_subsuu_s_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_subsuu_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_subsuu_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_subsuu_s_d(cpu_env, twd, tws, twt); + break; + } + break; + + case OPC_DOTP_S_df: + case OPC_DOTP_U_df: + case OPC_DPADD_S_df: + case OPC_DPADD_U_df: + case OPC_DPSUB_S_df: + case OPC_HADD_S_df: + case OPC_DPSUB_U_df: + case OPC_HADD_U_df: + case OPC_HSUB_S_df: + case OPC_HSUB_U_df: + if (df =3D=3D DF_BYTE) { + generate_exception_end(ctx, EXCP_RI); + break; + } + switch (MASK_MSA_3R(ctx->opcode)) { + case OPC_HADD_S_df: + switch (df) { + case DF_HALF: + gen_helper_msa_hadd_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_hadd_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_hadd_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_HADD_U_df: + switch (df) { + case DF_HALF: + gen_helper_msa_hadd_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_hadd_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_hadd_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_HSUB_S_df: + switch (df) { + case DF_HALF: + gen_helper_msa_hsub_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_hsub_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_hsub_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_HSUB_U_df: + switch (df) { + case DF_HALF: + gen_helper_msa_hsub_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_hsub_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_hsub_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_DOTP_S_df: + switch (df) { + case DF_HALF: + gen_helper_msa_dotp_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_dotp_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_dotp_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_DOTP_U_df: + switch (df) { + case DF_HALF: + gen_helper_msa_dotp_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_dotp_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_dotp_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_DPADD_S_df: + switch (df) { + case DF_HALF: + gen_helper_msa_dpadd_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_dpadd_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_dpadd_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_DPADD_U_df: + switch (df) { + case DF_HALF: + gen_helper_msa_dpadd_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_dpadd_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_dpadd_u_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_DPSUB_S_df: + switch (df) { + case DF_HALF: + gen_helper_msa_dpsub_s_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_dpsub_s_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_dpsub_s_d(cpu_env, twd, tws, twt); + break; + } + break; + case OPC_DPSUB_U_df: + switch (df) { + case DF_HALF: + gen_helper_msa_dpsub_u_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_dpsub_u_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_dpsub_u_d(cpu_env, twd, tws, twt); + break; + } + break; + } + break; + default: + MIPS_INVAL("MSA instruction"); + generate_exception_end(ctx, EXCP_RI); + break; + } + tcg_temp_free_i32(twd); + tcg_temp_free_i32(tws); + tcg_temp_free_i32(twt); + tcg_temp_free_i32(tdf); +} + +static void gen_msa_elm_3e(DisasContext *ctx) +{ +#define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16))) + uint8_t source =3D (ctx->opcode >> 11) & 0x1f; + uint8_t dest =3D (ctx->opcode >> 6) & 0x1f; + TCGv telm =3D tcg_temp_new(); + TCGv_i32 tsr =3D tcg_const_i32(source); + TCGv_i32 tdt =3D tcg_const_i32(dest); + + switch (MASK_MSA_ELM_DF3E(ctx->opcode)) { + case OPC_CTCMSA: + gen_load_gpr(telm, source); + gen_helper_msa_ctcmsa(cpu_env, telm, tdt); + break; + case OPC_CFCMSA: + gen_helper_msa_cfcmsa(telm, cpu_env, tsr); + gen_store_gpr(telm, dest); + break; + case OPC_MOVE_V: + gen_helper_msa_move_v(cpu_env, tdt, tsr); + break; + default: + MIPS_INVAL("MSA instruction"); + generate_exception_end(ctx, EXCP_RI); + break; + } + + tcg_temp_free(telm); + tcg_temp_free_i32(tdt); + tcg_temp_free_i32(tsr); +} + +static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n) +{ +#define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) + uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + + TCGv_i32 tws =3D tcg_const_i32(ws); + TCGv_i32 twd =3D tcg_const_i32(wd); + TCGv_i32 tn =3D tcg_const_i32(n); + TCGv_i32 tdf =3D tcg_const_i32(df); + + switch (MASK_MSA_ELM(ctx->opcode)) { + case OPC_SLDI_df: + gen_helper_msa_sldi_df(cpu_env, tdf, twd, tws, tn); + break; + case OPC_SPLATI_df: + gen_helper_msa_splati_df(cpu_env, tdf, twd, tws, tn); + break; + case OPC_INSVE_df: + gen_helper_msa_insve_df(cpu_env, tdf, twd, tws, tn); + break; + case OPC_COPY_S_df: + case OPC_COPY_U_df: + case OPC_INSERT_df: +#if !defined(TARGET_MIPS64) + /* Double format valid only for MIPS64 */ + if (df =3D=3D DF_DOUBLE) { + generate_exception_end(ctx, EXCP_RI); + break; + } + if ((MASK_MSA_ELM(ctx->opcode) =3D=3D OPC_COPY_U_df) && + (df =3D=3D DF_WORD)) { + generate_exception_end(ctx, EXCP_RI); + break; + } +#endif + switch (MASK_MSA_ELM(ctx->opcode)) { + case OPC_COPY_S_df: + if (likely(wd !=3D 0)) { + switch (df) { + case DF_BYTE: + gen_helper_msa_copy_s_b(cpu_env, twd, tws, tn); + break; + case DF_HALF: + gen_helper_msa_copy_s_h(cpu_env, twd, tws, tn); + break; + case DF_WORD: + gen_helper_msa_copy_s_w(cpu_env, twd, tws, tn); + break; +#if defined(TARGET_MIPS64) + case DF_DOUBLE: + gen_helper_msa_copy_s_d(cpu_env, twd, tws, tn); + break; +#endif + default: + assert(0); + } + } + break; + case OPC_COPY_U_df: + if (likely(wd !=3D 0)) { + switch (df) { + case DF_BYTE: + gen_helper_msa_copy_u_b(cpu_env, twd, tws, tn); + break; + case DF_HALF: + gen_helper_msa_copy_u_h(cpu_env, twd, tws, tn); + break; +#if defined(TARGET_MIPS64) + case DF_WORD: + gen_helper_msa_copy_u_w(cpu_env, twd, tws, tn); + break; +#endif + default: + assert(0); + } + } + break; + case OPC_INSERT_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_insert_b(cpu_env, twd, tws, tn); + break; + case DF_HALF: + gen_helper_msa_insert_h(cpu_env, twd, tws, tn); + break; + case DF_WORD: + gen_helper_msa_insert_w(cpu_env, twd, tws, tn); + break; +#if defined(TARGET_MIPS64) + case DF_DOUBLE: + gen_helper_msa_insert_d(cpu_env, twd, tws, tn); + break; +#endif + default: + assert(0); + } + break; + } + break; + default: + MIPS_INVAL("MSA instruction"); + generate_exception_end(ctx, EXCP_RI); + } + tcg_temp_free_i32(twd); + tcg_temp_free_i32(tws); + tcg_temp_free_i32(tn); + tcg_temp_free_i32(tdf); +} + +static void gen_msa_elm(DisasContext *ctx) +{ + uint8_t dfn =3D (ctx->opcode >> 16) & 0x3f; + uint32_t df =3D 0, n =3D 0; + + if ((dfn & 0x30) =3D=3D 0x00) { + n =3D dfn & 0x0f; + df =3D DF_BYTE; + } else if ((dfn & 0x38) =3D=3D 0x20) { + n =3D dfn & 0x07; + df =3D DF_HALF; + } else if ((dfn & 0x3c) =3D=3D 0x30) { + n =3D dfn & 0x03; + df =3D DF_WORD; + } else if ((dfn & 0x3e) =3D=3D 0x38) { + n =3D dfn & 0x01; + df =3D DF_DOUBLE; + } else if (dfn =3D=3D 0x3E) { + /* CTCMSA, CFCMSA, MOVE.V */ + gen_msa_elm_3e(ctx); + return; + } else { + generate_exception_end(ctx, EXCP_RI); + return; + } + + gen_msa_elm_df(ctx, df, n); +} + +static void gen_msa_3rf(DisasContext *ctx) +{ +#define MASK_MSA_3RF(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) + uint8_t df =3D (ctx->opcode >> 21) & 0x1; + uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; + uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + + TCGv_i32 twd =3D tcg_const_i32(wd); + TCGv_i32 tws =3D tcg_const_i32(ws); + TCGv_i32 twt =3D tcg_const_i32(wt); + TCGv_i32 tdf =3D tcg_temp_new_i32(); + + /* adjust df value for floating-point instruction */ + tcg_gen_movi_i32(tdf, df + 2); + + switch (MASK_MSA_3RF(ctx->opcode)) { + case OPC_FCAF_df: + gen_helper_msa_fcaf_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FADD_df: + gen_helper_msa_fadd_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCUN_df: + gen_helper_msa_fcun_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSUB_df: + gen_helper_msa_fsub_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCOR_df: + gen_helper_msa_fcor_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCEQ_df: + gen_helper_msa_fceq_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FMUL_df: + gen_helper_msa_fmul_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCUNE_df: + gen_helper_msa_fcune_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCUEQ_df: + gen_helper_msa_fcueq_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FDIV_df: + gen_helper_msa_fdiv_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCNE_df: + gen_helper_msa_fcne_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCLT_df: + gen_helper_msa_fclt_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FMADD_df: + gen_helper_msa_fmadd_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_MUL_Q_df: + tcg_gen_movi_i32(tdf, df + 1); + gen_helper_msa_mul_q_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCULT_df: + gen_helper_msa_fcult_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FMSUB_df: + gen_helper_msa_fmsub_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_MADD_Q_df: + tcg_gen_movi_i32(tdf, df + 1); + gen_helper_msa_madd_q_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCLE_df: + gen_helper_msa_fcle_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_MSUB_Q_df: + tcg_gen_movi_i32(tdf, df + 1); + gen_helper_msa_msub_q_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FCULE_df: + gen_helper_msa_fcule_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FEXP2_df: + gen_helper_msa_fexp2_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSAF_df: + gen_helper_msa_fsaf_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FEXDO_df: + gen_helper_msa_fexdo_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSUN_df: + gen_helper_msa_fsun_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSOR_df: + gen_helper_msa_fsor_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSEQ_df: + gen_helper_msa_fseq_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FTQ_df: + gen_helper_msa_ftq_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSUNE_df: + gen_helper_msa_fsune_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSUEQ_df: + gen_helper_msa_fsueq_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSNE_df: + gen_helper_msa_fsne_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSLT_df: + gen_helper_msa_fslt_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FMIN_df: + gen_helper_msa_fmin_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_MULR_Q_df: + tcg_gen_movi_i32(tdf, df + 1); + gen_helper_msa_mulr_q_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSULT_df: + gen_helper_msa_fsult_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FMIN_A_df: + gen_helper_msa_fmin_a_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_MADDR_Q_df: + tcg_gen_movi_i32(tdf, df + 1); + gen_helper_msa_maddr_q_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSLE_df: + gen_helper_msa_fsle_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FMAX_df: + gen_helper_msa_fmax_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_MSUBR_Q_df: + tcg_gen_movi_i32(tdf, df + 1); + gen_helper_msa_msubr_q_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FSULE_df: + gen_helper_msa_fsule_df(cpu_env, tdf, twd, tws, twt); + break; + case OPC_FMAX_A_df: + gen_helper_msa_fmax_a_df(cpu_env, tdf, twd, tws, twt); + break; + default: + MIPS_INVAL("MSA instruction"); + generate_exception_end(ctx, EXCP_RI); + break; + } + + tcg_temp_free_i32(twd); + tcg_temp_free_i32(tws); + tcg_temp_free_i32(twt); + tcg_temp_free_i32(tdf); +} + +static void gen_msa_2r(DisasContext *ctx) +{ +#define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \ + (op & (0x7 << 18))) + uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; + uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + uint8_t df =3D (ctx->opcode >> 16) & 0x3; + TCGv_i32 twd =3D tcg_const_i32(wd); + TCGv_i32 tws =3D tcg_const_i32(ws); + TCGv_i32 twt =3D tcg_const_i32(wt); + TCGv_i32 tdf =3D tcg_const_i32(df); + + switch (MASK_MSA_2R(ctx->opcode)) { + case OPC_FILL_df: +#if !defined(TARGET_MIPS64) + /* Double format valid only for MIPS64 */ + if (df =3D=3D DF_DOUBLE) { + generate_exception_end(ctx, EXCP_RI); + break; + } +#endif + gen_helper_msa_fill_df(cpu_env, tdf, twd, tws); /* trs */ + break; + case OPC_NLOC_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_nloc_b(cpu_env, twd, tws); + break; + case DF_HALF: + gen_helper_msa_nloc_h(cpu_env, twd, tws); + break; + case DF_WORD: + gen_helper_msa_nloc_w(cpu_env, twd, tws); + break; + case DF_DOUBLE: + gen_helper_msa_nloc_d(cpu_env, twd, tws); + break; + } + break; + case OPC_NLZC_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_nlzc_b(cpu_env, twd, tws); + break; + case DF_HALF: + gen_helper_msa_nlzc_h(cpu_env, twd, tws); + break; + case DF_WORD: + gen_helper_msa_nlzc_w(cpu_env, twd, tws); + break; + case DF_DOUBLE: + gen_helper_msa_nlzc_d(cpu_env, twd, tws); + break; + } + break; + case OPC_PCNT_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_pcnt_b(cpu_env, twd, tws); + break; + case DF_HALF: + gen_helper_msa_pcnt_h(cpu_env, twd, tws); + break; + case DF_WORD: + gen_helper_msa_pcnt_w(cpu_env, twd, tws); + break; + case DF_DOUBLE: + gen_helper_msa_pcnt_d(cpu_env, twd, tws); + break; + } + break; + default: + MIPS_INVAL("MSA instruction"); + generate_exception_end(ctx, EXCP_RI); + break; + } + + tcg_temp_free_i32(twd); + tcg_temp_free_i32(tws); + tcg_temp_free_i32(twt); + tcg_temp_free_i32(tdf); +} + +static void gen_msa_2rf(DisasContext *ctx) +{ +#define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \ + (op & (0xf << 17))) + uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; + uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + uint8_t df =3D (ctx->opcode >> 16) & 0x1; + TCGv_i32 twd =3D tcg_const_i32(wd); + TCGv_i32 tws =3D tcg_const_i32(ws); + TCGv_i32 twt =3D tcg_const_i32(wt); + /* adjust df value for floating-point instruction */ + TCGv_i32 tdf =3D tcg_const_i32(df + 2); + + switch (MASK_MSA_2RF(ctx->opcode)) { + case OPC_FCLASS_df: + gen_helper_msa_fclass_df(cpu_env, tdf, twd, tws); + break; + case OPC_FTRUNC_S_df: + gen_helper_msa_ftrunc_s_df(cpu_env, tdf, twd, tws); + break; + case OPC_FTRUNC_U_df: + gen_helper_msa_ftrunc_u_df(cpu_env, tdf, twd, tws); + break; + case OPC_FSQRT_df: + gen_helper_msa_fsqrt_df(cpu_env, tdf, twd, tws); + break; + case OPC_FRSQRT_df: + gen_helper_msa_frsqrt_df(cpu_env, tdf, twd, tws); + break; + case OPC_FRCP_df: + gen_helper_msa_frcp_df(cpu_env, tdf, twd, tws); + break; + case OPC_FRINT_df: + gen_helper_msa_frint_df(cpu_env, tdf, twd, tws); + break; + case OPC_FLOG2_df: + gen_helper_msa_flog2_df(cpu_env, tdf, twd, tws); + break; + case OPC_FEXUPL_df: + gen_helper_msa_fexupl_df(cpu_env, tdf, twd, tws); + break; + case OPC_FEXUPR_df: + gen_helper_msa_fexupr_df(cpu_env, tdf, twd, tws); + break; + case OPC_FFQL_df: + gen_helper_msa_ffql_df(cpu_env, tdf, twd, tws); + break; + case OPC_FFQR_df: + gen_helper_msa_ffqr_df(cpu_env, tdf, twd, tws); + break; + case OPC_FTINT_S_df: + gen_helper_msa_ftint_s_df(cpu_env, tdf, twd, tws); + break; + case OPC_FTINT_U_df: + gen_helper_msa_ftint_u_df(cpu_env, tdf, twd, tws); + break; + case OPC_FFINT_S_df: + gen_helper_msa_ffint_s_df(cpu_env, tdf, twd, tws); + break; + case OPC_FFINT_U_df: + gen_helper_msa_ffint_u_df(cpu_env, tdf, twd, tws); + break; + } + + tcg_temp_free_i32(twd); + tcg_temp_free_i32(tws); + tcg_temp_free_i32(twt); + tcg_temp_free_i32(tdf); +} + +static void gen_msa_vec_v(DisasContext *ctx) +{ +#define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21))) + uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; + uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + TCGv_i32 twd =3D tcg_const_i32(wd); + TCGv_i32 tws =3D tcg_const_i32(ws); + TCGv_i32 twt =3D tcg_const_i32(wt); + + switch (MASK_MSA_VEC(ctx->opcode)) { + case OPC_AND_V: + gen_helper_msa_and_v(cpu_env, twd, tws, twt); + break; + case OPC_OR_V: + gen_helper_msa_or_v(cpu_env, twd, tws, twt); + break; + case OPC_NOR_V: + gen_helper_msa_nor_v(cpu_env, twd, tws, twt); + break; + case OPC_XOR_V: + gen_helper_msa_xor_v(cpu_env, twd, tws, twt); + break; + case OPC_BMNZ_V: + gen_helper_msa_bmnz_v(cpu_env, twd, tws, twt); + break; + case OPC_BMZ_V: + gen_helper_msa_bmz_v(cpu_env, twd, tws, twt); + break; + case OPC_BSEL_V: + gen_helper_msa_bsel_v(cpu_env, twd, tws, twt); + break; + default: + MIPS_INVAL("MSA instruction"); + generate_exception_end(ctx, EXCP_RI); + break; + } + + tcg_temp_free_i32(twd); + tcg_temp_free_i32(tws); + tcg_temp_free_i32(twt); +} + +static void gen_msa_vec(DisasContext *ctx) +{ + switch (MASK_MSA_VEC(ctx->opcode)) { + case OPC_AND_V: + case OPC_OR_V: + case OPC_NOR_V: + case OPC_XOR_V: + case OPC_BMNZ_V: + case OPC_BMZ_V: + case OPC_BSEL_V: + gen_msa_vec_v(ctx); + break; + case OPC_MSA_2R: + gen_msa_2r(ctx); + break; + case OPC_MSA_2RF: + gen_msa_2rf(ctx); + break; + default: + MIPS_INVAL("MSA instruction"); + generate_exception_end(ctx, EXCP_RI); + break; + } +} + +void gen_msa(DisasContext *ctx) +{ + uint32_t opcode =3D ctx->opcode; + + check_msa_access(ctx); + + switch (MASK_MSA_MINOR(opcode)) { + case OPC_MSA_I8_00: + case OPC_MSA_I8_01: + case OPC_MSA_I8_02: + gen_msa_i8(ctx); + break; + case OPC_MSA_I5_06: + case OPC_MSA_I5_07: + gen_msa_i5(ctx); + break; + case OPC_MSA_BIT_09: + case OPC_MSA_BIT_0A: + gen_msa_bit(ctx); + break; + case OPC_MSA_3R_0D: + case OPC_MSA_3R_0E: + case OPC_MSA_3R_0F: + case OPC_MSA_3R_10: + case OPC_MSA_3R_11: + case OPC_MSA_3R_12: + case OPC_MSA_3R_13: + case OPC_MSA_3R_14: + case OPC_MSA_3R_15: + gen_msa_3r(ctx); + break; + case OPC_MSA_ELM: + gen_msa_elm(ctx); + break; + case OPC_MSA_3RF_1A: + case OPC_MSA_3RF_1B: + case OPC_MSA_3RF_1C: + gen_msa_3rf(ctx); + break; + case OPC_MSA_VEC: + gen_msa_vec(ctx); + break; + case OPC_LD_B: + case OPC_LD_H: + case OPC_LD_W: + case OPC_LD_D: + case OPC_ST_B: + case OPC_ST_H: + case OPC_ST_W: + case OPC_ST_D: + { + int32_t s10 =3D sextract32(ctx->opcode, 16, 10); + uint8_t rs =3D (ctx->opcode >> 11) & 0x1f; + uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; + uint8_t df =3D (ctx->opcode >> 0) & 0x3; + + TCGv_i32 twd =3D tcg_const_i32(wd); + TCGv taddr =3D tcg_temp_new(); + gen_base_offset_addr(ctx, taddr, rs, s10 << df); + + switch (MASK_MSA_MINOR(opcode)) { + case OPC_LD_B: + gen_helper_msa_ld_b(cpu_env, twd, taddr); + break; + case OPC_LD_H: + gen_helper_msa_ld_h(cpu_env, twd, taddr); + break; + case OPC_LD_W: + gen_helper_msa_ld_w(cpu_env, twd, taddr); + break; + case OPC_LD_D: + gen_helper_msa_ld_d(cpu_env, twd, taddr); + break; + case OPC_ST_B: + gen_helper_msa_st_b(cpu_env, twd, taddr); + break; + case OPC_ST_H: + gen_helper_msa_st_h(cpu_env, twd, taddr); + break; + case OPC_ST_W: + gen_helper_msa_st_w(cpu_env, twd, taddr); + break; + case OPC_ST_D: + gen_helper_msa_st_d(cpu_env, twd, taddr); + break; + } + + tcg_temp_free_i32(twd); + tcg_temp_free(taddr); + } + break; + default: + MIPS_INVAL("MSA instruction"); + generate_exception_end(ctx, EXCP_RI); + break; + } +} diff --git a/target/mips/translate.c b/target/mips/translate.c index d8553c626f3..5cd67459304 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1139,240 +1139,6 @@ enum { OPC_NMSUB_PS =3D 0x3E | OPC_CP3, }; =20 -/* MSA Opcodes */ -#define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) -enum { - OPC_MSA_I8_00 =3D 0x00 | OPC_MSA, - OPC_MSA_I8_01 =3D 0x01 | OPC_MSA, - OPC_MSA_I8_02 =3D 0x02 | OPC_MSA, - OPC_MSA_I5_06 =3D 0x06 | OPC_MSA, - OPC_MSA_I5_07 =3D 0x07 | OPC_MSA, - OPC_MSA_BIT_09 =3D 0x09 | OPC_MSA, - OPC_MSA_BIT_0A =3D 0x0A | OPC_MSA, - OPC_MSA_3R_0D =3D 0x0D | OPC_MSA, - OPC_MSA_3R_0E =3D 0x0E | OPC_MSA, - OPC_MSA_3R_0F =3D 0x0F | OPC_MSA, - OPC_MSA_3R_10 =3D 0x10 | OPC_MSA, - OPC_MSA_3R_11 =3D 0x11 | OPC_MSA, - OPC_MSA_3R_12 =3D 0x12 | OPC_MSA, - OPC_MSA_3R_13 =3D 0x13 | OPC_MSA, - OPC_MSA_3R_14 =3D 0x14 | OPC_MSA, - OPC_MSA_3R_15 =3D 0x15 | OPC_MSA, - OPC_MSA_ELM =3D 0x19 | OPC_MSA, - OPC_MSA_3RF_1A =3D 0x1A | OPC_MSA, - OPC_MSA_3RF_1B =3D 0x1B | OPC_MSA, - OPC_MSA_3RF_1C =3D 0x1C | OPC_MSA, - OPC_MSA_VEC =3D 0x1E | OPC_MSA, - - /* MI10 instruction */ - OPC_LD_B =3D (0x20) | OPC_MSA, - OPC_LD_H =3D (0x21) | OPC_MSA, - OPC_LD_W =3D (0x22) | OPC_MSA, - OPC_LD_D =3D (0x23) | OPC_MSA, - OPC_ST_B =3D (0x24) | OPC_MSA, - OPC_ST_H =3D (0x25) | OPC_MSA, - OPC_ST_W =3D (0x26) | OPC_MSA, - OPC_ST_D =3D (0x27) | OPC_MSA, -}; - -enum { - /* I5 instruction df(bits 22..21) =3D _b, _h, _w, _d */ - OPC_ADDVI_df =3D (0x0 << 23) | OPC_MSA_I5_06, - OPC_CEQI_df =3D (0x0 << 23) | OPC_MSA_I5_07, - OPC_SUBVI_df =3D (0x1 << 23) | OPC_MSA_I5_06, - OPC_MAXI_S_df =3D (0x2 << 23) | OPC_MSA_I5_06, - OPC_CLTI_S_df =3D (0x2 << 23) | OPC_MSA_I5_07, - OPC_MAXI_U_df =3D (0x3 << 23) | OPC_MSA_I5_06, - OPC_CLTI_U_df =3D (0x3 << 23) | OPC_MSA_I5_07, - OPC_MINI_S_df =3D (0x4 << 23) | OPC_MSA_I5_06, - OPC_CLEI_S_df =3D (0x4 << 23) | OPC_MSA_I5_07, - OPC_MINI_U_df =3D (0x5 << 23) | OPC_MSA_I5_06, - OPC_CLEI_U_df =3D (0x5 << 23) | OPC_MSA_I5_07, - OPC_LDI_df =3D (0x6 << 23) | OPC_MSA_I5_07, - - /* I8 instruction */ - OPC_ANDI_B =3D (0x0 << 24) | OPC_MSA_I8_00, - OPC_BMNZI_B =3D (0x0 << 24) | OPC_MSA_I8_01, - OPC_SHF_B =3D (0x0 << 24) | OPC_MSA_I8_02, - OPC_ORI_B =3D (0x1 << 24) | OPC_MSA_I8_00, - OPC_BMZI_B =3D (0x1 << 24) | OPC_MSA_I8_01, - OPC_SHF_H =3D (0x1 << 24) | OPC_MSA_I8_02, - OPC_NORI_B =3D (0x2 << 24) | OPC_MSA_I8_00, - OPC_BSELI_B =3D (0x2 << 24) | OPC_MSA_I8_01, - OPC_SHF_W =3D (0x2 << 24) | OPC_MSA_I8_02, - OPC_XORI_B =3D (0x3 << 24) | OPC_MSA_I8_00, - - /* VEC/2R/2RF instruction */ - OPC_AND_V =3D (0x00 << 21) | OPC_MSA_VEC, - OPC_OR_V =3D (0x01 << 21) | OPC_MSA_VEC, - OPC_NOR_V =3D (0x02 << 21) | OPC_MSA_VEC, - OPC_XOR_V =3D (0x03 << 21) | OPC_MSA_VEC, - OPC_BMNZ_V =3D (0x04 << 21) | OPC_MSA_VEC, - OPC_BMZ_V =3D (0x05 << 21) | OPC_MSA_VEC, - OPC_BSEL_V =3D (0x06 << 21) | OPC_MSA_VEC, - - OPC_MSA_2R =3D (0x18 << 21) | OPC_MSA_VEC, - OPC_MSA_2RF =3D (0x19 << 21) | OPC_MSA_VEC, - - /* 2R instruction df(bits 17..16) =3D _b, _h, _w, _d */ - OPC_FILL_df =3D (0x00 << 18) | OPC_MSA_2R, - OPC_PCNT_df =3D (0x01 << 18) | OPC_MSA_2R, - OPC_NLOC_df =3D (0x02 << 18) | OPC_MSA_2R, - OPC_NLZC_df =3D (0x03 << 18) | OPC_MSA_2R, - - /* 2RF instruction df(bit 16) =3D _w, _d */ - OPC_FCLASS_df =3D (0x00 << 17) | OPC_MSA_2RF, - OPC_FTRUNC_S_df =3D (0x01 << 17) | OPC_MSA_2RF, - OPC_FTRUNC_U_df =3D (0x02 << 17) | OPC_MSA_2RF, - OPC_FSQRT_df =3D (0x03 << 17) | OPC_MSA_2RF, - OPC_FRSQRT_df =3D (0x04 << 17) | OPC_MSA_2RF, - OPC_FRCP_df =3D (0x05 << 17) | OPC_MSA_2RF, - OPC_FRINT_df =3D (0x06 << 17) | OPC_MSA_2RF, - OPC_FLOG2_df =3D (0x07 << 17) | OPC_MSA_2RF, - OPC_FEXUPL_df =3D (0x08 << 17) | OPC_MSA_2RF, - OPC_FEXUPR_df =3D (0x09 << 17) | OPC_MSA_2RF, - OPC_FFQL_df =3D (0x0A << 17) | OPC_MSA_2RF, - OPC_FFQR_df =3D (0x0B << 17) | OPC_MSA_2RF, - OPC_FTINT_S_df =3D (0x0C << 17) | OPC_MSA_2RF, - OPC_FTINT_U_df =3D (0x0D << 17) | OPC_MSA_2RF, - OPC_FFINT_S_df =3D (0x0E << 17) | OPC_MSA_2RF, - OPC_FFINT_U_df =3D (0x0F << 17) | OPC_MSA_2RF, - - /* 3R instruction df(bits 22..21) =3D _b, _h, _w, d */ - OPC_SLL_df =3D (0x0 << 23) | OPC_MSA_3R_0D, - OPC_ADDV_df =3D (0x0 << 23) | OPC_MSA_3R_0E, - OPC_CEQ_df =3D (0x0 << 23) | OPC_MSA_3R_0F, - OPC_ADD_A_df =3D (0x0 << 23) | OPC_MSA_3R_10, - OPC_SUBS_S_df =3D (0x0 << 23) | OPC_MSA_3R_11, - OPC_MULV_df =3D (0x0 << 23) | OPC_MSA_3R_12, - OPC_DOTP_S_df =3D (0x0 << 23) | OPC_MSA_3R_13, - OPC_SLD_df =3D (0x0 << 23) | OPC_MSA_3R_14, - OPC_VSHF_df =3D (0x0 << 23) | OPC_MSA_3R_15, - OPC_SRA_df =3D (0x1 << 23) | OPC_MSA_3R_0D, - OPC_SUBV_df =3D (0x1 << 23) | OPC_MSA_3R_0E, - OPC_ADDS_A_df =3D (0x1 << 23) | OPC_MSA_3R_10, - OPC_SUBS_U_df =3D (0x1 << 23) | OPC_MSA_3R_11, - OPC_MADDV_df =3D (0x1 << 23) | OPC_MSA_3R_12, - OPC_DOTP_U_df =3D (0x1 << 23) | OPC_MSA_3R_13, - OPC_SPLAT_df =3D (0x1 << 23) | OPC_MSA_3R_14, - OPC_SRAR_df =3D (0x1 << 23) | OPC_MSA_3R_15, - OPC_SRL_df =3D (0x2 << 23) | OPC_MSA_3R_0D, - OPC_MAX_S_df =3D (0x2 << 23) | OPC_MSA_3R_0E, - OPC_CLT_S_df =3D (0x2 << 23) | OPC_MSA_3R_0F, - OPC_ADDS_S_df =3D (0x2 << 23) | OPC_MSA_3R_10, - OPC_SUBSUS_U_df =3D (0x2 << 23) | OPC_MSA_3R_11, - OPC_MSUBV_df =3D (0x2 << 23) | OPC_MSA_3R_12, - OPC_DPADD_S_df =3D (0x2 << 23) | OPC_MSA_3R_13, - OPC_PCKEV_df =3D (0x2 << 23) | OPC_MSA_3R_14, - OPC_SRLR_df =3D (0x2 << 23) | OPC_MSA_3R_15, - OPC_BCLR_df =3D (0x3 << 23) | OPC_MSA_3R_0D, - OPC_MAX_U_df =3D (0x3 << 23) | OPC_MSA_3R_0E, - OPC_CLT_U_df =3D (0x3 << 23) | OPC_MSA_3R_0F, - OPC_ADDS_U_df =3D (0x3 << 23) | OPC_MSA_3R_10, - OPC_SUBSUU_S_df =3D (0x3 << 23) | OPC_MSA_3R_11, - OPC_DPADD_U_df =3D (0x3 << 23) | OPC_MSA_3R_13, - OPC_PCKOD_df =3D (0x3 << 23) | OPC_MSA_3R_14, - OPC_BSET_df =3D (0x4 << 23) | OPC_MSA_3R_0D, - OPC_MIN_S_df =3D (0x4 << 23) | OPC_MSA_3R_0E, - OPC_CLE_S_df =3D (0x4 << 23) | OPC_MSA_3R_0F, - OPC_AVE_S_df =3D (0x4 << 23) | OPC_MSA_3R_10, - OPC_ASUB_S_df =3D (0x4 << 23) | OPC_MSA_3R_11, - OPC_DIV_S_df =3D (0x4 << 23) | OPC_MSA_3R_12, - OPC_DPSUB_S_df =3D (0x4 << 23) | OPC_MSA_3R_13, - OPC_ILVL_df =3D (0x4 << 23) | OPC_MSA_3R_14, - OPC_HADD_S_df =3D (0x4 << 23) | OPC_MSA_3R_15, - OPC_BNEG_df =3D (0x5 << 23) | OPC_MSA_3R_0D, - OPC_MIN_U_df =3D (0x5 << 23) | OPC_MSA_3R_0E, - OPC_CLE_U_df =3D (0x5 << 23) | OPC_MSA_3R_0F, - OPC_AVE_U_df =3D (0x5 << 23) | OPC_MSA_3R_10, - OPC_ASUB_U_df =3D (0x5 << 23) | OPC_MSA_3R_11, - OPC_DIV_U_df =3D (0x5 << 23) | OPC_MSA_3R_12, - OPC_DPSUB_U_df =3D (0x5 << 23) | OPC_MSA_3R_13, - OPC_ILVR_df =3D (0x5 << 23) | OPC_MSA_3R_14, - OPC_HADD_U_df =3D (0x5 << 23) | OPC_MSA_3R_15, - OPC_BINSL_df =3D (0x6 << 23) | OPC_MSA_3R_0D, - OPC_MAX_A_df =3D (0x6 << 23) | OPC_MSA_3R_0E, - OPC_AVER_S_df =3D (0x6 << 23) | OPC_MSA_3R_10, - OPC_MOD_S_df =3D (0x6 << 23) | OPC_MSA_3R_12, - OPC_ILVEV_df =3D (0x6 << 23) | OPC_MSA_3R_14, - OPC_HSUB_S_df =3D (0x6 << 23) | OPC_MSA_3R_15, - OPC_BINSR_df =3D (0x7 << 23) | OPC_MSA_3R_0D, - OPC_MIN_A_df =3D (0x7 << 23) | OPC_MSA_3R_0E, - OPC_AVER_U_df =3D (0x7 << 23) | OPC_MSA_3R_10, - OPC_MOD_U_df =3D (0x7 << 23) | OPC_MSA_3R_12, - OPC_ILVOD_df =3D (0x7 << 23) | OPC_MSA_3R_14, - OPC_HSUB_U_df =3D (0x7 << 23) | OPC_MSA_3R_15, - - /* ELM instructions df(bits 21..16) =3D _b, _h, _w, _d */ - OPC_SLDI_df =3D (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM, - OPC_CTCMSA =3D (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM, - OPC_SPLATI_df =3D (0x1 << 22) | (0x00 << 16) | OPC_MSA_ELM, - OPC_CFCMSA =3D (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM, - OPC_COPY_S_df =3D (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM, - OPC_MOVE_V =3D (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM, - OPC_COPY_U_df =3D (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM, - OPC_INSERT_df =3D (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM, - OPC_INSVE_df =3D (0x5 << 22) | (0x00 << 16) | OPC_MSA_ELM, - - /* 3RF instruction _df(bit 21) =3D _w, _d */ - OPC_FCAF_df =3D (0x0 << 22) | OPC_MSA_3RF_1A, - OPC_FADD_df =3D (0x0 << 22) | OPC_MSA_3RF_1B, - OPC_FCUN_df =3D (0x1 << 22) | OPC_MSA_3RF_1A, - OPC_FSUB_df =3D (0x1 << 22) | OPC_MSA_3RF_1B, - OPC_FCOR_df =3D (0x1 << 22) | OPC_MSA_3RF_1C, - OPC_FCEQ_df =3D (0x2 << 22) | OPC_MSA_3RF_1A, - OPC_FMUL_df =3D (0x2 << 22) | OPC_MSA_3RF_1B, - OPC_FCUNE_df =3D (0x2 << 22) | OPC_MSA_3RF_1C, - OPC_FCUEQ_df =3D (0x3 << 22) | OPC_MSA_3RF_1A, - OPC_FDIV_df =3D (0x3 << 22) | OPC_MSA_3RF_1B, - OPC_FCNE_df =3D (0x3 << 22) | OPC_MSA_3RF_1C, - OPC_FCLT_df =3D (0x4 << 22) | OPC_MSA_3RF_1A, - OPC_FMADD_df =3D (0x4 << 22) | OPC_MSA_3RF_1B, - OPC_MUL_Q_df =3D (0x4 << 22) | OPC_MSA_3RF_1C, - OPC_FCULT_df =3D (0x5 << 22) | OPC_MSA_3RF_1A, - OPC_FMSUB_df =3D (0x5 << 22) | OPC_MSA_3RF_1B, - OPC_MADD_Q_df =3D (0x5 << 22) | OPC_MSA_3RF_1C, - OPC_FCLE_df =3D (0x6 << 22) | OPC_MSA_3RF_1A, - OPC_MSUB_Q_df =3D (0x6 << 22) | OPC_MSA_3RF_1C, - OPC_FCULE_df =3D (0x7 << 22) | OPC_MSA_3RF_1A, - OPC_FEXP2_df =3D (0x7 << 22) | OPC_MSA_3RF_1B, - OPC_FSAF_df =3D (0x8 << 22) | OPC_MSA_3RF_1A, - OPC_FEXDO_df =3D (0x8 << 22) | OPC_MSA_3RF_1B, - OPC_FSUN_df =3D (0x9 << 22) | OPC_MSA_3RF_1A, - OPC_FSOR_df =3D (0x9 << 22) | OPC_MSA_3RF_1C, - OPC_FSEQ_df =3D (0xA << 22) | OPC_MSA_3RF_1A, - OPC_FTQ_df =3D (0xA << 22) | OPC_MSA_3RF_1B, - OPC_FSUNE_df =3D (0xA << 22) | OPC_MSA_3RF_1C, - OPC_FSUEQ_df =3D (0xB << 22) | OPC_MSA_3RF_1A, - OPC_FSNE_df =3D (0xB << 22) | OPC_MSA_3RF_1C, - OPC_FSLT_df =3D (0xC << 22) | OPC_MSA_3RF_1A, - OPC_FMIN_df =3D (0xC << 22) | OPC_MSA_3RF_1B, - OPC_MULR_Q_df =3D (0xC << 22) | OPC_MSA_3RF_1C, - OPC_FSULT_df =3D (0xD << 22) | OPC_MSA_3RF_1A, - OPC_FMIN_A_df =3D (0xD << 22) | OPC_MSA_3RF_1B, - OPC_MADDR_Q_df =3D (0xD << 22) | OPC_MSA_3RF_1C, - OPC_FSLE_df =3D (0xE << 22) | OPC_MSA_3RF_1A, - OPC_FMAX_df =3D (0xE << 22) | OPC_MSA_3RF_1B, - OPC_MSUBR_Q_df =3D (0xE << 22) | OPC_MSA_3RF_1C, - OPC_FSULE_df =3D (0xF << 22) | OPC_MSA_3RF_1A, - OPC_FMAX_A_df =3D (0xF << 22) | OPC_MSA_3RF_1B, - - /* BIT instruction df(bits 22..16) =3D _B _H _W _D */ - OPC_SLLI_df =3D (0x0 << 23) | OPC_MSA_BIT_09, - OPC_SAT_S_df =3D (0x0 << 23) | OPC_MSA_BIT_0A, - OPC_SRAI_df =3D (0x1 << 23) | OPC_MSA_BIT_09, - OPC_SAT_U_df =3D (0x1 << 23) | OPC_MSA_BIT_0A, - OPC_SRLI_df =3D (0x2 << 23) | OPC_MSA_BIT_09, - OPC_SRARI_df =3D (0x2 << 23) | OPC_MSA_BIT_0A, - OPC_BCLRI_df =3D (0x3 << 23) | OPC_MSA_BIT_09, - OPC_SRLRI_df =3D (0x3 << 23) | OPC_MSA_BIT_0A, - OPC_BSETI_df =3D (0x4 << 23) | OPC_MSA_BIT_09, - OPC_BNEGI_df =3D (0x5 << 23) | OPC_MSA_BIT_09, - OPC_BINSLI_df =3D (0x6 << 23) | OPC_MSA_BIT_09, - OPC_BINSRI_df =3D (0x7 << 23) | OPC_MSA_BIT_09, -}; - - /* * * AN OVERVIEW OF MXU EXTENSION INSTRUCTION SET @@ -2430,7 +2196,6 @@ static TCGv cpu_lladdr, cpu_llval; static TCGv_i32 hflags; TCGv_i32 fpu_fcr0, fpu_fcr31; TCGv_i64 fpu_f64[32]; -static TCGv_i64 msa_wr_d[64]; =20 #if defined(TARGET_MIPS64) /* Upper halves of R5900's 128-bit registers: MMRs (multimedia registers) = */ @@ -2512,25 +2277,6 @@ static const char * const fregnames[] =3D { "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", }; =20 -static const char * const msaregnames[] =3D { - "w0.d0", "w0.d1", "w1.d0", "w1.d1", - "w2.d0", "w2.d1", "w3.d0", "w3.d1", - "w4.d0", "w4.d1", "w5.d0", "w5.d1", - "w6.d0", "w6.d1", "w7.d0", "w7.d1", - "w8.d0", "w8.d1", "w9.d0", "w9.d1", - "w10.d0", "w10.d1", "w11.d0", "w11.d1", - "w12.d0", "w12.d1", "w13.d0", "w13.d1", - "w14.d0", "w14.d1", "w15.d0", "w15.d1", - "w16.d0", "w16.d1", "w17.d0", "w17.d1", - "w18.d0", "w18.d1", "w19.d0", "w19.d1", - "w20.d0", "w20.d1", "w21.d0", "w21.d1", - "w22.d0", "w22.d1", "w23.d0", "w23.d1", - "w24.d0", "w24.d1", "w25.d0", "w25.d1", - "w26.d0", "w26.d1", "w27.d0", "w27.d1", - "w28.d0", "w28.d1", "w29.d0", "w29.d1", - "w30.d0", "w30.d1", "w31.d0", "w31.d1", -}; - #if !defined(TARGET_MIPS64) static const char * const mxuregnames[] =3D { "XR1", "XR2", "XR3", "XR4", "XR5", "XR6", "XR7", "XR8", @@ -28566,1983 +28312,6 @@ static void decode_opc_special3(CPUMIPSState *en= v, DisasContext *ctx) } } =20 -/* MIPS SIMD Architecture (MSA) */ -static inline int check_msa_access(DisasContext *ctx) -{ - if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) && - !(ctx->hflags & MIPS_HFLAG_F64))) { - generate_exception_end(ctx, EXCP_RI); - return 0; - } - - if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) { - generate_exception_end(ctx, EXCP_MSADIS); - return 0; - } - return 1; -} - -static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt) -{ - /* generates tcg ops to check if any element is 0 */ - /* Note this function only works with MSA_WRLEN =3D 128 */ - uint64_t eval_zero_or_big =3D 0; - uint64_t eval_big =3D 0; - TCGv_i64 t0 =3D tcg_temp_new_i64(); - TCGv_i64 t1 =3D tcg_temp_new_i64(); - switch (df) { - case DF_BYTE: - eval_zero_or_big =3D 0x0101010101010101ULL; - eval_big =3D 0x8080808080808080ULL; - break; - case DF_HALF: - eval_zero_or_big =3D 0x0001000100010001ULL; - eval_big =3D 0x8000800080008000ULL; - break; - case DF_WORD: - eval_zero_or_big =3D 0x0000000100000001ULL; - eval_big =3D 0x8000000080000000ULL; - break; - case DF_DOUBLE: - eval_zero_or_big =3D 0x0000000000000001ULL; - eval_big =3D 0x8000000000000000ULL; - break; - } - tcg_gen_subi_i64(t0, msa_wr_d[wt << 1], eval_zero_or_big); - tcg_gen_andc_i64(t0, t0, msa_wr_d[wt << 1]); - tcg_gen_andi_i64(t0, t0, eval_big); - tcg_gen_subi_i64(t1, msa_wr_d[(wt << 1) + 1], eval_zero_or_big); - tcg_gen_andc_i64(t1, t1, msa_wr_d[(wt << 1) + 1]); - tcg_gen_andi_i64(t1, t1, eval_big); - tcg_gen_or_i64(t0, t0, t1); - /* if all bits are zero then all elements are not zero */ - /* if some bit is non-zero then some element is zero */ - tcg_gen_setcondi_i64(TCG_COND_NE, t0, t0, 0); - tcg_gen_trunc_i64_tl(tresult, t0); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); -} - -static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond) -{ - TCGv_i64 t0; - - check_msa_access(ctx); - - if (ctx->hflags & MIPS_HFLAG_BMASK) { - generate_exception_end(ctx, EXCP_RI); - return true; - } - t0 =3D tcg_temp_new_i64(); - tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]); - tcg_gen_setcondi_i64(cond, t0, t0, 0); - tcg_gen_trunc_i64_tl(bcond, t0); - tcg_temp_free_i64(t0); - - ctx->btarget =3D ctx->base.pc_next + (s16 << 2) + 4; - - ctx->hflags |=3D MIPS_HFLAG_BC; - ctx->hflags |=3D MIPS_HFLAG_BDS32; - - return true; -} - -static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool i= f_not) -{ - check_msa_access(ctx); - - if (ctx->hflags & MIPS_HFLAG_BMASK) { - generate_exception_end(ctx, EXCP_RI); - return true; - } - - gen_check_zero_element(bcond, df, wt); - if (if_not) { - tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0); - } - - ctx->btarget =3D ctx->base.pc_next + (s16 << 2) + 4; - ctx->hflags |=3D MIPS_HFLAG_BC; - ctx->hflags |=3D MIPS_HFLAG_BDS32; - - return true; -} - -void gen_msa_branch(DisasContext *ctx, uint32_t op1) -{ - uint8_t df =3D (ctx->opcode >> 21) & 0x3; - uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; - int64_t s16 =3D (int16_t)ctx->opcode; - - switch (op1) { - case OPC_BZ_V: - case OPC_BNZ_V: - gen_msa_BxZ_V(ctx, wt, s16, (op1 =3D=3D OPC_BZ_V) ? - TCG_COND_EQ : TCG_COND_NE); - break; - case OPC_BZ_B: - case OPC_BZ_H: - case OPC_BZ_W: - case OPC_BZ_D: - gen_msa_BxZ(ctx, df, wt, s16, false); - break; - case OPC_BNZ_B: - case OPC_BNZ_H: - case OPC_BNZ_W: - case OPC_BNZ_D: - gen_msa_BxZ(ctx, df, wt, s16, true); - break; - } -} - -static void gen_msa_i8(DisasContext *ctx) -{ -#define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24))) - uint8_t i8 =3D (ctx->opcode >> 16) & 0xff; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 ti8 =3D tcg_const_i32(i8); - - switch (MASK_MSA_I8(ctx->opcode)) { - case OPC_ANDI_B: - gen_helper_msa_andi_b(cpu_env, twd, tws, ti8); - break; - case OPC_ORI_B: - gen_helper_msa_ori_b(cpu_env, twd, tws, ti8); - break; - case OPC_NORI_B: - gen_helper_msa_nori_b(cpu_env, twd, tws, ti8); - break; - case OPC_XORI_B: - gen_helper_msa_xori_b(cpu_env, twd, tws, ti8); - break; - case OPC_BMNZI_B: - gen_helper_msa_bmnzi_b(cpu_env, twd, tws, ti8); - break; - case OPC_BMZI_B: - gen_helper_msa_bmzi_b(cpu_env, twd, tws, ti8); - break; - case OPC_BSELI_B: - gen_helper_msa_bseli_b(cpu_env, twd, tws, ti8); - break; - case OPC_SHF_B: - case OPC_SHF_H: - case OPC_SHF_W: - { - uint8_t df =3D (ctx->opcode >> 24) & 0x3; - if (df =3D=3D DF_DOUBLE) { - generate_exception_end(ctx, EXCP_RI); - } else { - TCGv_i32 tdf =3D tcg_const_i32(df); - gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, ti8); - tcg_temp_free_i32(tdf); - } - } - break; - default: - MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); - break; - } - - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(ti8); -} - -static void gen_msa_i5(DisasContext *ctx) -{ -#define MASK_MSA_I5(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) - uint8_t df =3D (ctx->opcode >> 21) & 0x3; - int8_t s5 =3D (int8_t) sextract32(ctx->opcode, 16, 5); - uint8_t u5 =3D (ctx->opcode >> 16) & 0x1f; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - - TCGv_i32 tdf =3D tcg_const_i32(df); - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 timm =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(timm, u5); - - switch (MASK_MSA_I5(ctx->opcode)) { - case OPC_ADDVI_df: - gen_helper_msa_addvi_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_SUBVI_df: - gen_helper_msa_subvi_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_MAXI_S_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_maxi_s_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_MAXI_U_df: - gen_helper_msa_maxi_u_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_MINI_S_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_mini_s_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_MINI_U_df: - gen_helper_msa_mini_u_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CEQI_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_ceqi_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CLTI_S_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_clti_s_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CLTI_U_df: - gen_helper_msa_clti_u_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CLEI_S_df: - tcg_gen_movi_i32(timm, s5); - gen_helper_msa_clei_s_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_CLEI_U_df: - gen_helper_msa_clei_u_df(cpu_env, tdf, twd, tws, timm); - break; - case OPC_LDI_df: - { - int32_t s10 =3D sextract32(ctx->opcode, 11, 10); - tcg_gen_movi_i32(timm, s10); - gen_helper_msa_ldi_df(cpu_env, tdf, twd, timm); - } - break; - default: - MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); - break; - } - - tcg_temp_free_i32(tdf); - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(timm); -} - -static void gen_msa_bit(DisasContext *ctx) -{ -#define MASK_MSA_BIT(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) - uint8_t dfm =3D (ctx->opcode >> 16) & 0x7f; - uint32_t df =3D 0, m =3D 0; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - - TCGv_i32 tdf; - TCGv_i32 tm; - TCGv_i32 twd; - TCGv_i32 tws; - - if ((dfm & 0x40) =3D=3D 0x00) { - m =3D dfm & 0x3f; - df =3D DF_DOUBLE; - } else if ((dfm & 0x60) =3D=3D 0x40) { - m =3D dfm & 0x1f; - df =3D DF_WORD; - } else if ((dfm & 0x70) =3D=3D 0x60) { - m =3D dfm & 0x0f; - df =3D DF_HALF; - } else if ((dfm & 0x78) =3D=3D 0x70) { - m =3D dfm & 0x7; - df =3D DF_BYTE; - } else { - generate_exception_end(ctx, EXCP_RI); - return; - } - - tdf =3D tcg_const_i32(df); - tm =3D tcg_const_i32(m); - twd =3D tcg_const_i32(wd); - tws =3D tcg_const_i32(ws); - - switch (MASK_MSA_BIT(ctx->opcode)) { - case OPC_SLLI_df: - gen_helper_msa_slli_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SRAI_df: - gen_helper_msa_srai_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SRLI_df: - gen_helper_msa_srli_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BCLRI_df: - gen_helper_msa_bclri_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BSETI_df: - gen_helper_msa_bseti_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BNEGI_df: - gen_helper_msa_bnegi_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BINSLI_df: - gen_helper_msa_binsli_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_BINSRI_df: - gen_helper_msa_binsri_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SAT_S_df: - gen_helper_msa_sat_s_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SAT_U_df: - gen_helper_msa_sat_u_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SRARI_df: - gen_helper_msa_srari_df(cpu_env, tdf, twd, tws, tm); - break; - case OPC_SRLRI_df: - gen_helper_msa_srlri_df(cpu_env, tdf, twd, tws, tm); - break; - default: - MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); - break; - } - - tcg_temp_free_i32(tdf); - tcg_temp_free_i32(tm); - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); -} - -static void gen_msa_3r(DisasContext *ctx) -{ -#define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23))) - uint8_t df =3D (ctx->opcode >> 21) & 0x3; - uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - - TCGv_i32 tdf =3D tcg_const_i32(df); - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 twt =3D tcg_const_i32(wt); - - switch (MASK_MSA_3R(ctx->opcode)) { - case OPC_BINSL_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_binsl_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_binsl_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_binsl_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_binsl_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_BINSR_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_binsr_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_binsr_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_binsr_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_binsr_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_BCLR_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_bclr_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_bclr_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_bclr_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_bclr_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_BNEG_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_bneg_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_bneg_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_bneg_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_bneg_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_BSET_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_bset_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_bset_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_bset_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_bset_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ADD_A_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_add_a_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_add_a_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_add_a_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_add_a_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ADDS_A_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_adds_a_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_adds_a_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_adds_a_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_adds_a_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ADDS_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_adds_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_adds_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_adds_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_adds_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ADDS_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_adds_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_adds_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_adds_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_adds_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ADDV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_addv_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_addv_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_addv_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_addv_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_AVE_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ave_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ave_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ave_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ave_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_AVE_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ave_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ave_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ave_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ave_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_AVER_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_aver_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_aver_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_aver_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_aver_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_AVER_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_aver_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_aver_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_aver_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_aver_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_CEQ_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ceq_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ceq_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ceq_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ceq_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_CLE_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_cle_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_cle_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_cle_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_cle_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_CLE_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_cle_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_cle_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_cle_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_cle_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_CLT_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_clt_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_clt_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_clt_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_clt_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_CLT_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_clt_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_clt_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_clt_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_clt_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DIV_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_div_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_div_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_div_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_div_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DIV_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_div_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_div_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_div_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_div_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MAX_A_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_max_a_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_max_a_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_max_a_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_max_a_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MAX_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_max_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_max_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_max_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_max_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MAX_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_max_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_max_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_max_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_max_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MIN_A_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_min_a_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_min_a_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_min_a_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_min_a_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MIN_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_min_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_min_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_min_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_min_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MIN_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_min_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_min_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_min_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_min_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MOD_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_mod_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_mod_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_mod_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_mod_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MOD_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_mod_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_mod_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_mod_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_mod_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MADDV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_maddv_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_maddv_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_maddv_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_maddv_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MSUBV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_msubv_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_msubv_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_msubv_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_msubv_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ASUB_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_asub_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_asub_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_asub_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_asub_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ASUB_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_asub_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_asub_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_asub_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_asub_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ILVEV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ilvev_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ilvev_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ilvev_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ilvev_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ILVOD_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ilvod_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ilvod_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ilvod_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ilvod_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ILVL_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ilvl_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ilvl_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ilvl_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ilvl_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_ILVR_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_ilvr_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_ilvr_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_ilvr_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_ilvr_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_PCKEV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_pckev_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_pckev_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_pckev_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_pckev_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_PCKOD_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_pckod_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_pckod_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_pckod_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_pckod_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SLL_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_sll_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_sll_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_sll_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_sll_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SRA_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_sra_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_sra_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_sra_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_sra_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SRAR_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_srar_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_srar_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_srar_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_srar_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SRL_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_srl_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_srl_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_srl_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_srl_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SRLR_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_srlr_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_srlr_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_srlr_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_srlr_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SUBS_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_subs_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_subs_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_subs_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_subs_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_MULV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_mulv_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_mulv_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_mulv_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_mulv_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SLD_df: - gen_helper_msa_sld_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_VSHF_df: - gen_helper_msa_vshf_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_SUBV_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_subv_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_subv_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_subv_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_subv_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SUBS_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_subs_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_subs_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_subs_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_subs_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SPLAT_df: - gen_helper_msa_splat_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_SUBSUS_U_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_subsus_u_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_subsus_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_subsus_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_subsus_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_SUBSUU_S_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_subsuu_s_b(cpu_env, twd, tws, twt); - break; - case DF_HALF: - gen_helper_msa_subsuu_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_subsuu_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_subsuu_s_d(cpu_env, twd, tws, twt); - break; - } - break; - - case OPC_DOTP_S_df: - case OPC_DOTP_U_df: - case OPC_DPADD_S_df: - case OPC_DPADD_U_df: - case OPC_DPSUB_S_df: - case OPC_HADD_S_df: - case OPC_DPSUB_U_df: - case OPC_HADD_U_df: - case OPC_HSUB_S_df: - case OPC_HSUB_U_df: - if (df =3D=3D DF_BYTE) { - generate_exception_end(ctx, EXCP_RI); - break; - } - switch (MASK_MSA_3R(ctx->opcode)) { - case OPC_HADD_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_hadd_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_hadd_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_hadd_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_HADD_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_hadd_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_hadd_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_hadd_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_HSUB_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_hsub_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_hsub_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_hsub_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_HSUB_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_hsub_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_hsub_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_hsub_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DOTP_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dotp_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dotp_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dotp_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DOTP_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dotp_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dotp_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dotp_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DPADD_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dpadd_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dpadd_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dpadd_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DPADD_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dpadd_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dpadd_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dpadd_u_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DPSUB_S_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dpsub_s_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dpsub_s_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dpsub_s_d(cpu_env, twd, tws, twt); - break; - } - break; - case OPC_DPSUB_U_df: - switch (df) { - case DF_HALF: - gen_helper_msa_dpsub_u_h(cpu_env, twd, tws, twt); - break; - case DF_WORD: - gen_helper_msa_dpsub_u_w(cpu_env, twd, tws, twt); - break; - case DF_DOUBLE: - gen_helper_msa_dpsub_u_d(cpu_env, twd, tws, twt); - break; - } - break; - } - break; - default: - MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); - break; - } - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(twt); - tcg_temp_free_i32(tdf); -} - -static void gen_msa_elm_3e(DisasContext *ctx) -{ -#define MASK_MSA_ELM_DF3E(op) (MASK_MSA_MINOR(op) | (op & (0x3FF << 16))) - uint8_t source =3D (ctx->opcode >> 11) & 0x1f; - uint8_t dest =3D (ctx->opcode >> 6) & 0x1f; - TCGv telm =3D tcg_temp_new(); - TCGv_i32 tsr =3D tcg_const_i32(source); - TCGv_i32 tdt =3D tcg_const_i32(dest); - - switch (MASK_MSA_ELM_DF3E(ctx->opcode)) { - case OPC_CTCMSA: - gen_load_gpr(telm, source); - gen_helper_msa_ctcmsa(cpu_env, telm, tdt); - break; - case OPC_CFCMSA: - gen_helper_msa_cfcmsa(telm, cpu_env, tsr); - gen_store_gpr(telm, dest); - break; - case OPC_MOVE_V: - gen_helper_msa_move_v(cpu_env, tdt, tsr); - break; - default: - MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); - break; - } - - tcg_temp_free(telm); - tcg_temp_free_i32(tdt); - tcg_temp_free_i32(tsr); -} - -static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n) -{ -#define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tn =3D tcg_const_i32(n); - TCGv_i32 tdf =3D tcg_const_i32(df); - - switch (MASK_MSA_ELM(ctx->opcode)) { - case OPC_SLDI_df: - gen_helper_msa_sldi_df(cpu_env, tdf, twd, tws, tn); - break; - case OPC_SPLATI_df: - gen_helper_msa_splati_df(cpu_env, tdf, twd, tws, tn); - break; - case OPC_INSVE_df: - gen_helper_msa_insve_df(cpu_env, tdf, twd, tws, tn); - break; - case OPC_COPY_S_df: - case OPC_COPY_U_df: - case OPC_INSERT_df: -#if !defined(TARGET_MIPS64) - /* Double format valid only for MIPS64 */ - if (df =3D=3D DF_DOUBLE) { - generate_exception_end(ctx, EXCP_RI); - break; - } - if ((MASK_MSA_ELM(ctx->opcode) =3D=3D OPC_COPY_U_df) && - (df =3D=3D DF_WORD)) { - generate_exception_end(ctx, EXCP_RI); - break; - } -#endif - switch (MASK_MSA_ELM(ctx->opcode)) { - case OPC_COPY_S_df: - if (likely(wd !=3D 0)) { - switch (df) { - case DF_BYTE: - gen_helper_msa_copy_s_b(cpu_env, twd, tws, tn); - break; - case DF_HALF: - gen_helper_msa_copy_s_h(cpu_env, twd, tws, tn); - break; - case DF_WORD: - gen_helper_msa_copy_s_w(cpu_env, twd, tws, tn); - break; -#if defined(TARGET_MIPS64) - case DF_DOUBLE: - gen_helper_msa_copy_s_d(cpu_env, twd, tws, tn); - break; -#endif - default: - assert(0); - } - } - break; - case OPC_COPY_U_df: - if (likely(wd !=3D 0)) { - switch (df) { - case DF_BYTE: - gen_helper_msa_copy_u_b(cpu_env, twd, tws, tn); - break; - case DF_HALF: - gen_helper_msa_copy_u_h(cpu_env, twd, tws, tn); - break; -#if defined(TARGET_MIPS64) - case DF_WORD: - gen_helper_msa_copy_u_w(cpu_env, twd, tws, tn); - break; -#endif - default: - assert(0); - } - } - break; - case OPC_INSERT_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_insert_b(cpu_env, twd, tws, tn); - break; - case DF_HALF: - gen_helper_msa_insert_h(cpu_env, twd, tws, tn); - break; - case DF_WORD: - gen_helper_msa_insert_w(cpu_env, twd, tws, tn); - break; -#if defined(TARGET_MIPS64) - case DF_DOUBLE: - gen_helper_msa_insert_d(cpu_env, twd, tws, tn); - break; -#endif - default: - assert(0); - } - break; - } - break; - default: - MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); - } - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(tn); - tcg_temp_free_i32(tdf); -} - -static void gen_msa_elm(DisasContext *ctx) -{ - uint8_t dfn =3D (ctx->opcode >> 16) & 0x3f; - uint32_t df =3D 0, n =3D 0; - - if ((dfn & 0x30) =3D=3D 0x00) { - n =3D dfn & 0x0f; - df =3D DF_BYTE; - } else if ((dfn & 0x38) =3D=3D 0x20) { - n =3D dfn & 0x07; - df =3D DF_HALF; - } else if ((dfn & 0x3c) =3D=3D 0x30) { - n =3D dfn & 0x03; - df =3D DF_WORD; - } else if ((dfn & 0x3e) =3D=3D 0x38) { - n =3D dfn & 0x01; - df =3D DF_DOUBLE; - } else if (dfn =3D=3D 0x3E) { - /* CTCMSA, CFCMSA, MOVE.V */ - gen_msa_elm_3e(ctx); - return; - } else { - generate_exception_end(ctx, EXCP_RI); - return; - } - - gen_msa_elm_df(ctx, df, n); -} - -static void gen_msa_3rf(DisasContext *ctx) -{ -#define MASK_MSA_3RF(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22))) - uint8_t df =3D (ctx->opcode >> 21) & 0x1; - uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 twt =3D tcg_const_i32(wt); - TCGv_i32 tdf =3D tcg_temp_new_i32(); - - /* adjust df value for floating-point instruction */ - tcg_gen_movi_i32(tdf, df + 2); - - switch (MASK_MSA_3RF(ctx->opcode)) { - case OPC_FCAF_df: - gen_helper_msa_fcaf_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FADD_df: - gen_helper_msa_fadd_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCUN_df: - gen_helper_msa_fcun_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSUB_df: - gen_helper_msa_fsub_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCOR_df: - gen_helper_msa_fcor_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCEQ_df: - gen_helper_msa_fceq_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMUL_df: - gen_helper_msa_fmul_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCUNE_df: - gen_helper_msa_fcune_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCUEQ_df: - gen_helper_msa_fcueq_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FDIV_df: - gen_helper_msa_fdiv_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCNE_df: - gen_helper_msa_fcne_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCLT_df: - gen_helper_msa_fclt_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMADD_df: - gen_helper_msa_fmadd_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_MUL_Q_df: - tcg_gen_movi_i32(tdf, df + 1); - gen_helper_msa_mul_q_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCULT_df: - gen_helper_msa_fcult_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMSUB_df: - gen_helper_msa_fmsub_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_MADD_Q_df: - tcg_gen_movi_i32(tdf, df + 1); - gen_helper_msa_madd_q_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCLE_df: - gen_helper_msa_fcle_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_MSUB_Q_df: - tcg_gen_movi_i32(tdf, df + 1); - gen_helper_msa_msub_q_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FCULE_df: - gen_helper_msa_fcule_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FEXP2_df: - gen_helper_msa_fexp2_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSAF_df: - gen_helper_msa_fsaf_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FEXDO_df: - gen_helper_msa_fexdo_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSUN_df: - gen_helper_msa_fsun_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSOR_df: - gen_helper_msa_fsor_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSEQ_df: - gen_helper_msa_fseq_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FTQ_df: - gen_helper_msa_ftq_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSUNE_df: - gen_helper_msa_fsune_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSUEQ_df: - gen_helper_msa_fsueq_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSNE_df: - gen_helper_msa_fsne_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSLT_df: - gen_helper_msa_fslt_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMIN_df: - gen_helper_msa_fmin_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_MULR_Q_df: - tcg_gen_movi_i32(tdf, df + 1); - gen_helper_msa_mulr_q_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSULT_df: - gen_helper_msa_fsult_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMIN_A_df: - gen_helper_msa_fmin_a_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_MADDR_Q_df: - tcg_gen_movi_i32(tdf, df + 1); - gen_helper_msa_maddr_q_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSLE_df: - gen_helper_msa_fsle_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMAX_df: - gen_helper_msa_fmax_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_MSUBR_Q_df: - tcg_gen_movi_i32(tdf, df + 1); - gen_helper_msa_msubr_q_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FSULE_df: - gen_helper_msa_fsule_df(cpu_env, tdf, twd, tws, twt); - break; - case OPC_FMAX_A_df: - gen_helper_msa_fmax_a_df(cpu_env, tdf, twd, tws, twt); - break; - default: - MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); - break; - } - - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(twt); - tcg_temp_free_i32(tdf); -} - -static void gen_msa_2r(DisasContext *ctx) -{ -#define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \ - (op & (0x7 << 18))) - uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - uint8_t df =3D (ctx->opcode >> 16) & 0x3; - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 twt =3D tcg_const_i32(wt); - TCGv_i32 tdf =3D tcg_const_i32(df); - - switch (MASK_MSA_2R(ctx->opcode)) { - case OPC_FILL_df: -#if !defined(TARGET_MIPS64) - /* Double format valid only for MIPS64 */ - if (df =3D=3D DF_DOUBLE) { - generate_exception_end(ctx, EXCP_RI); - break; - } -#endif - gen_helper_msa_fill_df(cpu_env, tdf, twd, tws); /* trs */ - break; - case OPC_NLOC_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_nloc_b(cpu_env, twd, tws); - break; - case DF_HALF: - gen_helper_msa_nloc_h(cpu_env, twd, tws); - break; - case DF_WORD: - gen_helper_msa_nloc_w(cpu_env, twd, tws); - break; - case DF_DOUBLE: - gen_helper_msa_nloc_d(cpu_env, twd, tws); - break; - } - break; - case OPC_NLZC_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_nlzc_b(cpu_env, twd, tws); - break; - case DF_HALF: - gen_helper_msa_nlzc_h(cpu_env, twd, tws); - break; - case DF_WORD: - gen_helper_msa_nlzc_w(cpu_env, twd, tws); - break; - case DF_DOUBLE: - gen_helper_msa_nlzc_d(cpu_env, twd, tws); - break; - } - break; - case OPC_PCNT_df: - switch (df) { - case DF_BYTE: - gen_helper_msa_pcnt_b(cpu_env, twd, tws); - break; - case DF_HALF: - gen_helper_msa_pcnt_h(cpu_env, twd, tws); - break; - case DF_WORD: - gen_helper_msa_pcnt_w(cpu_env, twd, tws); - break; - case DF_DOUBLE: - gen_helper_msa_pcnt_d(cpu_env, twd, tws); - break; - } - break; - default: - MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); - break; - } - - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(twt); - tcg_temp_free_i32(tdf); -} - -static void gen_msa_2rf(DisasContext *ctx) -{ -#define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \ - (op & (0xf << 17))) - uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - uint8_t df =3D (ctx->opcode >> 16) & 0x1; - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 twt =3D tcg_const_i32(wt); - /* adjust df value for floating-point instruction */ - TCGv_i32 tdf =3D tcg_const_i32(df + 2); - - switch (MASK_MSA_2RF(ctx->opcode)) { - case OPC_FCLASS_df: - gen_helper_msa_fclass_df(cpu_env, tdf, twd, tws); - break; - case OPC_FTRUNC_S_df: - gen_helper_msa_ftrunc_s_df(cpu_env, tdf, twd, tws); - break; - case OPC_FTRUNC_U_df: - gen_helper_msa_ftrunc_u_df(cpu_env, tdf, twd, tws); - break; - case OPC_FSQRT_df: - gen_helper_msa_fsqrt_df(cpu_env, tdf, twd, tws); - break; - case OPC_FRSQRT_df: - gen_helper_msa_frsqrt_df(cpu_env, tdf, twd, tws); - break; - case OPC_FRCP_df: - gen_helper_msa_frcp_df(cpu_env, tdf, twd, tws); - break; - case OPC_FRINT_df: - gen_helper_msa_frint_df(cpu_env, tdf, twd, tws); - break; - case OPC_FLOG2_df: - gen_helper_msa_flog2_df(cpu_env, tdf, twd, tws); - break; - case OPC_FEXUPL_df: - gen_helper_msa_fexupl_df(cpu_env, tdf, twd, tws); - break; - case OPC_FEXUPR_df: - gen_helper_msa_fexupr_df(cpu_env, tdf, twd, tws); - break; - case OPC_FFQL_df: - gen_helper_msa_ffql_df(cpu_env, tdf, twd, tws); - break; - case OPC_FFQR_df: - gen_helper_msa_ffqr_df(cpu_env, tdf, twd, tws); - break; - case OPC_FTINT_S_df: - gen_helper_msa_ftint_s_df(cpu_env, tdf, twd, tws); - break; - case OPC_FTINT_U_df: - gen_helper_msa_ftint_u_df(cpu_env, tdf, twd, tws); - break; - case OPC_FFINT_S_df: - gen_helper_msa_ffint_s_df(cpu_env, tdf, twd, tws); - break; - case OPC_FFINT_U_df: - gen_helper_msa_ffint_u_df(cpu_env, tdf, twd, tws); - break; - } - - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(twt); - tcg_temp_free_i32(tdf); -} - -static void gen_msa_vec_v(DisasContext *ctx) -{ -#define MASK_MSA_VEC(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21))) - uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; - uint8_t ws =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv_i32 tws =3D tcg_const_i32(ws); - TCGv_i32 twt =3D tcg_const_i32(wt); - - switch (MASK_MSA_VEC(ctx->opcode)) { - case OPC_AND_V: - gen_helper_msa_and_v(cpu_env, twd, tws, twt); - break; - case OPC_OR_V: - gen_helper_msa_or_v(cpu_env, twd, tws, twt); - break; - case OPC_NOR_V: - gen_helper_msa_nor_v(cpu_env, twd, tws, twt); - break; - case OPC_XOR_V: - gen_helper_msa_xor_v(cpu_env, twd, tws, twt); - break; - case OPC_BMNZ_V: - gen_helper_msa_bmnz_v(cpu_env, twd, tws, twt); - break; - case OPC_BMZ_V: - gen_helper_msa_bmz_v(cpu_env, twd, tws, twt); - break; - case OPC_BSEL_V: - gen_helper_msa_bsel_v(cpu_env, twd, tws, twt); - break; - default: - MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); - break; - } - - tcg_temp_free_i32(twd); - tcg_temp_free_i32(tws); - tcg_temp_free_i32(twt); -} - -static void gen_msa_vec(DisasContext *ctx) -{ - switch (MASK_MSA_VEC(ctx->opcode)) { - case OPC_AND_V: - case OPC_OR_V: - case OPC_NOR_V: - case OPC_XOR_V: - case OPC_BMNZ_V: - case OPC_BMZ_V: - case OPC_BSEL_V: - gen_msa_vec_v(ctx); - break; - case OPC_MSA_2R: - gen_msa_2r(ctx); - break; - case OPC_MSA_2RF: - gen_msa_2rf(ctx); - break; - default: - MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); - break; - } -} - -void gen_msa(DisasContext *ctx) -{ - uint32_t opcode =3D ctx->opcode; - - check_msa_access(ctx); - - switch (MASK_MSA_MINOR(opcode)) { - case OPC_MSA_I8_00: - case OPC_MSA_I8_01: - case OPC_MSA_I8_02: - gen_msa_i8(ctx); - break; - case OPC_MSA_I5_06: - case OPC_MSA_I5_07: - gen_msa_i5(ctx); - break; - case OPC_MSA_BIT_09: - case OPC_MSA_BIT_0A: - gen_msa_bit(ctx); - break; - case OPC_MSA_3R_0D: - case OPC_MSA_3R_0E: - case OPC_MSA_3R_0F: - case OPC_MSA_3R_10: - case OPC_MSA_3R_11: - case OPC_MSA_3R_12: - case OPC_MSA_3R_13: - case OPC_MSA_3R_14: - case OPC_MSA_3R_15: - gen_msa_3r(ctx); - break; - case OPC_MSA_ELM: - gen_msa_elm(ctx); - break; - case OPC_MSA_3RF_1A: - case OPC_MSA_3RF_1B: - case OPC_MSA_3RF_1C: - gen_msa_3rf(ctx); - break; - case OPC_MSA_VEC: - gen_msa_vec(ctx); - break; - case OPC_LD_B: - case OPC_LD_H: - case OPC_LD_W: - case OPC_LD_D: - case OPC_ST_B: - case OPC_ST_H: - case OPC_ST_W: - case OPC_ST_D: - { - int32_t s10 =3D sextract32(ctx->opcode, 16, 10); - uint8_t rs =3D (ctx->opcode >> 11) & 0x1f; - uint8_t wd =3D (ctx->opcode >> 6) & 0x1f; - uint8_t df =3D (ctx->opcode >> 0) & 0x3; - - TCGv_i32 twd =3D tcg_const_i32(wd); - TCGv taddr =3D tcg_temp_new(); - gen_base_offset_addr(ctx, taddr, rs, s10 << df); - - switch (MASK_MSA_MINOR(opcode)) { - case OPC_LD_B: - gen_helper_msa_ld_b(cpu_env, twd, taddr); - break; - case OPC_LD_H: - gen_helper_msa_ld_h(cpu_env, twd, taddr); - break; - case OPC_LD_W: - gen_helper_msa_ld_w(cpu_env, twd, taddr); - break; - case OPC_LD_D: - gen_helper_msa_ld_d(cpu_env, twd, taddr); - break; - case OPC_ST_B: - gen_helper_msa_st_b(cpu_env, twd, taddr); - break; - case OPC_ST_H: - gen_helper_msa_st_h(cpu_env, twd, taddr); - break; - case OPC_ST_W: - gen_helper_msa_st_w(cpu_env, twd, taddr); - break; - case OPC_ST_D: - gen_helper_msa_st_d(cpu_env, twd, taddr); - break; - } - - tcg_temp_free_i32(twd); - tcg_temp_free(taddr); - } - break; - default: - MIPS_INVAL("MSA instruction"); - generate_exception_end(ctx, EXCP_RI); - break; - } - -} - static void decode_opc(CPUMIPSState *env, DisasContext *ctx) { int32_t offset; @@ -31577,24 +29346,6 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, in= t flags) } } =20 -static void msa_translate_init(void) -{ - int i; - - for (i =3D 0; i < 32; i++) { - int off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); - - /* - * The MSA vector registers are mapped on the - * scalar floating-point unit (FPU) registers. - */ - msa_wr_d[i * 2] =3D fpu_f64[i]; - off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); - msa_wr_d[i * 2 + 1] =3D - tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1= ]); - } -} - void mips_tcg_init(void) { int i; diff --git a/target/mips/meson.build b/target/mips/meson.build index 35dbbbf6519..b6697e2fd72 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -10,6 +10,7 @@ 'mod-msa_helper.c', =20 'translate.c', + 'mod-msa_translate.c', )) mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 --=20 2.26.2 From nobody Wed May 15 19:53:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.46 as permitted sender) client-ip=209.85.218.46; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-f46.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id ng1sm13094570ejb.112.2020.12.07.16.38.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 16:38:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=x3EHUPkL70HlyKVB+n5bDV2NTA2TeWYMrsf4zc9uRWc=; b=tazcftDdhrH5Siz3vGPCkHIw5jTrupE0v8r0/N+j1BdLFSfuGPwZv/t5NCx7BWXmaz pzqAgixJPmxmKf9xisHP3PHOVYHXU72hIJNxpETgpYFU+kjrnF0/Xcw21gnfSO2AlcWX dE7+Do5RAUfQ+AV0+rrFcbRV9J03t8+v+hNJLXuYQRDIYyMvJc2xuZW26u3SXHbWMge6 i3BXYrH7QweNGMhM0kdb6+3LL6flma+xWsugezogcadlwvWWs36zDyqvFj7EMUXRrK/3 xCbI6ZV6irdeZUJtjR36PHnr+waw8IW3QOGM9m7OezCK0TNFwgTw4pmtmGb/KVcSctUe nC4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=x3EHUPkL70HlyKVB+n5bDV2NTA2TeWYMrsf4zc9uRWc=; b=LH+38RxUxcf+T1oEMlP9WTIoGaEN6FmMUgyS7Q9BdUpIVeU/cFzL4IzWG8uNXB6sBu UR8MnD9XeUzE+s/rFRkWZoc8gjO4Yw0SMhmdfZ2aLE33Iu2FZll3mMki9qA1/W1DKIHd PwayjyZeAMgHGJIIe057BldmyrOEGV7EpUGuWENuaHU9TwNR3lQIAmWl91IsCDvwB5Xj zFaspcqusLJWoapCKG1S7T3HNbv1MlOkXfu2hcPh8Oh7buvbMORtWpkLoVj/5Ela5cmU E0xZrBG5dGz6MsssYvKFRhoEUN/BVyR5sqr2FD+SWPZW7SnkAEeOgbqyfR/l6r2DW/Z4 Aksg== X-Gm-Message-State: AOAM532YjuJ78ist+rvAfNdMe7weP8kv7vZbFJJdoKe7sUQ8DIDYG7ST QiOOghTw9hanbpRaBTUlBuA= X-Google-Smtp-Source: ABdhPJy9vmqIycYCXzmH4+3/R4YJU0CpD/y+Mx6BvObtS63jSrNwW1BfO7jCjPNhnnEx8gI4kz5l/w== X-Received: by 2002:a17:906:9acc:: with SMTP id ah12mr17761833ejc.386.1607387909940; Mon, 07 Dec 2020 16:38:29 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , kvm@vger.kernel.org, Richard Henderson , Aurelien Jarno , Huacai Chen , Jiaxun Yang Subject: [PATCH 16/17] target/mips: Introduce decode tree bindings for MSA opcodes Date: Tue, 8 Dec 2020 01:37:01 +0100 Message-Id: <20201208003702.4088927-17-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201208003702.4088927-1-f4bug@amsat.org> References: <20201208003702.4088927-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Introduce the 'mod-msa32' decodetree config for the 32-bit MSA ASE. We decode the branch instructions, and all instructions based on the MSA opcode. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Tested-by: Jiaxun Yang --- target/mips/translate.h | 1 + target/mips/mod-msa32.decode | 24 ++++++++++++++++++++++++ target/mips/mod-msa_translate.c | 31 +++++++++++++++++++++++++++++++ target/mips/meson.build | 5 +++++ 4 files changed, 61 insertions(+) create mode 100644 target/mips/mod-msa32.decode diff --git a/target/mips/translate.h b/target/mips/translate.h index c26b0d9155d..c4fe18d187e 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -84,5 +84,6 @@ extern TCGv bcond; void msa_translate_init(void); void gen_msa(DisasContext *ctx); void gen_msa_branch(DisasContext *ctx, uint32_t op1); +bool decode_msa32(DisasContext *ctx, uint32_t insn); =20 #endif diff --git a/target/mips/mod-msa32.decode b/target/mips/mod-msa32.decode new file mode 100644 index 00000000000..d69675132b8 --- /dev/null +++ b/target/mips/mod-msa32.decode @@ -0,0 +1,24 @@ +# MIPS SIMD Architecture Module instruction set +# +# Copyright (C) 2020 Philippe Mathieu-Daud=C3=A9 +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: +# MIPS Architecture for Programmers Volume IV-j +# The MIPS32 SIMD Architecture Module, Revision 1.12 +# (Document Number: MD00866-2B-MSA32-AFP-01.12) +# + +&msa_bz df wt s16 + +@bz ...... ... .. wt:5 s16:16 &msa_bz df=3D3 +@bz_df ...... ... df:2 wt:5 s16:16 &msa_bz + +BZ_V 010001 01011 ..... ................ @bz +BNZ_V 010001 01111 ..... ................ @bz + +BZ_x 010001 110 .. ..... ................ @bz_df +BNZ_x 010001 111 .. ..... ................ @bz_df + +MSA 011110 -------------------------- diff --git a/target/mips/mod-msa_translate.c b/target/mips/mod-msa_translat= e.c index 55c2a2f1acc..02df39c6b6c 100644 --- a/target/mips/mod-msa_translate.c +++ b/target/mips/mod-msa_translate.c @@ -6,6 +6,7 @@ * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support) + * Copyright (c) 2020 Philippe Mathieu-Daud=C3=A9 * * SPDX-License-Identifier: LGPL-2.1-or-later */ @@ -17,6 +18,9 @@ #include "fpu_helper.h" #include "internal.h" =20 +/* Include the auto-generated decoder. */ +#include "decode-mod-msa32.c.inc" + #define OPC_MSA (0x1E << 26) =20 #define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) @@ -370,6 +374,16 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, i= nt s16, TCGCond cond) return true; } =20 +static bool trans_BZ_V(DisasContext *ctx, arg_msa_bz *a) +{ + return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_EQ); +} + +static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a) +{ + return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_NE); +} + static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool i= f_not) { check_msa_access(ctx); @@ -391,6 +405,16 @@ static bool gen_msa_BxZ(DisasContext *ctx, int df, int= wt, int s16, bool if_not) return true; } =20 +static bool trans_BZ_x(DisasContext *ctx, arg_msa_bz *a) +{ + return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, false); +} + +static bool trans_BNZ_x(DisasContext *ctx, arg_msa_bz *a) +{ + return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, true); +} + void gen_msa_branch(DisasContext *ctx, uint32_t op1) { uint8_t df =3D (ctx->opcode >> 21) & 0x3; @@ -2264,3 +2288,10 @@ void gen_msa(DisasContext *ctx) break; } } + +static bool trans_MSA(DisasContext *ctx, arg_MSA *a) +{ + gen_msa(ctx); + + return true; +} diff --git a/target/mips/meson.build b/target/mips/meson.build index b6697e2fd72..7d0414bbe23 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -1,4 +1,9 @@ +gen =3D [ + decodetree.process('mod-msa32.decode', extra_args: [ '--decode=3Ddecode_= msa32' ]), +] + mips_ss =3D ss.source_set() +mips_ss.add(gen) mips_ss.add(files( 'cpu.c', 'dsp_helper.c', --=20 2.26.2 From nobody Wed May 15 19:53:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.45 as permitted sender) client-ip=209.85.208.45; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id m7sm14982163eds.73.2020.12.07.16.38.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 16:38:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yhtDu79kLkCSqrQu4hOw+lBuuGt6Ru0GYKXsoZSpo/I=; b=E3A+KzHWpFwxE2ZVxAKr94LVEDqj52B826uiFo1WaCCB/6VWFE+udsYXGu3Gjco/G4 uf5ex+XeSJ0UD2PL8Ma2pWMiwa4ncAr930QT5QTihRkylPQyjPHNxvLeFWuV6yurH/x2 KaKl543PEwwPgDtpO0ZZtsvB+t33Z4pGYiIQ9W9xlXAwTvqOGvbS9aNHnaYSIx/ox5K1 rdrHhjoVq4WSIK6u623eLV0M0m36R3ri9vdkFOacZQfXxVV41Ch8+hbDAXyIbHuP8PMm Ud9CFsUKGLmrHdBsIMqjUq1qPetViIP8vMmd/QmreebyXIg1HZNdCAkpAU6ElgoTIRMY v8yA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=yhtDu79kLkCSqrQu4hOw+lBuuGt6Ru0GYKXsoZSpo/I=; b=mYIlxi1XprSlb8PJV37MqV3NAEhi4NfryA5CQkBcWEUFgJFcU8PboUWgShRfJUKeGf F12F50VqEi0cZyANc11Cee/fQ5ZfmtX1e3H+HhhaUvH/QYBMvHrXJdGU6C2+KoBguNjS vxblMKMAN/Jyxi0IP+xr8W8xWud83WT9TzAYhMyTAwZ4bk5Bnc7yNtqLFf8ElWzvxNrr 2faxRZB+cU1R2HY01wU90P2McEVc+VVLLwELreFekAFD1aJDJSAxsO8eHpAf/RvNgVNl trfh3nIhRDXIr2XM4EGKZh+yiXbw4i64O+8Zy0o/kg8Q9mdeNFCX2Hta+BCfBRQMo3Wk FaeA== X-Gm-Message-State: AOAM533LxJe+h2Tj+trFKIBJuc0X3Np9ixqY5ZmyDsJq3xGxrAw6xJHw 6/DD4PmJR4kr0Qo2Pb5vR5s= X-Google-Smtp-Source: ABdhPJxcQpisrofx2fgZIGzL7itmsuUM7YtMSDh1aO50Iwk09j8weVmNtpVCfwyqPUmbRb2lDRL/gg== X-Received: by 2002:aa7:d41a:: with SMTP id z26mr22580039edq.267.1607387915136; Mon, 07 Dec 2020 16:38:35 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , kvm@vger.kernel.org, Richard Henderson , Aurelien Jarno , Huacai Chen , Jiaxun Yang Subject: [PATCH 17/17] target/mips: Use decode_msa32() generated from decodetree Date: Tue, 8 Dec 2020 01:37:02 +0100 Message-Id: <20201208003702.4088927-18-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201208003702.4088927-1-f4bug@amsat.org> References: <20201208003702.4088927-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Now that we can decode the MSA ASE opcodes with decode_msa32(), use it and remove the unreachable code. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Jiaxun Yang --- target/mips/fpu_translate.h | 10 ---------- target/mips/translate.h | 2 -- target/mips/mod-msa_translate.c | 29 +---------------------------- target/mips/translate.c | 31 ++++++++++--------------------- 4 files changed, 11 insertions(+), 61 deletions(-) diff --git a/target/mips/fpu_translate.h b/target/mips/fpu_translate.h index f45314d2ec2..58e5e768c99 100644 --- a/target/mips/fpu_translate.h +++ b/target/mips/fpu_translate.h @@ -42,8 +42,6 @@ enum { OPC_BC1 =3D (0x08 << 21) | OPC_CP1, /* bc */ OPC_BC1ANY2 =3D (0x09 << 21) | OPC_CP1, OPC_BC1ANY4 =3D (0x0A << 21) | OPC_CP1, - OPC_BZ_V =3D (0x0B << 21) | OPC_CP1, - OPC_BNZ_V =3D (0x0F << 21) | OPC_CP1, OPC_S_FMT =3D (FMT_S << 21) | OPC_CP1, OPC_D_FMT =3D (FMT_D << 21) | OPC_CP1, OPC_E_FMT =3D (FMT_E << 21) | OPC_CP1, @@ -53,14 +51,6 @@ enum { OPC_PS_FMT =3D (FMT_PS << 21) | OPC_CP1, OPC_BC1EQZ =3D (0x09 << 21) | OPC_CP1, OPC_BC1NEZ =3D (0x0D << 21) | OPC_CP1, - OPC_BZ_B =3D (0x18 << 21) | OPC_CP1, - OPC_BZ_H =3D (0x19 << 21) | OPC_CP1, - OPC_BZ_W =3D (0x1A << 21) | OPC_CP1, - OPC_BZ_D =3D (0x1B << 21) | OPC_CP1, - OPC_BNZ_B =3D (0x1C << 21) | OPC_CP1, - OPC_BNZ_H =3D (0x1D << 21) | OPC_CP1, - OPC_BNZ_W =3D (0x1E << 21) | OPC_CP1, - OPC_BNZ_D =3D (0x1F << 21) | OPC_CP1, }; =20 #define MASK_CP1_FUNC(op) (MASK_CP1(op) | (op & 0x3F)) diff --git a/target/mips/translate.h b/target/mips/translate.h index c4fe18d187e..cba28f49753 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -82,8 +82,6 @@ extern TCGv bcond; =20 /* MSA */ void msa_translate_init(void); -void gen_msa(DisasContext *ctx); -void gen_msa_branch(DisasContext *ctx, uint32_t op1); bool decode_msa32(DisasContext *ctx, uint32_t insn); =20 #endif diff --git a/target/mips/mod-msa_translate.c b/target/mips/mod-msa_translat= e.c index 02df39c6b6c..7e7fc0644ff 100644 --- a/target/mips/mod-msa_translate.c +++ b/target/mips/mod-msa_translate.c @@ -415,33 +415,6 @@ static bool trans_BNZ_x(DisasContext *ctx, arg_msa_bz = *a) return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, true); } =20 -void gen_msa_branch(DisasContext *ctx, uint32_t op1) -{ - uint8_t df =3D (ctx->opcode >> 21) & 0x3; - uint8_t wt =3D (ctx->opcode >> 16) & 0x1f; - int64_t s16 =3D (int16_t)ctx->opcode; - - switch (op1) { - case OPC_BZ_V: - case OPC_BNZ_V: - gen_msa_BxZ_V(ctx, wt, s16, (op1 =3D=3D OPC_BZ_V) ? - TCG_COND_EQ : TCG_COND_NE); - break; - case OPC_BZ_B: - case OPC_BZ_H: - case OPC_BZ_W: - case OPC_BZ_D: - gen_msa_BxZ(ctx, df, wt, s16, false); - break; - case OPC_BNZ_B: - case OPC_BNZ_H: - case OPC_BNZ_W: - case OPC_BNZ_D: - gen_msa_BxZ(ctx, df, wt, s16, true); - break; - } -} - static void gen_msa_i8(DisasContext *ctx) { #define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24))) @@ -2191,7 +2164,7 @@ static void gen_msa_vec(DisasContext *ctx) } } =20 -void gen_msa(DisasContext *ctx) +static void gen_msa(DisasContext *ctx) { uint32_t opcode =3D ctx->opcode; =20 diff --git a/target/mips/translate.c b/target/mips/translate.c index 5cd67459304..41c0b59a473 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -6,6 +6,7 @@ * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support) + * Copyright (c) 2020 Philippe Mathieu-Daud=C3=A9 * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public @@ -141,8 +142,6 @@ enum { OPC_JIALC =3D (0x3E << 26), /* MDMX ASE specific */ OPC_MDMX =3D (0x1E << 26), - /* MSA ASE, same as MDMX */ - OPC_MSA =3D OPC_MDMX, /* Cache and prefetch */ OPC_CACHE =3D (0x2F << 26), OPC_PREF =3D (0x33 << 26), @@ -28336,6 +28335,13 @@ static void decode_opc(CPUMIPSState *env, DisasCon= text *ctx) gen_set_label(l1); } =20 + /* Transition to the auto-generated decoder. */ + + /* ISA Extensions */ + if (ase_msa_available(env) && decode_msa32(ctx, ctx->opcode)) { + return; + } + op =3D MASK_OP_MAJOR(ctx->opcode); rs =3D (ctx->opcode >> 21) & 0x1f; rt =3D (ctx->opcode >> 16) & 0x1f; @@ -28853,20 +28859,6 @@ static void decode_opc(CPUMIPSState *env, DisasCon= text *ctx) } break; } - case OPC_BZ_V: - case OPC_BNZ_V: - case OPC_BZ_B: - case OPC_BZ_H: - case OPC_BZ_W: - case OPC_BZ_D: - case OPC_BNZ_B: - case OPC_BNZ_H: - case OPC_BNZ_W: - case OPC_BNZ_D: - if (ase_msa_available(env)) { - gen_msa_branch(ctx, op1); - break; - } default: MIPS_INVAL("cp1"); generate_exception_end(ctx, EXCP_RI); @@ -29048,16 +29040,13 @@ static void decode_opc(CPUMIPSState *env, DisasCo= ntext *ctx) gen_compute_branch(ctx, op, 4, rs, rt, offset, 4); } break; - case OPC_MSA: /* OPC_MDMX */ + case OPC_MDMX: /* MMI_OPC_LQ */ if (ctx->insn_flags & INSN_R5900) { #if defined(TARGET_MIPS64) - gen_mmi_lq(env, ctx); /* MMI_OPC_LQ */ + gen_mmi_lq(env, ctx); #endif } else { /* MDMX: Not implemented. */ - if (ase_msa_available(env)) { - gen_msa(ctx); - } } break; case OPC_PCREL: --=20 2.26.2