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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id i26sm5515613eja.23.2020.12.07.14.43.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 14:43:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tiLrE9BtsdFPhNtY2DXHquXLU9v+7Ir7R7907jubF5Q=; b=IajCAjRN/jprrEGLfFvDqV5o6cm8o+06y0erRBPFmpQfqxVdoYiGhN4xMB9PF/ySx9 Mhw9IUCxf6qZ4yeZ3tgJUeBZ3COO5HGu2MFCI9cRWzerKEUDRQoBk9PdnK9+gBkJ2Hy0 pppaZHlzjYlbWaE8TXBwUvtIoeD3f8iUsf/pNKwLEWQag3id1DPGLw02XNjxTZJTJmht fcunrfWgwRTxBnmT+VuzB2dR9UiXdXQXVCg8IFz/a0uWWuVOEgi14zdrqIoRuhNLVeNO 2+uATZK7qhkwMZwFOevrTpOhGloy7wwnbCYuZMeXPNyhldsAIhfS7qDlWEAxEGDsHTdB NnPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=tiLrE9BtsdFPhNtY2DXHquXLU9v+7Ir7R7907jubF5Q=; b=PRMvlEXoLe5NUoekN4XF/gMe0UnAjfNLJUToYsm2pEwoeyh+/kzHo3t+L99/C4/kSy o9l/AHhgRsQfcvDV08mo+UvF03HnqIDINrf307zJRc01gfRAI7bgTTwtbsTlfuKgPJV1 jbGetIhY/U3Qj9Chq3CVhezpyy6cEwMEiGnYfUFyOdfveTBxqDwM6ND3soFzqVwKo/06 zVXQjou/GhonoA/k2Q3exnZq7xwvcq7qjgBmdNVdL/9PNky38Or4UpX/bhUv3AqhA5Xk NKGyk2YlNokmospoHHyccclcrWKftLo9Q6eRxHEsDb4ECXowCQ6qY9cbqsS/njGvopVm yodQ== X-Gm-Message-State: AOAM530zzd2OiiQh2hgJT/aX5OmVe3leiDqNpjGofI3VD+hjiLXA5d/s TLpsFg2vqBAPkn/rBQ4H7DVV5k7soG0= X-Google-Smtp-Source: ABdhPJxbbper1U3Iq6tiWqLjM7IKdsW0rn1V1BWe4MMLSx5A1v38VSmc0TGSdivsjHX7a4HRkvEiBA== X-Received: by 2002:a50:8a44:: with SMTP id i62mr19173995edi.97.1607381039368; Mon, 07 Dec 2020 14:43:59 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Laurent Vivier , Aurelien Jarno , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Huacai Chen , Richard Henderson Subject: [PATCH v4 4/6] linux-user/elfload: Introduce MIPS GET_FEATURE_REG_EQU() macro Date: Mon, 7 Dec 2020 23:43:33 +0100 Message-Id: <20201207224335.4030582-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201207224335.4030582-1-f4bug@amsat.org> References: <20201207224335.4030582-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) ISA features are usually denoted in read-only bits from CPU registers. Add the GET_FEATURE_REG_EQU() macro which checks if a CPU register has bits set to a specific value. Use the macro to check the 'Architecture Revision' level of the Config0 register, which is '2' when the Release 6 ISA is implemented. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/cpu.h | 1 + linux-user/elfload.c | 12 +++++++++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 23f8c6f96cd..2639b0ea06c 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -844,6 +844,7 @@ struct CPUMIPSState { #define CP0C0_MT 7 /* 9..7 */ #define CP0C0_VI 3 #define CP0C0_K0 0 /* 2..0 */ +#define CP0C0_AR_LENGTH 3 int32_t CP0_Config1; #define CP0C1_M 31 #define CP0C1_MMU 25 /* 30..25 */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index b7c6d30723a..8f943f93ba7 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -7,6 +7,7 @@ =20 #include "qemu.h" #include "disas/disas.h" +#include "qemu/bitops.h" #include "qemu/path.h" #include "qemu/queue.h" #include "qemu/guest-random.h" @@ -995,17 +996,26 @@ enum { #define GET_FEATURE_REG_SET(_reg, _mask, _hwcap) \ do { if (cpu->env._reg & (_mask)) { hwcaps |=3D _hwcap; } } while (0) =20 +#define GET_FEATURE_REG_EQU(_reg, _start, _length, _val, _hwcap) \ + do { \ + if (extract32(cpu->env._reg, (_start), (_length)) =3D=3D (_val)) {= \ + hwcaps |=3D _hwcap; \ + } \ + } while (0) + static uint32_t get_elf_hwcap(void) { MIPSCPU *cpu =3D MIPS_CPU(thread_cpu); uint32_t hwcaps =3D 0; =20 - GET_FEATURE_INSN(ISA_MIPS32R6 | ISA_MIPS64R6, HWCAP_MIPS_R6); + GET_FEATURE_REG_EQU(CP0_Config0, CP0C0_AR, CP0C0_AR_LENGTH, + 2, HWCAP_MIPS_R6); GET_FEATURE_REG_SET(CP0_Config3, 1 << CP0C3_MSAP, HWCAP_MIPS_MSA); =20 return hwcaps; } =20 +#undef GET_FEATURE_REG_EQU #undef GET_FEATURE_REG_SET #undef GET_FEATURE_INSN =20 --=20 2.26.2