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[88.21.205.111]) by smtp.gmail.com with ESMTPSA id ng1sm3123587ejb.112.2020.12.04.14.26.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Dec 2020 14:26:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=F/yHM9sV3U4iOKbuGdiODvNyEhg16gBWDYuuHF5veyA=; b=PhGBhwcg3ofPOv6DTFo2X+ZUN0ufMzPe4hKyEclqi/chkjlMar0QpjeRMQO+hOTMXQ t2DsLBWcGNvJP+sbbUDKgXdDepAyHVBIt3aY7FYJmMSdeJLUhWSVj2OOkGfKYbAD5JLR eRFkSOrCu+vrLK671n7qsyIpbyAG9CZ3eSq+/Vwq0v6EI8h20VVZaN49UJS/Je+E38dT WokKLGcHFC4Cpqx6I8w6G/2eIM+uno9srmvMogmrFkaf8wh8yMvy1n0DgkknrN2ZzZyv VpPmxqOboLRa9+iuxyoNNLxBsm2WUyyZLF8iIZyEZb8Mzj1+6yEeP1NQaqdUmmS5nKKI wgjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=F/yHM9sV3U4iOKbuGdiODvNyEhg16gBWDYuuHF5veyA=; b=jlEMm1dsjkKPLMGJjZA1ii1ExBixubTjTIklhilKQoccCZu7HFqd5PNAtkLY1bDGO9 a16wWkA9OX8Kryzl90wox6tujCLhVtvidxAt8PcGgh3xvrZcLHXHB0CT3wbbkoWzu/CA 1c2f8adxPuq9XJ9ky1/YYVOZq69Cf2Vk4Jb+YODWmPkaqoYOyH659AwGnhs//00YO4qs j6JYzmZYT1dAZgIOvUuWEjiLbNhL4ipGToRB1L6UgewLu8TdRWvsmeMITgmQ9KdrRHgm fiqX22jkzqK7Oy3sWkqUP7US0iLSMvav8Fzk/HMDNT8aWAmzf4weR08UH7uzbzfOaW4F A7Ig== X-Gm-Message-State: AOAM533hD1JBqn7KbEn8Hb9VZBYgphOVK/RY2p6b0y2cSr3LWY7eHMl9 /PV9KKjrb3jWULTkmkRuI+NwGC59EI4= X-Google-Smtp-Source: ABdhPJy/1Dr9Q3mUc80fvxJoOQA59NnPMM6x7RqcK7vXA2G2GjPSSEPh4qIthtl1EockkCuvvmqvDw== X-Received: by 2002:a17:907:6e9:: with SMTP id yh9mr9135349ejb.131.1607120795708; Fri, 04 Dec 2020 14:26:35 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Jiaxun Yang , Huacai Chen , qemu-devel@nongnu.org Cc: Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno Subject: [PATCH 2/5] target/mips: Introduce ase_mt_available() helper Date: Fri, 4 Dec 2020 23:26:19 +0100 Message-Id: <20201204222622.2743175-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201204222622.2743175-1-f4bug@amsat.org> References: <20201204222622.2743175-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Instead of accessing CP0_Config3 directly and checking the 'Multi-Threading Present' bit, introduce an helper to simplify code review. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/cpu.h | 7 +++++++ hw/mips/cps.c | 3 +-- target/mips/cp0_helper.c | 2 +- target/mips/cpu.c | 2 +- target/mips/helper.c | 2 +- target/mips/translate.c | 2 +- 6 files changed, 12 insertions(+), 6 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 2639b0ea06c..82c60a34751 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1289,6 +1289,13 @@ int cpu_mips_signal_handler(int host_signum, void *p= info, void *puc); =20 bool cpu_supports_cps_smp(const char *cpu_type); bool cpu_supports_isa(const char *cpu_type, uint64_t isa); + +/* Check presence of multi-threading ASE implementation */ +static inline bool ase_mt_available(CPUMIPSState *env) +{ + return env->CP0_Config3 & (1 << CP0C3_MT); +} + void cpu_set_exception_base(int vp_index, target_ulong address); =20 /* mips_int.c */ diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 962b1b0b87c..7a0d289efaf 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -58,8 +58,7 @@ static void main_cpu_reset(void *opaque) =20 static bool cpu_mips_itu_supported(CPUMIPSState *env) { - bool is_mt =3D (env->CP0_Config5 & (1 << CP0C5_VP)) || - (env->CP0_Config3 & (1 << CP0C3_MT)); + bool is_mt =3D (env->CP0_Config5 & (1 << CP0C5_VP)) || ase_mt_availabl= e(env); =20 return is_mt && !kvm_enabled(); } diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c index caaaefcc8ad..9718c93d18c 100644 --- a/target/mips/cp0_helper.c +++ b/target/mips/cp0_helper.c @@ -1166,7 +1166,7 @@ void helper_mtc0_entryhi(CPUMIPSState *env, target_ul= ong arg1) old =3D env->CP0_EntryHi; val =3D (arg1 & mask) | (old & ~mask); env->CP0_EntryHi =3D val; - if (env->CP0_Config3 & (1 << CP0C3_MT)) { + if (ase_mt_available(env)) { sync_c0_entryhi(env, env->current_tc); } /* If the ASID changes, flush qemu's TLB. */ diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 76d50b00b42..c03e5acf5bc 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -74,7 +74,7 @@ static bool mips_cpu_has_work(CPUState *cs) } =20 /* MIPS-MT has the ability to halt the CPU. */ - if (env->CP0_Config3 & (1 << CP0C3_MT)) { + if (ase_mt_available(env)) { /* * The QEMU model will issue an _WAKE request whenever the CPUs * should be woken up. diff --git a/target/mips/helper.c b/target/mips/helper.c index cc46ea887e5..608fe1512a3 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -419,7 +419,7 @@ void cpu_mips_store_status(CPUMIPSState *env, target_ul= ong val) tlb_flush(env_cpu(env)); } #endif - if (env->CP0_Config3 & (1 << CP0C3_MT)) { + if (ase_mt_available(env)) { sync_c0_status(env, env, env->current_tc); } else { compute_hflags(env); diff --git a/target/mips/translate.c b/target/mips/translate.c index 0db032fc5fb..ee45dce9a50 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31921,7 +31921,7 @@ void cpu_state_reset(CPUMIPSState *env) =20 cpu_mips_store_count(env, 1); =20 - if (env->CP0_Config3 & (1 << CP0C3_MT)) { + if (ase_mt_available(env)) { int i; =20 /* Only TC0 on VPE 0 starts as active. */ --=20 2.26.2