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bh=ekVYCvjOoDZtty0c3QtIsTdzejAGQctlL5G19DBS6x0=; b=gFkRkgvth36Wn1tet8SKKoBqBO3o5EAAxDKlUCbgCQ5Lr0dxWndH4K5jLHd31fZaQEmV+O 59af7M5PP9ayyjJ36yWgU75jXZXcM57bbepYD76NYLFBCHyH4hie+8ikmZ1yej+GO6MV6d iowDTYsnkJM4CVHFIltOR8dGjAvd+nA= X-MC-Unique: pkVMpksmOEO4FcRIfaAcsg-1 From: Igor Mammedov To: qemu-devel@nongnu.org Subject: [PATCH 2/8] acpi: cpuhp: introduce 'firmware performs eject' status/control bits Date: Fri, 4 Dec 2020 12:09:33 -0500 Message-Id: <20201204170939.1815522-3-imammedo@redhat.com> In-Reply-To: <20201204170939.1815522-1-imammedo@redhat.com> References: <20201204170939.1815522-1-imammedo@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=imammedo@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=63.128.21.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.496, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lersek@redhat.com, ankur.a.arora@oracle.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Adds bit #4 to status/control field of CPU hotplug MMIO interface. New bit will be used OSPM to mark CPUs as pending for removal by firmware, when it calls _EJ0 method on CPU device node. Later on, when firmware sees this bit set, it will perform CPU eject which will clear bit #4 as well. Signed-off-by: Igor Mammedov --- v1: - rearrange status/control bits description (Laszlo) - add clear bit #4 on eject - drop toggling logic from bit #4, it can be only set by guest and clear as part of cpu eject - exclude boot CPU from remove request - add trace events for new bit --- include/hw/acpi/cpu.h | 1 + docs/specs/acpi_cpu_hotplug.txt | 19 ++++++++++++++----- hw/acpi/cpu.c | 9 +++++++++ hw/acpi/trace-events | 2 ++ 4 files changed, 26 insertions(+), 5 deletions(-) diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h index 0eeedaa491..d71edde456 100644 --- a/include/hw/acpi/cpu.h +++ b/include/hw/acpi/cpu.h @@ -22,6 +22,7 @@ typedef struct AcpiCpuStatus { uint64_t arch_id; bool is_inserting; bool is_removing; + bool fw_remove; uint32_t ost_event; uint32_t ost_status; } AcpiCpuStatus; diff --git a/docs/specs/acpi_cpu_hotplug.txt b/docs/specs/acpi_cpu_hotplug.= txt index 9bb22d1270..9bd59ae0da 100644 --- a/docs/specs/acpi_cpu_hotplug.txt +++ b/docs/specs/acpi_cpu_hotplug.txt @@ -56,8 +56,11 @@ read access: no device check event to OSPM was issued. It's valid only when bit 0 is set. 2: Device remove event, used to distinguish device for which - no device eject request to OSPM was issued. - 3-7: reserved and should be ignored by OSPM + no device eject request to OSPM was issued. Firmware must + ignore this bit. + 3: reserved and should be ignored by OSPM + 4: if set to 1, OSPM requests firmware to perform device eject. + 5-7: reserved and should be ignored by OSPM [0x5-0x7] reserved [0x8] Command data: (DWORD access) contains 0 unless value last stored in 'Command field' is one of: @@ -79,10 +82,16 @@ write access: selected CPU device 2: if set to 1 clears device remove event, set by OSPM after it has emitted device eject request for the - selected CPU device + selected CPU device. 3: if set to 1 initiates device eject, set by OSPM when it - triggers CPU device removal and calls _EJ0 method - 4-7: reserved, OSPM must clear them before writing to register + triggers CPU device removal and calls _EJ0 method or by fir= mware + when bit #4 is set. In case bit #4 were set, it's cleared as + part of device eject. + 4: if set to 1, OSPM hands over device eject to firmware. + Firmware shall issue device eject request as described above + (bit #3) and OSPM should not touch device eject bit (#3) in= case + it's asked firmware to perform CPU device eject. + 5-7: reserved, OSPM must clear them before writing to register [0x5] Command field: (1 byte access) value: 0: selects a CPU device with inserting/removing events and diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c index f099b50927..811218f673 100644 --- a/hw/acpi/cpu.c +++ b/hw/acpi/cpu.c @@ -71,6 +71,7 @@ static uint64_t cpu_hotplug_rd(void *opaque, hwaddr addr,= unsigned size) val |=3D cdev->cpu ? 1 : 0; val |=3D cdev->is_inserting ? 2 : 0; val |=3D cdev->is_removing ? 4 : 0; + val |=3D cdev->fw_remove ? 16 : 0; trace_cpuhp_acpi_read_flags(cpu_st->selector, val); break; case ACPI_CPU_CMD_DATA_OFFSET_RW: @@ -148,6 +149,14 @@ static void cpu_hotplug_wr(void *opaque, hwaddr addr, = uint64_t data, hotplug_ctrl =3D qdev_get_hotplug_handler(dev); hotplug_handler_unplug(hotplug_ctrl, dev, NULL); object_unparent(OBJECT(dev)); + cdev->fw_remove =3D false; + } else if (data & 16) { + if (!cdev->cpu || cdev->cpu =3D=3D first_cpu) { + trace_cpuhp_acpi_fw_remove_invalid_cpu(cpu_st->selector); + break; + } + trace_cpuhp_acpi_fw_remove_cpu(cpu_st->selector); + cdev->fw_remove =3D true; } break; case ACPI_CPU_CMD_OFFSET_WR: diff --git a/hw/acpi/trace-events b/hw/acpi/trace-events index afbc77de1c..f91ced477d 100644 --- a/hw/acpi/trace-events +++ b/hw/acpi/trace-events @@ -29,6 +29,8 @@ cpuhp_acpi_clear_inserting_evt(uint32_t idx) "idx[0x%"PRI= x32"]" cpuhp_acpi_clear_remove_evt(uint32_t idx) "idx[0x%"PRIx32"]" cpuhp_acpi_ejecting_invalid_cpu(uint32_t idx) "0x%"PRIx32 cpuhp_acpi_ejecting_cpu(uint32_t idx) "0x%"PRIx32 +cpuhp_acpi_fw_remove_invalid_cpu(uint32_t idx) "0x%"PRIx32 +cpuhp_acpi_fw_remove_cpu(uint32_t idx) "0x%"PRIx32 cpuhp_acpi_write_ost_ev(uint32_t slot, uint32_t ev) "idx[0x%"PRIx32"] OST = EVENT: 0x%"PRIx32 cpuhp_acpi_write_ost_status(uint32_t slot, uint32_t st) "idx[0x%"PRIx32"] = OST STATUS: 0x%"PRIx32 =20 --=20 2.27.0