From nobody Mon Feb 9 08:11:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1607018287; cv=none; d=zohomail.com; s=zohoarc; b=nKj7x55GBHLOYmE8sr7rW5BD/+lKfNKRDwsP3AYu9498IqphepaZCeuZOj019yaTIgLE7GTil27uh/e/yB5nnSJrwxCSJiyR5vXWhheGE8X5WOmcbC5bvI2deq4gMp0OOV7kXrx4WpLhzCxlZSOcQfPCt99ThG2Oh85VzbW3NeQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1607018287; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qQ12plZNbjdrqzCYsNpSa/yzgLRJWhC6MUBt7ifldOY=; b=AlU2LGzCz5x8LBBPvmXqQSZBeglyf8A/1Y//GKbkUazqV+AZy1LgPH+CkPtM/li1j0eAvw8NuOPt+BoGl/ZHRQACWKMxsSC70HRqZPXYst4zxbGCBSZ2pMabvYNzIMTSZklgZYrTLcD5iuhpeVeBvZkvAeD7uf4x+biuDOgukXc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1607018287164960.867704521027; Thu, 3 Dec 2020 09:58:07 -0800 (PST) Received: from localhost ([::1]:38400 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kksN0-00011o-Lo for importer@patchew.org; Thu, 03 Dec 2020 12:26:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53352) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kksDL-00088W-N5 for qemu-devel@nongnu.org; Thu, 03 Dec 2020 12:16:19 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:21749) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kksDA-0001Ku-UT for qemu-devel@nongnu.org; Thu, 03 Dec 2020 12:16:16 -0500 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-43-KX64d0q7N-GyIsvSrvdwkA-1; Thu, 03 Dec 2020 12:16:03 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 7785C107ACE4; Thu, 3 Dec 2020 17:16:02 +0000 (UTC) Received: from localhost.localdomain (unknown [10.35.206.228]) by smtp.corp.redhat.com (Postfix) with ESMTP id 12CBF5D6AC; Thu, 3 Dec 2020 17:15:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1607015768; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qQ12plZNbjdrqzCYsNpSa/yzgLRJWhC6MUBt7ifldOY=; b=dK6hay+OHvxqBVjCL178oM4L6YlfEXA2nECzOS16/c2tYrI/D/p7PvrrNYt7kKYyRUTmRH rr4ZiHjUVu/goKH/vrZkrv/wM6lZkpH4++5tCnwXlLIj8udoHsZc1Bo2cveeJUnDlvxPTd 12esGULmoYer1aAxAWhQ/jeWG6+SXNQ= X-MC-Unique: KX64d0q7N-GyIsvSrvdwkA-1 From: Maxim Levitsky To: qemu-devel@nongnu.org Subject: [PATCH v2 2/2] Implement support for precise TSC migration Date: Thu, 3 Dec 2020 19:15:46 +0200 Message-Id: <20201203171546.372686-3-mlevitsk@redhat.com> In-Reply-To: <20201203171546.372686-1-mlevitsk@redhat.com> References: <20201203171546.372686-1-mlevitsk@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.205.24.124; envelope-from=mlevitsk@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.495, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Cornelia Huck , Eduardo Habkost , kvm@vger.kernel.org, "Michael S. Tsirkin" , Marcelo Tosatti , Richard Henderson , Maxim Levitsky , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" To enable it, you need to set -accel kvm,x-precise-tsc=3Don, and have a kernel that supports this feature. Signed-off-by: Maxim Levitsky --- accel/kvm/kvm-all.c | 28 +++++++++ include/sysemu/kvm.h | 1 + target/i386/cpu.h | 1 + target/i386/kvm.c | 140 +++++++++++++++++++++++++++++++++--------- target/i386/machine.c | 19 ++++++ 5 files changed, 161 insertions(+), 28 deletions(-) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index baaa54249d..3829f2e7a3 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -104,6 +104,8 @@ struct KVMState OnOffAuto kernel_irqchip_split; bool sync_mmu; uint64_t manual_dirty_log_protect; + /* Use KVM_GET_TSC_PRECISE/KVM_SET_TSC_PRECISE to access IA32_TSC */ + bool precise_tsc; /* The man page (and posix) say ioctl numbers are signed int, but * they're not. Linux, glibc and *BSD all treat ioctl numbers as * unsigned, and treating them as signed here can break things */ @@ -3194,6 +3196,24 @@ bool kvm_kernel_irqchip_split(void) return kvm_state->kernel_irqchip_split =3D=3D ON_OFF_AUTO_ON; } =20 +bool kvm_has_precise_tsc(void) +{ + return kvm_state && kvm_state->precise_tsc; +} + +static void kvm_set_precise_tsc(Object *obj, + bool value, Error **errp G_GNUC_UNUSED) +{ + KVMState *s =3D KVM_STATE(obj); + s->precise_tsc =3D value; +} + +static bool kvm_get_precise_tsc(Object *obj, Error **errp G_GNUC_UNUSED) +{ + KVMState *s =3D KVM_STATE(obj); + return s->precise_tsc; +} + static void kvm_accel_instance_init(Object *obj) { KVMState *s =3D KVM_STATE(obj); @@ -3222,6 +3242,14 @@ static void kvm_accel_class_init(ObjectClass *oc, vo= id *data) NULL, NULL); object_class_property_set_description(oc, "kvm-shadow-mem", "KVM shadow MMU size"); + + object_class_property_add_bool(oc, "x-precise-tsc", + kvm_get_precise_tsc, + kvm_set_precise_tsc); + + object_class_property_set_description(oc, "x-precise-tsc", + "Use precise tsc kvm API"); + } =20 static const TypeInfo kvm_accel_type =3D { diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index bb5d5cf497..14eff2b1c9 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -519,6 +519,7 @@ void kvm_init_irq_routing(KVMState *s); bool kvm_kernel_irqchip_allowed(void); bool kvm_kernel_irqchip_required(void); bool kvm_kernel_irqchip_split(void); +bool kvm_has_precise_tsc(void); =20 /** * kvm_arch_irqchip_create: diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 88e8586f8f..d2230d9735 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1460,6 +1460,7 @@ typedef struct CPUX86State { uint64_t tsc_adjust; uint64_t tsc_deadline; uint64_t tsc_aux; + uint64_t tsc_ns_timestamp; =20 uint64_t xcr0; =20 diff --git a/target/i386/kvm.c b/target/i386/kvm.c index a2934dda02..4adb7d6246 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -121,7 +121,6 @@ static int has_xsave; static int has_xcrs; static int has_pit_state2; static int has_exception_payload; - static bool has_msr_mcg_ext_ctl; =20 static struct kvm_cpuid2 *cpuid_cache; @@ -196,31 +195,112 @@ static int kvm_get_tsc(CPUState *cs) { X86CPU *cpu =3D X86_CPU(cs); CPUX86State *env =3D &cpu->env; - struct { - struct kvm_msrs info; - struct kvm_msr_entry entries[1]; - } msr_data =3D {}; int ret; =20 if (env->tsc_valid) { return 0; } =20 - memset(&msr_data, 0, sizeof(msr_data)); - msr_data.info.nmsrs =3D 1; - msr_data.entries[0].index =3D MSR_IA32_TSC; - env->tsc_valid =3D !runstate_is_running(); + if (kvm_has_precise_tsc()) { + struct kvm_tsc_state tsc_state; =20 - ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data); - if (ret < 0) { - return ret; + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_TSC_STATE, &tsc_state); + if (ret < 0) { + return ret; + } + + env->tsc =3D tsc_state.tsc; + + if (tsc_state.flags & KVM_TSC_STATE_TIMESTAMP_VALID) { + env->tsc_ns_timestamp =3D tsc_state.nsec; + } + + if (tsc_state.flags & KVM_TSC_STATE_TSC_ADJUST_VALID) { + env->tsc_adjust =3D tsc_state.tsc_adjust; + } + + } else { + struct { + struct kvm_msrs info; + struct kvm_msr_entry entries[2]; + } msr_data =3D { + .info.nmsrs =3D 1, + .entries[0].index =3D MSR_IA32_TSC, + }; + + if (has_msr_tsc_adjust) { + msr_data.info.nmsrs++; + msr_data.entries[1].index =3D MSR_TSC_ADJUST; + } + + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data); + if (ret < 0) { + return ret; + } + + assert(ret =3D=3D msr_data.info.nmsrs); + env->tsc =3D msr_data.entries[0].data; + if (has_msr_tsc_adjust) { + env->tsc_adjust =3D msr_data.entries[1].data; + } } =20 - assert(ret =3D=3D 1); - env->tsc =3D msr_data.entries[0].data; + env->tsc_valid =3D !runstate_is_running(); return 0; } =20 +static int kvm_set_tsc(CPUState *cs) +{ + int ret; + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + + if (kvm_has_precise_tsc()) { + struct kvm_tsc_state tsc_state =3D { + .tsc =3D env->tsc, + }; + + if (env->tsc_ns_timestamp) { + tsc_state.nsec =3D env->tsc_ns_timestamp; + tsc_state.flags |=3D KVM_TSC_STATE_TIMESTAMP_VALID; + } + + if (has_msr_tsc_adjust) { + tsc_state.tsc_adjust =3D env->tsc_adjust; + tsc_state.flags |=3D KVM_TSC_STATE_TSC_ADJUST_VALID; + } + + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_SET_TSC_STATE, &tsc_state); + if (ret < 0) { + return ret; + } + + } else { + struct { + struct kvm_msrs info; + struct kvm_msr_entry entries[2]; + } msr_data =3D { + .info.nmsrs =3D 1, + .entries[0].index =3D MSR_IA32_TSC, + .entries[0].data =3D env->tsc, + }; + + if (has_msr_tsc_adjust) { + msr_data.info.nmsrs++; + msr_data.entries[1].index =3D MSR_TSC_ADJUST; + msr_data.entries[1].data =3D env->tsc_adjust; + } + + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data); + if (ret < 0) { + return ret; + } + + assert(ret =3D=3D msr_data.info.nmsrs); + } + return ret; +} + static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data a= rg) { kvm_get_tsc(cpu); @@ -1780,6 +1860,13 @@ int kvm_arch_init_vcpu(CPUState *cs) } } =20 + if (kvm_has_precise_tsc()) { + if (!kvm_check_extension(cs->kvm_state, KVM_CAP_PRECISE_TSC)) { + error_report("kvm: Precise TSC is not supported by the host's = KVM"); + return -ENOTSUP; + } + } + if (cpu->vmware_cpuid_freq /* Guests depend on 0x40000000 to detect this feature, so only exp= ose * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */ @@ -2756,9 +2843,6 @@ static int kvm_put_msrs(X86CPU *cpu, int level) if (has_msr_tsc_aux) { kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux); } - if (has_msr_tsc_adjust) { - kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust); - } if (has_msr_misc_enable) { kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, env->msr_ia32_misc_enable); @@ -2802,7 +2886,6 @@ static int kvm_put_msrs(X86CPU *cpu, int level) * for normal writeback. Limit them to reset or full state updates. */ if (level >=3D KVM_PUT_RESET_STATE) { - kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc); kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr); kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr); if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) { @@ -3142,9 +3225,6 @@ static int kvm_get_msrs(X86CPU *cpu) if (has_msr_tsc_aux) { kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0); } - if (has_msr_tsc_adjust) { - kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0); - } if (has_msr_tsc_deadline) { kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0); } @@ -3178,10 +3258,6 @@ static int kvm_get_msrs(X86CPU *cpu) if (has_msr_virt_ssbd) { kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0); } - if (!env->tsc_valid) { - kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0); - env->tsc_valid =3D !runstate_is_running(); - } =20 #ifdef TARGET_X86_64 if (lm_capable_kernel) { @@ -3385,9 +3461,6 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_TSC_AUX: env->tsc_aux =3D msrs[i].data; break; - case MSR_TSC_ADJUST: - env->tsc_adjust =3D msrs[i].data; - break; case MSR_IA32_TSCDEADLINE: env->tsc_deadline =3D msrs[i].data; break; @@ -3995,6 +4068,11 @@ int kvm_arch_put_registers(CPUState *cpu, int level) if (ret < 0) { return ret; } + + ret =3D kvm_set_tsc(cpu); + if (ret < 0) { + return ret; + } } =20 ret =3D kvm_put_tscdeadline_msr(x86_cpu); @@ -4064,6 +4142,12 @@ int kvm_arch_get_registers(CPUState *cs) if (ret < 0) { goto out; } + + ret =3D kvm_get_tsc(cs); + if (ret < 0) { + goto out; + } + ret =3D 0; out: cpu_sync_bndcs_hflags(&cpu->env); diff --git a/target/i386/machine.c b/target/i386/machine.c index 233e46bb70..59b1c9be2b 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -1359,6 +1359,24 @@ static const VMStateDescription vmstate_msr_tsx_ctrl= =3D { } }; =20 + +static bool tsc_ns_timestamp_needed(void *opaque) +{ + return kvm_has_precise_tsc(); +} + +static const VMStateDescription vmstate_tsc_ns_timestamp =3D { + .name =3D "cpu/tsc_ns_timestamp", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D tsc_ns_timestamp_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.tsc_ns_timestamp, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + + VMStateDescription vmstate_x86_cpu =3D { .name =3D "cpu", .version_id =3D 12, @@ -1493,6 +1511,7 @@ VMStateDescription vmstate_x86_cpu =3D { #endif #ifdef CONFIG_KVM &vmstate_nested_state, + &vmstate_tsc_ns_timestamp, #endif &vmstate_msr_tsx_ctrl, NULL --=20 2.26.2