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[88.21.205.111]) by smtp.gmail.com with ESMTPSA id d7sm575737edv.17.2020.12.02.10.44.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Dec 2020 10:44:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=g86VgmSNy4f4zzNJeVPl770oLi4Jhzj+nbmAAlUIF60=; b=Oi1mz7FptywDHxL4wFFotazbFkvsdN+8GtFfpfUzmHCiPc/x2VxgbGdYABGUrTFIbU 5Hmko5FGjblPU29p6aui0qp6lJMZsFt92u1DXkyHFhFVxQNCQyXUaxO1CRI/M8hlioKF z8NaUrdaS0ptFNJ96W+aVYOn5EOkM4DBCzMrpZ112PWuQL6BS1jdFvt3UGE+hkXf2mL8 DveDDsY4P6Yp1kXA0meLFC8kNo2Zm+ZO8yb257XDpNMHd0ieSMxfTKQHdwc43X+FNJmh jykwuofme+rQ2v8HYxmRURyGMbJjTCkqpgjCfRkljDq3OmfTpfzmMUSHVSoxmcVDsvH+ ucGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=g86VgmSNy4f4zzNJeVPl770oLi4Jhzj+nbmAAlUIF60=; b=gC2ijtZpTWiHXGr4eBXC0t4VQN/UGDqguMdje4D9V4+3NVZro+fI/FCMydhym0NFeW lFQOvl2llwRdSEBo7k+g8HygzPyuWJMh1YMqyhS3avJuKJYuDODCmbU7intU4MP9fEyB qcxhY5pKtfXW/2nVKHDbtOFlI9Q0QZuANzXmr0Jhiu73WlcCa1TTthy6gPvIahiW6wEq zRVDb4BVvehywHKOTxoZzgJIk3DnblwRP79YG3MuRkVOAxY8RgJtitXt/e59H5Ow+sqj DP7GmDYph9IuJqL7Gghq5hne/uXT60EaX/W4wFVZkjeItw2uBa9xp2lM0o2TVegST/JK eFHw== X-Gm-Message-State: AOAM533gOaZKF0eUmYN6eqpMB7J7u7PBzLwJLAMOv9/sQDOSWh7kHkQ+ YphPDEeTX4hCTGi0Kx5l5K4= X-Google-Smtp-Source: ABdhPJwjeCuvpeuBnGWFwyPDgCk9BaHv5eStq6XWq+D3+5rh2254O9WeuxjHg+qB3zX5zSHBorSF5A== X-Received: by 2002:a17:906:6713:: with SMTP id a19mr1164126ejp.468.1606934695848; Wed, 02 Dec 2020 10:44:55 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Huacai Chen , Richard Henderson , kvm@vger.kernel.org, Aleksandar Rikalo , Paolo Bonzini , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 7/9] target/mips: Extract msa_translate_init() from mips_tcg_init() Date: Wed, 2 Dec 2020 19:44:13 +0100 Message-Id: <20201202184415.1434484-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201202184415.1434484-1-f4bug@amsat.org> References: <20201202184415.1434484-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Extract the logic initialization of the MSA registers from the generic initialization. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/translate.c | 35 ++++++++++++++++++++--------------- 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 41880f21abd..a5112acc351 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31672,6 +31672,24 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, in= t flags) } } =20 +static void msa_translate_init(void) +{ + int i; + + for (i =3D 0; i < 32; i++) { + int off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); + + /* + * The MSA vector registers are mapped on the + * scalar floating-point unit (FPU) registers. + */ + msa_wr_d[i * 2] =3D fpu_f64[i]; + off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); + msa_wr_d[i * 2 + 1] =3D + tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1= ]); + } +} + void mips_tcg_init(void) { int i; @@ -31685,22 +31703,9 @@ void mips_tcg_init(void) for (i =3D 0; i < 32; i++) { int off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); =20 - fpu_f64[i] =3D tcg_global_mem_new_i64(cpu_env, off, msaregnames[i = * 2]); + fpu_f64[i] =3D tcg_global_mem_new_i64(cpu_env, off, fregnames[i]); } - /* MSA */ - for (i =3D 0; i < 32; i++) { - int off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); - - /* - * The MSA vector registers are mapped on the - * scalar floating-point unit (FPU) registers. - */ - msa_wr_d[i * 2] =3D fpu_f64[i]; - off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); - msa_wr_d[i * 2 + 1] =3D - tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1= ]); - } - + msa_translate_init(); cpu_PC =3D tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, active_tc.PC), "PC"= ); for (i =3D 0; i < MIPS_DSP_ACC; i++) { --=20 2.26.2