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[88.21.205.111]) by smtp.gmail.com with ESMTPSA id e12sm570657edm.48.2020.12.02.10.44.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Dec 2020 10:44:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=O0Gmy5kVHrWtz2x/frWgI7xbHwcEYiFbHswDBnArJKk=; b=Cy9L94FFo4sSHWJnhtRu1Ih4nCtDWyS9sjq2wZBOV77ZLvh8BUlgDknPH9FR1PoIzt Dw/0hHJ6B8ugGuyL2qEKrB6fF0GkTonB76CuDVUCU0vB4vRRjLiGquMiky7KCDI7iNEz n7laZwqSDybgcWtezsBFArsIEiTm+MSRfw+BTblAKpR9IUR9iuopeoqdkjlOkqU7NlHJ Mzc7B1uzoCREAVxXMpWU8gtXQA22fbdepHUyBbMB3jCp17yDkAyUC8K1sbNiaOkcioZU yb7HtSCUwL+s4z3yrJgdENlNCi+0Yctgf5pLZ3rawYbNHDPVlYlMzLsvP135t+7JS9Xs mUmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=O0Gmy5kVHrWtz2x/frWgI7xbHwcEYiFbHswDBnArJKk=; b=XO3tdSSmkGYBODDeVRmUVCIQJQOzjr+RQkdZYYgN2cNF1+iWEGlu7kpiW9G4Xv56xM Yd5KQOKNRZEBfDFXNhsR8HErzuVgD6djSJriq9Td6XxW+bsK52w0RmsxkBkVj7UrhE7r z0eYPr/y4EYuqRCliKU1hApL16xP9xo1cN7NhXsLnIsYmhD/blEUc4vDCM1Vp2DD79l/ UimTin93tJcyQxfkMfLuL/kSHGtHtBnvVxp1j0EUzW6hs4nRRq3T4UYc4qTN3Aw4x5aY GHfJ5EOmDxLkJ47gI70hVZKeioR0EQNJVQ5CU7npgm0uKSDJvDTK0IFbO0BQC6MqstF2 sFzw== X-Gm-Message-State: AOAM533Q1CzK5m1ZMQapZ03K7kKFg7Cuf2GgnHqehjOIPIogfOB7Ijgt X01Q0zj9yNkwVOURZCyS3j0= X-Google-Smtp-Source: ABdhPJzH0s/mvRJGBWMPJEUdTKPTxukUS8ZrESWtCMCmpvq+4sQLddwuyMLZaTIeUkLh/3YtQrq5zw== X-Received: by 2002:a50:ff0c:: with SMTP id a12mr1312530edu.79.1606934690471; Wed, 02 Dec 2020 10:44:50 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Huacai Chen , Richard Henderson , kvm@vger.kernel.org, Aleksandar Rikalo , Paolo Bonzini , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 6/9] target/mips: Alias MSA vector registers on FPU scalar registers Date: Wed, 2 Dec 2020 19:44:12 +0100 Message-Id: <20201202184415.1434484-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201202184415.1434484-1-f4bug@amsat.org> References: <20201202184415.1434484-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Commits 863f264d10f ("add msa_reset(), global msa register") and cb269f273fd ("fix multiple TCG registers covering same data") removed the FPU scalar registers and replaced them by aliases to the MSA vector registers. While this might be the case for CPU implementing MSA, this makes QEMU code incoherent for CPU not implementing it. It is simpler to inverse the logic and alias the MSA vector registers on the FPU scalar ones. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/translate.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index a05c25e50b8..41880f21abd 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31682,16 +31682,20 @@ void mips_tcg_init(void) offsetof(CPUMIPSState, active_tc.gpr[i]), regnames[i]); - for (i =3D 0; i < 32; i++) { int off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); - msa_wr_d[i * 2] =3D - tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2]); + + fpu_f64[i] =3D tcg_global_mem_new_i64(cpu_env, off, msaregnames[i = * 2]); + } + /* MSA */ + for (i =3D 0; i < 32; i++) { + int off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); + /* - * The scalar floating-point unit (FPU) registers are mapped on - * the MSA vector registers. + * The MSA vector registers are mapped on the + * scalar floating-point unit (FPU) registers. */ - fpu_f64[i] =3D msa_wr_d[i * 2]; + msa_wr_d[i * 2] =3D fpu_f64[i]; off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); msa_wr_d[i * 2 + 1] =3D tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1= ]); --=20 2.26.2