From nobody Sun Feb 8 14:45:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1606743702; cv=none; d=zohomail.com; s=zohoarc; b=nSlHP2G9dkN8AhRvj9jWtmAloJZN8W6ufeV4GR+KrdnUdSiFSYS4fFE6u10RrB4kDMy2LjzlD16xf7QBriYw1kRc7ooV0spQ95qsjIyPlAiJXQOCOBATImbQ5OGTQobxhIqXTGpAFTe8tsgrGExE9AILyr4+Y5ha4GaSw1dujcA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1606743702; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=uohsauvIsjYEA0XUxpazEHeSKdAgOCIc129bvX1wErE=; b=lKqX13C9PjXqojJeidlvTopArRjaN1cDyvHR56aM19uAIlZ+KHvo9jyIKJfGfX7s8JkwVCDmmUZamV1p9trlmbFFGvUGchcBeqZzQOrgPbC7MAmUrGc23XCjbwkaWGu1I2Xh3HO/QQlx1reVxL+A/FpbkQaW5ZEM5Z9Khrxi6II= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1606743702888890.2250267320803; Mon, 30 Nov 2020 05:41:42 -0800 (PST) Received: from localhost ([::1]:51632 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kjjQz-0006b4-Gq for importer@patchew.org; Mon, 30 Nov 2020 08:41:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37778) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kjjOR-0005Ix-SE for qemu-devel@nongnu.org; Mon, 30 Nov 2020 08:39:03 -0500 Received: from us-smtp-delivery-124.mimecast.com ([63.128.21.124]:31101) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kjjOP-0008LI-JO for qemu-devel@nongnu.org; Mon, 30 Nov 2020 08:39:03 -0500 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-244-dur6NQcVP3WZhMlsigyNIg-1; Mon, 30 Nov 2020 08:38:58 -0500 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 7AD0C1009462; Mon, 30 Nov 2020 13:38:57 +0000 (UTC) Received: from localhost.localdomain (unknown [10.35.206.90]) by smtp.corp.redhat.com (Postfix) with ESMTP id 4982D60867; Mon, 30 Nov 2020 13:38:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1606743540; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=uohsauvIsjYEA0XUxpazEHeSKdAgOCIc129bvX1wErE=; b=T7M/PzxEbuiZEzUmmhgBXR5zO8x4/ZcGUKpNV7kJOqN+LjWjKh2AFSArU1vq/zAGCk67g0 09G6fS68Y7i5Squ7K7DbJjpCjrn1mG3Dcm58pMpTjP28AHIJ80Yy7EpN5jOcu+lMGqi0+A Cccu0v5klZgXsxFEDpasgrVksGfdDrI= X-MC-Unique: dur6NQcVP3WZhMlsigyNIg-1 From: Maxim Levitsky To: qemu-devel@nongnu.org Subject: [PATCH 1/2] Update the kernel headers for 5.10-rc5 + TSC Date: Mon, 30 Nov 2020 15:38:44 +0200 Message-Id: <20201130133845.233552-2-mlevitsk@redhat.com> In-Reply-To: <20201130133845.233552-1-mlevitsk@redhat.com> References: <20201130133845.233552-1-mlevitsk@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=63.128.21.124; envelope-from=mlevitsk@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.496, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marcelo Tosatti , Eduardo Habkost , kvm@vger.kernel.org, "Michael S. Tsirkin" , Cornelia Huck , Richard Henderson , Maxim Levitsky , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Maxim Levitsky --- include/standard-headers/asm-x86/kvm_para.h | 1 + linux-headers/asm-x86/kvm.h | 2 + linux-headers/linux/kvm.h | 70 ++++++++++++++++++++- 3 files changed, 72 insertions(+), 1 deletion(-) diff --git a/include/standard-headers/asm-x86/kvm_para.h b/include/standard= -headers/asm-x86/kvm_para.h index 07877d3295..215d01b4ec 100644 --- a/include/standard-headers/asm-x86/kvm_para.h +++ b/include/standard-headers/asm-x86/kvm_para.h @@ -32,6 +32,7 @@ #define KVM_FEATURE_POLL_CONTROL 12 #define KVM_FEATURE_PV_SCHED_YIELD 13 #define KVM_FEATURE_ASYNC_PF_INT 14 +#define KVM_FEATURE_MSI_EXT_DEST_ID 15 =20 #define KVM_HINTS_REALTIME 0 =20 diff --git a/linux-headers/asm-x86/kvm.h b/linux-headers/asm-x86/kvm.h index 89e5f3d1bb..2a60fc6674 100644 --- a/linux-headers/asm-x86/kvm.h +++ b/linux-headers/asm-x86/kvm.h @@ -12,6 +12,7 @@ =20 #define KVM_PIO_PAGE_OFFSET 1 #define KVM_COALESCED_MMIO_PAGE_OFFSET 2 +#define KVM_DIRTY_LOG_PAGE_OFFSET 64 =20 #define DE_VECTOR 0 #define DB_VECTOR 1 @@ -403,6 +404,7 @@ struct kvm_sync_regs { #define KVM_X86_QUIRK_LAPIC_MMIO_HOLE (1 << 2) #define KVM_X86_QUIRK_OUT_7E_INC_RIP (1 << 3) #define KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT (1 << 4) +#define KVM_X86_QUIRK_TSC_HOST_ACCESS (1 << 5) =20 #define KVM_STATE_NESTED_FORMAT_VMX 0 #define KVM_STATE_NESTED_FORMAT_SVM 1 diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index 56ce14ad20..55dd0f563c 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -250,6 +250,7 @@ struct kvm_hyperv_exit { #define KVM_EXIT_ARM_NISV 28 #define KVM_EXIT_X86_RDMSR 29 #define KVM_EXIT_X86_WRMSR 30 +#define KVM_EXIT_DIRTY_RING_FULL 31 =20 /* For KVM_EXIT_INTERNAL_ERROR */ /* Emulate instruction failed. */ @@ -1053,6 +1054,9 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_X86_USER_SPACE_MSR 188 #define KVM_CAP_X86_MSR_FILTER 189 #define KVM_CAP_ENFORCE_PV_FEATURE_CPUID 190 +#define KVM_CAP_SYS_HYPERV_CPUID 191 +#define KVM_CAP_DIRTY_LOG_RING 192 +#define KVM_CAP_PRECISE_TSC 193 =20 #ifdef KVM_CAP_IRQ_ROUTING =20 @@ -1166,6 +1170,15 @@ struct kvm_clock_data { __u32 pad[9]; }; =20 + +#define KVM_TSC_STATE_TSC_ADJUST_VALID 1 +struct kvm_tsc_state { + __u32 flags; + __u64 nsec; + __u64 tsc; + __u64 tsc_adjust; +}; + /* For KVM_CAP_SW_TLB */ =20 #define KVM_MMU_FSL_BOOKE_NOHV 0 @@ -1511,7 +1524,7 @@ struct kvm_enc_region { /* Available with KVM_CAP_MANUAL_DIRTY_LOG_PROTECT_2 */ #define KVM_CLEAR_DIRTY_LOG _IOWR(KVMIO, 0xc0, struct kvm_clear_d= irty_log) =20 -/* Available with KVM_CAP_HYPERV_CPUID */ +/* Available with KVM_CAP_HYPERV_CPUID (vcpu) / KVM_CAP_SYS_HYPERV_CPUID (= system) */ #define KVM_GET_SUPPORTED_HV_CPUID _IOWR(KVMIO, 0xc1, struct kvm_cpuid2) =20 /* Available with KVM_CAP_ARM_SVE */ @@ -1557,6 +1570,13 @@ struct kvm_pv_cmd { /* Available with KVM_CAP_X86_MSR_FILTER */ #define KVM_X86_SET_MSR_FILTER _IOW(KVMIO, 0xc6, struct kvm_msr_filter) =20 +/* Available with KVM_CAP_DIRTY_LOG_RING */ +#define KVM_RESET_DIRTY_RINGS _IO(KVMIO, 0xc7) + +/* Available with KVM_CAP_PRECISE_TSC*/ +#define KVM_SET_TSC_STATE _IOW(KVMIO, 0xc8, struct kvm_tsc_state) +#define KVM_GET_TSC_STATE _IOR(KVMIO, 0xc9, struct kvm_tsc_state) + /* Secure Encrypted Virtualization command */ enum sev_cmd_id { /* Guest initialization commands */ @@ -1710,4 +1730,52 @@ struct kvm_hyperv_eventfd { #define KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE (1 << 0) #define KVM_DIRTY_LOG_INITIALLY_SET (1 << 1) =20 +/* + * Arch needs to define the macro after implementing the dirty ring + * feature. KVM_DIRTY_LOG_PAGE_OFFSET should be defined as the + * starting page offset of the dirty ring structures. + */ +#ifndef KVM_DIRTY_LOG_PAGE_OFFSET +#define KVM_DIRTY_LOG_PAGE_OFFSET 0 +#endif + +/* + * KVM dirty GFN flags, defined as: + * + * |---------------+---------------+--------------| + * | bit 1 (reset) | bit 0 (dirty) | Status | + * |---------------+---------------+--------------| + * | 0 | 0 | Invalid GFN | + * | 0 | 1 | Dirty GFN | + * | 1 | X | GFN to reset | + * |---------------+---------------+--------------| + * + * Lifecycle of a dirty GFN goes like: + * + * dirtied harvested reset + * 00 -----------> 01 -------------> 1X -------+ + * ^ | + * | | + * +------------------------------------------+ + * + * The userspace program is only responsible for the 01->1X state + * conversion after harvesting an entry. Also, it must not skip any + * dirty bits, so that dirty bits are always harvested in sequence. + */ +#define KVM_DIRTY_GFN_F_DIRTY BIT(0) +#define KVM_DIRTY_GFN_F_RESET BIT(1) +#define KVM_DIRTY_GFN_F_MASK 0x3 + +/* + * KVM dirty rings should be mapped at KVM_DIRTY_LOG_PAGE_OFFSET of + * per-vcpu mmaped regions as an array of struct kvm_dirty_gfn. The + * size of the gfn buffer is decided by the first argument when + * enabling KVM_CAP_DIRTY_LOG_RING. + */ +struct kvm_dirty_gfn { + __u32 flags; + __u32 slot; + __u64 offset; +}; + #endif /* __LINUX_KVM_H */ --=20 2.26.2 From nobody Sun Feb 8 14:45:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1606743720; cv=none; d=zohomail.com; s=zohoarc; b=gXdkBls43qvq6N1An+4pay1bHatSX+SNvdCDMDd+qclicgi6LBQsUA65jcn7fVFvwZE38TzlHexXiDKH6sNtk5Pabikv8QYDhKHJguTbAFoKT5jadcvERmC17IDAHP5rzUJPPsWJCk+p6IY6z599qiNElnd8LXB+Crs07lLYmCM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1606743720; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qVdHxkntzGO9QMXR9mKR8JkaFo2idIgLEfwDs2MnucI=; b=OFXHw+AmnzSbRUM46DYenKQOC0zNze4+q0RklZQMcpH0F0s+1qtoPm2EL9Kj7m2PLVKdn7ZxecfuHdejAYBidl2F/S2/eqqC32UEaHoeaZaNqQUvPYYmyZlxB2SBGPszebdJPPVMG0CKHFW0SFPJDqFnZWvcZe9laUgY8syRazQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1606743720992284.72770616884156; Mon, 30 Nov 2020 05:42:00 -0800 (PST) Received: from localhost ([::1]:52364 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kjjRH-000716-4e for importer@patchew.org; Mon, 30 Nov 2020 08:41:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37806) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kjjOX-0005Ri-H3 for qemu-devel@nongnu.org; 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s=mimecast20190719; t=1606743546; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qVdHxkntzGO9QMXR9mKR8JkaFo2idIgLEfwDs2MnucI=; b=W1+VlsIOfjL2BZN9JnpIYvSX8aTnCU2NMjvoM3tzxlhxdxv8nUsGfm9rJ2d4ZfJeS4oE+V 5ZhqZi9MTbuH42GREbZcs11z8GGxHABT2cMw7geN155PI6I70Y8Jmo+QIPEx311PAzqxfC JhJTi7sQfLinyA3NUxval0w/LGq7Gjo= X-MC-Unique: cXAaBnGcOO-eToQXPV_IMQ-1 From: Maxim Levitsky To: qemu-devel@nongnu.org Subject: [PATCH 2/2] Implement support for precise TSC migration Date: Mon, 30 Nov 2020 15:38:45 +0200 Message-Id: <20201130133845.233552-3-mlevitsk@redhat.com> In-Reply-To: <20201130133845.233552-1-mlevitsk@redhat.com> References: <20201130133845.233552-1-mlevitsk@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=63.128.21.124; envelope-from=mlevitsk@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.496, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marcelo Tosatti , Eduardo Habkost , kvm@vger.kernel.org, "Michael S. Tsirkin" , Cornelia Huck , Richard Henderson , Maxim Levitsky , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Currently to enable it, you need to set x-precise-tsc=3Don for each vcpu. Signed-off-by: Maxim Levitsky --- target/i386/cpu.c | 1 + target/i386/cpu.h | 4 ++ target/i386/kvm.c | 141 ++++++++++++++++++++++++++++++++++-------- target/i386/machine.c | 20 ++++++ 4 files changed, 139 insertions(+), 27 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5a8c96072e..3c82864930 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7231,6 +7231,7 @@ static Property x86_cpu_properties[] =3D { false), DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, true), + DEFINE_PROP_BOOL("x-precise-tsc", X86CPU, precise_tsc, false), DEFINE_PROP_END_OF_LIST() }; =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 88e8586f8f..fd355057b8 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1460,6 +1460,7 @@ typedef struct CPUX86State { uint64_t tsc_adjust; uint64_t tsc_deadline; uint64_t tsc_aux; + uint64_t tsc_ns_timestamp; =20 uint64_t xcr0; =20 @@ -1743,6 +1744,9 @@ struct X86CPU { /* Number of physical address bits supported */ uint32_t phys_bits; =20 + /* Use KVM_GET_TSC_PRECISE/KVM_SET_TSC_PRECISE to access IA32_TSC */ + bool precise_tsc; + /* in order to simplify APIC support, we leave this pointer to the user */ struct DeviceState *apic_state; diff --git a/target/i386/kvm.c b/target/i386/kvm.c index a2934dda02..f0488aa6cc 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -121,6 +121,7 @@ static int has_xsave; static int has_xcrs; static int has_pit_state2; static int has_exception_payload; +static int has_precise_tsc; =20 static bool has_msr_mcg_ext_ctl; =20 @@ -196,31 +197,109 @@ static int kvm_get_tsc(CPUState *cs) { X86CPU *cpu =3D X86_CPU(cs); CPUX86State *env =3D &cpu->env; - struct { - struct kvm_msrs info; - struct kvm_msr_entry entries[1]; - } msr_data =3D {}; int ret; =20 if (env->tsc_valid) { return 0; } =20 - memset(&msr_data, 0, sizeof(msr_data)); - msr_data.info.nmsrs =3D 1; - msr_data.entries[0].index =3D MSR_IA32_TSC; - env->tsc_valid =3D !runstate_is_running(); + if (cpu->precise_tsc) { + struct kvm_tsc_state tsc_state; =20 - ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data); - if (ret < 0) { - return ret; + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_TSC_STATE, &tsc_state); + if (ret < 0) { + return ret; + } + + env->tsc =3D tsc_state.tsc; + if (tsc_state.flags & KVM_TSC_STATE_TSC_ADJUST_VALID) { + env->tsc_adjust =3D tsc_state.tsc_adjust; + } + env->tsc_ns_timestamp =3D tsc_state.nsec; + + } else { + struct { + struct kvm_msrs info; + struct kvm_msr_entry entries[2]; + } msr_data =3D {}; + + memset(&msr_data, 0, sizeof(msr_data)); + msr_data.info.nmsrs =3D 1; + msr_data.entries[0].index =3D MSR_IA32_TSC; + + if (has_msr_tsc_adjust) { + msr_data.info.nmsrs++; + msr_data.entries[1].index =3D MSR_TSC_ADJUST; + } + + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data); + if (ret < 0) { + return ret; + } + + assert(ret =3D=3D msr_data.info.nmsrs); + + env->tsc =3D msr_data.entries[0].data; + if (has_msr_tsc_adjust) { + env->tsc_adjust =3D msr_data.entries[1].data; + } } =20 - assert(ret =3D=3D 1); - env->tsc =3D msr_data.entries[0].data; + env->tsc_valid =3D !runstate_is_running(); return 0; } =20 +static int kvm_set_tsc(CPUState *cs) +{ + int ret; + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + + if (cpu->precise_tsc) { + struct kvm_tsc_state tsc_state; + + memset(&tsc_state, 0, sizeof(tsc_state)); + + tsc_state.tsc =3D env->tsc; + tsc_state.nsec =3D env->tsc_ns_timestamp; + + if (has_msr_tsc_adjust) { + tsc_state.tsc_adjust =3D env->tsc_adjust; + tsc_state.flags |=3D KVM_TSC_STATE_TSC_ADJUST_VALID; + } + + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_SET_TSC_STATE, &tsc_state); + if (ret < 0) { + return ret; + } + + } else { + struct { + struct kvm_msrs info; + struct kvm_msr_entry entries[2]; + } msr_data =3D {}; + + memset(&msr_data, 0, sizeof(msr_data)); + msr_data.info.nmsrs =3D 1; + msr_data.entries[0].index =3D MSR_IA32_TSC; + msr_data.entries[0].data =3D env->tsc; + + if (has_msr_tsc_adjust) { + msr_data.info.nmsrs++; + msr_data.entries[1].index =3D MSR_TSC_ADJUST; + msr_data.entries[1].data =3D env->tsc_adjust; + } + + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data); + if (ret < 0) { + return ret; + } + + assert(ret =3D=3D msr_data.info.nmsrs); + } + return ret; +} + static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data a= rg) { kvm_get_tsc(cpu); @@ -1780,6 +1859,13 @@ int kvm_arch_init_vcpu(CPUState *cs) } } =20 + if (cpu->precise_tsc) { + if (!kvm_check_extension(cs->kvm_state, KVM_CAP_PRECISE_TSC)) { + error_report("kvm: Precise TSC is not supported by the host's = KVM"); + return -ENOTSUP; + } + } + if (cpu->vmware_cpuid_freq /* Guests depend on 0x40000000 to detect this feature, so only exp= ose * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */ @@ -2196,6 +2282,8 @@ int kvm_arch_init(MachineState *ms, KVMState *s) int disable_exits =3D kvm_check_extension(s, KVM_CAP_X86_DISABLE_E= XITS); int ret; =20 + + /* Work around for kernel header with a typo. TODO: fix header and drop. */ #if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_H= LT) #define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL @@ -2215,6 +2303,8 @@ int kvm_arch_init(MachineState *ms, KVMState *s) } } =20 + has_precise_tsc =3D kvm_check_extension(s, KVM_CAP_PRECISE_TSC); + return 0; } =20 @@ -2756,9 +2846,6 @@ static int kvm_put_msrs(X86CPU *cpu, int level) if (has_msr_tsc_aux) { kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux); } - if (has_msr_tsc_adjust) { - kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust); - } if (has_msr_misc_enable) { kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, env->msr_ia32_misc_enable); @@ -2802,7 +2889,6 @@ static int kvm_put_msrs(X86CPU *cpu, int level) * for normal writeback. Limit them to reset or full state updates. */ if (level >=3D KVM_PUT_RESET_STATE) { - kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc); kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr); kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr); if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) { @@ -3142,9 +3228,6 @@ static int kvm_get_msrs(X86CPU *cpu) if (has_msr_tsc_aux) { kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0); } - if (has_msr_tsc_adjust) { - kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0); - } if (has_msr_tsc_deadline) { kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0); } @@ -3178,10 +3261,6 @@ static int kvm_get_msrs(X86CPU *cpu) if (has_msr_virt_ssbd) { kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0); } - if (!env->tsc_valid) { - kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0); - env->tsc_valid =3D !runstate_is_running(); - } =20 #ifdef TARGET_X86_64 if (lm_capable_kernel) { @@ -3385,9 +3464,6 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_TSC_AUX: env->tsc_aux =3D msrs[i].data; break; - case MSR_TSC_ADJUST: - env->tsc_adjust =3D msrs[i].data; - break; case MSR_IA32_TSCDEADLINE: env->tsc_deadline =3D msrs[i].data; break; @@ -3995,6 +4071,11 @@ int kvm_arch_put_registers(CPUState *cpu, int level) if (ret < 0) { return ret; } + + ret =3D kvm_set_tsc(cpu); + if (ret < 0) { + return ret; + } } =20 ret =3D kvm_put_tscdeadline_msr(x86_cpu); @@ -4064,6 +4145,12 @@ int kvm_arch_get_registers(CPUState *cs) if (ret < 0) { goto out; } + + ret =3D kvm_get_tsc(cs); + if (ret < 0) { + goto out; + } + ret =3D 0; out: cpu_sync_bndcs_hflags(&cpu->env); diff --git a/target/i386/machine.c b/target/i386/machine.c index 233e46bb70..4f4296a3e4 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -1359,6 +1359,25 @@ static const VMStateDescription vmstate_msr_tsx_ctrl= =3D { } }; =20 + +static bool tsc_info_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + return cpu->precise_tsc; +} + +static const VMStateDescription vmstate_tsc_info =3D { + .name =3D "cpu/tsc_nsec_info", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D tsc_info_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.tsc_ns_timestamp, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + + VMStateDescription vmstate_x86_cpu =3D { .name =3D "cpu", .version_id =3D 12, @@ -1493,6 +1512,7 @@ VMStateDescription vmstate_x86_cpu =3D { #endif #ifdef CONFIG_KVM &vmstate_nested_state, + &vmstate_tsc_info, #endif &vmstate_msr_tsx_ctrl, NULL --=20 2.26.2