From nobody Sat May 4 04:32:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1606504547; cv=none; d=zohomail.com; s=zohoarc; b=lpyaHz74G67FfjxsYdzcf96JfvfE+fMHZEKS0OK2Y/OswSWb3sUHQKALosmWZR1PYZkxc0lTvWBsXR4Fy3m9GqKrWxRm+VtYcaDxO6SXFjTaXckn7OTB/8XuQq+7bW/1K046h+Ncbzu69s05rCsSqT/Vj3LGbEaVlPbZWArsT8I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1606504547; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rYWSqU97TTIF2G1xrqc542TJUc1cxfiAAwoKNqxMB2k=; b=UmZwnBDm1/9VRHxFFLsT+fO52DnHXg1zs8koD8HEMC5TggWS6CrI9C9p5wC0Ov124Yn5aLYlb1k/pPO88+e7jcJAZhxbQZ8QPPcIiLiXrt/xeF81BlzGTtidbvL9Hc2tAPOWBbi4jMULYMwFeb/ZBnHB6KyyfA2OYnABvuFFrOg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1606504547836964.9568462819009; Fri, 27 Nov 2020 11:15:47 -0800 (PST) Received: from localhost ([::1]:49156 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kijDe-0006W0-M5 for importer@patchew.org; Fri, 27 Nov 2020 14:15:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59732) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kijAf-0005BA-5Z for qemu-devel@nongnu.org; Fri, 27 Nov 2020 14:12:41 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:40814) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kijAd-0004Ry-58 for qemu-devel@nongnu.org; Fri, 27 Nov 2020 14:12:40 -0500 Received: by mail-wr1-x444.google.com with SMTP id m6so6611325wrg.7 for ; Fri, 27 Nov 2020 11:12:38 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id 34sm15809722wrh.78.2020.11.27.11.12.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Nov 2020 11:12:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rYWSqU97TTIF2G1xrqc542TJUc1cxfiAAwoKNqxMB2k=; b=BPLfzU85eJVQGqkQrhMoE5qQep0feWBiXTOeODemiohJnjmV2E7V0mkPAVy/K2fTML Pbpsz8ZVgfL8NptqmQb3WlNhtKGoHuZVCUY9V/XyztOTFVl74nLHhR3BuRU5xMtDQM0v cxfHMm+OO9Z1LMICEAHl+NqXwvfK9IlNaWkc4huS71OF9K7BqhJS/yfjwIcZzTrr1Ock LkB3zwn0w2b/wLky7pVLFzRLQeF3X2DIR0qF+phmUtkrMTMmTafoCUjeZtC8iOntCVYf hKw6dMTXOUCcAaO8Ka0u7TcRWMv83/d9AqD6kO1Zjd9XOMJgnh26dm9WBI2LSUDO1DXt 8BXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rYWSqU97TTIF2G1xrqc542TJUc1cxfiAAwoKNqxMB2k=; b=txKTLYEoDTF0ucVEfL+EsNjMqTVSpzt/qdGtU1vEjREmSowB642NMUOJAM0TY0dNO2 o9Sk6S6qfmnDTN7G4F5TQAwg2V5CBRaSNiYr/T7byK0c8U+Z8PoDJKfwYVizkjH0oV35 zbnFbz60+r0kr12+sZsoLqGUeS+CaWRBgUvU/nDi6jy7xDHtf6vwSTbtp0jk7TIUSL79 9bo7yN85guypm2OjwlgZGonNlKzNAdGUcsEmwrXdvL6F/OlVtgbAi+l9l3azvkeWMZbX nYk7tZV+Ih+9rORnh80bevQK665trBH2SH7w56bqZDEvU40sbnghOxDNKTxHLkrWvtYj JEoA== X-Gm-Message-State: AOAM530gtBQ/LqeFvVhX2z5TSL04FiJkhNX6OzocPGfhX38wrW8eTNLV tLgykP5QdV5paB0FHu5jqEY8e1qlTIuGSw== X-Google-Smtp-Source: ABdhPJxyO1WEHJ//UynGQqRCIs4/9b/BgnCJjsu5hsWkPwORACRzQJ9Cn5OvpbyWDC4WS1v/lu/0aA== X-Received: by 2002:adf:f08e:: with SMTP id n14mr12189592wro.136.1606504357271; Fri, 27 Nov 2020 11:12:37 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 1/2] target/nios2: Move cpu_pic code into CPU object proper Date: Fri, 27 Nov 2020 19:12:32 +0000 Message-Id: <20201127191233.11200-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201127191233.11200-1-peter.maydell@linaro.org> References: <20201127191233.11200-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x444.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Sandra Loosemore , Chris Wulff , Wentong Wu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The nios2 code uses an old style of interrupt handling, where a separate standalone set of qemu_irqs invoke a function nios2_pic_cpu_handler() which signals the interrupt to the CPU proper by directly calling cpu_interrupt() and cpu_reset_interrupt(). Because CPU objects now inherit (indirectly) from TYPE_DEVICE, they can have GPIO input lines themselves, and the neater modern way to implement this is to simply have the CPU object itself provide the input IRQ lines. Create named "NMI" and "IRQ" GPIO inputs to the Nios2 CPU object, and make the only user of nios2_cpu_pic_init() wire up directly to those instead. This fixes a Coverity-reported trivial memory leak of the IRQ array allocated in nios2_cpu_pic_init(). Fixes: Coverity CID 1421916 Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/nios2/cpu.h | 1 - hw/nios2/10m50_devboard.c | 8 +++----- hw/nios2/cpu_pic.c | 31 ------------------------------- target/nios2/cpu.c | 34 ++++++++++++++++++++++++++++++++++ 4 files changed, 37 insertions(+), 37 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 86bbe1d8670..b7efb54ba7e 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -201,7 +201,6 @@ void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr= addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); =20 -qemu_irq *nios2_cpu_pic_init(Nios2CPU *cpu); void nios2_check_interrupts(CPUNios2State *env); =20 void do_nios2_semihosting(CPUNios2State *env); diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c index 5c13b74306f..ac1993e8c08 100644 --- a/hw/nios2/10m50_devboard.c +++ b/hw/nios2/10m50_devboard.c @@ -52,7 +52,7 @@ static void nios2_10m50_ghrd_init(MachineState *machine) ram_addr_t tcm_size =3D 0x1000; /* 1 kiB, but QEMU limit is 4 kiB */ ram_addr_t ram_base =3D 0x08000000; ram_addr_t ram_size =3D 0x08000000; - qemu_irq *cpu_irq, irq[32]; + qemu_irq irq[32]; int i; =20 /* Physical TCM (tb_ram_1k) with alias at 0xc0000000 */ @@ -76,14 +76,12 @@ static void nios2_10m50_ghrd_init(MachineState *machine) /* Create CPU -- FIXME */ cpu =3D NIOS2_CPU(cpu_create(TYPE_NIOS2_CPU)); =20 - /* Register: CPU interrupt controller (PIC) */ - cpu_irq =3D nios2_cpu_pic_init(cpu); - /* Register: Internal Interrupt Controller (IIC) */ dev =3D qdev_new("altera,iic"); object_property_add_const_link(OBJECT(dev), "cpu", OBJECT(cpu)); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, + qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", 0)); for (i =3D 0; i < 32; i++) { irq[i] =3D qdev_get_gpio_in(dev, i); } diff --git a/hw/nios2/cpu_pic.c b/hw/nios2/cpu_pic.c index 5ea7e52ab83..3fb621c5c85 100644 --- a/hw/nios2/cpu_pic.c +++ b/hw/nios2/cpu_pic.c @@ -26,32 +26,6 @@ =20 #include "boot.h" =20 -static void nios2_pic_cpu_handler(void *opaque, int irq, int level) -{ - Nios2CPU *cpu =3D opaque; - CPUNios2State *env =3D &cpu->env; - CPUState *cs =3D CPU(cpu); - int type =3D irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD; - - if (type =3D=3D CPU_INTERRUPT_HARD) { - env->irq_pending =3D level; - - if (level && (env->regs[CR_STATUS] & CR_STATUS_PIE)) { - env->irq_pending =3D 0; - cpu_interrupt(cs, type); - } else if (!level) { - env->irq_pending =3D 0; - cpu_reset_interrupt(cs, type); - } - } else { - if (level) { - cpu_interrupt(cs, type); - } else { - cpu_reset_interrupt(cs, type); - } - } -} - void nios2_check_interrupts(CPUNios2State *env) { if (env->irq_pending && @@ -60,8 +34,3 @@ void nios2_check_interrupts(CPUNios2State *env) cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HARD); } } - -qemu_irq *nios2_cpu_pic_init(Nios2CPU *cpu) -{ - return qemu_allocate_irqs(nios2_pic_cpu_handler, cpu, 2); -} diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 8f7011fcb92..4b21e7c6d1c 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -64,6 +64,37 @@ static void nios2_cpu_reset(DeviceState *dev) #endif } =20 +#ifndef CONFIG_USER_ONLY +static void nios2_cpu_set_nmi(void *opaque, int irq, int level) +{ + Nios2CPU *cpu =3D opaque; + CPUState *cs =3D CPU(cpu); + + if (level) { + cpu_interrupt(cs, CPU_INTERRUPT_NMI); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_NMI); + } +} + +static void nios2_cpu_set_irq(void *opaque, int irq, int level) +{ + Nios2CPU *cpu =3D opaque; + CPUNios2State *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); + + env->irq_pending =3D level; + + if (level && (env->regs[CR_STATUS] & CR_STATUS_PIE)) { + env->irq_pending =3D 0; + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } else if (!level) { + env->irq_pending =3D 0; + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } +} +#endif + static void nios2_cpu_initfn(Object *obj) { Nios2CPU *cpu =3D NIOS2_CPU(obj); @@ -72,6 +103,9 @@ static void nios2_cpu_initfn(Object *obj) =20 #if !defined(CONFIG_USER_ONLY) mmu_init(&cpu->env); + + qdev_init_gpio_in_named(DEVICE(cpu), nios2_cpu_set_nmi, "NMI", 1); + qdev_init_gpio_in_named(DEVICE(cpu), nios2_cpu_set_irq, "IRQ", 1); #endif } =20 --=20 2.20.1 From nobody Sat May 4 04:32:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1606504551; cv=none; d=zohomail.com; s=zohoarc; b=nR3CZUVSfCI+UQd6hcs88ce3kR5qoLx236BAuIIbdBWwYZISpeAocB4qMO7EgHYkJ+zJvVofGaYdKKQyQVA/fabH0/CAp+MfncS9skSeAP/9UIegS+SkEGmKHolzjhvmGOigfYb005hxAGzZMu/VhkEkUo5XtzAl+kszkf7R9rc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1606504551; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Qmdrf344izPcOsTR220jVZVjgW4nvR4+9igArZxzefE=; b=R3SX5yE0I//pPDhApX+TbXs07FIVKWiAPwOswNvzYF1sMqFQOBG/hV1jzJBCWSPBZ90TEz69MDTIudKSQHnCnSnI+J9gGK/4SqKWaE8VwV6aQcExipsHHgcaESW5h/B87UQrN5ZUz1ol2HWgNRxdP/TpL9UKMPuTsPWbVJK1w2E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 160650455138084.74741615018502; Fri, 27 Nov 2020 11:15:51 -0800 (PST) Received: from localhost ([::1]:49284 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kijDi-0006ZA-B0 for importer@patchew.org; Fri, 27 Nov 2020 14:15:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:59752) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kijAf-0005C2-Ul for qemu-devel@nongnu.org; Fri, 27 Nov 2020 14:12:41 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:34693) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kijAe-0004SJ-0u for qemu-devel@nongnu.org; Fri, 27 Nov 2020 14:12:41 -0500 Received: by mail-wr1-x444.google.com with SMTP id k14so6652095wrn.1 for ; Fri, 27 Nov 2020 11:12:39 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id 34sm15809722wrh.78.2020.11.27.11.12.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Nov 2020 11:12:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Qmdrf344izPcOsTR220jVZVjgW4nvR4+9igArZxzefE=; b=p5ezlC+agbP+bkj8naInWfC3/JKnHif7E+N+d3TuL75NvRWPSx19MdgK3ou702xq7m PaxkvhTkSM8ZvS5hJzUUo46+O+HiFIHEE5+3Oip4DwI1qHMfrAano4wHIlf+zqqzBw0M rh7fx6ka1aQ6L2XNMs2VfBAhVOAAtYdfjlrLhAYjRMHzWiF9hD0q7XCvw7E72vAvi8+s MlPYP5xTQ8tC0CA5YsCp7pvu8ZU0uA03Rwr03B8hKHj0Q6YR6MjYDiSkZ0CHJLTjB5Yi h8HKgdmcHqihUsM0koi1ALuCFxGDLkU4hSgdSlnDbHOOzIGMM5By0igDHNC6RBdk2hFK Cdqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Qmdrf344izPcOsTR220jVZVjgW4nvR4+9igArZxzefE=; b=JAloKoLMnlfyBhCkKMpuVP6algwNQUmIR2rw2Ai4dBsXFU6Gk5iS/P2dysIh7s+T91 /weyTn7y+nkm/6nr7jXNsYpot4wnaENEFbAI6USWpOgqduFzuvQbN4zmnBygu4lG06QJ G/YLkBJWKJSJINmIWsUvTzYPH0eBr6zBRkjrakquzPom860ZME4uMQTe5QYqTTT/kyIX fCrupgEHfd5gKjMKIi8bkRZ3bOA1jGehhfPCs13ChPa8fTwtpLv0jw1xsBzivwp+ZFaB 25Ro1cK4pujvNj7pCsrTyK2abAJtTU2b5w0GUO79YnNc4HlZr7XHv+5jloqGO/3fzCgW f+oQ== X-Gm-Message-State: AOAM530a3Earg1BDEgNOsXizMdsO94rMvSKvUVrkRpwP3nWzYE1xDzkV ni53sHeYb6z/LOV7vDwV+AE5TEfBh4ECEw== X-Google-Smtp-Source: ABdhPJyeHZnaffxKBqfYgObJCbZZuPcdUrmRAtT9vFfIY2w+jAUm71d+m3S1beiUvE/4INzFl7SMCA== X-Received: by 2002:adf:f881:: with SMTP id u1mr12661343wrp.103.1606504358455; Fri, 27 Nov 2020 11:12:38 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 2/2] target/nios2: Move nios2_check_interrupts() into target/nios2 Date: Fri, 27 Nov 2020 19:12:33 +0000 Message-Id: <20201127191233.11200-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201127191233.11200-1-peter.maydell@linaro.org> References: <20201127191233.11200-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x444.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Sandra Loosemore , Chris Wulff , Wentong Wu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The function nios2_check_interrupts)() looks only at CPU-internal state; it belongs in target/nios2, not hw/nios2. Move it into the same file as its only caller, so it can just be local to that file. This removes the only remaining code from cpu_pic.c, so we can delete that file entirely. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/nios2/cpu.h | 2 -- hw/nios2/cpu_pic.c | 36 ------------------------------------ target/nios2/op_helper.c | 9 +++++++++ hw/nios2/meson.build | 2 +- 4 files changed, 10 insertions(+), 39 deletions(-) delete mode 100644 hw/nios2/cpu_pic.c diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index b7efb54ba7e..2ab82fdc713 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -201,8 +201,6 @@ void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr= addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); =20 -void nios2_check_interrupts(CPUNios2State *env); - void do_nios2_semihosting(CPUNios2State *env); =20 #define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU diff --git a/hw/nios2/cpu_pic.c b/hw/nios2/cpu_pic.c deleted file mode 100644 index 3fb621c5c85..00000000000 --- a/hw/nios2/cpu_pic.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Altera Nios2 CPU PIC - * - * Copyright (c) 2016 Marek Vasut - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see - * - */ - -#include "qemu/osdep.h" -#include "cpu.h" -#include "hw/irq.h" - -#include "qemu/config-file.h" - -#include "boot.h" - -void nios2_check_interrupts(CPUNios2State *env) -{ - if (env->irq_pending && - (env->regs[CR_STATUS] & CR_STATUS_PIE)) { - env->irq_pending =3D 0; - cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HARD); - } -} diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index a60730faac3..a59003855ab 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -36,6 +36,15 @@ void helper_mmu_write(CPUNios2State *env, uint32_t rn, u= int32_t v) mmu_write(env, rn, v); } =20 +static void nios2_check_interrupts(CPUNios2State *env) +{ + if (env->irq_pending && + (env->regs[CR_STATUS] & CR_STATUS_PIE)) { + env->irq_pending =3D 0; + cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HARD); + } +} + void helper_check_interrupts(CPUNios2State *env) { qemu_mutex_lock_iothread(); diff --git a/hw/nios2/meson.build b/hw/nios2/meson.build index dd66ebb32f6..6c58e8082b4 100644 --- a/hw/nios2/meson.build +++ b/hw/nios2/meson.build @@ -1,5 +1,5 @@ nios2_ss =3D ss.source_set() -nios2_ss.add(files('boot.c', 'cpu_pic.c')) +nios2_ss.add(files('boot.c')) nios2_ss.add(when: 'CONFIG_NIOS2_10M50', if_true: files('10m50_devboard.c'= )) nios2_ss.add(when: 'CONFIG_NIOS2_GENERIC_NOMMU', if_true: files('generic_n= ommu.c')) =20 --=20 2.20.1