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Fri, 27 Nov 2020 13:36:56 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A90E0A4053; Fri, 27 Nov 2020 13:36:56 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av23.portsmouth.uk.ibm.com (Postfix) with SMTP; Fri, 27 Nov 2020 13:36:56 +0000 (GMT) Received: from yukon.ibmuc.com (sig-9-145-95-195.uk.ibm.com [9.145.95.195]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id B2E2922013F; Fri, 27 Nov 2020 14:36:55 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Subject: [PATCH] xive: Add more trace events Date: Fri, 27 Nov 2020 14:36:54 +0100 Message-Id: <20201127133654.290177-1-clg@kaod.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-11-27_06:2020-11-26, 2020-11-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 spamscore=0 malwarescore=0 mlxlogscore=637 lowpriorityscore=0 bulkscore=0 phishscore=0 mlxscore=0 suspectscore=2 clxscore=1034 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2011270078 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=148.163.158.5; envelope-from=clg@kaod.org; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" These are useful to understand IRQ requests from the OS. Signed-off-by: C=C3=A9dric Le Goater --- David, Feel free to merge with the previous. hw/intc/spapr_xive.c | 6 ++++++ hw/intc/spapr_xive_kvm.c | 5 +++++ hw/intc/trace-events | 7 +++++++ 3 files changed, 18 insertions(+) diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 644cc85cbdc9..db6d0e7a3a12 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -563,6 +563,8 @@ static int spapr_xive_claim_irq(SpaprInterruptControlle= r *intc, int lisn, =20 assert(lisn < xive->nr_irqs); =20 + trace_spapr_xive_claim_irq(lisn, lsi); + if (xive_eas_is_valid(&xive->eat[lisn])) { error_setg(errp, "IRQ %d is not free", lisn); return -EBUSY; @@ -588,6 +590,8 @@ static void spapr_xive_free_irq(SpaprInterruptControlle= r *intc, int lisn) SpaprXive *xive =3D SPAPR_XIVE(intc); assert(lisn < xive->nr_irqs); =20 + trace_spapr_xive_free_irq(lisn); + xive->eat[lisn].w &=3D cpu_to_be64(~EAS_VALID); } =20 @@ -654,6 +658,8 @@ static void spapr_xive_set_irq(SpaprInterruptController= *intc, int irq, int val) { SpaprXive *xive =3D SPAPR_XIVE(intc); =20 + trace_spapr_xive_set_irq(irq, val); + if (spapr_xive_in_kernel(xive)) { kvmppc_xive_source_set_irq(&xive->source, irq, val); } else { diff --git a/hw/intc/spapr_xive_kvm.c b/hw/intc/spapr_xive_kvm.c index e8667ce5f621..acc8c3650c4c 100644 --- a/hw/intc/spapr_xive_kvm.c +++ b/hw/intc/spapr_xive_kvm.c @@ -20,6 +20,7 @@ #include "hw/ppc/spapr_xive.h" #include "hw/ppc/xive.h" #include "kvm_ppc.h" +#include "trace.h" =20 #include =20 @@ -163,6 +164,8 @@ int kvmppc_xive_cpu_connect(XiveTCTX *tctx, Error **err= p) =20 vcpu_id =3D kvm_arch_vcpu_id(tctx->cs); =20 + trace_kvm_xive_cpu_connect(vcpu_id); + ret =3D kvm_vcpu_enable_cap(tctx->cs, KVM_CAP_PPC_IRQ_XIVE, 0, xive->f= d, vcpu_id, 0); if (ret < 0) { @@ -308,6 +311,8 @@ uint64_t kvmppc_xive_esb_rw(XiveSource *xsrc, int srcno= , uint32_t offset, return xive_esb_rw(xsrc, srcno, offset, data, 1); } =20 + trace_kvm_xive_source_reset(srcno); + /* * Special Load EOI handling for LSI sources. Q bit is never set * and the interrupt should be re-triggered if the level is still diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 77addc100f72..8ed397a0d587 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -205,6 +205,9 @@ bcm2835_ic_set_gpu_irq(int irq, int level) "GPU irq #%d= level %d" bcm2835_ic_set_cpu_irq(int irq, int level) "CPU irq #%d level %d" =20 # spapr_xive.c +spapr_xive_claim_irq(uint32_t lisn, bool lsi) "lisn=3D0x%x lsi=3D%d" +spapr_xive_free_irq(uint32_t lisn) "lisn=3D0x%x" +spapr_xive_set_irq(uint32_t lisn, uint32_t val) "lisn=3D0x%x val=3D%d" spapr_xive_get_source_info(uint64_t flags, uint64_t lisn) "flags=3D0x%"PRI= x64" lisn=3D0x%"PRIx64 spapr_xive_set_source_config(uint64_t flags, uint64_t lisn, uint64_t targe= t, uint64_t priority, uint64_t eisn) "flags=3D0x%"PRIx64" lisn=3D0x%"PRIx64= " target=3D0x%"PRIx64" priority=3D0x%"PRIx64" eisn=3D0x%"PRIx64 spapr_xive_get_source_config(uint64_t flags, uint64_t lisn) "flags=3D0x%"P= RIx64" lisn=3D0x%"PRIx64 @@ -217,6 +220,10 @@ spapr_xive_esb(uint64_t flags, uint64_t lisn, uint64_t= offset, uint64_t data) "f spapr_xive_sync(uint64_t flags, uint64_t lisn) "flags=3D0x%"PRIx64" lisn= =3D0x%"PRIx64 spapr_xive_reset(uint64_t flags) "flags=3D0x%"PRIx64 =20 +# spapr_xive_kvm.c +kvm_xive_cpu_connect(uint32_t id) "connect CPU%d to KVM device" +kvm_xive_source_reset(uint32_t srcno) "IRQ 0x%x" + # xive.c xive_tctx_accept(uint32_t index, uint8_t ring, uint8_t ipb, uint8_t pipr, = uint8_t cppr, uint8_t nsr) "target=3D%d ring=3D0x%x IBP=3D0x%02x PIPR=3D0x%= 02x CPPR=3D0x%02x NSR=3D0x%02x ACK" xive_tctx_notify(uint32_t index, uint8_t ring, uint8_t ipb, uint8_t pipr, = uint8_t cppr, uint8_t nsr) "target=3D%d ring=3D0x%x IBP=3D0x%02x PIPR=3D0x%= 02x CPPR=3D0x%02x NSR=3D0x%02x raise !" --=20 2.26.2