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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=66.111.4.27; envelope-from=its@irrelevant.dk; helo=out3-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , qemu-block@nongnu.org, Klaus Jensen , Max Reitz , Keith Busch , Stefan Hajnoczi , Klaus Jensen Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen Add the Zone Append command. Signed-off-by: Klaus Jensen --- hw/block/nvme.h | 5 ++++ include/block/nvme.h | 7 ++++++ hw/block/nvme.c | 53 +++++++++++++++++++++++++++++++++++++++++++ hw/block/trace-events | 1 + 4 files changed, 66 insertions(+) diff --git a/hw/block/nvme.h b/hw/block/nvme.h index 0cf3b303e34e..65d3070dec8c 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -16,6 +16,10 @@ typedef struct NvmeParams { uint32_t aer_max_queued; uint8_t mdts; bool use_intel_id; + + struct { + uint8_t zasl; + } zns; } NvmeParams; =20 typedef struct NvmeAsyncEvent { @@ -65,6 +69,7 @@ static inline const char *nvme_io_opc_str(uint8_t opc) case NVME_CMD_COPY: return "NVME_NVM_CMD_COPY"; case NVME_CMD_ZONE_MGMT_SEND: return "NVME_ZONED_CMD_ZONE_MGMT_SEND"; case NVME_CMD_ZONE_MGMT_RECV: return "NVME_ZONED_CMD_ZONE_MGMT_RECV"; + case NVME_CMD_ZONE_APPEND: return "NVME_ZONED_CMD_ZONE_APPEND"; default: return "NVME_NVM_CMD_UNKNOWN"; } } diff --git a/include/block/nvme.h b/include/block/nvme.h index 4c2b6fbb799a..9ea7dfc40cc6 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -487,6 +487,7 @@ enum NvmeIoCommands { NVME_CMD_COPY =3D 0x19, NVME_CMD_ZONE_MGMT_SEND =3D 0x79, NVME_CMD_ZONE_MGMT_RECV =3D 0x7a, + NVME_CMD_ZONE_APPEND =3D 0x7d, }; =20 typedef struct QEMU_PACKED NvmeDeleteQ { @@ -1059,6 +1060,11 @@ enum NvmeIdCtrlLpa { NVME_LPA_EXTENDED =3D 1 << 2, }; =20 +typedef struct QEMU_PACKED NvmeIdCtrlZns { + uint8_t zasl; + uint8_t rsvd1[4095]; +} NvmeIdCtrlZns; + #define NVME_CTRL_SQES_MIN(sqes) ((sqes) & 0xf) #define NVME_CTRL_SQES_MAX(sqes) (((sqes) >> 4) & 0xf) #define NVME_CTRL_CQES_MIN(cqes) ((cqes) & 0xf) @@ -1293,6 +1299,7 @@ static inline void _nvme_check_size(void) QEMU_BUILD_BUG_ON(sizeof(NvmeFwSlotInfoLog) !=3D 512); QEMU_BUILD_BUG_ON(sizeof(NvmeSmartLog) !=3D 512); QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrl) !=3D 4096); + QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrlZns) !=3D 4096); QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsNvm) !=3D 4096); QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsZns) !=3D 4096); QEMU_BUILD_BUG_ON(sizeof(NvmeSglDescriptor) !=3D 16); diff --git a/hw/block/nvme.c b/hw/block/nvme.c index f0f4d72266bf..3c2b255294d3 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -953,6 +953,21 @@ static inline uint16_t nvme_check_mdts(NvmeCtrl *n, si= ze_t len) return NVME_SUCCESS; } =20 +static inline uint16_t nvme_check_zasl(NvmeCtrl *n, size_t len) +{ + uint8_t zasl =3D n->params.zns.zasl; + + if (!zasl) { + return nvme_check_mdts(n, len); + } + + if (len > n->page_size << zasl) { + return NVME_INVALID_FIELD | NVME_DNR; + } + + return NVME_SUCCESS; +} + static inline uint16_t nvme_check_bounds(NvmeNamespace *ns, uint64_t slba, uint32_t nlb) { @@ -1169,6 +1184,7 @@ static void nvme_aio_err(NvmeRequest *req, int ret, N= vmeZone *zone) case NVME_CMD_FLUSH: case NVME_CMD_WRITE: case NVME_CMD_WRITE_ZEROES: + case NVME_CMD_ZONE_APPEND: status =3D NVME_WRITE_FAULT; break; default: @@ -1228,6 +1244,7 @@ static void nvme_rw_cb(void *opaque, int ret) switch (req->cmd.opcode) { case NVME_CMD_WRITE: case NVME_CMD_WRITE_ZEROES: + case NVME_CMD_ZONE_APPEND: nvme_zns_advance_wp(req); default: break; @@ -2308,8 +2325,13 @@ static uint16_t nvme_write(NvmeCtrl *n, NvmeRequest = *req) uint64_t data_offset; BlockBackend *blk =3D ns->blkconf.blk; bool wrz =3D rw->opcode =3D=3D NVME_CMD_WRITE_ZEROES; + bool append =3D rw->opcode =3D=3D NVME_CMD_ZONE_APPEND; uint16_t status; =20 + if (append && !nvme_ns_zoned(ns)) { + return NVME_INVALID_OPCODE | NVME_DNR; + } + trace_pci_nvme_write(nvme_cid(req), nvme_io_opc_str(rw->opcode), nvme_nsid(ns), nlb, data_size, slba); =20 @@ -2331,6 +2353,24 @@ static uint16_t nvme_write(NvmeCtrl *n, NvmeRequest = *req) NvmeZone *zone =3D nvme_ns_zone(ns, slba); assert(zone); =20 + if (append) { + uint64_t wp =3D zone->wp_staging; + + if (slba !=3D nvme_zslba(zone)) { + trace_pci_nvme_err_invalid_zslba(slba); + return NVME_INVALID_FIELD | NVME_DNR; + } + + status =3D nvme_check_zasl(n, data_size); + if (status) { + trace_pci_nvme_err_zasl(nvme_cid(req), data_size); + goto invalid; + } + + slba =3D wp; + rw->slba =3D req->cqe.qw0 =3D cpu_to_le64(wp); + } + status =3D nvme_check_zone_write(slba, nlb, zone); if (status) { goto invalid; @@ -2408,6 +2448,7 @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeRequest = *req) return nvme_flush(n, req); case NVME_CMD_WRITE_ZEROES: case NVME_CMD_WRITE: + case NVME_CMD_ZONE_APPEND: return nvme_write(n, req); case NVME_CMD_READ: return nvme_read(n, req); @@ -2677,6 +2718,8 @@ static void nvme_effects_zoned(NvmeEffectsLog *effect= s) effects->iocs[NVME_CMD_ZONE_MGMT_RECV] =3D NVME_EFFECTS_CSUPP; effects->iocs[NVME_CMD_ZONE_MGMT_SEND] =3D NVME_EFFECTS_CSUPP | NVME_EFFECTS_LBCC; + effects->iocs[NVME_CMD_ZONE_APPEND] =3D NVME_EFFECTS_CSUPP | + NVME_EFFECTS_LBCC; } =20 static uint16_t nvme_effects_log(NvmeCtrl *n, uint32_t buf_len, uint64_t o= ff, @@ -4169,6 +4212,11 @@ static void nvme_check_constraints(NvmeCtrl *n, Erro= r **errp) return; } =20 + if (params->zns.zasl && params->zns.zasl > params->mdts) { + error_setg(errp, "zns.zasl must be less than or equal to mdts"); + return; + } + if (n->pmrdev) { if (host_memory_backend_is_mapped(n->pmrdev)) { error_setg(errp, "can't use already busy memdev: %s", @@ -4364,12 +4412,16 @@ static void nvme_init_pci(NvmeCtrl *n, PCIDevice *p= ci_dev, Error **errp) static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev) { NvmeIdCtrl *id =3D &n->id_ctrl; + NvmeIdCtrlZns *id_zns; uint8_t *pci_conf =3D pci_dev->config; char *subnqn; =20 n->id_ctrl_iocss[NVME_IOCS_NVM] =3D g_new0(NvmeIdCtrl, 1); n->id_ctrl_iocss[NVME_IOCS_ZONED] =3D g_new0(NvmeIdCtrl, 1); =20 + id_zns =3D n->id_ctrl_iocss[NVME_IOCS_ZONED]; + id_zns->zasl =3D n->params.zns.zasl; + id->vid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID)); id->ssvid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR= _ID)); strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' '); @@ -4511,6 +4563,7 @@ static Property nvme_props[] =3D { DEFINE_PROP_UINT32("aer_max_queued", NvmeCtrl, params.aer_max_queued, = 64), DEFINE_PROP_UINT8("mdts", NvmeCtrl, params.mdts, 7), DEFINE_PROP_BOOL("use-intel-id", NvmeCtrl, params.use_intel_id, false), + DEFINE_PROP_UINT8("zns.zasl", NvmeCtrl, params.zns.zasl, 0), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/block/trace-events b/hw/block/trace-events index f62dfda279cd..221dc1af36c9 100644 --- a/hw/block/trace-events +++ b/hw/block/trace-events @@ -114,6 +114,7 @@ pci_nvme_mmio_shutdown_cleared(void) "shutdown bit clea= red" =20 # nvme traces for error conditions pci_nvme_err_mdts(uint16_t cid, size_t len) "cid %"PRIu16" len %zu" +pci_nvme_err_zasl(uint16_t cid, size_t len) "cid %"PRIu16" len %zu" pci_nvme_err_req_status(uint16_t cid, uint32_t nsid, uint16_t status, uint= 8_t opc) "cid %"PRIu16" nsid %"PRIu32" status 0x%"PRIx16" opc 0x%"PRIx8"" pci_nvme_err_addr_read(uint64_t addr) "addr 0x%"PRIx64"" pci_nvme_err_addr_write(uint64_t addr) "addr 0x%"PRIx64"" --=20 2.29.2